WO2020177577A1 - Procédé et appareil permettant à un dispositif de commande de charger un micrologiciel multimémoire, et dispositif informatique - Google Patents

Procédé et appareil permettant à un dispositif de commande de charger un micrologiciel multimémoire, et dispositif informatique Download PDF

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Publication number
WO2020177577A1
WO2020177577A1 PCT/CN2020/076595 CN2020076595W WO2020177577A1 WO 2020177577 A1 WO2020177577 A1 WO 2020177577A1 CN 2020076595 W CN2020076595 W CN 2020076595W WO 2020177577 A1 WO2020177577 A1 WO 2020177577A1
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WIPO (PCT)
Prior art keywords
cpu
core firmware
nandflash
controller
page
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Ceased
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PCT/CN2020/076595
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English (en)
Chinese (zh)
Inventor
杨志佳
冯元元
周强
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Shenzhen Union Memory Information System Co Ltd
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Shenzhen Union Memory Information System Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating

Definitions

  • This application relates to the technical field of solid-state hard disks, and in particular to a method, device and computer equipment for a controller to load multi-core firmware.
  • the Bootloader (multi-core firmware loading project) of the solid-state hard disk controller runs in a single CPU, and its function is to load the multi-core firmware from Nandflash to the storage area of the controller to run.
  • the controller usually reads and caches the multi-core firmware from Nandflash to DRAM (Dynamic Random Access Memory), and then moves the firmware.
  • the process of loading multi-core firmware is shown in Figure 1.
  • the Bootrom startup code
  • the bootrom will load the Bootloader from the designated area of NandFlash to run.
  • Bootloader will initialize the modules related to the controller, including CRM (clock module), NFC (NandFlash controller), DMAC (direct memory access module controller), and DRAM.
  • CRM clock module
  • NFC NandFlash controller
  • DMAC direct memory access module controller
  • DRAM direct memory access module controller
  • Bootloader applies for a cache space in SRAM (Static Random Access Memory), the controller reads the data of each Page to this cache space, and the first CPU (CPU0) copies the data in the cache to DRAM in order Until the multi-core firmware has been read.
  • the complete multi-core firmware is stored in the DRAM of the solid state drive.
  • CPU0 cannot move the data in DRAM to the ITCM (kernel instruction operating area) or DTCM (kernel data operating area) of other CPUs through CPU copy, the data can only be transferred through external modules, usually the controller uses DMA to transfer Move the multi-core firmware to the designated storage area of the designated CPU. CPU0 then releases other CPUs, allowing other CPUs to run normally, and CPU0 then jumps to zero address to run. At this time, all CPUs are running the system-wide multi-core firmware normally.
  • the solid-state hard disk controller Bootloader has high requirements for loading multi-core firmware. Once the startup time is too long, the solid-state hard disk and the host cannot send and receive commands normally.
  • the above method has the following problems: usually the multi-core firmware file is large, and the existing bootloader needs to move the data from the particle to the specified storage area of the specified CPU three times. First, move it from NandFlash to a cache through NFC, and then copy it through the CPU. The method is moved from the cache to the DRAM. Finally, the DMAC is used to move the data in the DRAM to the designated location of each CPU. It takes too long to load the firmware. Once the time is too long, the SSD and the host will not be able to send and receive commands normally. In addition, there are too many modules that need to be initialized, resulting in too long time for initialization.
  • One of the objectives of the embodiments of the present application is to provide a method, device, and computer equipment for a controller to load multi-core firmware, so as to solve the problem of a long time for the controller to load multi-core firmware.
  • a method for a controller to load multi-core firmware includes:
  • the first CPU runs the startup code
  • the startup code loads the multi-core firmware loading project from Nandflash
  • the first CPU runs the multi-core firmware loading project
  • the Nandflash controller moves the multi-core firmware of each page in Nandflash to the designated storage area of the CPU;
  • the multi-core firmware loading project run by the first CPU releases all CPUs except the first CPU, and the first CPU jumps to the zero address to run.
  • a device for a controller to load multi-core firmware including a first running unit, a loading unit, a second running unit, a moving unit, and a releasing unit;
  • the first running unit is configured to run the startup code by the first CPU
  • the loading unit is used for starting code to load a multi-core firmware loading project from Nandflash;
  • the second running unit is used for the first CPU to run the multi-core firmware loading project
  • the moving unit is used for the Nandflash controller to move the multi-core firmware of each page in Nandflash to the designated storage area of the CPU;
  • the release unit is used for the multi-core firmware loading project run by the first CPU to release all CPUs except the first CPU, and the first CPU then jumps to zero address to run.
  • a computer device including a memory, a processor, and a computer program stored in the memory and capable of running on the processor.
  • the processor implements the controller described in the first aspect when the processor executes the computer program Steps of the method of loading multi-core firmware.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method for loading multi-core firmware by the controller in the first aspect are realized.
  • the beneficial effects of the method and device for loading multi-core firmware by the controller provided by the embodiments of the application and the computer equipment are: the method for loading multi-core firmware by the controller provided by the present application avoids using DMA to move the multi-core firmware in the DRAM to a specified The designated storage area of the CPU, instead of directly moving the multi-core firmware of each page in Nandflash to the designated storage area of the CPU through the Nandflash controller, greatly reducing the time for the controller to load the multi-core firmware.
  • the use of clock modules, direct memory access module controllers, and dynamic random access memory is eliminated, further shortening the time for multi-core firmware loading.
  • Figure 1 is a flow chart of loading multi-core firmware for a prior art controller
  • FIG. 2 is a flowchart of a specific embodiment of a method for a controller to load multi-core firmware according to this application;
  • FIG. 3 is a schematic structural diagram of a specific embodiment of an apparatus for loading multi-core firmware by a controller according to this application;
  • FIG. 4 is a schematic block diagram of a specific embodiment of a computer device according to this application.
  • the present application provides a method for a controller to load multi-core firmware.
  • the method includes the following steps:
  • the first CPU runs the startup code
  • the startup code loads the multi-core firmware loading project from Nandflash;
  • the first CPU runs the multi-core firmware loading project
  • the multi-core firmware loading project reads the first page of the channel where the multi-core firmware is located to obtain information about the movement of the multi-core firmware;
  • Nandflash controller moves the multi-core firmware of each page (page) in Nandflash to the designated storage area of the CPU;
  • step S70 Judge whether all pages have been read, if yes, go to step S80, if no, go back to step S60;
  • the relevant information includes the designated CPU number, the storage area address, and the moved data length.
  • the designated storage area is the kernel data operation area and the kernel instruction operation area.
  • the first CPU (referred to as CPU0) runs the startup code.
  • the startup code will load the multi-core firmware loading project from Nandflash, and then CPU0 will run the multi-core firmware loading project.
  • NFC Nandflash controller
  • the SSD controller uses NFC to directly move the firmware in each page to the kernel data operation area and kernel instruction operation area of the designated CPU through the SSD system bus. Since the related information of the multi-core firmware movement is stored in the first page of Nandflash, the controller first reads the first page in Nandflash before moving the data to obtain the relevant information of the multi-core firmware. After the data is moved, the multi-core firmware loading project run by CPU0 releases all CPUs except CPU0, and CPU0 jumps to the zero address to run, thereby making the multi-core firmware run successfully.
  • the present application provides an apparatus for a controller to load multi-core firmware.
  • the device includes a first operating unit 1, a loading unit 2, a second operating unit 3, a moving unit 4 and a releasing unit 5, an initialization unit 6, a reading unit 7, and a judgment unit 8;
  • the first running unit 1 is used for the first CPU to run the startup code
  • Loading unit 2 used to load the multi-core firmware loading project from Nandflash with the startup code
  • the second running unit 3 is used for the first CPU to run the multi-core firmware loading project
  • the moving unit 4 is used for the Nandflash controller to move the multi-core firmware of each page in Nandflash to the designated storage area of the CPU;
  • the release unit 5 is used for the multi-core firmware loading project run by the first CPU to release all CPUs except the first CPU, and the first CPU then jumps to zero address to run;
  • the initialization unit 6 is used to initialize the Nandflash controller
  • the reading unit 7 is used for the multi-core firmware loading project to read the first page of the channel where the multi-core firmware is located, so as to obtain information about the movement of the multi-core firmware;
  • the judging unit 8 is used to judge whether all pages have been read.
  • the related information includes the designated CPU number, storage area address, and moved data length.
  • the designated storage area is the kernel data operation area and the kernel instruction operation area.
  • the first CPU (referred to as CPU0) runs the startup code.
  • the startup code will load the multi-core firmware loading project from Nandflash, and then CPU0 will run the multi-core firmware loading project.
  • NFC Nandflash controller
  • the SSD controller uses NFC to directly move the firmware in each page to the kernel data operation area and kernel instruction operation area of the designated CPU through the SSD system bus. Since the related information of the multi-core firmware movement is stored in the first page of Nandflash, the controller first reads the first page in Nandflash before moving the data to obtain the relevant information of the multi-core firmware. After the data is moved, the multi-core firmware loading project run by CPU0 releases all CPUs except CPU0, and CPU0 jumps to the zero address to run, thus making the multi-core firmware run successfully.
  • the present application also provides a computer device, including a memory, a processor, and a computer program stored in the memory and running on the processor.
  • the processor executes the computer program, the controller can be loaded as described above. Method steps for multi-core firmware.
  • the computer device 700 may be a terminal or a server.
  • the computer device 700 includes a processor 720, a memory, and a network interface 750 connected through a system bus 710, where the memory may include a non-volatile storage medium 730 and an internal memory 740.
  • the non-volatile storage medium 730 can store an operating system 731 and a computer program 732.
  • the processor 720 can execute any method for the controller to load multi-core firmware.
  • the processor 720 is used to provide computing and control capabilities, and support the operation of the entire computer device 700.
  • the internal memory 740 provides an environment for the operation of the computer program 732 in the non-volatile storage medium 730.
  • the processor 720 can execute any method for loading multi-core firmware by the controller.
  • the network interface 750 is used for network communication, such as sending assigned tasks.
  • the structure shown in FIG. 4 is only a block diagram of part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device 700 to which the solution of the present application is applied.
  • the specific computer device 700 may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.
  • the processor 720 is configured to run the program code stored in the memory to implement the following steps:
  • the first CPU runs the startup code
  • the startup code loads the multi-core firmware loading project from Nandflash
  • the first CPU runs the multi-core firmware loading project
  • the Nandflash controller moves the multi-core firmware of each page in Nandflash to the designated storage area of the CPU;
  • the multi-core firmware loading project run by the first CPU releases all CPUs except the first CPU, and the first CPU jumps to the zero address to run.
  • the multi-core firmware loading project reads the first page of the channel where the multi-core firmware is located to obtain information about the movement of the multi-core firmware.
  • the Nandflash controller moves the multi-core firmware of each page in Nandflash to the designated storage area of the CPU, it further includes the following steps:
  • the processor 720 may be a central processing unit (Central Processing Unit, CPU), and the processor 720 may also be other general-purpose processors, digital signal processors (Digital Signal Processors, DSPs), Application Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor.
  • the structure of the computer device 700 shown in FIG. 4 does not constitute a limitation on the computer device 700, and may include more or less components than shown, or a combination of certain components, or different components Layout.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • a computer readable storage medium includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code .
  • the disclosed device and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical function division.
  • there may be other division methods for example, multiple units or components may be It can be combined or integrated into another device, or some features can be omitted or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

L'invention concerne un procédé et un appareil permettant à un dispositif de commande de charger un micrologiciel multimémoire, et un dispositif informatique. Le procédé consiste : à mettre en oeuvre, par le biais d'une première CPU, un code de démarrage (S10) ; à charger, par le biais du code de démarrage, un projet de chargement de micrologiciel multimémoire à partir de Nandflash (S20) ; à mettre en oeuvre, par le biais de la première CPU, le projet de chargement de micrologiciel multimémoire (S30) ; à déplacer, par le biais d'un dispositif de commande Nandflash, le micrologiciel multimémoire de chaque page dans le Nandflash vers une zone de mémoire spécifiée d'une CPU (S60) ; à libérer, par le biais du projet de chargement de micrologiciel multimémoire mis en oeuvre par la première CPU, toutes les CPU à l'exception de la première CPU, et à faire sauter la première CPU vers l'adresse zéro afin d'être mise en oeuvre (S80). Selon le procédé, l'utilisation de DMA permettant de déplacer un micrologiciel multimémoire dans une DRAM vers une zone de mémoire spécifiée d'une CPU spécifiée est évitée ; au lieu de cela, un micrologiciel multimémoire de chaque page dans Nandflash est directement déplacé vers la zone de mémoire spécifiée de la CPU au moyen d'un dispositif de commande de mémoire Nandflash, ce qui permet de réduire considérablement le temps nécessaire au dispositif de commande afin de charger le micrologiciel à noyaux multiples.
PCT/CN2020/076595 2019-03-07 2020-02-25 Procédé et appareil permettant à un dispositif de commande de charger un micrologiciel multimémoire, et dispositif informatique Ceased WO2020177577A1 (fr)

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CN201910170875.9 2019-03-07

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CN110286963B (zh) * 2019-06-28 2022-08-12 Oppo广东移动通信有限公司 控制代码加载方法、装置、启动控制器以及电子设备
CN110727466B (zh) * 2019-10-15 2023-04-11 上海兆芯集成电路有限公司 多晶粒的多核计算机平台及其开机方法
CN113110891B (zh) * 2021-04-21 2022-03-29 深圳忆联信息系统有限公司 固态硬盘的固件加载方法、装置、计算机设备及存储介质
CN113687868A (zh) * 2021-08-31 2021-11-23 联想(北京)有限公司 设备固件启动方法、装置及电子设备
CN114594975B (zh) * 2022-03-16 2025-04-15 飞腾信息技术有限公司 固件管理方法、装置、存储介质及电子设备
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