WO2020258062A1 - Appareil et système d'extension d'adresse, et plateforme mobile - Google Patents

Appareil et système d'extension d'adresse, et plateforme mobile Download PDF

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Publication number
WO2020258062A1
WO2020258062A1 PCT/CN2019/092886 CN2019092886W WO2020258062A1 WO 2020258062 A1 WO2020258062 A1 WO 2020258062A1 CN 2019092886 W CN2019092886 W CN 2019092886W WO 2020258062 A1 WO2020258062 A1 WO 2020258062A1
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WIPO (PCT)
Prior art keywords
address
unit
original
comparison result
mapping unit
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Ceased
Application number
PCT/CN2019/092886
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English (en)
Chinese (zh)
Inventor
李刚
卢华
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SZ DJI Technology Co Ltd
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SZ DJI Technology Co Ltd
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Publication date
Application filed by SZ DJI Technology Co Ltd filed Critical SZ DJI Technology Co Ltd
Priority to CN201980012299.3A priority Critical patent/CN111712805A/zh
Priority to PCT/CN2019/092886 priority patent/WO2020258062A1/fr
Publication of WO2020258062A1 publication Critical patent/WO2020258062A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Definitions

  • the embodiments of the present application relate to the field of computer technology, and in particular to an address extension device, system, and movable platform.
  • the input bus is used to transmit the original address input by the external device to be expanded to the address conversion circuit, so that the original address is processed by the address mapping unit in the address conversion circuit in turn;
  • the address mapping unit is configured to determine a mapped address according to the original address, and transmit the mapped address to the output bus;
  • the address expansion device includes an input bus, an output bus, and at least one address conversion circuit, each of the address conversion circuits is respectively connected to the input bus and the output bus; each of the address conversion circuits includes a plurality of address mappings unit;
  • the output bus is used to transmit the mapped address to a preset memory, so that the external device to be expanded can perform an addressing operation on the memory according to the mapped address.
  • Figure 2 is a second schematic diagram of the application scenario provided by this application.
  • FIG. 4 is a first structural diagram of an address extension apparatus provided by another embodiment of this application.
  • FIG. 7 is a schematic structural diagram of an address extension device provided by another embodiment of this application.
  • FIG. 9 is a schematic structural diagram of an address extension system provided by an embodiment of this application.
  • the address mapping unit 7 is specifically used to convert the original address to generate a mapped address if the comparison result is a match.
  • the address mapping unit 7 For each original address, if the address mapping unit 7 determines that the comparison result between the original address and the matching address corresponding to the current address mapping unit 7 is a match; in addition, the address mapping unit 7 can also determine the original address and various other addresses. The comparison results between the matching addresses corresponding to the address mapping unit 7 are all unmatched; then, the address mapping unit 7 can determine that the match between itself and the original address is optimal, and the address mapping unit 7 can compare the original Address conversion to generate a mapped address.
  • each address mapping unit 7 is composed of a comparison unit 8, a priority unit 9 and a conversion unit 10.
  • the comparison unit 8 is connected to the priority unit 9, and the priority unit 9 is connected to the The conversion unit 10 is connected.
  • the comparison unit 8 can receive the original address transmitted by the input bus 4.
  • each address mapping unit 7 is composed of a comparison unit 8 and a conversion unit 10, wherein the comparison unit 8 is connected to the conversion unit 10; optionally, each address mapping unit A priority unit 9 is provided in 7, the priority unit 9 is connected to the comparison unit 8, and the priority unit 9 is connected to the conversion unit 10.
  • the conversion unit 10 and the priority unit 9 please refer to the second implementation manner described above, and will not be repeated.
  • each address mapping unit 7 is pre-configured with a corresponding mapping space size, and there is a one-to-one correspondence between the address mapping unit 7 and the mapping space size.
  • a corresponding destination base address is pre-configured for each address mapping unit 7, and there is a one-to-one correspondence between the address mapping unit 7 and the destination base address.
  • the address mapping unit 7 generates a mask mask according to the mapping space size K corresponding to the current address mapping unit 7; then, the address mapping unit 7 performs bitwise AND operation on the received original address addr_in and the mask mask to obtain the first Address signal addr_in&mask, and perform a bit-AND operation between the matching address addr_base corresponding to the address mapping unit 7 and the mask mask to obtain the second address signal addr_base&mask; then, the address mapping unit 7 combines the first address signal addr_in&mask with the second address signal
  • the address signal addr_base&mask is compared to determine whether the two are consistent; if the address mapping unit 7 determines that the first address signal addr_in&mask is consistent with the second address signal addr_base&mask, it determines the comparison result between the original address and the matching address corresponding to the address mapping unit 7 , Is a match, at this time, the original address and the matching address corresponding to the address mapping unit 7, the high-order address between the two are the same
  • the address mapping unit 7 is based on the comparison result between the original address and the matching address corresponding to the address mapping unit 7, the comparison result between the original address and the matching address corresponding to the other address mapping unit 7, and the priority of each address mapping unit 7
  • the address mapping unit 7 can invert the generated mask mask to obtain the inverted mask ⁇ mask; then, the address mapping unit 7 combines the original address addr_in with Perform a bit-AND operation between the reversed mask ⁇ mask to generate the offset of the mapped address (addr_in& ⁇ mask); then, the address mapping unit 7 compares the destination base address addr_tgt corresponding to the address mapping unit 7 to the offset of the mapped address A bit-OR operation is performed between the shift amounts (addr_in& ⁇ mask) to generate a mapping address ⁇ addr_tgt,0x0_0000 ⁇
  • the address mapping unit 7 determines that the comparison results between the other original addresses and the matching addresses corresponding to the other address mapping units 7 are not matched, or the address mapping unit 7 determines that its own priority is the highest, then the address mapping Unit 7 performs the inversion operation on the mask mask to obtain the inverted mask ⁇ mask; then, the address mapping unit 7 obtains ⁇ 0x1_1780_0000,0x0_0000 ⁇
  • the matching method provided in this embodiment it can be determined that the original address is located in the original address segment; then, through the address extension method provided in this embodiment, that is, through the mapping method, the mapped address can be obtained, and the mapped address is located in the extended address segment.
  • the expanded address in Figure 11 is the above-mentioned mapped address. As shown in FIG. 11, through the solution provided in this embodiment, the address space of 4 GB can be expanded to the address space of 16 GB.
  • the address mapping unit 7 may perform the same mask operation on the original address and the matching address corresponding to the address mapping unit 7 respectively, and then compare to obtain the comparison result;
  • the address mapping unit 7 can determine the conversion of the original address according to the comparison result output by the comparison unit 8, the comparison result of other address mapping units 7, and the preset priority information of each address mapping unit 7; the address mapping unit 7 is based on the pre-configuration To determine whether the original address and the matching address corresponding to the address mapping unit 7 match.
  • the address mapping unit 7 When it is determined that the comparison result between the original address and the matching address corresponding to the address mapping unit 7 is a match, the original The address and the matching address corresponding to the address mapping unit 7, the high-order address between the two are the same; the address mapping unit 7 performs bit operations on the original address based on the pre-configured destination base address and mask to obtain the mapped address, Among them, the address offset of the original address and the address offset of the mapped address are the same.
  • the above process is simple and the hardware structure used is small, and the space of other external devices can be quickly expanded; and the address expansion device 3 provided in this embodiment has a lower cost.
  • multiple address mapping units 7 have a one-to-one correspondence with multiple matching addresses, multiple target base addresses, and multiple mapping space sizes, which can realize segment mapping.
  • multiple matching addresses, multiple target base addresses, and multiple mapping space sizes can be configured by external devices, which can realize mapping granular configuration with high flexibility.
  • the address mapping unit 7 includes the following several implementation modes.
  • the address mapping unit 7 includes a first comparison unit 11, a second comparison unit 12, and a conversion unit 10 connected in sequence; the first comparison unit 11 is used to compare the original address and the address mapping unit 7 corresponds to the matching address to generate the first comparison result and transmit the first comparison result to the second comparison unit 12; the second comparison unit 12 is used to compare the attribute control of the original address when the first comparison result is a match Bit and the attribute identification bit of the address mapping unit 7 to generate a second comparison result, and transmit the second comparison result to the conversion unit 10; the conversion unit 10 is configured to convert the original address according to the second comparison result to generate a mapped address , And transfer the mapped address to the output bus 5.
  • the second implementation of the address mapping unit 7 includes a first comparison unit 11, a second comparison unit 12, and a conversion unit 10 connected in sequence; the first comparison unit 11 is used to compare the attribute control bits of the original address And the attribute identification bit of the address mapping unit 7 to generate the first comparison result and transmit the first comparison result to the conversion unit 10; the second comparison unit 12 is used to compare the original address and the address when the first comparison result is a match The matching address corresponding to the mapping unit 7 is used to generate a second comparison result, and the second comparison result is transmitted to the conversion unit 10; the conversion unit 10 is configured to convert the original address according to the second comparison result to generate a mapped address, and Transfer the mapped address to output bus 5.
  • attribute control bit is any one or more of the following: read control bit, write control bit, read/write control bit, and address security control bit;
  • attribute identification bit is any one or more of the following: read control bit , Write control bit, read and write control bit and address security control bit.
  • the attribute control bit is a read control bit and the attribute identification bit is a read control bit or a read-write control bit
  • the original address is converted.
  • address mapping unit 7 is also used for:
  • the attribute control bit is the write control bit and the attribute identification bit is the read/write prohibited control bit, an error signal is generated, and the error information is stored in the register 13.
  • the attribute control bit is an address security control bit and the attribute identification bit is an address unsafe control bit, an error signal is generated and the error information is stored in the register 13.
  • An attribute control bit can be set for the original address; an attribute flag bit is set for each address mapping unit 7, wherein there is a one-to-one correspondence between the address mapping unit 7 and the attribute flag bit.
  • the attribute control bits include but are not limited to any one or more of the following: read control bits, write control bits, read and write control bits, and address security control bits.
  • the attribute control bit is a read control bit, which indicates that the original address indicates a read operation; the attribute control bit is a write control bit, which indicates that the original address indicates a write operation; the attribute control bit is a read and write control bit, then It indicates that the original address indicates a read and write operation; the attribute control bit is the address security control bit, and the address security control bit can be safe or unsafe, indicating the security of the original address.
  • the attribute identification bits include but are not limited to any one or more of the following: read control bits, write control bits, read and write control bits, and address security control bits.
  • the attribute identification bit is a read control bit, which indicates that the address mapping unit 7 is configured with a readable matching address;
  • the attribute identification bit is a write control bit, which indicates that the address mapping unit 7 is configured with a writable matching address Address;
  • the attribute identification bit is the read-write control bit, which indicates that the address mapping unit 7 is configured with a readable and writable matching address;
  • the attribute identification bit is the address security control bit, the address security control bit can be safe or unsafe, then It indicates the security of the matching address configured by the address mapping unit 7.
  • the second comparison unit 12 in the first implementation manner and the first comparison unit 11 in the second implementation manner can complete the mapping between the attribute control bits of the original address and the address based on the above attribute control bits and attribute identification bits. Comparison between the attribute identification bits of unit 7.
  • the address mapping unit 7 determines the way to perform the original address, that is, it determines that the original address Convert; when the address mapping unit 7 determines that the attribute control bit is the read control bit and the attribute identification bit is the read/write prohibited control bit, it generates an error signal, and the address mapping unit 7 stores the error information in the register 13, and then waits for the address expansion Device 3 handles the error situation.
  • the address extension device 3 of this embodiment can implement access authority control and error recording, and it can be used as a hardware firewall.
  • the address mapping unit 7 determines the way to perform the original address, that is, determines that the original address can be converted; When the address mapping unit 7 determines that the attribute control bit is the address security control bit and the attribute identification bit is the address unsafe control bit, it generates an error signal, and the address mapping unit 7 stores the error information in the register 13, and then waits for the address extension device 3 Deal with error conditions.
  • each address mapping unit 7 can adopt the following implementation manners.
  • each address mapping unit 7 is configured with attribute flags.
  • the address mapping unit 7 determines that the attribute control bits are consistent with the attribute flags, Only then can the original address be converted; thus, it is ensured that the address mapping unit 7 can successfully process the original address.
  • the input buffer circuit 14 is connected to the input bus 4 and at least one address conversion circuit 6 respectively; the output buffer circuit 15 is connected to at least one address conversion circuit 6 and the output bus 5 respectively.
  • the address expansion device 3 may also include any one or more of the following structures: the configuration bus 16, the register 13, the input buffer circuit 14, and the output buffer circuit 15.
  • the input buffer circuit 14 is connected to the input bus 4, and the input buffer circuit 14 is connected to each address conversion circuit 6 respectively; the output buffer circuit 15 is connected to each address conversion circuit 6 respectively, and the output buffer circuit 15 is connected to The output bus 5 is connected.
  • the register 13 can also configure whether the original address skips the address conversion circuit 6. When configured to skip, the original address can also directly skip the address conversion circuit 6 and directly transmit to the output bus 5; when the address expansion device 3 also includes When the input buffer circuit 14 and the output buffer circuit 15 are input, the register 13 can also configure whether the original address skips the input buffer circuit 14 and the output buffer circuit 15. When configured to skip, the original address can also directly skip the input buffer circuit 14 When transmitted to the address conversion circuit 6, the destination address output by the address conversion circuit 6 can also skip the output buffer circuit 15 and be directly transmitted to the output bus 5.
  • the address mapping unit is used for determining the mapping address according to the original address, and transmitting the mapping address to the output bus.
  • the output bus is used to transmit the mapped address to the preset memory, so that the external device to be expanded 17 can address the memory according to the mapped address.
  • the address mapping unit is specifically configured to convert the original address to generate a mapped address if the comparison result is a match.
  • the address mapping unit is specifically used to convert the original address to generate a mapping based on the comparison result of the address mapping unit, the comparison result of other address mapping units, and the preset priority information of each address mapping unit address.
  • the comparison unit is used to compare the original address and the matching address corresponding to the address mapping unit, and transmit the comparison result to the priority unit.
  • the conversion unit is used to convert the original address according to the address conversion control signal to generate a mapped address, and transmit the mapped address to the output bus.
  • the address mapping unit includes a comparison unit and a conversion unit
  • the address conversion circuit further includes a priority unit; the priority units are respectively connected to the comparison unit and the conversion unit.
  • the original address includes an attribute control bit; a plurality of address mapping units correspond to a plurality of pre-configured attribute flags in a one-to-one correspondence; the address mapping unit is also used for the attribute control bits of the original address and the address mapping unit When the attribute identification bit matches, the original address is converted.
  • the address mapping unit includes a first comparison unit, a second comparison unit, and a conversion unit that are sequentially connected.
  • the second comparison unit is configured to compare the attribute control bit of the original address with the attribute identification bit of the address mapping unit when the first comparison result is a match to generate a second comparison result, and transmit the second comparison result to the conversion unit.
  • the address mapping unit includes a first comparison unit, a second comparison unit, and a conversion unit that are sequentially connected.
  • the conversion unit is configured to convert the original address to generate a mapped address according to the second comparison result, and transmit the mapped address to the output bus.
  • the attribute control bit is a read control bit and the attribute identification bit is a read control bit or a read-write control bit
  • the original address is converted.
  • the attribute control bit is a write control bit and the attribute identification bit is a write control bit or a read-write control bit
  • the original address is converted.
  • the attribute control bit is an address security control bit and the attribute identification bit is an address security control bit
  • the original address is converted.
  • the address expansion device 3 including the address expansion device 3, it also includes a register, which is connected to the register address conversion circuit; and the register is used to store configuration information of the address conversion circuit.
  • the address mapping unit is specifically configured to: if the comparison result is a match, the comparison result of at least one other address mapping unit is a match, and the priority of at least one other address mapping unit is less than the priority of the address mapping unit When the original address is converted to generate a mapped address.
  • the priority unit is used to generate an address conversion control signal according to the comparison result output by the comparison unit, the comparison result of other address mapping units, and the preset priority information of each address mapping unit.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

L'invention concerne un appareil et un système d'extension d'adresse, ainsi qu'une plateforme mobile. L'appareil comprend : un bus d'entrée, un bus de sortie et au moins un circuit de conversion d'adresse, chaque circuit de conversion d'adresse comprenant une pluralité d'unités de mappage d'adresse ; chaque circuit de conversion d'adresse est respectivement connecté au bus d'entrée et au bus de sortie ; le bus d'entrée transmet, au circuit de conversion d'adresse, une adresse d'origine introduite par un dispositif externe à étendre, et les unités de mappage d'adresse déterminent une adresse de mappage en fonction de l'adresse d'origine et transmettent l'adresse de mappage au bus de sortie ; et le bus de sortie transmet l'adresse de mappage à une mémoire prédéfinie, de telle sorte que le dispositif externe à étendre effectue une opération d'adressage sur la mémoire conformément à l'adresse de mappage. L'appareil d'extension d'adresse décrit dans le présent mode de réalisation n'a pas besoin d'être incorporé dans un processeur et est un appareil indépendant, et l'espace de dispositifs autres que le processeur peut être étendu. De plus, l'appareil d'extension d'adresse décrit dans le présent mode de réalisation utilise moins de structures matérielles, a un processus de traitement simple et peut étendre rapidement l'espace d'autres dispositifs externes.
PCT/CN2019/092886 2019-06-26 2019-06-26 Appareil et système d'extension d'adresse, et plateforme mobile Ceased WO2020258062A1 (fr)

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Application Number Priority Date Filing Date Title
CN201980012299.3A CN111712805A (zh) 2019-06-26 2019-06-26 地址扩展装置、系统和可移动平台
PCT/CN2019/092886 WO2020258062A1 (fr) 2019-06-26 2019-06-26 Appareil et système d'extension d'adresse, et plateforme mobile

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PCT/CN2019/092886 WO2020258062A1 (fr) 2019-06-26 2019-06-26 Appareil et système d'extension d'adresse, et plateforme mobile

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