WO2021003806A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2021003806A1
WO2021003806A1 PCT/CN2019/101738 CN2019101738W WO2021003806A1 WO 2021003806 A1 WO2021003806 A1 WO 2021003806A1 CN 2019101738 W CN2019101738 W CN 2019101738W WO 2021003806 A1 WO2021003806 A1 WO 2021003806A1
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Prior art keywords
layer
semiconductor device
trench
metal layer
well region
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PCT/CN2019/101738
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English (en)
French (fr)
Inventor
崔京京
黄玉恩
章剑锋
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Ween Semiconductors Co Ltd
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Ween Semiconductors Co Ltd
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Priority to KR1020237033276A priority Critical patent/KR102697260B1/ko
Priority to JP2019564780A priority patent/JP7382061B2/ja
Priority to US16/613,800 priority patent/US11264450B2/en
Priority to EP19783408.8A priority patent/EP3792980A4/en
Priority to SG11201910866XA priority patent/SG11201910866XA/en
Priority to KR1020197036448A priority patent/KR20210008296A/ko
Publication of WO2021003806A1 publication Critical patent/WO2021003806A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H10D8/605—Schottky-barrier diodes  of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6349—Deposition of epitaxial materials
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/044—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a semiconductor device and a manufacturing method thereof.
  • Schottky diodes are ultra-high-speed semiconductor devices, which are widely used in the field of energy conversion and are mostly used in high-frequency application environments.
  • Increasing the forward conduction capability per unit area of the Schottky diode means a better forward conduction capability, which makes the conduction energy loss smaller, thereby improving the energy efficiency of the product.
  • the traditional improvement of the forward conduction capability per unit area of the Schottky diode often leads to an increase in the reverse blocking leakage current.
  • the embodiment of the present invention provides a semiconductor device and a manufacturing method thereof, which can improve the forward conduction capability without affecting the reverse blocking capability.
  • an embodiment of the present invention provides a semiconductor device, including: a first electrode layer; a substrate layer located on the first electrode layer, the substrate layer having a first conductivity type with a first doping concentration; an epitaxial layer located on The substrate layer has a first surface away from the substrate layer, the epitaxial layer is of the first conductivity type with a second doping concentration; the well region is of the second conductivity type, and the well region extends from the first surface into the epitaxial layer, The orthographic projections of the plurality of well regions on the first surface are spaced apart; the second electrode layer includes a first metal layer disposed between adjacent well regions on the first surface, and a potential is formed between the first metal layer and the epitaxial layer. Schottky contacts with different barrier heights.
  • the Schottky contact barrier height of the first metal layer near the well region is lower than the Schottky contact barrier height of other regions.
  • At least a part of the well region of the epitaxial layer is correspondingly provided with a trench, and the well region corresponding to the trench is provided in the epitaxial layer around the sidewall and the bottom of the trench.
  • the opening width of the trench is greater than the bottom width of the trench.
  • the second electrode layer further includes a second metal layer covering the sidewall and bottom of the trench.
  • At least a part of the well region of the epitaxial layer is provided with blind holes correspondingly, and the well region corresponding to the blind holes is arranged in the epitaxial layer around the sidewall and the bottom of the blind hole.
  • the second electrode layer further includes a third metal layer, and the third metal layer covers the sidewall and bottom of the blind hole.
  • the depth of the trench is greater than or equal to the depth of the blind hole.
  • one or more blind holes are provided between adjacent trenches.
  • the opening width of the trench is greater than the opening width of the blind hole.
  • the second electrode layer further includes an electrical connection layer, and the first metal layer, the second metal layer, and the third metal layer are electrically connected through the electrical connection layer.
  • an ohmic contact is formed between the first electrode layer and the substrate layer, and an ohmic contact is formed between the second metal layer and the third metal layer and the corresponding well regions.
  • the first doping concentration is higher than the second doping concentration
  • the first conductivity type is opposite to the second conductivity type
  • the first conductivity type is N-type
  • an embodiment of the present invention provides a method for manufacturing a semiconductor device, including the steps of: providing a first electrode layer; providing a substrate layer, the substrate layer is located on the first electrode layer, and the substrate layer has a first doping concentration The first conductivity type; provide an epitaxial layer, the epitaxial layer is located on the substrate layer and has a first surface away from the substrate layer, the epitaxial layer is the first conductivity type with the second doping concentration; provides a well region, the well region is a second conductivity Type, the well region extends from the first surface into the epitaxial layer, and the orthographic projections of the multiple well regions on the first surface are spaced apart; a second electrode layer is provided, and the second electrode layer includes adjacent wells disposed on the first surface The first metal layer between the regions forms Schottky contacts with different barrier heights between the first metal layer and the epitaxial layer.
  • the first metal layer with different Schottky contact barrier heights is formed by alloying different metal materials with different Schottky contact barrier heights.
  • the first metal layer with different Schottky contact barrier heights is formed by alloying the metal material through two metal coatings and applying different annealing temperatures after each coating.
  • the method for manufacturing a semiconductor device further includes the step of providing a trench or a blind hole on the first surface of the epitaxial layer, and surrounding the sidewall and bottom of the trench or the blind hole in the epitaxial layer by ion implantation.
  • a well region is arranged inside, and the implantation angle of ion implantation at the sidewall of the trench or blind hole is greater than or equal to 7°.
  • a Schottky contact with a different barrier height is formed between the first metal layer in the second electrode layer and the epitaxial layer, and the part of the Schottky contact with a higher barrier height can make the semiconductor device Withstanding higher electric field strength, the part with lower Schottky contact barrier height can reduce the turn-on voltage of the semiconductor device during forward conduction, thereby improving the forward conduction capability, but does not affect the reverse blocking capability.
  • trenches and/or blind holes are provided on the epitaxial layer, and the well regions are arranged in the epitaxial layer around the sidewalls and bottoms of the trenches and/or blind holes, so that the depth of the well region is deeper, It can better protect the Schottky contact area.
  • the trench is deeper or wider than the blind hole, so that the well region corresponding to the trench can be opened earlier when the semiconductor device is conducting surge current, thereby improving the semiconductor device's conduction surge. Current capability. Further, the trench is deeper, and when the well region corresponding to the trench is reversely broken down, the avalanche point will occur at the corner of the trench, which can increase the avalanche energy borne by the semiconductor device.
  • the width of the opening of the trench is greater than the width of the bottom of the trench, which can reduce the dead area that the current line passes through, thereby improving the overall current conduction capability.
  • the first conductivity type is N-type, that is, the epitaxial layer and the substrate layer are N-type semiconductors. There are a large number of electrons in the N-type semiconductors, and the electrons have higher mobility and thus have stronger The current conduction capability.
  • FIG. 1 shows a schematic diagram of a cross-sectional structure of a semiconductor device according to an embodiment of the present invention
  • FIG. 2 shows a schematic cross-sectional structure diagram of a semiconductor device according to another embodiment of the present invention.
  • FIG. 3 shows a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 3- epitaxial layer 30- first surface; 31- groove; 32- blind hole;
  • FIG. 1 shows a schematic diagram of a cross-sectional structure of a semiconductor device according to an embodiment of the present invention.
  • FIG. 1 shows a schematic cross-sectional structure diagram of an active working region of a semiconductor device according to an embodiment of the present invention.
  • a semiconductor device according to an embodiment of the present invention includes a first electrode layer 1, a substrate layer 2, an epitaxial layer 3, a well region 4 and a second electrode layer 5.
  • the semiconductor device according to the embodiment of the present invention may be a semiconductor device such as silicon carbide and silicon.
  • the semiconductor device according to the embodiment of the present invention is a silicon carbide semiconductor device.
  • the first electrode layer 1 serves as a cathode of the semiconductor device.
  • the first electrode layer 1 may be a metal layer, and the metal may be gold, silver, copper, etc., or a combination thereof.
  • the substrate layer 2 is located on the first electrode layer 1. In one embodiment, an ohmic contact is formed between the first electrode layer 1 and the substrate layer 2.
  • the substrate layer 2 has a first conductivity type with a first doping concentration.
  • the epitaxial layer 3 is located on the substrate layer 2 and has a first surface 30 away from the substrate layer 2.
  • the epitaxial layer 3 is of the first conductivity type with a second doping concentration.
  • the first conductivity type is N-type
  • the substrate layer 2 and the epitaxial layer 3 are both N-type semiconductors.
  • the first doping concentration is higher than the second doping concentration.
  • the substrate layer 2 is a heavily doped N-type semiconductor
  • the epitaxial layer 3 is a lightly doped N-type semiconductor.
  • the well region 4 extends from the first surface 30 of the epitaxial layer 3 into the epitaxial layer 3.
  • the well region 4 is formed in the epitaxial layer 3 and at least part of the area overlaps the first surface 30 of the epitaxial layer 3.
  • the epitaxial layer 3 may have a plurality of well regions 4.
  • the orthographic projections of the plurality of well regions 4 on the first surface 30 are spaced apart from each other.
  • the orthographic projection of the well region 4 on the first surface 30 may be circular, oblong, polygonal, or elongated.
  • the well region 4 is of the second conductivity type.
  • the first conductivity type is opposite to the second conductivity type, that is, the well region 4 is P-type.
  • the second electrode layer 5 includes a first metal layer 51 disposed between adjacent well regions 4 on the first surface 30.
  • the second electrode layer 5 serves as the anode of the semiconductor device.
  • the first metal layer 51 may be a metal layer of gold, silver, copper, etc. or a combination thereof.
  • the first metal layer 51 is located in a region on the first surface 30 of the epitaxial layer 3 that does not correspond to the well region 4.
  • the first metal layer 51 is disposed on all regions on the first surface 30 of the epitaxial layer 3 that do not correspond to the well region 4. It can be understood that the first metal layer 51 may also be provided on a part of the region on the first surface 30 of the epitaxial layer 3 that does not correspond to the well region 4.
  • the Schottky contacts with different barrier heights are formed between the first metal layer 51 and the epitaxial layer 3. That is, the Schottky contact formed between the first metal layer 51 and the epitaxial layer 3 has two or more barrier heights.
  • the areas of the same barrier height in the Schottky contact areas of different barrier heights can be continuous or discontinuous.
  • there are two barrier heights that is, a part of the barrier height of the Schottky contact of the first metal layer 51 is relatively high, and the other part of the barrier height is relatively low.
  • the Schottky contact barrier height of the first metal layer 51 near the well region 4 is lower than the Schottky contact barrier height of other regions.
  • the Schottky contact barrier height of the first metal layer 51 between adjacent well regions 4 on the first surface 30 in the central region between the adjacent well regions 4 is higher than that of the Schottky contacts on both sides of the central region. Barrier height. It is understandable that the central area does not refer to the complete center position, and may include a certain offset range on both sides of the center position.
  • the first metal layer 51 is continuous. In another embodiment, the first metal layers 51 are spaced apart, and the spaced first metal layers 51 are electrically connected to each other.
  • the first surface 30 of the epitaxial layer 3 is provided with a metal layer in the region corresponding to the well region 4, and the metal layer forms a contact with the well region 4, preferably an ohmic contact. The metal layer 51 is electrically connected.
  • a Schottky contact with a different barrier height is formed between the first metal layer 51 in the second electrode layer 5 and the epitaxial layer 3, and the part of the Schottky contact with a higher barrier height can be
  • the semiconductor device can withstand higher electric field strength, and the part with a lower Schottky contact barrier height can reduce the turn-on voltage of the semiconductor device during forward conduction, thereby improving the forward conduction ability and improving the energy efficiency of the semiconductor device, but does not affect Reverse blocking capability.
  • FIG. 2 shows a schematic cross-sectional structure diagram of a semiconductor device according to another embodiment of the present invention.
  • the well region 4 of the epitaxial layer 3 is provided with a trench 31 correspondingly, and the well region 4 corresponding to the trench 31 is provided around the sidewall and bottom of the trench 31 Within the epitaxial layer 3.
  • the trench 31 may be provided on the first surface 30 of the epitaxial layer 3, and the first surface 30 is recessed into the epitaxial layer 3.
  • the groove 31 may be an oblong shape, an elongated shape, etc., and the groove 31 may also be a circular shape, a polygonal shape, or the like.
  • the position of the trench 31 corresponds to the well region 4.
  • the well region 4 corresponding to the trench 31 separates the trench 31 from other regions of the epitaxial layer 3.
  • the opening width of the trench 31 is greater than the bottom width of the trench 31.
  • the sidewall of the trench 31 may be inclined, and the trench 31 is generally formed in an inverted trapezoid shape.
  • the well region 4 generates a depletion region during reverse blocking.
  • the depletion region will expand inside the epitaxial layer 3, and the depletion regions of adjacent well regions 4 will gradually approach, forming a shielding protection for the middle Schottky contact region , The deeper the depth of the well region 4, the better the shielding and protection effect.
  • a trench 31 is provided on the epitaxial layer 3 and the well region 4 is arranged in the epitaxial layer 3 around the sidewall and bottom of the trench 31, so that the well region 4 The deeper the depth, it can better protect the Schottky contact area.
  • the opening width of the trench 31 is greater than the bottom width of the trench 31, which can reduce the dead area of the current line under the bottom of the trench 31, thereby improving the overall current conduction capability.
  • the second electrode layer 5 further includes a second metal layer 52 covering the sidewall and bottom of the trench 31. An ohmic contact is formed between the second metal layer 52 and the corresponding well region 4 correspondingly.
  • the second metal layer 52 may form an electrical connection with the first metal layer 51.
  • the second metal layer 52 may be a metal layer of gold, silver, copper, etc. or a combination thereof.
  • the well region 4 of the epitaxial layer 3 is provided with a blind hole 32 correspondingly, and the well region 4 corresponding to the blind hole 32 is provided in the epitaxial layer 3 around the sidewall and bottom of the blind hole 32 .
  • the blind hole 32 may be provided on the first surface 30 of the epitaxial layer 3, and the first surface 30 is recessed into the epitaxial layer 3.
  • the blind hole 32 may be circular, polygonal, etc., and the blind hole 32 may also be oblong, elongated, or the like.
  • the position of the blind hole 32 corresponds to the well region 4.
  • the well region 4 corresponding to the blind hole 32 separates the blind hole 32 from other regions of the epitaxial layer 3.
  • a blind hole 32 is provided on the epitaxial layer 3 and a well region 4 is arranged in the epitaxial layer 3 around the sidewall and bottom of the blind hole 32, so that the depth of the well region 4 is deeper and the Schottky contact area can be better protected.
  • the opening width of the blind hole 32 may be equal to the bottom width of the blind hole 32.
  • the side wall of the blind hole 32 may extend vertically, that is, extend vertically relative to the first surface 30.
  • the second electrode layer 5 further includes a third metal layer 53 covering the sidewall and bottom of the blind hole 32. An ohmic contact is formed between the third metal layer 53 and the corresponding well region 4 correspondingly.
  • the third metal layer 53 may form an electrical connection with the first metal layer 51.
  • the third metal layer 53 may be a metal layer of gold, silver, copper, etc. or a combination thereof.
  • the depth of the trench 31 is greater than or equal to the depth of the blind hole 32.
  • the depth of the groove 31 is greater than the depth of the blind hole 32.
  • the opening width of the trench 31 is greater than the opening width of the blind hole 32.
  • the trench 31 is deeper or wider than the blind hole 32, so that the well region corresponding to the trench 31 can be opened earlier when the semiconductor device is conducting surge current, thereby improving the surge current capability of the semiconductor device.
  • the depth of the trench 31 is deeper, and when the well region 4 corresponding to the trench 31 is reversely broken down, the avalanche point will occur at the corner of the trench 31 instead of the edge terminal area of the semiconductor device, so the avalanche current has low resistance leakage Path, which can increase the avalanche energy that the semiconductor device withstands.
  • one or more blind holes 32 are provided between adjacent grooves 31.
  • a plurality of blind holes 32 between adjacent grooves 31 are arranged at intervals.
  • a plurality of grooves 31 are distributed in parallel, and there are a plurality of blind holes 32 between two adjacent grooves 31.
  • the second electrode layer 5 further includes an electrical connection layer, and the first metal layer 51, the second metal layer 52, and the third metal layer 53 are electrically connected through the electrical connection layer.
  • the electrical connection layer may be a metal layer laid on the first metal layer 51, the second metal layer 52 and the third metal layer 53 at the same time. The first metal layer 51, the second metal layer 52 and the third metal layer 53 pass through the electrical connection layer. Form an electrical short circuit.
  • the electrical connection layer may be a thick metal layer.
  • the electrical connection layer may be a metal layer of gold, silver, copper, etc. or a combination thereof.
  • the outermost periphery of the active working area in the semiconductor device according to the embodiment of the present invention may also be provided with a terminal structure such as a field limiting loop or a junction terminal extension.
  • FIG. 2 only a part of the semiconductor device according to the embodiment of the present invention is shown.
  • two blind holes 32 arranged at intervals are exemplarily shown between adjacent grooves 31.
  • the arrangement of the blind holes 32 is not limited to that shown in the figure.
  • FIG. 3 shows a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • a method for manufacturing a semiconductor device includes the steps:
  • S120 Provide a substrate layer 2, the substrate layer 2 is located on the first electrode layer 1, and the substrate layer 2 is of the first conductivity type with a first doping concentration;
  • S130 Provide an epitaxial layer 3, the epitaxial layer 3 is located on the substrate layer 2 and has a first surface 30 away from the substrate layer 2, and the epitaxial layer 3 is of the first conductivity type with a second doping concentration;
  • S140 Provide a well region 4, the well region 4 is of the second conductivity type, the well region 4 is extended from the first surface 30 into the epitaxial layer 3, and the orthographic projections of the plurality of well regions 4 on the first surface 30 are separated from each other;
  • the second electrode layer 5 includes a first metal layer 51 disposed between adjacent well regions 4 on the first surface 30, and a potential barrier is formed between the first metal layer 51 and the epitaxial layer 3 Schottky contacts of varying heights.
  • the first metal layer 51 with different Schottky contact barrier heights is formed by alloying different metal materials with different Schottky contact barrier heights.
  • the first metal layer 51 with different Schottky contact barrier heights is formed by alloying the metal material through two metal coatings and applying different annealing temperatures after each coating.
  • the semiconductor device manufacturing method further includes the step of: providing a trench 31 or a blind hole 32 on the first surface 30 of the epitaxial layer 3, and surrounding the trench 31 or the blind hole 32 by ion implantation.
  • the wall and the bottom are provided with a well region 4 in the epitaxial layer 3, and the implantation angle of the ion implantation at the sidewall of the trench 31 or the blind hole 32 is greater than or equal to 7°.
  • the semiconductor device manufacturing method according to the embodiment of the present invention includes the steps:
  • a heavily doped N-type substrate layer 2 is provided; a lightly doped N-type epitaxial layer 3 is grown on the substrate layer 2; a space is formed by dry etching on the first surface 30 of the epitaxial layer 3 away from the substrate layer 2; A plurality of arranged grooves 31 recessed in the epitaxial layer 3; the first surface 30 of the epitaxial layer 3 between the grooves 31 is formed by another dry etching to form a spaced-apart recessed inside the epitaxial layer 3 The blind hole 32.
  • the ratio of the physical anisotropic etching part (such as argon ion bombardment etching) and the chemical co-etching part (such as fluorine-based gas) in the dry etching gas or using sidewall etching inhibitor gas (such as Bosh process) ) to control the lateral etching ratio to tilt the sidewall of the trench 31 to ensure that the opening width of the trench 31 is greater than the bottom width of the trench 31, and the sidewall of the blind hole 32 is substantially vertical.
  • the depth of the blind hole 32 is not greater than the depth of the trench 31 by controlling the etching speed and the etching time of the dry etching.
  • the method for manufacturing a semiconductor device further includes the step of forming a P-type well region 4 in the epitaxial layer 3 surrounding the sidewalls and bottoms of the trench 31 and the blind hole 32 through a high-temperature ion implantation process.
  • the implantation angle is greater than 7°; after completing the ion implantation operation, high temperature annealing is performed to activate the implanted ions.
  • the width of the corresponding area of the Schottky contact can be appropriately increased, which is beneficial to reduce subsequent processes, especially the Schottky Difficulty of regional lithography process.
  • a first metal layer 51 is formed on the area of the first surface 30 of the epitaxial layer 3 that does not correspond to the trench 31 and the blind hole 32.
  • the first metal layer 51 forms a Schottky contact with the epitaxial layer 3.
  • the specific steps include: The etching process forms a metal layer between the blind hole 32 and the trench 31 of the first surface 30 or the central area between the adjacent blind holes 32, and performs a first annealing process on the metal layer to form a gap between the metal layer and the epitaxial layer 3.
  • the metal materials forming the metal layers with the above two barrier heights may be the same metal material or different metal materials.
  • the temperature of the first annealing process is higher than the temperature of the second annealing process.
  • a second metal layer 52 is formed on the sidewall and bottom of the trench 31 by a photolithography process; a third metal layer 53 is formed on the sidewall and bottom of the blind hole 32 by a photolithography process; on the substrate layer 2 away from the epitaxial layer 3
  • the first electrode layer 1 with metal deposited on the surface; the second metal layer 52 and the corresponding well region 4, the third metal layer 53 and the corresponding well region 4, and the first electrode layer 1 and the substrate layer 2 are formed simultaneously by annealing process Ohmic contact.
  • the second metal layer 52 and the third metal layer 53 can be the same metal and formed at the same time, which can simplify the process steps and save costs.
  • a thick metal layer is deposited on the first metal layer 51, the second metal layer 52, and the third metal layer 53 to form an electrical short circuit.
  • the first metal layer 51, the second metal layer 52, the third metal layer 53 and the thick metal layer The layers together form the anode of the semiconductor device of the inventive embodiment.

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Abstract

一种半导体器件及其制造方法。半导体器件包括第一电极层（1）；衬底层（2），位于第一电极层（1）上；外延层（3），位于衬底层（2）上并具有远离衬底层（2）的第一表面（30）；阱区（4），阱区（4）由第一表面（30）向外延层（3）内延伸设置，多个阱区（4）在第一表面（30）上的正投影相互间隔；第二电极层（5），包括设置于第一表面（30）上相邻阱区（4）之间的第一金属层（51），第一金属层（51）与外延层（3）之间形成势垒高度不同的肖特基接触。该半导体器件，能够提高正向导通能力，又不影响反向阻断能力。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请要求享有于2019年07月11日提交的名称为“半导体器件及其制造方法”的中国专利申请201910624457.2的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体器件及其制造方法。
背景技术
肖特基二极管作为发展时间久、技术成熟的半导体器件结构，其属于一种超高速半导体器件，在能源转换领域得到广泛应用，多用作高频应用环境。提高肖特基二极管的单位面积正向导通能力表示更好的正向导通能力，使得导通能量损耗更小，从而可以提升产品能源利用效率。但是传统的对肖特基二极管的单位面积正向导通能力的提高，往往会导致反向阻断漏电流的增大。
因此，亟需一种新的改进的半导体器件。
发明内容
本发明实施例提供一种半导体器件及其制造方法，能够提高正向导通能力，又不影响反向阻断能力。
第一方面，本发明实施例提供一种半导体器件，包括：第一电极层；衬底层，位于第一电极层上，衬底层为具有第一掺杂浓度的第一导电类型；外延层，位于衬底层上并具有远离衬底层的第一表面，外延层为具有第二掺杂浓度的第一导电类型；阱区，为第二导电类型，阱区由第一表面 向外延层内延伸设置，多个阱区在第一表面上的正投影相互间隔；第二电极层，包括设置于第一表面上相邻阱区之间的第一金属层，第一金属层与外延层之间形成势垒高度不同的肖特基接触。
根据本发明实施例的一个方面，第一金属层的靠近阱区区域的肖特基接触势垒高度低于其他区域的肖特基接触势垒高度。
根据本发明实施例的一个方面，外延层的至少部分的阱区对应设置有沟槽，对应有沟槽的阱区围绕沟槽的侧壁和底部设置在外延层内。
根据本发明实施例的一个方面，沟槽的开口宽度大于沟槽的底部宽度。
根据本发明实施例的一个方面，第二电极层还包括第二金属层，第二金属层覆盖在沟槽的侧壁和底部。
根据本发明实施例的一个方面，外延层的至少部分的阱区对应设置有盲孔，对应有盲孔的阱区围绕盲孔的侧壁和底部设置在外延层内。
根据本发明实施例的一个方面，第二电极层还包括第三金属层，第三金属层覆盖在盲孔的侧壁和底部。
根据本发明实施例的一个方面，沟槽的深度大于等于盲孔的深度。
根据本发明实施例的一个方面，相邻沟槽之间设置有一个或多个盲孔。
根据本发明实施例的一个方面，沟槽的开口宽度大于盲孔的开口宽度。
根据本发明实施例的一个方面，第二电极层还包括电连接层，第一金属层、第二金属层和第三金属层通过电连接层电连接。
根据本发明实施例的一个方面，第一电极层与衬底层之间形成欧姆接触，第二金属层和第三金属层与对应的阱区之间对应形成欧姆接触。
根据本发明实施例的一个方面，第一掺杂浓度高于第二掺杂浓度，第一导电类型与第二导电类型相反，第一导电类型为N型。
第二方面，本发明实施例提供一种一种半导体器件制造方法，包括步骤：提供第一电极层；提供衬底层，衬底层位于第一电极层上，衬底层为具有第一掺杂浓度的第一导电类型；提供外延层，外延层位于衬底层上并 具有远离衬底层的第一表面，外延层为具有第二掺杂浓度的第一导电类型；提供阱区，阱区为第二导电类型，阱区由第一表面向外延层内延伸设置，多个阱区在第一表面上的正投影相互间隔；提供第二电极层，第二电极层包括设置于第一表面上相邻阱区之间的第一金属层，第一金属层与外延层之间形成势垒高度不同的肖特基接触。
根据本发明实施例的一个方面，通过将肖特基接触势垒高度不同的不同金属材料经过合金化形成肖特基接触势垒高度不同的第一金属层。
根据本发明实施例的一个方面，通过将金属材料经过两次金属镀膜且其中每次镀膜后施加不同退火温度而合金化形成肖特基接触势垒高度不同的第一金属层。
根据本发明实施例的一个方面，半导体器件制造方法还包括步骤：在外延层的第一表面设置沟槽或盲孔，通过离子注入的方式围绕沟槽或盲孔的侧壁和底部在外延层内设置阱区，沟槽或盲孔的侧壁处离子注入的注入角度大于等于7°。
根据本发明实施例的半导体器件，第二电极层中的第一金属层与外延层之间形成势垒高度不同的肖特基接触，肖特基接触势垒高度较高的部分可以使半导体器件承受更高电场强度，肖特基接触势垒高度较低的部分可以减少半导体器件正向导通时的开启电压，从而提升正向导通能力，但不影响反向阻断能力。
在一些可选的实施例中，在外延层上设置沟槽和/或盲孔且阱区围绕沟槽和/或盲孔的侧壁和底部设置在外延层内，使得阱区的深度更深，能够更好地对肖特基接触区域进行保护。
在一些可选的实施例中，沟槽相比盲孔更深或开口更宽，能够在半导体器件正向导通浪涌电流时沟槽对应的阱区更早的开启，提高半导体器件导通浪涌电流能力。进一步地，沟槽更深，沟槽对应的阱区在反向击穿时，雪崩点会发生在沟槽拐角处，能够提高半导体器件承受的雪崩能量。
在一些可选的实施例中，沟槽的开口宽度大于沟槽的底部宽度，能够减小电流线经过较少的区域(dead area)，进而提升整体导通电流能力。
在一些可选的实施例中，第一导电类型为N型，即外延层和衬底层为 N型半导体，N型半导体中存在着大量的电子，电子具备更高的迁移率，从而拥有更强的电流导通能力。
附图说明
下面将通过参考附图来描述本申请示例性实施例的特征、优点和技术效果。
图1示出根据本发明一个实施例的半导体器件的截面结构示意图；
图2示出根据本发明另一个实施例的半导体器件的截面结构示意图；
图3示出根据本发明一个实施例的半导体器件制造方法的流程图。
在附图中，附图并未按照实际的比例绘制。
标记说明：
1-第一电极层；
2-衬底层；
3-外延层；30-第一表面；31-沟槽；32-盲孔；
4-阱区；
5-第二电极层；51-第一金属层；52-第二金属层；53-第三金属层。
具体实施方式
下面结合附图和实施例对本申请的实施方式作进一步详细描述。以下实施例的详细描述和附图用于示例性地说明本申请的原理，但不能用来限制本申请的范围，即本申请不限于所描述的实施例。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者 设备中还存在另外的相同要素。
应当理解，在描述部件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将部件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
图1示出根据本发明一个实施例的半导体器件的截面结构示意图。在本实施例中，图1示出根据本发明实施例的半导体器件的有源工作区的截面结构示意图。参阅图1，根据本发明实施例的半导体器件包括第一电极层1、衬底层2、外延层3、阱区4和第二电极层5。根据本发明实施例的半导体器件可以是碳化硅、硅等半导体器件。优选地，根据本发明实施例的半导体器件是碳化硅半导体器件。
第一电极层1作为半导体器件的阴极。第一电极层1可以为金属层，该金属可以是金、银、铜等或其组合。
衬底层2位于第一电极层1上，在一个实施例中，第一电极层1与衬底层2之间形成欧姆接触。衬底层2为具有第一掺杂浓度的第一导电类型。
外延层3，位于衬底层2上并具有远离衬底层2的第一表面30，外延层3为具有第二掺杂浓度的第一导电类型。在一些可选的实施方式中，第一导电类型为N型，则衬底层2和外延层3均为N型半导体。N型半导体中存在着大量的电子，电子具备更高的迁移率，从而拥有更强的电流导通能力。在一些可选的实施方式中，第一掺杂浓度高于第二掺杂浓度，例如衬底层2为重掺杂的N型半导体，外延层3为轻掺杂的N型半导体。
阱区4由外延层3的第一表面30向外延层3内延伸设置。在一个实施例中，阱区4形成在外延层3内并且至少部分区域与外延层3的第一表面30重叠。外延层3可以具有多个阱区4。多个阱区4在第一表面30上的正投影相互间隔。阱区4在第一表面30上的正投影可以是圆形、长圆形、多边形或长条状等。阱区4为第二导电类型。在一些可选的实施方式中，第一导电类型与第二导电类型相反，即阱区4为P型。
第二电极层5包括设置于第一表面30上相邻阱区4之间的第一金属层51。第二电极层5作为半导体器件的阳极。第一金属层51可以是金、银、铜等或其组合的金属层。第一金属层51位于外延层3的第一表面30上的不对应阱区4的区域。在一个实施例中，第一金属层51设置于外延层3的第一表面30上的不对应阱区4的所有区域上。可以理解的是，第一金属层51还可以设置于外延层3的第一表面30上的不对应阱区4的区域中的部分区域。第一金属层51与外延层3之间形成势垒高度不同的肖特基接触。即第一金属层51与外延层3之间形成的肖特基接触具有两种以上的势垒高度。不同势垒高度的肖特基接触区域中相同势垒高度的区域可以是连续的，也可以是间断的。在一个实施例中，势垒高度为两种，即第一金属层51的肖特基接触中一部分势垒高度相对较高，而另一部分势垒高度相对较低。在一些可选的实施方式中，第一金属层51的靠近阱区4区域的肖特基接触势垒高度低于其他区域的肖特基接触势垒高度。即第一表面30上相邻阱区4之间的第一金属层51在该相邻阱区4之间的中心区域的肖特基接触势垒高度高于中心区域两侧的肖特基接触势垒高度。可以理解的是，中心区域并非指完全正中位置，可以包含正中位置两侧一定的偏移范围。在一个实施例中，第一金属层51为连续的。在另一个实施例中，第一金属层51为间隔开的，并且间隔的第一金属层51之间电连接。在一个实施例中，外延层3的第一表面30对应阱区4的区域设置有金属层，该金属层与阱区4之间形成接触，优选地形成欧姆接触，该金属层可以与第一金属层51电连接。
根据本发明实施例的半导体器件，第二电极层5中的第一金属层51与外延层3之间形成势垒高度不同的肖特基接触，肖特基接触势垒高度较高的部分可以使半导体器件承受更高电场强度，肖特基接触势垒高度较低的部分可以减少半导体器件正向导通时的开启电压，从而提升正向导通能力，提升半导体器件的能源利用效率，但不影响反向阻断能力。
图2示出根据本发明另一个实施例的半导体器件的截面结构示意图。在一些可选的实施方式中，参阅图2，外延层3的至少部分的阱区4对应设置有沟槽31，对应有沟槽31的阱区4围绕沟槽31的侧壁和底部设置在 外延层3内。沟槽31可以设置于外延层3的第一表面30，由第一表面30向外延层3内凹入成型。沟槽31可以是长圆形、长条形等，沟槽31还可以是圆形、多边形等。沟槽31的位置与阱区4相对应。对应沟槽31的阱区4使该沟槽31与外延层3的其他区域间隔开。在一些可选的实施方式中，沟槽31的开口宽度大于沟槽31的底部宽度。沟槽31的侧壁可以是倾斜的，沟槽31大体形成倒梯形。
阱区4在反向阻断时产生耗尽区，耗尽区会向外延层3内部扩展，相邻的阱区4的耗尽区会逐渐靠近，形成对中间肖特基接触区域的屏蔽保护，阱区4的深度越深，屏蔽保护的效果越好，在外延层3上设置沟槽31且阱区4围绕沟槽31的侧壁和底部设置在外延层3内，使得阱区4的深度更深，能够更好地对肖特基接触区域进行保护。
进一步地，沟槽31的开口宽度大于沟槽31的底部宽度，能够减小位于沟槽31的底部下方的电流线经过较少的区域(dead area)，进而提升整体导通电流能力。
在一些可选的实施方式中，第二电极层5还包括第二金属层52，第二金属层52覆盖在沟槽31的侧壁和底部。第二金属层52与对应的阱区4之间对应形成欧姆接触。第二金属层52可以与第一金属层51形成电连接。第二金属层52可以是金、银、铜等或其组合的金属层。
在一些可选的实施方式中，外延层3的至少部分的阱区4对应设置有盲孔32，对应有盲孔32的阱区4围绕盲孔32的侧壁和底部设置在外延层3内。盲孔32可以设置于外延层3的第一表面30，由第一表面30向外延层3内凹入成型。盲孔32可以是圆形、多边形等，盲孔32还可以是长圆形、长条形等。盲孔32的位置与阱区4相对应。对应盲孔32的阱区4使该盲孔32与外延层3的其他区域间隔开。在外延层3上设置盲孔32且阱区4围绕盲孔32的侧壁和底部设置在外延层3内，使得阱区4的深度更深，能够更好地对肖特基接触区域进行保护。盲孔32的开口宽度可以等于盲孔32的底部宽度。盲孔32的侧壁可以是竖直延伸的，即相对于第一表面30垂直延伸。
在一些可选的实施方式中，第二电极层5还包括第三金属层53，第三 金属层53覆盖在盲孔32的侧壁和底部。第三金属层53与对应的阱区4之间对应形成欧姆接触。第三金属层53可以与第一金属层51形成电连接。第三金属层53可以是金、银、铜等或其组合的金属层。
在一些可选的实施方式中，沟槽31的深度大于等于盲孔32的深度。优选地，沟槽31的深度大于盲孔32的深度。沟槽31的开口宽度大于盲孔32的开口宽度。沟槽31相比盲孔32更深或开口更宽，能够在半导体器件正向导通浪涌电流时沟槽31对应的阱区更早的开启，提高半导体器件导通浪涌电流能力。进一步地，沟槽31深度更深，沟槽31对应的阱区4在反向击穿时，雪崩点会发生在沟槽31拐角处而非半导体器件边缘终端区域，因此雪崩电流具有低阻泄放路径，从而能够提高半导体器件承受的雪崩能量。
在一些可选的实施方式中，相邻沟槽31之间设置有一个或多个盲孔32。相邻沟槽31之间的多个盲孔32间隔排布。在一个实施例中，多个沟槽31平行分布，相邻两个沟槽31之间具有多个盲孔32。
在一些可选的实施方式中，第二电极层5还包括电连接层，第一金属层51、第二金属层52和第三金属层53通过电连接层电连接。电连接层可以是同时敷设在第一金属层51、第二金属层52和第三金属层53的金属层，第一金属层51、第二金属层52和第三金属层53通过电连接层形成电学短接。电连接层可以是厚金属层。电连接层可以是金、银、铜等或其组合的金属层。
可以理解的是，根据本发明实施例的半导体器件中有源工作区的最外围还可以设置场限环或结终端扩展等终端结构。
还可以理解的是，图2所示的实施例中，仅示出了跟据本发明实施例的半导体器件的部分。并且图2所述的实施例中，相邻沟槽31之间示例性地示出为设置有间隔排布的两个盲孔32。在其他可选实施例中，相邻沟槽31之间还可以设置有1个、3个、4个、10个、100个等数量的盲孔32。并且多个盲孔32之间的排布形式不限于图中所示。
图3示出根据本发明一个实施例的半导体器件制造方法的流程图。
参阅图3，根据本发明实施例的半导体器件制造方法包括步骤：
S110：提供第一电极层1；
S120：提供衬底层2，衬底层2位于第一电极层1上，衬底层2为具有第一掺杂浓度的第一导电类型；
S130：提供外延层3，外延层3位于衬底层2上并具有远离衬底层2的第一表面30，外延层3为具有第二掺杂浓度的第一导电类型；
S140：提供阱区4，阱区4为第二导电类型，阱区4由第一表面30向外延层3内延伸设置，多个阱区4在第一表面30上的正投影相互间隔；
S150：提供第二电极层5，第二电极层5包括设置于第一表面30上相邻阱区4之间的第一金属层51，第一金属层51与外延层3之间形成势垒高度不同的肖特基接触。
在一些可选的实施方式中，通过将肖特基接触势垒高度不同的不同金属材料经过合金化形成肖特基接触势垒高度不同的第一金属层51。
在一些可选的实施方式中，通过将金属材料经过两次金属镀膜且其中每次镀膜后施加不同退火温度而合金化形成肖特基接触势垒高度不同的第一金属层51。
在一些可选的实施方式中，半导体器件制造方法还包括步骤：在外延层3的第一表面30设置沟槽31或盲孔32，通过离子注入的方式围绕沟槽31或盲孔32的侧壁和底部在外延层3内设置阱区4，沟槽31或盲孔32的侧壁处离子注入的注入角度大于等于7°。
在一个具体的实施例中，根据本发明实施例的半导体器件制造方法包括步骤：
提供重掺杂的N型的衬底层2；在衬底层2上生长轻掺杂的N型的外延层3；在外延层3的远离衬底层2的第一表面30通过干法刻蚀形成间隔排布的多个向外延层3内凹陷的沟槽31；在沟槽31之间的外延层3的第一表面30通过另一次干法刻蚀形成个间隔排布的向外延层3内部凹陷的盲孔32。
其中，通过改变干法刻蚀气体中物理异性刻蚀部分(如氩离子轰击刻蚀)和化学同向刻蚀部分(如氟基气体)的比例或者使用侧壁刻蚀抑制气体(如Bosh工艺)来控制横向刻蚀比例以使沟槽31的侧壁倾斜，确保沟 槽31的开孔宽度大于沟槽31的底部宽度，并且使盲孔32的侧壁大体垂直。并且，通过控制干法刻蚀的刻蚀速度与刻蚀时间使盲孔32的深度不大于沟槽31的深度。
根据本发明实施例的半导体器件制造方法还包括步骤：在围绕沟槽31和盲孔32的侧壁和底部的外延层3内通过高温离子注入工艺形成P型的阱区4，在对侧壁进行离子注入时注入角度大于7°；完成离子注入操作后进行高温退火以激活注入的离子。
通过设置沟槽31和盲孔32并围绕沟槽31和盲孔32的侧壁和底部形成阱区4，可以适当地增加肖特基接触对应区域的宽度，利于降低后续工艺尤其是肖特基区域光刻工艺的难度。
根据本发明实施例的半导体器件制造方法还包括步骤：
在外延层3的第一表面30的不对应沟槽31和盲孔32的区域上形成第一金属层51，第一金属层51与外延层3形成肖特基接触，具体步骤包括：通过光刻工艺在第一表面30的盲孔32与沟槽31之间或相邻盲孔32之间的中心区域形成金属层，并对该金属层进行第一退火工艺以形成与外延层3之间的高势垒高度的肖特基接触；通过光刻工艺在第一表面30中靠近盲孔32或沟槽31的区域形成另一金属层，并对该金属层进行第二退火工艺以形成与外延层3之间的低势垒高度的肖特基接触。其中，形成以上两种势垒高度的金属层的金属材料可以为同种金属材料也可以为不同金属材料。第一退火工艺的温度高于第二退火工艺的温度。
根据本发明实施例的半导体器件制造方法还包括步骤：
通过光刻工艺在沟槽31的侧壁和底部形成第二金属层52；通过光刻工艺在盲孔32的侧壁和底部形成第三金属层53；在衬底层2的背离外延层3的表面沉积金属的第一电极层1；通过退火工艺使第二金属层52与对应的阱区4，第三金属层53与对应的阱区4，以及第一电极层1与衬底层2同时形成欧姆接触。其中，第二金属层52和第三金属层53可以为同种金属并同时形成，能够简化工艺步骤，节约成本。
根据本发明实施例的半导体器件制造方法还包括步骤：
在第一金属层51、第二金属层52与第三金属层53上方淀积厚金属层 以形成电学短接，第一金属层51、第二金属层52、第三金属层53以及厚金属层共同形成发明实施例的半导体器件的阳极。
需要说明的是，在本文中，工艺步骤顺序只是作为本实施例的一个举例说明，按照成本控制，制造工艺能力不同，前后顺序可以做适当调动，不影响本发明实施例的实施效果，这对本领域技术人员也是显而易见的。
虽然已经参考优选实施例对本申请进行了描述，但在不脱离本申请的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本申请并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (17)

  1. 一种半导体器件，其特征在于，包括：
    第一电极层(1)；
    衬底层(2)，位于所述第一电极层(1)上，所述衬底层(2)为具有第一掺杂浓度的第一导电类型；
    外延层(3)，位于所述衬底层(2)上并具有远离所述衬底层(2)的第一表面(30)，所述外延层(3)为具有第二掺杂浓度的第一导电类型；
    阱区(4)，为第二导电类型，所述阱区(4)由所述第一表面(30)向所述外延层(3)内延伸设置，多个所述阱区(4)在所述第一表面(30)上的正投影相互间隔；
    第二电极层(5)，包括设置于所述第一表面(30)上相邻所述阱区(4)之间的第一金属层(51)，所述第一金属层(51)与所述外延层(3)之间形成势垒高度不同的肖特基接触。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述第一金属层(51)的靠近所述阱区(4)区域的肖特基接触势垒高度低于其他区域的肖特基接触势垒高度。
  3. 根据权利要求1所述的半导体器件，其特征在于，所述外延层(3)的至少部分的所述阱区(4)对应设置有沟槽(31)，对应有所述沟槽(31)的所述阱区(4)围绕所述沟槽(31)的侧壁和底部设置在所述外延层(3)内。
  4. 根据权利要求1所述的半导体器件，其特征在于，所述沟槽(31)的开口宽度大于所述沟槽(31)的底部宽度。
  5. 根据权利要求3所述的半导体器件，其特征在于，所述第二电极层(5)还包括第二金属层(52)，所述第二金属层(52)覆盖在所述沟槽(31)的侧壁和底部。
  6. 根据权利要求1所述的半导体器件，其特征在于，所述外延层(3)的至少部分的所述阱区(4)对应设置有盲孔(32)，对应有所述盲孔 (32)的所述阱区(4)围绕所述盲孔(32)的侧壁和底部设置在所述外延层(3)内。
  7. 根据权利要求6所述的半导体器件，其特征在于，所述第二电极层(5)还包括第三金属层(53)，所述第三金属层(53)覆盖在所述盲孔(32)的侧壁和底部。
  8. 根据权利要求3至7任一项所述的半导体器件，其特征在于，所述沟槽(31)的深度大于等于所述盲孔(32)的深度。
  9. 根据权利要求3至7任一项所述的半导体器件，其特征在于，相邻所述沟槽(31)之间设置有一个或多个所述盲孔(32)。
  10. 根据权利要求3至7任一项所述的半导体器件，其特征在于，所述沟槽(31)的开口宽度大于所述盲孔(32)的开口宽度。
  11. 根据权利要求1至7任一项所述的半导体器件，其特征在于，所述第二电极层(5)还包括电连接层，所述第一金属层(51)、所述第二金属层(52)和所述第三金属层(53)通过所述电连接层电连接。
  12. 根据权利要求1至7任一项所述的半导体器件，其特征在于，所述第一电极层(1)与衬底层(2)之间形成欧姆接触，所述第二金属层(52)和所述第三金属层(53)与对应的所述阱区(4)之间对应形成欧姆接触。
  13. 根据权利要求1所述的半导体器件，其特征在于，所述第一掺杂浓度高于所述第二掺杂浓度，所述第一导电类型与所述第二导电类型相反，所述第一导电类型为N型。
  14. 一种半导体器件制造方法，其特征在于，包括步骤：
    提供第一电极层(1)；
    提供衬底层(2)，所述衬底层(2)位于所述第一电极层(1)上，所述衬底层(2)为具有第一掺杂浓度的第一导电类型；
    提供外延层(3)，所述外延层(3)位于所述衬底层(2)上并具有远离所述衬底层(2)的第一表面(30)，所述外延层(3)为具有第二掺杂浓度的第一导电类型；
    提供阱区(4)，所述阱区(4)为第二导电类型，所述阱区(4)由 所述第一表面(30)向所述外延层(3)内延伸设置，多个所述阱区(4)在所述第一表面(30)上的正投影相互间隔；
    提供第二电极层(5)，所述第二电极层(5)包括设置于所述第一表面(30)上相邻所述阱区(4)之间的第一金属层(51)，所述第一金属层(51)与所述外延层(3)之间形成势垒高度不同的肖特基接触。
  15. 根据权利要求14所述的半导体器件制造方法，其特征在于，通过将肖特基接触势垒高度不同的不同金属材料经过合金化形成肖特基接触势垒高度不同的所述第一金属层(51)。
  16. 根据权利要求14所述的半导体器件制造方法，其特征在于，通过将金属材料经过两次金属镀膜且其中每次镀膜后施加不同退火温度而合金化形成肖特基接触势垒高度不同的所述第一金属层(51)。
  17. 根据权利要求14所述的半导体器件制造方法，其特征在于，所述半导体器件制造方法还包括步骤：在所述外延层(3)的所述第一表面(30)设置沟槽(31)或盲孔(32)，通过离子注入的方式围绕所述沟槽(31)或所述盲孔(32)的侧壁和底部在所述外延层(3)内设置所述阱区(4)，所述沟槽(31)或所述盲孔(32)的侧壁处离子注入的注入角度大于等于7°。
PCT/CN2019/101738 2019-07-11 2019-08-21 半导体器件及其制造方法 Ceased WO2021003806A1 (zh)

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