WO2021077334A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021077334A1
WO2021077334A1 PCT/CN2019/112797 CN2019112797W WO2021077334A1 WO 2021077334 A1 WO2021077334 A1 WO 2021077334A1 CN 2019112797 W CN2019112797 W CN 2019112797W WO 2021077334 A1 WO2021077334 A1 WO 2021077334A1
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WIPO (PCT)
Prior art keywords
contact pads
insulating layer
layer
display
display substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/112797
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English (en)
French (fr)
Inventor
杨中流
税禹单
刁永富
王文康
陈祯祐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP19945409.1A priority Critical patent/EP4050659B1/en
Priority to JP2021571478A priority patent/JP7448564B2/ja
Priority to CN201980002088.1A priority patent/CN113099732B/zh
Priority to PCT/CN2019/112797 priority patent/WO2021077334A1/zh
Priority to CN202410670547.6A priority patent/CN118647231A/zh
Priority to US16/976,191 priority patent/US11232755B2/en
Publication of WO2021077334A1 publication Critical patent/WO2021077334A1/zh
Anticipated expiration legal-status Critical
Priority to JP2024030309A priority patent/JP7747801B2/ja
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/046—Pixel structures with an emissive area and a light-modulating area combined in one pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate, a preparation method thereof, and a display device.
  • the electronic display product includes a display substrate. After the display substrate is manufactured, the display substrate needs to be subjected to a bonding process to connect the display substrate with external circuit signals.
  • At least one embodiment of the present disclosure provides a display substrate, which includes:
  • the base substrate includes a display area and a bonding area located on at least one side of the display area;
  • a plurality of data lines located in the display area, configured to provide data signals for the plurality of sub-pixels
  • a plurality of data leads located in the bonding area and electrically connected to the plurality of data lines;
  • At least one set of contact pads located in the bonding zone, wherein the at least one set of contact pads includes a first set of contact pads and a second set of contact pads, the first set of contact pads and the second set of contact pads
  • the pads respectively include a plurality of contact pads, the second set of contact pads are located on the side of the first set of contact pads away from the display area, and the plurality of data leads are connected to the first set of contact pads and the first set of contact pads. Two sets of contact pads are electrically connected;
  • the first insulating layer is located in the bonding area, the first insulating layer is located in the gaps between the plurality of contact pads and covers the edges of the plurality of contact pads, and is configured to expose the plurality of contacts The surface of the pad facing away from the base substrate.
  • the vertical distance between the surface of the first insulating layer on the side away from the base substrate and the base substrate is not less than the vertical distance between the plurality of contact pads away from the base substrate The vertical distance between the surface of one side and the base substrate.
  • At least a part of the first insulating layer is located in the gap between the adjacent contact pads of the first set of contact pads.
  • At least part of the first insulating layer is located in the gap between adjacent contact pads in the second set of contact pads.
  • At least part of the first insulating layer is located in the gap between adjacent contact pads in the first set of contact pads and is located in the same position in the second set of contact pads. In the gap between adjacent contact pads.
  • the plurality of contact pads of the first group of contact pads are arranged in at least a first row
  • the plurality of contact pads of the second group of contact pads are arranged in at least a second row.
  • the row direction of the first row and the second row is parallel to the extending direction of the side of the display area facing the bonding area, and at least part of the first insulating layer is located in the first row And the gap between the second row.
  • each of the plurality of openings of the first insulating layer has a side wall, and the side wall of at least one of the plurality of openings has a slope angle relative to the base substrate.
  • the value range of is 40 degrees to 60 degrees.
  • At least one of the plurality of contact pads has a length ranging from 650 ⁇ m to 750 ⁇ m and a width ranging from 34 ⁇ m to 42 ⁇ m.
  • At least one of the plurality of sub-pixels includes a thin film transistor, a planarization layer, and a light-emitting element
  • the planarization layer is located on the side of the thin film transistor away from the base substrate to Covering the thin film transistor
  • the light emitting element is located on the side of the planarization layer away from the base substrate
  • the planarization layer includes a first planarization layer via hole
  • the thin film transistor includes located on the base substrate
  • the active layer, the gate located on the side of the active layer away from the base substrate, and the source and drain located on the side of the gate away from the base substrate, and the source and One of the drains is electrically connected to the light-emitting element through the first planarization layer via hole; the first insulating layer and the planarization layer are provided in the same layer.
  • the thickness of the first insulating layer in the bonding region is smaller than the thickness of the planarization layer in the display region.
  • each of the plurality of contact pads includes at least one metal layer, the at least one metal layer includes a first metal layer, and the first metal layer is connected to the source electrode and the The drain is arranged in the same layer.
  • the plurality of data leads include a first set of data leads and a second set of data leads, and the first set of data leads are electrically connected to the first set of contact pads in a one-to-one correspondence.
  • the second set of data leads are electrically connected to the second set of contact pads in a one-to-one correspondence, and relative to the base substrate, the first set of data leads and the second set of data leads are located in different layers, respectively .
  • the at least one of the plurality of sub-pixels further includes a storage capacitor
  • the storage capacitor includes two capacitor electrodes
  • the first set of data leads and the gate are on the same layer
  • the second set of data leads and one of the two capacitor electrodes of the storage capacitor are arranged in the same layer; or, the second set of data leads and the gate are arranged in the same layer, and the first set of data
  • the lead wire and one of the two capacitor electrodes of the storage capacitor are arranged in the same layer.
  • the display substrate of the foregoing embodiment may further include: an interlayer insulating layer in a bonding area, located in the bonding area, between the plurality of contact pads and the leads, and between the first insulating layer and the bonding area.
  • an interlayer insulating layer in a bonding area located in the bonding area, between the plurality of contact pads and the leads, and between the first insulating layer and the bonding area.
  • the second gate insulating layer is located in the bonding region, between the first gate insulating layer of the bonding region and the interlayer insulating layer of the bonding region, and is laminated with the interlayer insulating layer of the bonding region
  • the first set of contact pads are electrically connected to the first set of data leads in a one-to-one correspondence through a plurality of first contact pad vias in the interlayer insulating layer of the bonding region
  • the second The set of contact pads are electrically connected to the second set of data leads through a plurality of second
  • the second set of contact pads are electrically connected to the second set of data leads in a one-to-one correspondence through a plurality of second contact pad vias in the interlayer insulating layer of the first bonding region, so
  • the first set of contact pads correspond to the first set of data leads through a plurality of first contact pad vias passing through the interlayer insulating layer of the bonding region and the second gate insulating layer of the bonding region Electric connection.
  • the at least one of the plurality of sub-pixels further includes an interlayer insulating layer in the display area, a first gate insulating layer in the display area, and a second gate insulating layer in the display area.
  • the interlayer insulating layer, the first gate insulating layer in the display area, and the second gate insulating layer in the display area are respectively connected to the interlayer insulating layer in the bonding area, the first gate insulating layer in the bonding area, and the second gate insulating layer in the bonding area.
  • the gate insulating layer is arranged in the same layer; the display area interlayer insulating layer is located between the gate and the source and drain electrodes, and the display area first gate insulating layer is located in the display area interlayer insulating Layer close to the side of the base substrate, the second gate insulating layer in the display area is located between the interlayer insulating layer in the display area and the first gate insulating layer in the display area; the two capacitor electrodes include a first A capacitor electrode and a second capacitor electrode, the first capacitor electrode and the gate electrode are arranged in the same layer, and the second capacitor electrode is arranged on the interlayer insulating layer in the display area and the second gate insulating layer in the display area between.
  • the first set of data leads are arranged in the same layer as the first capacitor electrode and the gate, and the second set of data leads are in the same layer as the second capacitor electrode.
  • the second group of data leads are arranged in the same layer as the first capacitor electrode and the gate, and the first group of data leads and the second capacitor electrode are arranged in the same layer.
  • the surface of the first insulating layer in the gap between the adjacent contact pads in the first group of contact pads and the second group of contact pads has recessed portions
  • the surface of the first insulating layer located in the gap between the first row and the second row has a recessed portion.
  • the portion of the data lead electrically connected to at least one contact pad of the second set of contact pads that passes through the first set of contact pads is located in the first set of contact pads
  • the gaps between adjacent contact pads are covered by the first insulating layer.
  • At least one data lead in the first set of data leads extends obliquely with respect to the edge of the display substrate, or at least one data lead in the second set of data leads extends relative to the edge of the display substrate.
  • the edge of the display substrate extends obliquely.
  • At least two data leads in the first set of data leads extend obliquely with respect to the edge of the display substrate, and the at least two data leads in the first set of data leads
  • the included angles of the data leads in the same rotation direction relative to the edge of the display substrate are the same or complementary.
  • At least two data leads in the second set of data leads extend obliquely with respect to the edge of the display substrate, and the at least two data leads in the second set of data leads
  • the included angles of the two data leads in the same rotation direction relative to the edge of the display substrate are the same or complementary.
  • At least one contact pad of the first set of contact pads extends obliquely with respect to the edge of the display substrate, or at least one of the second set of contact pads is relative to the display substrate.
  • the edge extends obliquely.
  • At least two contact pads of the first set of contact pads extend obliquely with respect to the edge of the display substrate, and the at least two contact pads of the first set of contact pads Relative to the edge of the display substrate, the included angles of the same rotation direction are the same or complementary.
  • At least two contact pads of the second set of contact pads extend obliquely with respect to the edge of the display substrate, and the at least two contact pads in the second set of contact pads Relative to the edge of the display substrate, the included angles of the same rotation direction are the same or complementary.
  • Another embodiment of the present disclosure provides a display device including the display substrate described in any of the above embodiments.
  • Another embodiment of the present disclosure provides a manufacturing method of a display substrate, the manufacturing method including:
  • the base substrate includes a display area and a bonding area located on at least one side of the display area;
  • At least one set of contact pads is formed in the bonding area, wherein the at least one set of contact pads includes a first set of contact pads and a second set of contact pads, the first set of contact pads and the second set of contact pads
  • the pads respectively include a plurality of contact pads, the second set of contact pads are located on the side of the first set of contact pads away from the display area, and the plurality of data leads are connected to the first set of contact pads and the first set of contact pads.
  • the two sets of contact pads are electrically connected in one-to-one correspondence;
  • first insulating layer in the bonding area, wherein the first insulating layer is located in the bonding area and is located in the gap between the plurality of contact pads and covers the edges of the plurality of contact pads, And is configured to expose the surfaces of the plurality of contact pads facing away from the base substrate.
  • 1A is a plan view of a bonding area of a display substrate provided by some embodiments of the present disclosure
  • FIG. 1B is a cross-sectional view of the display substrate shown in FIG. 1A along the line M1-N1;
  • FIG. 1C is a cross-sectional view of the display substrate shown in FIG. 1A along the line M2-N2;
  • FIG. 1D is a cross-sectional view of the display substrate shown in FIG. 1A along the line M1-N1 according to another embodiment
  • FIG. 2 is a plan view of a partial area of a display substrate provided by some embodiments of the present disclosure
  • FIG. 3 is a cross-sectional view of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 4 is a cross-sectional view of a display device provided by some embodiments of the present disclosure.
  • 5A is a plan view of a display substrate provided by some embodiments of the present disclosure.
  • 5B(1) and 5B(2) are plan views of the bonding area of the display substrate shown in FIG. 5A;
  • 5C is a cross-sectional view of the display substrate shown in FIG. 5A along the line M3-N3;
  • 5D is a cross-sectional view of the display substrate along the line M4-N4 shown in FIG. 5B(1);
  • Fig. 5E is a cross-sectional view of the display substrate along the line M5-N5 shown in Fig. 5B(1);
  • 5F is a cross-sectional view of the display substrate shown in FIG. 5A along the line M3-N3 provided by another implementation;
  • FIG. 5G is a cross-sectional view of the display substrate along the line M4-N4 shown in FIG. 5B(1) provided by another implementation;
  • 5H is a cross-sectional view of the display substrate along the line M5-N5 shown in FIG. 5B(1) provided by another implementation;
  • FIG. 6 is a cross-sectional view of the display area of the display substrate shown in FIG. 5B.
  • FIGS. 7A to 7L are process diagrams of another method for preparing a display substrate provided by some embodiments of the present disclosure.
  • the display substrate needs to be connected to an external circuit (for example, a circuit such as a control chip), so as to control or drive the display substrate through the external circuit during the display process.
  • the external circuit may include a flexible circuit (Chip On Film, COF for short) board, and the flexible circuit board is provided with a control chip or a driving chip.
  • the display substrate is provided with contact pads to connect with the circuit of the flexible circuit board through a bonding process. If there is a step difference between the contact pad of the display substrate and its surrounding area, that is, the height of the contact pad is greater than its surrounding area, then in the bonding process, the pressure applied by the indenter of the device for providing pressure on the substrate is unevenly distributed.
  • the pressure is concentrated on the contact pads and is difficult to be applied to the gap area between the contact pads.
  • the display substrate may be broken due to uneven force.
  • the film layer in the gap between the contact pads may break under the action of the tensile stress caused by uneven force, and damage the display substrate.
  • the film layer (such as an insulating layer) included in the display substrate is formed by physical or chemical vapor deposition (such as plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, referred to as PECVD)).
  • PECVD plasma enhanced chemical vapor deposition
  • the crystals in the layer usually have defects in the microstructure.
  • applying pressure to the contact pad will cause uneven stress in the bonding area and cause stress concentration.
  • the stress is concentrated in the area where the tip (for example, the corner) of the contact pad is located, and the stress concentration will aggravate the crystal defects in the film layer, and further make the film layer easy to break.
  • the area between the contact pads will be applied to the The positive and negative tensile stresses of the two contact pads cause the film layer of this part to be broken due to tension.
  • the tensile stress generated in the portion of the film layer formed of silicon nitride located in the gap between the contact pads is approximately 182 MPa to 712 MPa.
  • At least one embodiment of the present disclosure provides a display substrate, a preparation method thereof, and a display device.
  • the display substrate includes a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data leads, at least one set of contact pads and a first insulating layer.
  • the base substrate includes a display area and a bonding area located on at least one side of the display area; multiple sub-pixels are located in the display area; multiple data lines are located in the display area and configured to provide data signals for the multiple sub-pixels; multiple data leads are located In the bonding area and electrically connected to multiple data lines; at least one set of contact pads is located in the bonding area, the at least one set of contact pads includes a first set of contact pads and a second set of contact pads, the first set of contact pads and the first set of contact pads The two sets of contact pads respectively include a plurality of contact pads, the second set of contact pads is located on the side of the first set of contact pads away from the display area, and the plurality of data leads are electrically connected to the first set of contact pads and the second set of contact pads;
  • the insulating layer is located in the bonding area, and the first insulating layer is located in the gaps between the contact pads and covers the edges of the contact pads, and is configured to expose the surfaces of the contact pads facing away from the base
  • the gaps between the plurality of contact pads cover the edges of the plurality of contact pads, and are configured to expose the surfaces of the plurality of contact pads facing away from the base substrate. .
  • the first insulating layer in the gap between the contact pads can reduce or eliminate the step difference between the contact pad and the gap between the contact pads. Therefore, in the bonding process, the pressure head is applied to the surface of the first insulating layer and The force on the surface of the contact pad is dispersed and the distribution is more uniform (for example, the pressure is equal), that is, the pressure distribution applied by the indenter at the contact pad and the gap between the contact pad is more uniform.
  • the display substrate (the bonding area) will not be damaged due to uneven forces during the bonding process, which improves the yield of the display substrate in actual production and reduces the manufacturing cost.
  • a spatial rectangular coordinate system is established based on the base substrate of the display substrate to describe the position of each structure in the display substrate.
  • the X axis and the Y axis are parallel to the surface where the base substrate is located, and the Z axis is perpendicular to the surface where the base substrate is located.
  • At least one embodiment of the present disclosure provides a display substrate, and the structure of the display substrate will be described in detail below.
  • the display substrate includes a base substrate, a plurality of contact pads, and a first insulating layer.
  • the base substrate includes a display area and a peripheral area at least partially surrounding the display area.
  • the peripheral area further includes at least one bonding area (for example, multiple bonding areas) located on at least one side of the display area, and a plurality of contact pads are located in the bonding area. There is a gap between the regions and each other, that is, the contact pads are spaced apart from each other by a certain distance.
  • FIG. 1A is a plan view of a bonding area of a display substrate provided by some embodiments of the present disclosure.
  • a bonding area as an example, as shown in FIG. 1A, a plurality of contact pads are arranged in at least two rows, and at least part of the first insulating layer is also located in gaps between contact pads in different rows.
  • the contact pads 200a are arranged in two rows, namely the first row L1 and the second row L2, the contact pads 200a of the first row L1 and the contact pads 200a of the second row L2
  • a first insulating layer 310a is provided in the gap therebetween.
  • the gap between the contact pads in different rows is usually larger than the gap between the contact pads in the same row.
  • the location of the display substrate is different.
  • the part at the gap between the contact pads of the row is more likely to be broken during the bonding process.
  • the first insulating layer 310a can prevent the part of the display substrate in the gap between the contact pads in different rows from being broken during the bonding process; moreover, more contact pads can be arranged in the bonding area.
  • the vertical distance between the surface of the first insulating layer on the side away from the base substrate and the base substrate is not less than the distance from the surface of the plurality of contact pads on the side away from the base substrate.
  • the vertical distance of the bottom substrate is not less than the distance from the surface of the plurality of contact pads on the side away from the base substrate.
  • the surface of the first insulating layer 310a and the contact pad 200a facing away from the base substrate 100a are substantially on the same plane, that is, the first insulating layer 310a and the contact pad 200a are opposite to The height of the base substrate 100a is substantially equal.
  • the "height" is the vertical distance from the surface of the structure (for example, the contact pad 200a) away from the base substrate to the base substrate. It should be noted that, in the embodiments of the present disclosure, the height of the first insulating layer may be greater than or less than the height of the contact pad, for example, slightly greater or slightly less than the height of the contact pad, and is not limited to those shown in FIG. 1B and FIG. 1C. The situation of equality.
  • the height of the first insulating layer 310a is greater than the height of the contact pad 200a.
  • the "height" here refers to the vertical distance from the surface of the structure (for example, the contact pad 200a) away from the base substrate to the base substrate.
  • the increase in the height of the first insulating layer 310a that is, the increase in the thickness of the first insulating layer 310a, can increase the structural strength of the gap portion between the contact pads in different rows of the display substrate, thereby further preventing the display substrate from being located in different rows. The part of the gap between the contact pads is broken during the bonding process.
  • the first insulating layer may not only be located in the gap between the contact pads, as shown in FIG. 1A, except for the area where the contact pads are located and the gap between the contact pads, the first insulating layer An insulating layer may also be provided to cover other areas of the bonding area, and may further cover other areas of the peripheral area. In this way, in the plane direction determined by XY, each contact pad can be surrounded by the first insulating layer.
  • the bonding area of the display substrate is uniformly stressed, which not only prevents breakage in the gap between the contact pads , It can also prevent other areas of the bonding area from breaking due to uneven forces.
  • the display substrate, its preparation method, and the display device in at least one embodiment of the present disclosure will be described below.
  • multiple data leads located in the bonding area may correspond to multiple contact pads one-to-one, and one end of each data lead is connected to its corresponding contact pad, and the other end The portion extends to the display area, so as to be electrically connected to the corresponding signal line in the display area.
  • the elements in the display area can be connected to the control chip via a flexible circuit board and other signals.
  • the layer where the lead is located is located between the layer where the contact pad is located and the base substrate.
  • the end of the lead that is electrically connected to the contact pad and the contact pad are electrically connected to each other.
  • the pads overlap in a direction perpendicular to the base substrate and are located between the contact pads and the base substrate.
  • the data leads connected to the contact pads of the row far from the display area are located between the contact pads of the row close to the display area. gap. In this way, when the leads in the bonding area are all in the same layer, it is possible to prevent the leads connected to the contact pads in different rows from contacting each other.
  • the part of the data lead 400a connected to the contact pad 200a located in the first row L1 and located in the second row L2 is routed on the contact pad of the second row L2 In the gap 200a and covered by the first insulating layer 310a, that is, the data lead 400a connected to the contact pad 200a of the first row L1 far away from the display area passes through the gap of the contact pad 200a of the second row L2 close to the display area. Then, it extends to the display area to be electrically connected to the signal line in the display area.
  • the data leads and the signal lines are formed in different layers, for example, the two are electrically connected in a one-to-one correspondence through one or more vias in the insulating layer sandwiched between the two;
  • the data leads and the signal lines are formed in the same layer, for example, so as to be directly electrically connected.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a second insulating layer located between the contact pad and the data lead, wherein the second insulating layer is provided with a via hole, and each data lead passes through the via hole and corresponds to the second insulating layer.
  • the contact pads are connected.
  • the second insulating layer 320a is located between the contact pad 200a and the data lead 400a, and the second insulating layer 320a covers the data lead 400a.
  • the contact pad 200a is electrically connected to the data lead 400a through one or more via holes 321a provided in the second insulating layer 320a.
  • the second row L2 since the second insulating layer 320a covers the data leads 400a connected to the contact pads of the first row L1, when the contact pads 200a are formed, only the gap between the contact pads 200a needs to be considered such that The contact pads 200a may be spaced apart from each other. In this case, the contact pads may have a larger design area.
  • the data lead 400a located between the two contact pads 200a may partially overlap the contact pad 200a of the second row L2.
  • the first insulating layer, contact pads, second insulating layer, and data leads in the bonding area may be formed together with the corresponding structure layer of the display area, thereby reducing the manufacturing process of the display substrate. Process.
  • the data leads and the contact pads when the data leads and the contact pads are located in different layers, the data leads and the contact pads may be respectively configured to be arranged in the same layer as the different conductive layers of the display area.
  • the display substrate of the above embodiment further includes a pixel structure for sub-pixels located in the display area.
  • the pixel structure includes a pixel drive circuit, a planarization layer, and a light-emitting element.
  • the planarization layer is on the side of the pixel drive circuit away from the base substrate to provide a planarized surface and includes a first via hole.
  • the light-emitting element is on the planarized surface and passes through The first via hole is electrically connected to the pixel driving circuit, and the first insulating layer and the planarization layer are provided in the same layer.
  • the pixel driving circuit includes a thin film transistor, the thin film transistor includes an active layer, a gate insulating layer, a gate, an interlayer dielectric layer, a source and a drain, etc.; the pixel driving circuit may also include a storage capacitor, and the storage capacitor includes two Capacitor electrodes facing each other.
  • the display substrate includes a thin film transistor 500 and an interlayer dielectric layer 600 of sub-pixels located in the display area 101.
  • the thin film transistor 500 may be a driving transistor or a light emission control transistor in a pixel circuit, and it may include a gate 510, a gate insulating layer 520, an active layer 530, and a source/drain electrode layer 540 sequentially located on the base substrate 100a.
  • the source-drain electrode layer 540 includes the source and drain of the transistor, and one of the source and the drain is electrically connected to the light-emitting element.
  • the interlayer dielectric layer 600 is located between the active layer 530 and the source/drain electrode layer 540.
  • the data lead 400a and the gate electrode 510 are arranged in the same layer.
  • this embodiment is not limited to the thin film transistor 500 being a driving transistor or a light-emitting control transistor in a pixel circuit, and may also be other transistors on the display substrate, such as a transistor for realizing the compensation function of the pixel circuit.
  • “same-layer arrangement” means that two structures (for example, the data lead 400a and the gate electrode 510) are formed of the same layer and the same material, that is, the two structures are formed of the same material layer, for example, It is formed by the same material layer through a patterning process.
  • the first conductive layer includes the source and drain electrode layers of the thin film transistor, for example, further includes a data line; the second conductive layer includes the gate of the thin film transistor, for example, further includes a gate line.
  • the contact pad 200a and the source and drain electrode layers 540 are configured in the same layer, and the second insulating layer 320a and the interlayer dielectric layer 600 are configured in the same layer.
  • an insulating material layer is deposited, and the insulating material layer may be deposited in the bonding area at the same time to form a layer such as 1B
  • the second insulating layer 320a is shown.
  • the display area is provided with a planarization layer to planarize the surface of the display substrate, and the first insulating layer may be configured to be provided in the same layer as the planarization layer.
  • an insulating material for example, the first material layer in the following embodiments
  • the surface of the display substrate is planarized, and the insulating material is formed as a planarization layer 700 in a portion of the display area 101, and a portion located in the bonding area 102 is formed as a first insulating layer 310a.
  • the data lead of the bonding area may be a data lead for a gate line, a data line, or other types of signal lines, for example, the data lead is electrically connected to the data lead.
  • the thin film transistor in the display substrate may be a bottom-gate thin film transistor as shown in FIG. 2, or may be configured as a top-gate thin film transistor, a double-gate thin film transistor, or other types of thin film transistors.
  • Thin film transistors for example, in the case where the thin film transistor 500 shown in FIG. 2 is a bottom-gate thin film transistor, the second insulating layer 320a and the gate insulating layer 520 can also be arranged in the same layer. Accordingly, or The insulating layer of the same layer as the interlayer dielectric layer 600 is not provided.
  • the thickness of the contact pads, leads, and the second insulating layer is not limited, and can be designed according to specific processes.
  • the thickness of the first insulating layer can be determined according to the thickness of the contact pads, the data leads, and the second insulating layer.
  • the thickness is designed.
  • the thickness of the data lead 400a can be 2000 angstroms to 3000 angstroms, such as 2300 angstroms, 2500 angstroms, 2700 angstroms, etc.
  • the thickness of the second insulating layer 320a can be 4000 angstroms to 3000 angstroms.
  • the thickness of the contact pad 200a can be 6000 angstroms to 7000 angstroms, such as 6300 angstroms, 6500 angstroms, 6700 angstroms, etc. It should be noted that in the embodiments of the present disclosure, the "thickness" may be the distance from the surface of the structure (for example, the contact pad) facing away from the base substrate to the surface facing the base substrate.
  • the display area 101 of the display substrate is provided with a light emitting structure layer 800 located on the side of the planarization layer 700 away from the base substrate 100.
  • the light-emitting structure layer 800 may include a plurality of light-emitting elements corresponding to a plurality of sub-pixels arranged in an array.
  • Each light-emitting element is, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), and may include a first electrode and a second electrode. Two electrodes and a light-emitting layer located between the first electrode and the second electrode.
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • a via 701 may be provided in the planarization layer 700, and one of the first electrode and the second electrode is connected to the first conductive layer (for example, the drain of the thin film transistor) in the pixel structure through the via 701.
  • the first electrode is an anode and the second electrode is a cathode.
  • the light-emitting layer may include small molecular organic materials or polymer molecular organic materials, which may be fluorescent light-emitting materials or phosphorescent light-emitting materials, which can emit red light, green light, blue light, or white light; and, light-emitting as required
  • the layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer may include quantum dot materials, for example, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, selenium Lead fluoride quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the display substrate further includes an encapsulation layer 900 covering the light emitting structure layer 800.
  • the encapsulation layer 900 may extend to the bonding area, and the encapsulation layer 900 does not cover the contact pad 200a. .
  • the encapsulation layer 900 may be a single-layer structure or a composite structure of at least two layers.
  • the material of the encapsulation layer may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • the encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer that are sequentially disposed on the light emitting structure layer.
  • the materials of the first inorganic encapsulation layer and the second inorganic encapsulation layer may include inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc.
  • the inorganic materials have high density and can prevent the intrusion of water, oxygen, etc.; for example,
  • the material of the organic encapsulation layer can be a polymer material containing a desiccant or a polymer material that can block water vapor, such as polymer resin to planarize the surface of the display substrate, and can relieve the first inorganic encapsulation layer and
  • the stress of the second inorganic encapsulation layer may also include water-absorbing materials such as desiccant to absorb substances such as water and oxygen that have penetrated into the interior.
  • At least one embodiment of the present disclosure provides a display device, which may include the display substrate of any one of the above-mentioned embodiments.
  • the display device includes a flexible circuit board 910 on which a control chip 920 is disposed, and the flexible circuit board 910 is electrically connected to the contact pad 200a.
  • control chip may be a central processing unit, a digital signal processor, a system chip (SoC), and so on.
  • the control chip may also include a memory, and may also include a power supply module, etc., and the functions of power supply and signal input and output are realized through separately provided wires, signal lines, and the like.
  • the control chip may also include hardware circuits and computer executable codes.
  • Hardware circuits can include conventional very large-scale integration (VLSI) circuits or gate arrays, and existing semiconductors such as logic chips, transistors, or other discrete components; hardware circuits can also include field programmable gate arrays, programmable array logic, Programmable logic equipment, etc.
  • VLSI very large-scale integration
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display substrate includes a base substrate, and the base substrate includes a display area 1101 and at least Partly surrounding the peripheral area 1103 of the display area 1101, the peripheral area 1103 further includes at least one bonding area 1102 located on at least one side of the display area 1101 (for example, four bonding areas are shown in the figure), and a plurality of contact pads 1200 It is located in each bonding area 1102 and has a gap with each other, that is, the contact pads 1200 are spaced apart from each other by a certain distance.
  • the display area 1101 includes a plurality of sub-pixels extending in the first direction (X-axis direction in the figure) signal lines 11011 (for example, gate line G) and signal lines extending in the second direction (Y-axis direction in the figure).
  • Line 11012 (for example, data line D.
  • the display substrate includes a plurality of data leads 1400 located in the bonding area 1102. These signal lines extend or route to the bonding area located on at least one side of the display area 1101, for example, the signal lines 11012 and Corresponding data leads are electrically connected, so that they can be electrically connected to the driving chip, flexible circuit board, etc. in the bonding area.
  • the wiring of the signal lines in the display area around the display substrate becomes more and more dense. Therefore, in this embodiment, in order to avoid mutual interference or short circuit between adjacent leads in the peripheral area of the display substrate, the peripheral of the display area can be used for adjacent leads of the same type (such as data leads).
  • the traces are arranged on different conductive layers.
  • the display substrate includes a plurality of leads that are electrically connected to a plurality of contact pads in a one-to-one correspondence, and one end of each of the plurality of leads is electrically connected to a corresponding one of the plurality of contact pads, and the other end The portion extends toward the display area so as to be electrically connected to the corresponding signal line in the display area.
  • These leads and the corresponding signal lines may be located on the same layer to be directly electrically connected, or located on different layers, so as to be electrically connected in a one-to-one correspondence through one or more vias in the insulating layer sandwiched between the two.
  • the plurality of contact pads are arranged in at least two rows, and at least part of the first insulating layer is located in the gap between the plurality of contact pads in one row, or at least part of the contact pads are located in different rows.
  • the gap therebetween, or the gap between multiple contact pads in a row at least partially at the same time, and the gap between contact pads in different rows.
  • the display substrate further includes a plurality of insulating layers, which are respectively located between different conductive layers in a direction perpendicular to the base substrate, so as to separate the conductive layers from each other.
  • the contact pads 1200 are arranged in two rows, that is, the first The second set of contact pads 1200 in row L3 and the first set of contact pads 1200' in second row L4.
  • a first insulating layer 1310 is provided at the gap between 1200 and the first group of contact pads 1200' of the second row L4, or at all types of gaps mentioned above.
  • the gap between the contact pads in different rows is usually larger than the gap between the contact pads in the same row.
  • the display substrate is located The part at the gap between the contact pads of different rows is more likely to be broken during the bonding process.
  • the provision of the first insulating layer 1310 makes the part located in the gap between the contact pads of different rows less likely to be broken during the bonding process, which improves the yield and reduces the cost.
  • the multiple data leads include a first set of data leads and a second set of data leads.
  • the first set of data leads are electrically connected to the first set of contact pads in a one-to-one correspondence
  • the second set of data leads are electrically connected to the second set of contact pads in a one-to-one correspondence.
  • the first group of data leads and the second group of data leads are located on different layers.
  • FIG. 5C is a cross-sectional view of the display substrate shown in FIG. 5A along the line M3-N3.
  • the contact pads 1201, 1203 located in the second row L4 and the contact pads 1202, 1204 located in the first row L3 in FIG. 5B are located in the same layer.
  • the first group of data leads electrically connected to the first group of contact pads and the second group of data leads electrically connected to the second group of contact pads are located on different layers.
  • the plurality of data leads 1400 includes a first group of data leads 1401 and a second group of data leads 1402.
  • the first set of data leads 1401 is disposed between the first gate insulating layer 1322 (ie, the first gate insulating layer in the bonding region) and the second gate insulating layer 1323 (ie, the second gate insulating layer of the bonding region).
  • the group data lead 1401 is electrically connected to the contact pad 1201 at the end of the bonding region through one or more vias passing through the second gate insulating layer 1323 and the interlayer insulating layer 1324 (the interlayer gate insulating layer of the bonding region).
  • the second set of data leads 1402 are arranged between the second gate insulating layer 1323 and the interlayer insulating layer 1324.
  • the second set of data leads 1402 pass through one or more of the interlayer insulating layer 1324 at the end of the bonding region and the contact pad 1202. Electrical connection via vias.
  • a buffer layer 1321 is provided between the first gate insulating layer 1322 and the base substrate 1100.
  • the first group of data leads 1401 and the second group of data leads 1402 are arranged in different layers, so that the spacing between adjacent leads in the same layer can be made larger, and This reduces or avoids the interference between the leads on the same layer when the leads are arranged.
  • FIG. 5D is a cross-sectional view of the display substrate shown in FIG. 5B(1) along the line M4-N4 on the second row L4.
  • the contact pad 1201 and the contact pad 1203 in the second row L4 in FIG. 5B(1) are located in the same layer.
  • the contact pad 1201 and the contact pad 1203 on the second row L4 are electrically connected to two of the first group of data leads 1401, respectively.
  • one end of the second group of data leads 1402 located on a different layer from the first group of data leads 1401 extends from the gap between the contact pad 1201 and the contact pad 1203 of the second row L4 close to the display area 1101 to the display area.
  • the other end of the second group of data leads 1402 is electrically connected to the second group of contact pads 1200 through one or more vias passing through the interlayer insulating layer 1324. Therefore, the above arrangement can avoid mutual interference or short circuit between adjacent leads.
  • FIG. 5E is a cross-sectional view of the display substrate shown in FIG. 5B(1) along the first row L3 of the line M5-N5.
  • the contact pad 1202 and the contact pad 1204 in the first row L3 in FIG. 5B(1) are located in the same layer.
  • the contact pad 1202 and the contact pad 1204 on the first row L3 are electrically connected to the two second set of data leads 1402, respectively.
  • the first group of data leads 1401 are not arranged on the second row L3, so that the contact pads have a larger arrangement space.
  • the height of the first insulating layer 1310 is greater than the height of the contact pad 1200, so that the surface of the first insulating layer 1310 is higher than the surface of the contact pad 1200.
  • the “height” here also refers to the distance from the surface of the structure (for example, the contact pad 1200) away from the base substrate to the base substrate.
  • the increase in the height of the first insulating layer 1310 that is, the increase in the thickness of the first insulating layer 1310, can increase the structural strength of the gap portion between the contact pads in different rows of the display substrate, thereby further reducing the gap between the contact pads Part of the risk of fracture during the bonding process.
  • the first insulating layer 1310 covers the edge of the contact pad 1200 and is configured to expose the surface of the contact pad facing away from the base substrate. As shown in FIGS. 5C-5E, in the bonding area, the first insulating layer 1310 has a plurality of openings corresponding to the plurality of contact pads one-to-one, that is, each opening exposes a surface of a contact pad facing away from the base substrate.
  • the opening has a side wall surrounding the corresponding contact pad, and the side wall at least partly or completely has a slope angle X1 that is an acute angle with respect to the base substrate, and the slope angle X1 ranges from about 40 degrees to 60 degrees, for example Alternatively, the value range of the slope angle X1 may be selected to be 45 degrees to 55 degrees, or the value of the slope angle X1 may be selected to be about 50 degrees.
  • “about” means that the range of the numerical value can be varied within ⁇ 5% of the given numerical value.
  • the slope angle X1 can make the first insulating layer 1310 have an appropriate thickness to provide sufficient structural strength, and can also reduce the step difference between the surface of the contact pad and the surface of the first insulating layer 1310, so that during the bonding process, The anisotropic conductive adhesive can more easily enter the opening and contact the contact pad, which improves the process yield.
  • the first insulating layer 1310 covers the edge of the contact pad 1200 and is configured to expose the surface of the contact pad facing away from the base substrate.
  • the first insulating layer 1310 has a plurality of openings corresponding to the plurality of contact pads one-to-one, that is, each opening exposes a surface of a contact pad facing away from the base substrate.
  • the surface of the first insulating layer 1310 has a recessed portion C.
  • the recessed portion prevents the anisotropic conductive adhesive from flowing in the bonding process, thereby improving the yield of the bonding process.
  • the arrangement of the contact pads 1200 can also be arranged in a row, so that there will be no gaps between the contact pads located in different rows, and only the contact pads located in the same row need to be considered.
  • the problem of the gap is not limited to the number of rows of contact pads in the bonding area.
  • At least one data lead in the first set of data leads extends obliquely with respect to the edge of the display substrate, or at least one data lead in the second set of data leads extends obliquely with respect to the edge of the display substrate.
  • At least two data leads in the first group of data leads extend obliquely with respect to the edge of the display substrate, and at least two data leads in the first group of data leads have the same rotation direction with respect to the edge of the display substrate
  • at least two data leads in the second set of data leads extend obliquely with respect to the edge of the display substrate, and at least two data leads in the second set of data leads extend with respect to the edge of the display substrate.
  • the included angles of the edges of the display substrate in the same rotation direction are the same or complementary.
  • the angle between the lead (ie, the extending direction of the lead) and the edge of the display substrate is the angle at which the lead rotates clockwise to coincide with the edge of the display substrate.
  • the same direction of rotation refers to the clockwise direction.
  • the first group of data leads 1401 in the bonding area extends obliquely with respect to the edge of the display substrate, and the first group of data leads 1401 is between the edge of the display substrate.
  • the included angle of is the angle at which the first group of data leads 1401 rotate in the clockwise direction S (shown in FIG. 5B (2)) to coincide with the edge of the display substrate.
  • the first set of data leads 1401 on the left side of the figure all have a first lead angle ⁇ 1, and the first set of data leads 1401 on the right side of the figure all have a second lead angle ⁇ 2.
  • the first lead wire included angle ⁇ 1 and the second lead wire included angle ⁇ 2 are complementary to each other (that is, the sum of each other is 180 degrees).
  • the second set of data leads 1402 in the bonding area extends obliquely with respect to the edge of the display substrate, and the second set of data leads 1402 on the left side of the figure all have a third lead angle ⁇ 1, and the second set of data leads 1402 on the right side of the figure has a third lead angle ⁇ 1.
  • Both sets of data leads 1402 have a fourth lead angle ⁇ 2.
  • the third lead angle ⁇ 1 and the fourth lead angle ⁇ 2 are complementary to each other (that is, the sum of each other is 180 degrees).
  • At least one contact pad of the first set of contact pads extends obliquely with respect to the edge of the display substrate, or at least one contact pad of the second set of contact pads extends obliquely with respect to the edge of the display substrate.
  • At least two contact pads of the first group of contact pads extend obliquely with respect to the edge of the display substrate, and at least two contact pads of the first group of contact pads have the same rotation angle with respect to the edge of the display substrate.
  • at least two contact pads of the second set of contact pads extend obliquely with respect to the edge of the display substrate, and at least two contact pads in the second set of contact pads are rotated with respect to the edge of the display substrate.
  • the angles of the two directions are the same or complementary.
  • the first contact pads in the L4 row of the bonding area extend obliquely with respect to the edge of the display substrate, and the first set of contacts on the left side of the figure are all There is a first contact pad included angle A1, and the first group of contact pads on the right side of the figure all have a second contact pad included angle A2.
  • the included angle A1 of the first contact pad and the included angle A2 of the second contact pad are complementary to each other (that is, the sum of each other is 180 degrees).
  • the second set of contact pads in the L3 row of the bonding area extend obliquely with respect to the edge of the display substrate, and the second set of contact pads on the left side of the figure all have the third contact pad angle B1, the right side of the figure
  • the second group of contact pads all have a fourth contact pad angle B2.
  • the included angle B1 of the third contact pad and the included angle B2 of the fourth contact pad are complementary to each other (that is, the sum of each other is 180 degrees).
  • the first lead angle ⁇ 1 is equal to the first contact pad angle A1; the third lead lead angle ⁇ 1 is equal to the third contact pad angle B1.
  • At least one of the plurality of contact pads has a length Y1, and the value range of the length Y1 is about 650 micrometers to 750 micrometers.
  • the value range of the length Y1 can be selected to be about 680 micrometers.
  • the value of length Y1 can be selected to be about 700 micrometers.
  • At least one of the plurality of contact pads further has a width Z1, and the value range of the width Z1 is about 34 micrometers to 42 micrometers.
  • the value range of the width Z1 can be selected from about 36 micrometers to 40 micrometers, or the value of the width Z1 You can choose to be about 38 microns. It should be noted that the word "about" indicates that the value range can be varied within ⁇ 5% of the given value.
  • the material of the buffer layer 1321 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the first gate insulating layer 1322, the second gate insulating layer 1323 may include insulating materials such as silicon oxide and silicon nitride.
  • the interlayer insulating layer 1324 may include insulating materials such as silicon oxide and silicon nitride.
  • the buffer layer, the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, the first set of data leads, and the second set of data leads in the bonding region may be connected to each other.
  • the corresponding structural layers of the display area are formed together, thereby reducing the flow of the manufacturing process of the display substrate.
  • the first insulating layer 1310 of the display substrate continues to extend from the bonding area 1200 to the surroundings, so that the area covered by the first insulating layer 1310 is larger than the bonding area, for example, the first insulating layer 1310 Covering part or all of the area except the bonding area, as shown in FIG. 5A, the first insulating layer 1310 covers the peripheral area 1103 surrounding the bonding area.
  • the length D represents the distance that the peripheral area 1103 of the first insulating layer 1310 extends on one side relative to the bonding area 1200.
  • the length D may be about 40 microns to 60 microns, such as 50 microns.
  • the bonding area is located in the coverage area of the first insulating layer 1310, so as to reduce the risk of fracture and cracks in the bonding area during the bonding process.
  • the pixel array of the display area 1101 of the display substrate includes a plurality of sub-pixels 1110.
  • Each sub-pixel may include a pixel circuit, a planarization layer, and a light-emitting element.
  • the pixel circuit includes a plurality of thin film transistors and storage capacitors.
  • the flattening layer is located on the side of the thin film transistor away from the base substrate to cover the thin film transistor and the storage capacitor.
  • the light emitting element is located on the side of the flattening layer away from the base substrate.
  • the flattening layer includes the first flat layer via hole.
  • the thin film transistor includes The active layer on the substrate, the gate located on the side of the active layer away from the base substrate, and the source and drain located on the side of the gate away from the base substrate, and one of the source and drain passes through
  • the first planarization layer via hole is electrically connected to the light-emitting element; the first insulating layer and the planarization layer are arranged in the same layer.
  • the light-emitting element may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • the type of the pixel circuit is as described above, and will not be repeated here, and the embodiment of the present disclosure does not limit this.
  • part of the structure of the display area is formed in the same layer and the same material as the bonding area, thereby reducing the manufacturing process flow.
  • the buffer layer 1321 of the display area 1101 is disposed on the base substrate 1100 to provide a flat surface for forming pixel circuits.
  • the buffer layer 1321 of the display area of the display area and the buffer layer 1321 of the bonding area are arranged in the same layer.
  • a barrier layer may be provided between the buffer layer 1321 and the base substrate 1100.
  • the material of the buffer layer 1321 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the semiconductor layer 121 of the display area 1101 is disposed on the buffer layer 1321 of the display area.
  • the semiconductor layer 121 may include polysilicon or an oxide semiconductor, and the semiconductor layer 121 including an oxide semiconductor may be covered by a separate passivation layer (not shown).
  • the semiconductor layer 121 includes a channel region that is not doped with impurities, and a source region and a drain region located at opposite sides of the channel region and doped with impurities (N-type impurities or P-type impurities).
  • the first gate insulating layer 1322 of the display area 1101 (ie, the first gate insulating layer of the display area) is disposed on the semiconductor layer 121.
  • the first gate insulating layer 1322 in the display area and the first gate insulating layer 1322 in the bonding area are arranged in the same layer.
  • the gate 1510 and the first capacitor electrode 1601 are disposed on the first gate insulating layer 1322.
  • the gate 1510 overlaps the channel region of the semiconductor layer 121.
  • the gate electrode 1510 and the first capacitor electrode 1601 are made of the same material.
  • the gate electrode 1510, the first capacitor electrode 1601 and the first group of data leads 1401 are arranged in the same conductive layer, which may be referred to as a second conductive layer.
  • the second gate insulating layer 1323 of the display area 1101 may be disposed on the gate 1510 and the first capacitor electrode 1601, and the second capacitor electrode 1602 is disposed on the second gate insulating layer 1323.
  • the second capacitor electrode 1602 overlaps the first capacitor electrode 1601 and at least partially overlaps in the direction perpendicular to the base substrate 1100.
  • the first capacitor electrode 1601 and the second capacitor electrode 1602 use the second gate insulating layer 1323 as a dielectric material To form a storage capacitor.
  • the second gate insulating layer 1323 in the display area and the second gate insulating layer 1323 in the bonding area are arranged in the same layer.
  • the second capacitor electrode 1602 and the second group of data leads 1402 of the bonding area are arranged in the same conductive layer, and for example, are arranged in the same layer as the gates of other transistors on the display substrate except the transistor shown in FIG. 6, For another example, it is provided in the same layer as the power line that supplies the power supply voltage to the pixel circuit, and this conductive layer may be referred to as the second gate conductive layer.
  • the first capacitance electrode of the storage capacitor is still arranged in the same layer as the gate 1510, and the second capacitance electrode of the storage capacitor is the same as the source 1541 and the drain 1541 of the thin film transistor. 1542 is set on the same floor.
  • the second group of data leads 1402 are no longer arranged in the same layer as the second capacitor electrode.
  • the first capacitance electrode of the storage capacitor is no longer provided in the same layer as the gate 1510, but is located between the second gate insulating layer 1323 and the interlayer insulating layer 1324 (ie , The interlayer insulating layer in the display area), and the second capacitor electrode of the storage capacitor is arranged in the same layer as the drain electrode 1541 and the source electrode 1542 of the thin film transistor.
  • the second group of data leads 1402 are no longer arranged in the same layer as the second capacitor electrode, but are arranged in the same layer as the first capacitor electrode.
  • the material of the gate may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the multi-layer structure is a multi-metal laminated layer (such as Titanium, aluminum and titanium three-layer metal stack (Ti/Al/Ti)).
  • the materials of the first capacitor electrode and the second capacitor electrode may include one or more of gold, silver, copper, nickel, platinum, aluminum, and molybdenum.
  • the interlayer insulating layer 1324 of the display area 1101 can be disposed on the second capacitor electrode 1602, and the source and drain electrode layer 1540 is disposed on the interlayer insulating layer 1324.
  • the source and drain electrode layer 1540 of the thin film transistor includes a drain electrode 1541 and a source electrode 1542.
  • the interlayer insulating layer 1324 in the display area and the interlayer insulating layer 1324 in the bonding area are arranged in the same layer.
  • the drain electrode 1541 and the source electrode 1542 may include a single metal layer or multiple layers formed of molybdenum, aluminum, titanium, and the like.
  • the drain 1541 and the source 1542 are arranged in the same layer as the contact pads of the bonding region.
  • the thin film transistor in the display substrate can be a top gate thin film transistor as shown in FIG. 6, but it can also be set as a bottom gate thin film transistor, a double gate thin film transistor or other types of thin film transistors. The example does not limit this.
  • the first insulating layer 1310 of the display area 1101 covers the thin film transistor and an OLED is formed thereon, and the first insulating layer 1310 of the display area 1101 serves as a planarization layer 1310.
  • the first insulating layer 1310 may include an organic insulating material or an inorganic insulating material, or may be formed of a combination of an organic insulating material and an inorganic insulating material.
  • the first insulating layer 1310 in the display area and the first insulating layer 1310 in the bonding area are formed in the same layer.
  • the OLED as a light-emitting element in the sub-pixels of the display area 1101 includes a pixel electrode 127, a light-emitting layer 128 and a common electrode 129.
  • the pixel electrode 127 is separately formed in each sub-pixel on the first insulating layer 1310 as a planarization layer, and is connected to the drain electrode 1542 of the thin film transistor through a via 1271 formed on the first insulating layer 1310.
  • the pixel defining layer (or partition wall) 113 is provided on the first insulating layer 1310 and on the edge of the pixel electrode 127.
  • the light emitting layer 128 is disposed on the pixel electrode 127, and the common electrode 129 is disposed on the entire display area.
  • the pixel electrode 127 may include a reflective layer, and the common electrode 129 may include a transparent layer or a semi-transparent layer.
  • the light emitted from the light emitting layer 128 is reflected by the pixel electrode 127, and passes through the common electrode 129 to be emitted into the external environment to realize a display function.
  • the common electrode 129 includes a semi-transmissive layer, some light reflected by the pixel electrode 127 is reflected again through the common electrode 129, so the pixel electrode 127 and the common electrode 129 form a resonance structure, so that light extraction efficiency can be improved.
  • the material of the pixel electrode 127 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • the pixel electrode 127 may include a metal having high reflectivity as a reflective layer, such as silver (Ag).
  • the light-emitting layer 128 may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, may emit red, green, blue, or white light; and, as required
  • the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer may include quantum dot materials, for example, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, selenium Lead fluoride quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the common electrode 129 may include various conductive materials.
  • the common electrode 129 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the material of the pixel defining layer 113 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • the insulating material is not limited in the embodiment of the present disclosure.
  • the display substrate may further include an encapsulation layer 190, which covers the light-emitting element and the pixel circuit.
  • the encapsulation layer 190 seals the OLED, so that deterioration of the OLED caused by moisture and/or oxygen included in the environment may be reduced or prevented.
  • the encapsulation layer 190 may include a structure in which an inorganic layer and an organic layer are stacked.
  • the encapsulation layer 190 may include a first inorganic layer 191, an organic layer 192, and a second inorganic layer 193.
  • the encapsulation layer 190 may extend to the bonding area, but the encapsulation layer does not cover the contact pads.
  • the material of the encapsulation layer may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water and oxygen;
  • the material of the organic encapsulation layer can be a polymer material containing a desiccant or a polymer material that can block water vapor, etc.
  • polymer resins are used to flatten the surface of the display substrate, and can relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and can also include water-absorbing materials such as desiccant to absorb water intruding into the interior, Oxygen and other substances.
  • “same layer arrangement” means that two structures (for example, the contact pad 1200 and the source and drain electrode layer 1540) are formed of the same layer and the same material, that is, the two structures are formed of the same material layer, for example It can be formed from the same material layer through a patterning process.
  • At least one embodiment of the present disclosure further provides a display device, which may include the display substrate of any one of the embodiments shown in Figs. 5A to 5E and Fig. 6 above.
  • the display device includes a flexible circuit board on which a control chip is arranged, and the flexible circuit board is electrically connected to the contact pad 1200.
  • control chip may be a central processing unit, a digital signal processor, a system chip (SoC), and so on.
  • the control chip may also include a memory, and may also include a power supply module, etc., and the functions of power supply and signal input and output are realized through separately provided wires, signal lines, and the like.
  • the control chip may also include hardware circuits and computer executable codes.
  • Hardware circuits can include conventional very large-scale integration (VLSI) circuits or gate arrays, and existing semiconductors such as logic chips, transistors, or other discrete components; hardware circuits can also include field programmable gate arrays, programmable array logic, Programmable logic equipment, etc.
  • VLSI very large-scale integration
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate, including: providing a base substrate, wherein the base substrate includes a display area and a bonding area located on at least one side of the display area; A plurality of sub-pixels and a plurality of data lines are formed in the display area, wherein the plurality of data lines are configured to provide data signals for the plurality of sub-pixels; a plurality of data leads are formed in the bonding area; At least one set of contact pads is formed in the region, wherein the at least one set of contact pads includes a first set of contact pads and a second set of contact pads, and the first set of contact pads and the second set of contact pads respectively include a plurality of Contact pads, the second set of contact pads are located on a side of the first set of contact pads away from the display area, and the plurality of data leads are the same as the first set of contact pads and the second set of contact pads A corresponding electrical connection; forming a first insulating layer in the bonding area, wherein the
  • the first insulating layer is formed such that the vertical distance between the surface of the first insulating layer on the side away from the base substrate and the base substrate is not less than the vertical distance from the base substrate.
  • forming the first insulating layer in the bonding region includes: after forming the plurality of contact pads, depositing a first material layer on the base substrate to planarize the The surface of the display substrate; a patterning process is performed on the first material layer, so that a portion of the first material layer located in the display area is formed as a planarization layer, and a plurality of parts of the first material layer are removed The overlapping portion of the contact pads, and the portion of the first material layer located in the bonding area and the gap between the contact pads is thinned to form the first insulating layer.
  • the first insulating layer is formed to cover the edge of each of the plurality of contact pads, and includes a plurality of openings to respectively expose the deviation of each of the plurality of contact pads.
  • the surface of the base substrate is formed to cover the edge of each of the plurality of contact pads, and includes a plurality of openings to respectively expose the deviation of each of the plurality of contact pads.
  • the patterning process of the first material layer includes: coating photoresist on the first material layer; providing a first mask to perform the photolithography The photoresist is exposed and developed to remove the part of the photoresist that overlaps with the contact pads; the remaining photoresist is used as a mask to pattern the first material layer to remove the first material The portion of the layer overlapping the plurality of contact pads; removing the remaining photoresist in the bonding region; and in the bonding region, etching the first material layer located on the plurality of contact pads The gap therebetween is away from the surface portion of the base substrate, so that the remaining first material layer is formed as the first insulating layer.
  • the process of patterning the first material layer includes: coating photoresist on the first material layer; The photoresist is exposed, and the exposed photoresist is developed to remove the part of the photoresist that overlaps the plurality of contact pads and thin the photoresist and the plurality of contact pads. And in the bonding area, the first material layer is etched to remove the overlapped portion of the first material layer with the plurality of contact pads, and an ashing process is performed to Removing the portion of the photoresist that overlaps the gaps of the plurality of contact pads, and removing the thickness of the portion of the first material layer that overlaps the gaps of the plurality of contact pads away from the base substrate.
  • the first material layer includes a photosensitive resin material
  • the patterning process on the first material layer includes: using a gray tone mask or a halftone mask to apply A material layer is exposed, and the exposed photoresist is developed so that the portion of the first material layer located in the display area is formed as the planarization layer, and the AND of the first material layer is removed
  • the overlapping portion of the plurality of contact pads, and the portion of the first material layer located in the bonding area and the gap between the plurality of contact pads is thinned to form the first insulating layer.
  • each of the plurality of contact pads includes at least one metal layer
  • forming the plurality of contact pads includes: depositing a first conductive material film on the base substrate and aligning it. The patterning process is performed, wherein a portion of the first conductive material film located in the display area is formed as a first conductive layer, and a portion of the first conductive material film located in the bonding area is formed as the plurality of At least one metal layer of the contact pad, wherein at least one of the plurality of sub-pixels includes a thin film transistor, the planarization layer is located on the side of the thin film transistor away from the base substrate, and the thin film transistor includes Source and drain in a conductive layer.
  • the plurality of data leads include a first set of data leads and a second set of data leads, and the first set of data leads are electrically connected to the first set of contact pads in a one-to-one correspondence.
  • the second set of data leads are electrically connected to the second set of contact pads in a one-to-one correspondence, and relative to the base substrate, the first set of data leads and the second set of data leads are located in different layers, respectively .
  • Forming a plurality of data leads in the bonding area includes: forming a first interlayer insulating layer on the base substrate; and forming the first group on the first interlayer insulating layer in the bonding area Data leads, forming a second interlayer insulating layer on the base substrate to cover the first set of data leads, and forming the second set of data leads on the second interlayer insulating layer in the bonding region Or, forming the second set of data leads on the first interlayer insulating layer in the bonding area, and forming a second interlayer insulating layer on the base substrate to cover the second set of data leads , Forming the first set of data leads on a second interlayer insulating layer in the bonding region, wherein the plurality of contact pads and the first insulating layer are formed on the second interlayer insulating layer on.
  • forming a plurality of data leads in the bonding region further includes: forming a plurality of first contact pad via holes in the first interlayer insulating layer to make The first set of contact pads are electrically connected to the first set of data leads through the plurality of first contact pad vias in a one-to-one correspondence, and are formed to pass through the first interlayer insulating layer and the second interlayer A plurality of second contact pad vias in the insulating layer, so that the second set of contact pads are electrically connected to the second set of data leads through the plurality of second contact pad vias in a one-to-one correspondence; or, forming Pass through the plurality of second contact pad vias in the first interlayer insulating layer, so that the second set of contact pads can communicate with the second set of data by passing through the plurality of second contact pad vias
  • the leads are electrically connected in a one-to-one correspondence, forming a plurality of first contact pad vias passing through the first interlayer insulating
  • the at least one of the plurality of sub-pixels further includes a storage capacitor
  • the storage capacitor includes two capacitor electrodes
  • the thin film transistor includes a gate
  • the manufacturing method further includes : Forming the first set of data leads and the gate in the same layer, and forming the second set of data leads and one of the two capacitor electrodes of the storage capacitor in the same layer; or, forming the second set of data leads and one of the two capacitor electrodes of the storage capacitor in the same layer
  • the data leads and the gate are formed in the same layer, and the first set of data leads and one of the two capacitor electrodes of the storage capacitor are formed in the same layer.
  • the two capacitor electrodes include a first capacitor electrode and a second capacitor electrode, and the first capacitor electrode and the gate electrode are provided in the same layer, and the two capacitor electrodes are arranged in the display area.
  • the second capacitor electrode is disposed between the first interlayer insulating layer and the second interlayer insulating layer.
  • the preparation method of the display substrate of any embodiment shown in FIGS. 5A to 5E and FIG. 6 will be described in detail below.
  • the height of the first insulating layer in the bonding area is greater than the height of the bonding area, and the preparation process is shown in FIGS. 7A to 7L.
  • a base substrate 1100 is provided and an insulating material is deposited on the base substrate 1100 to form a buffer layer 1321.
  • the buffer layer covers the display area 1101 and the bonding area 1102.
  • a semiconductor material is deposited on the buffer layer of the display region to form a semiconductor layer 121, which includes a channel region not doped with impurities in the middle and a channel region located on the opposite side of the channel region and doped with impurities (N-type impurities or P-type impurities) The source and drain regions.
  • An insulating material 11 is deposited on the buffer layer of the bonding area 1102 and the display area 1101 to form a first gate insulating layer.
  • the base substrate may be a glass plate, a quartz plate, a metal plate, or a resin-based plate.
  • the material of the base substrate may include an organic material.
  • the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, and polyethylene terephthalate.
  • resin materials such as polyethylene naphthalate.
  • the base substrate may be formed of multiple material layers.
  • the base substrate may include a base, and the material of the base may be composed of the above-mentioned materials.
  • a buffer layer can be formed on the surface of the base as a transition layer, which can prevent harmful substances in the base substrate from intruding into the interior of the display substrate, and can increase the adhesion of the film layer in the display substrate on the base substrate.
  • the material of the buffer layer may be silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • a first conductive material is deposited on the first gate insulating layer 1322 of the bonding region 1102 and the display region 1101 to form a first conductive material layer 21.
  • the patterning process is performed on the first conductive material layer, the portion of the first conductive material layer 21 located in the display area forms the gate 1510 and the first capacitor electrode 1601, and the portion of the first conductive material layer 21 located in the bonding area A portion of the first group of data leads 1401 is formed.
  • the first conductive material layer 21 may be a metal or a metal alloy, or other conductive materials.
  • the first conductive material layer 21 may have a single-layer structure, or may be a laminate composed of multiple film layers, for example, a laminate composed of three metal film layers of Ti-AL-Ti.
  • the gate 1510 can be used as a mask to form a conductive source region and a drain region by doping the active layer, and the channel between the source region and the drain region The region is undoped due to the shielding effect of the gate.
  • an insulating material is deposited in the display area and the bonding area to form a second gate insulating layer 1323 covering the gate 1510 in the display area, and a second gate covering the first set of data leads 1401 is formed in the bonding area. Insulation layer 1323.
  • a second conductive material is deposited on the second gate insulating layer 1323 of the bonding region 1102 to form a second conductive material layer 22.
  • the second conductive material layer 22 may be a metal or a metal alloy, or other conductive materials.
  • the second conductive material layer 22 may have a single-layer structure, or may be a laminate composed of multiple film layers, for example, a laminate composed of three metal film layers of Ti-AL-Ti.
  • a patterning process is performed on the second conductive material layer 22, the portion of the second conductive material layer 22 located in the bonding area forms a second set of data leads 1402, and the second conductive material layer 22 located in the display area
  • the second capacitor electrode 1602 is partially formed.
  • an insulating material is deposited in the display area and the bonding area to form an interlayer insulating layer 1324 covering the second gate insulating layer 1323 in the display area, and an interlayer covering the second set of data leads 1402 is formed in the bonding area. Insulation layer 1324.
  • a patterning process is performed on the second gate insulating layer 1323 and the interlayer insulating layer 1324 that overlap the first set of data leads 1401 in the bonding area, so as to form a pattern on the second gate insulating layer 1323 and the interlayer insulating layer 1324.
  • One or more vias are formed in it.
  • the interlayer insulating layer 1324 overlapping the second group of data lines in the bonding area is patterned to form one or more via holes in the interlayer insulating layer 1324.
  • the patterning process is performed on the first gate insulating layer 1322, the second gate insulating layer 1323, and the interlayer insulating layer 1324 in the display area, so as to be in the first gate insulating layer 1322, the second gate insulating layer 1323, and the interlayer insulating layer 1324.
  • Form vias a third conductive material layer 23 is deposited in the display area and the bonding area.
  • the third conductive material layer 23 is respectively connected to the active layer 121, the first group of data leads 1401, and the second group of data leads 1402 through via holes.
  • the third conductive material layer 23 may be a metal or a metal alloy, or other conductive materials.
  • the third conductive material layer 23 may have a single-layer structure, or may be a laminate composed of multiple film layers, for example, a laminate composed of three metal film layers of Ti-AL-Ti.
  • a patterning process is performed on the third conductive material layer 23, and the portion of the third conductive material layer 23 in the display area is formed as a drain electrode 1541 and a source electrode 1542.
  • the portion of the third conductive material layer 23 located in the bonding area forms a contact pad 1200.
  • a first insulating material layer 1710 is deposited on the display area and the bonding area to planarize the surface of the display substrate, that is, the first insulating material layer 1710 covers the thin film transistor and covers the contact pad 1200, and the first insulating material layer 1710 covers the thin film transistor and covers the contact pad 1200.
  • the surface of the material layer 1710 facing away from the base substrate 1100 is a plane.
  • the preparation material of the first insulating material layer may include organic materials such as polymer resins, for example, may include polyimide, polyacrylate, polyacrylate polyurethane, polyurea, polyarylester or others.
  • a photoresist 1040 is covered on the first insulating material layer 1710.
  • a third mask 1042 is provided to expose the photoresist 1040.
  • the third mask 1042 includes a first light-transmitting pattern 1421 overlapping the contact pad 1201 and the contact pad 1202 and a second light-transmitting pattern 1422 overlapping the gap between the contact pad 1201 and the contact pad 1202.
  • the third mask 1042 includes a first light-transmitting pattern 1421 and a non-light-transmitting pattern 1423 that overlap the via holes of the planarization layer. That is, the third mask 1042 is a gray tone mask or a half tone mask.
  • the photoresist is a positive photoresist.
  • the light transmittance of the first light-transmitting pattern 1421 is greater than the light transmittance of the second light-transmitting pattern 1422.
  • the part of the photoresist 1040 corresponding to the first light-transmitting pattern 1421 is completely exposed in the exposure process, the part of the photoresist 1040 corresponding to the second light-transmitting pattern 1422 is partially exposed. The portion of 1040 corresponding to the non-light-transmitting pattern 1423 is not exposed.
  • the photoresist 1040 is developed, and the exposed part of the photoresist 1040 is removed, that is, in the bonding region, the photoresist 1040 overlapping the contact pad 1200 is removed, and the remaining photoresist
  • the glue 1040 is thinned, and in the display area, the photoresist overlapping with the via hole of the planarization layer is removed.
  • the photoresist 1040 is formed into a third photoresist pattern 1042.
  • the first insulating material layer 1710 is etched to remove the insulating material layer overlapped by the contact pads, and a via 1271 is formed in the display area.
  • the third photoresist pattern 1042 in the bonding area is removed, and then the remaining first insulating material layer 1710 in the bonding area is etched and the etching thickness is controlled to remove the gap with the contact pad
  • the thickness of the part of the overlapped insulating material layer away from the base substrate forms a first insulating layer 1310 whose height is greater than that of the contact pad.
  • the photoresist 1042 in the display area is removed, and the first insulating layer 1310 is formed as a planarization layer by etching and controlling the etching thickness.
  • the display substrate of the embodiment shown in FIG. 5C can be obtained.
  • an etching end point detector or the like can be used for real-time monitoring, or the etching solution concentration and/or etching time can be adjusted according to experimental data.
  • the first insulating layer can reduce or eliminate the gap between the contact pads and the contact pads.
  • the pressure head is applied to the surface of the first insulating layer and the contact pads.
  • the force distribution on the surface of the display is uniform (for example, the pressure is equal), that is, the pressure applied by the indenter at the contact pad and the gap between the contact pads is uniform, and the display substrate (the bonding area) will not be in the bonding process In the actual production, the yield rate of the display substrate is improved due to the damage due to uneven force.
  • a display substrate includes: a base substrate including a display area and a bonding area located on at least one side of the display area; a plurality of contact pads located in the bonding area with gaps between each other; a first insulating layer located in The gaps between the contact pads are configured to expose the surface of the contact pads facing away from the base substrate.
  • the surface of the first insulating layer facing away from the base substrate is higher than the surface of the contact pad facing away from the base substrate or is located on the same plane as the surface of the contact pad facing away from the base substrate.
  • the plurality of contact pads are arranged in at least one row, and the row direction is parallel to the extending direction of the side of the display area facing the bonding area, and at least part of the first insulating layer is located in a row.
  • the gap between the contact pads is located in a row.
  • the display substrate further includes a plurality of leads, wherein the plurality of leads are electrically connected to the plurality of contact pads in a one-to-one correspondence, and one end of each of the plurality of leads is connected to a corresponding one of the plurality of contact pads It is electrically connected and the other end extends toward the display area.
  • the plurality of contact pads are arranged in at least two rows, and at least part of the first insulating layer is located in gaps between the contact pads in different rows.
  • the at least two rows include a first row and a second row located between the first row and the display area, and a lead connected to the contact pad located in the first row is located in the second row.
  • the part of the row is located in the gap of the contact pad in the second row and is covered by the first insulating layer.
  • the end of the lead that is electrically connected to the contact pad overlaps the contact pad and is located between the contact pad and the base substrate.
  • the leads connected to the contact pads located in the first row include a first set of data leads and a second set of data leads that are adjacent to each other, and the first set of data leads and the second set of data leads are opposite to each other.
  • the base substrate is located in different layers.
  • the display substrate further includes a second insulating layer located between the contact pad and the lead, wherein a via hole is provided in the second insulating layer, and the lead passes through the via hole and corresponds to the contact pad. connection.
  • the display substrate further includes a thin film transistor, a light emitting element, and an interlayer dielectric layer in the sub-pixels of the display area, wherein one of the source and drain of the thin film transistor is electrically connected to the light emitting element;
  • the interlayer dielectric layer is located between the active layer and the source and drain electrode layers of the thin film transistor, and the second insulating layer and the interlayer dielectric layer are arranged in the same layer.
  • the display substrate further includes a thin film transistor, a light emitting element, and a planarization layer covering the thin film transistor in the sub-pixels of the display area, wherein one of the source electrode and the drain electrode of the thin film transistor is electrically connected to the light emitting element ;
  • the first insulating layer and the planarization layer are configured in the same layer.
  • the display device includes the display substrate as described above.
  • a method for preparing a display substrate includes: providing a base substrate, the base substrate including a display area and a bonding area located on at least one side of the display area; forming a plurality of spaced apart in the bonding area Contact pads; forming a first insulating layer in the gaps between a plurality of the contact pads, wherein the first insulating layer is formed to expose the surface of the contact pads facing away from the base substrate.
  • the first insulating layer is formed such that the surface of the first insulating layer facing away from the substrate is higher than the surface of the contact pad facing away from the base substrate or the surface of the contact pad facing away from the substrate
  • the surface of the substrate is basically on the same plane.
  • the forming the first insulating layer between the contact pads includes: after forming the contact pads, depositing a first material layer on the base substrate to planarize the surface of the display substrate; The first material layer is subjected to a patterning process so that the portion of the first material layer located in the display area is formed as a planarization layer, and the portion of the first material layer overlapping with the contact pad is removed and thinned The portion of the first material layer located in the bonding area and located in the gap between the contact pads forms the first insulating layer.
  • the patterning process of the first material layer includes: coating photoresist on the first material layer; providing a first mask to expose and develop the photoresist to remove the The portion of the photoresist that overlaps the contact pad; the remaining photoresist is used as a mask to pattern the first material layer to remove the portion of the first material layer that overlaps the contact pad; The remaining photoresist in the bonding area; and in the bonding area, the surface portion of the first material layer located in the gap of the contact pad and away from the base substrate is etched, and the remaining portion The first material layer is formed as the first insulating layer.
  • the patterning process of the first material layer includes: coating photoresist on the first material layer; exposing the photoresist by using a gray-tone mask or a half-tone mask, after exposing After developing the photoresist, to remove the part of the photoresist that overlaps the contact pad and thin the part where the gap between the photoresist and the contact pad overlaps; and in the bonding area Etch the first material layer to remove the portion of the first material layer that overlaps the contact pad, and perform an ashing process to remove the overlapped portion of the photoresist and the contact pad, And remove the part of the thickness of the first material layer that overlaps with the gap of the contact pad away from the base substrate.
  • the first material layer includes a photosensitive resin material
  • the patterning process of the first material layer further includes: exposing the first material layer using a gray tone mask or a half tone mask, and exposing the After the photoresist is developed, the portion of the first material layer located in the display area is formed as the planarization layer, and the portion of the first material layer overlapping with the contact pad is removed, and reduced A portion of the first material layer located in the bonding area and located in the gap between the contact pads is thinned to form the first insulating layer.
  • Forming the contact pad includes: depositing a first conductive material film on the base substrate and performing a patterning process on it, wherein a portion of the first conductive material film located in the display area is formed as a first conductive layer The part of the first conductive material film located in the bonding area is formed as the contact pad.
  • the preparation method further includes: before depositing the first conductive material film, forming a lead in the bonding area, wherein the first end of the lead extends to the display area, and forming the contact After the pad, the second end of the lead overlaps and connects with the contact pad.
  • Forming the leads in the bonding area includes: forming the first group of data leads and the second group of data leads in different layers with respect to the base substrate in the bonding area.
  • the preparation method further includes: after forming the lead and before depositing the first conductive material film, depositing an insulating material film on the base substrate to cover the second conductive layer and the lead; Patterning the insulating material film to form a via hole exposing the second end of the lead; and after depositing the first conductive material film, the first conductive material film passes through the via hole and The lead connection; wherein the portion of the insulating material film located in the display area is an interlayer dielectric layer, and the portion of the insulating material film located in the bonding area is a second insulating layer.

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Abstract

一种显示基板及其制备方法、显示装置。该显示基板包括衬底基板(1100)、多个子像素(1110)、多条数据线(11011)、多条数据引线(1400)、至少一组接触垫(1200)及第一绝缘层(1310)，衬底基板(1100)包括显示区(1101)和位于显示区(1101)至少一侧的邦定区(1102)；多条数据线(11011)位于所述显示区中，配置为多个子像素(1110)提供数据信号；多条数据引线(1400)位于邦定区(1102)中且与多条数据线(11011)电连接；至少一组接触垫(1200)位于邦定区中，至少一组接触垫(1200)包括第一组接触垫(1200')和第二组接触垫(1200)；第一绝缘层(1310)位于邦定区，第一绝缘层(1310)位于多个接触垫(1200)之间的间隙并覆盖多个接触垫(1200)的边缘，且被配置为露出多个接触垫(1200)的背离衬底基板(1100)的表面。

Description

显示基板及其制备方法、显示装置 技术领域
本公开至少一个实施例涉及一种显示基板及其制备方法、显示装置。
背景技术
随着社会的发展和进步，电子显示产品的应用越来越广泛，用户对电子显示产品的质量的要求也越来越高。电子显示产品中包括显示基板，在完成显示基板的制造后，需要对显示基板进行邦定(Bonding)工艺以使得显示基板与外部电路信号连接。
发明内容
本公开至少一个实施例提供一种显示基板，该显示基板包括：
衬底基板，包括显示区和位于所述显示区至少一侧的邦定区；
多个子像素，位于所述显示区中；
多条数据线，位于所述显示区中，配置为所述多个子像素提供数据信号；
多条数据引线，位于所述邦定区中且与所述多条数据线电连接；
至少一组接触垫，位于所述邦定区中，其中，所述至少一组接触垫包括第一组接触垫和第二组接触垫，所述第一组接触垫和所述第二组接触垫分别包括多个接触垫，所述第二组接触垫位于所述第一组接触垫远离所述显示区的一侧，所述多条数据引线与所述第一组接触垫和所述第二组接触垫电连接；
第一绝缘层，位于所述邦定区，所述第一绝缘层位于所述多个接触垫之间的间隙并覆盖所述多个接触垫的边缘，且被配置为露出所述多个接触垫的背离所述衬底基板的表面。
例如，在上述实施例的显示基板中，所述第一绝缘层远离所述衬底基板一侧的表面距离所述衬底基板的垂直距离不小于所述多个接触垫远离所述衬底基板一侧的表面距离所述衬底基板的垂直距离。
例如，在上述实施例的显示基板中，所述第一绝缘层的至少部分位 于所述第一组接触垫相邻的接触垫之间的间隙中。
例如，在上述实施例的显示基板中，所述第一绝缘层的至少部分位于所述第二组接触垫中相邻的接触垫之间的间隙中。
例如，在上述实施例的显示基板中，所述第一绝缘层的至少部分位于所述第一组接触垫中相邻的接触垫之间的间隙中和位于所述第二组接触垫中相邻的接触垫之间的间隙中。
例如，在上述实施例的显示基板中，所述第一组接触垫的多个接触垫排布为至少第一行，所述第二组接触垫的多个接触垫排布为至少第二行；所述第一行和所述第二行的行方向与所述显示区的面向所述邦定区的侧边的延伸方向平行，所述第一绝缘层的至少部分位于所述第一行与所述第二行之间的间隙。
例如，在上述实施例的显示基板中，所述第一绝缘层的多个开口每个具有侧壁，且所述多个开口中至少一个的侧壁具有相对于所述衬底基板的坡度角的取值范围为40度至60度。
例如，在上述实施例的显示基板中，所述多个接触垫中至少一个具有的长度的取值范围为650微米至750微米及具有的宽度的取值范围为34微米至42微米。
例如，在上述实施例的显示基板中，所述多个子像素中至少一个包括薄膜晶体管、平坦化层以及发光元件，所述平坦化层位于所述薄膜晶体管远离所述衬底基板一侧，以覆盖所述薄膜晶体管，所述发光元件位于所述平坦化层远离所述衬底基板一侧，所述平坦化层包括第一平坦层过孔，所述薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所处衬底基板一侧的栅极，以及位于所述栅极远离所述衬底基板一侧的源极和漏极，并且所述源极和所述漏极中之一通过所述第一平坦层过孔与所述发光元件电连接；所述第一绝缘层与所述平坦化层为同层设置。
例如，在上述实施例的显示基板中，相对于所述衬底基板，在所述邦定区中的所述第一绝缘层的厚度小于所述显示区域中的所述平坦化层的厚度。
例如，在上述实施例的显示基板中，所述多个接触垫每个包括至少一个金属层，所述至少一个金属层包括第一金属层，所述第一金属层与 所述源极和所述漏极同层设置。
例如，在上述实施例的显示基板中，所述多条数据引线包括第一组数据引线和第二组数据引线，所述第一组数据引线与所述第一组接触垫一一对应电连接，所述第二组数据引线与所述第二组接触垫一一对应电连接，并且相对于所述衬底基板，所述第一组数据引线和所述第二组数据引线分别位于不同层。
例如，在上述实施例的显示基板中，所述多个子像素中所述至少一个还包括存储电容，所述存储电容包括两个电容电极，所述第一组数据引线与所述栅极同层设置，且所述第二组数据引线与所述存储电容的两个电容电极之一同层设置；或者，所述第二组数据引线与所述栅极同层设置，且所述第一组数据引线与所述存储电容的两个电容电极之一同层设置。
例如，上述实施例的显示基板还可以包括：邦定区层间绝缘层，位于所述邦定区中，并且位于所述多个接触垫与所述引线之间和所述第一绝缘层与所述衬底基板之间；邦定区第一栅绝缘层，位于所述绑定区中，且位于所述邦定区层间绝缘层靠近所述衬底基板的一侧；以及邦定区第二栅绝缘层，位于所述邦定区中，且位于所述邦定区第一栅绝缘层及所述邦定区层间绝缘层之间，与所述邦定区层间绝缘层层叠；其中，所述第一组接触垫通过穿过所述邦定区层间绝缘层中的多个第一接触垫过孔与所述第一组数据引线一一对应电连接，所述第二组接触垫通过穿过所述第一邦定区层间绝缘层和所述邦定区第二栅绝缘层中的多个第二接触垫过孔与所述第二组数据引线一一对应电连接；或者，所述第二组接触垫通过穿过所述第一邦定区层间绝缘层中的多个第二接触垫过孔与所述第二组数据引线一一对应电连接，所述第一组接触垫通过穿过所述邦定区层间绝缘层和所述邦定区第二栅绝缘层中的多个第一接触垫过孔与所述第一组数据引线一一对应电连接。
例如，在上述实施例的显示基板中，所述多个子像素中所述至少一个还包括显示区层间绝缘层、显示区第一栅绝缘层以及显示区第二栅绝缘层，所述显示区层间绝缘层、显示区第一栅绝缘层和所述显示区第二栅绝缘层分别与所述邦定区层间绝缘层、邦定区第一栅绝缘层和所述邦定区第二栅绝缘层同层设置；所述显示区层间绝缘层位于所述栅极与所 述源极和所述漏极之间，所述显示区第一栅绝缘层位于所述显示区层间绝缘层靠近所述衬底基板的一侧，所述显示区第二栅绝缘层位于所述显示区层间绝缘层与所述显示区第一栅绝缘层之间；所述两个电容电极包括第一电容电极和第二电容电极，所述第一电容电极与所述栅极同层设置，所述第二电容电极设置在所述显示区层间绝缘层与所述显示区第二栅绝缘层之间。
例如，在上述实施例的显示基板中，所述第一组数据引线与所述第一电容电极和所述栅极同层设置，且所述第二组数据引线与所述第二电容电极同层设置，或者所述第二组数据引线与所述第一电容电极和所述栅极同层设置，且所述第一组数据引线与所述第二电容电极同层设置。
例如，在上述实施例的显示基板中，所述第一绝缘层位于所述第一组接触垫和所述第二组接触垫中相邻的接触垫之间的间隙中的表面具有凹陷部分，或者所述第一绝缘层位于所述第一行与所述第二行之间的间隙中的表面具有凹陷部分。
例如，在上述实施例的显示基板中，与所述第二组接触垫中至少一个接触垫电连接的数据引线的经过所述第一组接触垫的部分，位于所述第一组接触垫中相邻的接触垫的间隙中且由所述第一绝缘层覆盖。
例如，在上述实施例的显示基板中，所述第一组数据引线中至少一条数据引线相对于所述显示基板的边缘倾斜延伸，或者所述第二组数据引线中至少一条数据引线相对于所述显示基板的所述边缘倾斜延伸。
例如，在上述实施例的显示基板中，所述第一组数据引线中至少两条数据引线相对于所述显示基板的边缘倾斜延伸，且所述第一组数据引线中的所述至少两条数据引线相对于所述显示基板的边缘相同旋向的夹角相同或互补。
例如，在上述实施例的显示基板中，所述第二组数据引线中至少两条数据引线相对于所述显示基板的所述边缘倾斜延伸，且所述第二组数据引线中的所述至少两条数据引线相对于所述显示基板的边缘相同旋向的夹角相同或互补。
例如，在上述实施例的显示基板中，所述第一组接触垫至少一个接触垫相对于所述显示基板的边缘倾斜延伸，或者所述第二组接触垫中至少一个相对于所述显示基板的所述边缘倾斜延伸。
例如，在上述实施例的显示基板中，所述第一组接触垫至少两个接触垫相对于所述显示基板的边缘倾斜延伸，且所述第一组接触垫中所述至少两个接触垫相对于所述显示基板的边缘相同旋向的夹角相同或互补。
例如，在上述实施例的显示基板中，所述第二组接触垫至少两个接触垫相对于所述显示基板的边缘倾斜延伸，且所述第二组接触垫中所述至少两个接触垫相对于所述显示基板的边缘相同旋向的夹角相同或互补。
本公开的另一个实施例提供了一种显示装置，包括上述任一实施例所述的显示基板。
本公开的另一个实施例提供了一种显示基板的制备方法，该制备方法包括：
提供衬底基板，其中，所述衬底基板包括显示区和位于所述显示区至少一侧的邦定区；
在所述显示区中形成多个子像素以及多条数据线，其中，所述多条数据线配置为所述多个子像素提供数据信号；
在所述邦定区中形成多条数据引线；
在所述邦定区中形成至少一组接触垫，其中，所述至少一组接触垫包括第一组接触垫和第二组接触垫，所述第一组接触垫和所述第二组接触垫分别包括多个接触垫，所述第二组接触垫位于所述第一组接触垫远离所述显示区的一侧，所述多条数据引线与所述第一组接触垫和所述第二组接触垫一一对应电连接；
在所述邦定区中形成第一绝缘层，其中，所述第一绝缘层位于所述邦定区且位于所述多个接触垫之间的间隙并覆盖所述多个接触垫的边缘，且被配置为露出所述多个接触垫的背离所述衬底基板的表面。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为本公开一些实施例提供的一种显示基板的邦定区的平面图；
图1B为图1A所示显示基板沿线M1-N1的截面图；
图1C为图1A所示显示基板沿线M2-N2的截面图；
图1D为另一实施例提供的图1A所示显示基板沿线M1-N1截面图；
图2为本公开一些实施例提供的一种显示基板的部分区域的平面图；
图3为本公开一些实施例提供的一种显示基板的截面图；
图4为本公开一些实施例提供的一种显示装置的截面图；
图5A为本公开一些实施例提供的一种显示基板的平面图；
图5B(1)及图5B(2)为图5A所示显示基板的邦定区的平面图；
图5C为图5A所示显示基板沿线M3-N3的截面图；
图5D为图5B(1)所示显示基板沿线M4-N4的截面图；
图5E为图5B(1)所示显示基板沿线M5-N5的截面图；
图5F为另一实施提供的图5A所示显示基板沿线M3-N3的截面图；
图5G为另一实施提供的图5B(1)所示显示基板沿线M4-N4的截面图；
图5H为另一实施提供的图5B(1)所示显示基板沿线M5-N5的截面图；
图6为图5B所示显示基板的显示区的截面图；以及
图7A～图7L为本公开一些实施例提供的一种显示基板的另一种制备方法的过程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。 “上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
通常，在完成显示基板的制备工艺之后，需要将显示基板与外部电路(例如控制芯片等电路)连接，以在显示过程中，通过该外部电路对显示基板进行控制或驱动。例如，该外部电路可以包括柔性电路(Chip On Film，简称COF)板，该柔性电路板上设置有控制芯片或驱动芯片等。显示基板上设置接触垫，以通过邦定(bonding)工艺与柔性电路板的电路连接。如果显示基板的接触垫与其周边区域存在段差，即，接触垫的高度大于其周边区域，那么在邦定工艺中，用于提供压力的设备的压头在基板上施加的压力分布不均。例如，该压力集中在接触垫上并难以施加在接触垫之间的间隙区域。显示基板因为受力不均，可能会发生断裂。例如，接触垫之间的间隙部分的膜层会在因受力不均而产生的拉应力的作用下发生断裂，损坏显示基板。
例如，在显示基板的制造过程中，显示基板所包括的膜层(例如绝缘层)通过物理或化学气相沉积(例如等离子增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，简称PECVD))形成，该膜层中的晶体通常在微观结构上存在缺陷。在实际的工艺中，在接触垫与其周边区域存在段差的情况下，向接触垫施加压力，会使得邦定区受力不均而产生应力集中的现象。例如，应力集中在接触垫的尖端(例如角部)所在的区域，该应力集中会加剧膜层中的晶体缺陷，进一步使得膜层容易断裂。
例如，在实际工艺中，通过检测和对显示基板进行力学仿真分析，在膜层的位于两个接触垫之间的区域的部分，在邦定时，会产生沿接触垫之间的区域分别施加至两个接触垫的正向和反向的拉应力，从而使得该部分的膜层因受拉而断裂。例如在接触垫之间的间隙为50mm～100mm的情况下，由氮化硅形成的膜层位于接触垫之间的间隙的部分产生的拉应力大致为182MPa～712MPa。
本公开至少一个实施例提供一种显示基板及其制备方法、显示装置。该显示基板包括衬底基板、多个子像素、多条数据线、多条数据引线、至少一组接触垫及第一绝缘层。衬底基板，包括显示区和位于显示区至少一侧的邦定区；多个子像素位于显示区中；多条数据线位于显示区中，配置为多个子像素提供数据信号；多条数据引线位于邦定区中且与多条数据线电连接；至少一组接触垫，位于邦定区中，至少一组接触垫包括第一组接触垫和第二组 接触垫，第一组接触垫和第二组接触垫分别包括多个接触垫，第二组接触垫位于第一组接触垫远离显示区的一侧，多条数据引线述第一组接触垫和第二组接触垫电连接；第一绝缘层位于邦定区，第一绝缘层位于多个接触垫之间的间隙并覆盖多个接触垫的边缘，且被配置为露出多个接触垫的背离衬底基板的表面。
例如，在本公开至少一个实施例中，位于多个接触垫之间的间隙并覆盖多个接触垫的边缘，且被配置为露出多个接触垫的背离衬底基板的表面。。如此，在位于接触垫之间的间隙中的第一绝缘层可以降低或者消除接触垫与接触垫之间的间隙的段差，因此在邦定工艺中，压头施加在第一绝缘层的表面和接触垫的表面上的力被分散，分布更均匀(例如压强相等)，即，由压头施加在接触垫以及接触垫之间的间隙处的压力分布更均匀。显示基板(其中的邦定区)不会在邦定工艺中因为受力不均而损坏，这在实际生产中提高了显示基板的良率，降低了制造成本。
下面，结合附图对根据本公开至少一个实施例中的显示基板及其制备方法、显示装置进行说明。
在本公开的各个附图中，基于显示基板的衬底基板建立空间直角坐标系，以对显示基板中的各个结构的位置进行说明。在该空间直角坐标系中，X轴和Y轴平行于衬底基板所在面，Z轴垂直于衬底基板所在面。
本公开至少一个实施例提供一种显示基板，以下对该显示基板的结构进行详细描述。
例如，显示基板包括衬底基板、多个接触垫及第一绝缘层。衬底基板包括显示区和至少部分围绕显示区的周边区，该周边区进一步包括位于显示区至少一侧的至少一个邦定区(例如，多个邦定区)，多个接触垫位于邦定区中且彼此具有间隙，即，接触垫彼此间隔开一定距离。
图1A为本公开一些实施例提供的一种显示基板的邦定区的平面图。以一个邦定区为例，如图1A所示，多个接触垫排布为至少两行，第一绝缘层的至少部分还位于不同行的接触垫之间的间隙。示例性的，在显示基板的邦定区中，接触垫200a排布为两行，即第一行L1和第二行L2，第一行L1的接触垫200a和第二行L2的接触垫200a之间的间隙处设置有第一绝缘层310a。在实际工艺中，因为工艺条件等的限制，不同行的接触垫之间的间隙通常较同一行的接触垫之间的间隙大，在未设置第一绝缘层的情况下，显示基板的位于不同行 的接触垫之间的间隙处的部分在邦定工艺中更容易发生断裂。如此，第一绝缘层310a可以防止显示基板的位于不同行的接触垫之间的间隙的部分在邦定工艺中断裂；而且，邦定区中可以设置较多的接触垫，在实际工艺中，可以允许接触垫具有较大的设计尺寸，也允许接触垫之间具有较大的间隙，从而降低制造工艺的难度，降低制造成本。
例如，在本公开的至少一个实例中，所述第一绝缘层的远离衬底基板一侧的表面距离衬底基板的垂直距离不小于多个接触垫的远离衬底基板一侧的表面距离衬底基板的垂直距离。
在至少一个示例中，如图1B及图1C所示，第一绝缘层310a和接触垫200a的背离衬底基板100a的表面基本位于同一平面，即，第一绝缘层310a和接触垫200a相对于衬底基板100a的高度基本相等。
在本公开的实施例中，“高度”为结构(例如接触垫200a)的背离衬底基板的表面至衬底基板的垂直距离。需要说明的是，在本公开的实施例中，第一绝缘层的高度可以大于或者小于接触垫的高度，例如略大于或者略小于接触垫的高度，而不限于如图1B及图1C所示的相等的情形。
如图1D所示的显示面板的邦定区中与图1B所示的实施例的显示面板的邦定区相比，第一绝缘层310a的高度大于接触垫200a的高度。需要说明的是，这里的“高度”为结构(例如接触垫200a)的背离衬底基板的表面至衬底基板的垂直距离。第一绝缘层310a的高度增大，即第一绝缘层310a的厚度增大，可增加显示基板的位于不同行的接触垫之间的间隙部分的结构强度，从而进一步防止显示基板的位于不同行的接触垫之间的间隙的部分在邦定工艺中断裂。
需要说明的是，在本公开至少一个实施例中，第一绝缘层可以不仅位于接触垫之间的间隙，如图1A所示，除接触垫所在区域以及接触垫之间的间隙之外，第一绝缘层还可以设置为覆盖邦定区的其它区域，并且可以进一步地覆盖周边区的其他区域。如此，在X-Y确定的平面方向上，每个接触垫都可以被第一绝缘层包围，在邦定工艺中，显示基板的邦定区受力均匀，不仅防止接触垫之间的间隙处发生断裂，还可以防止邦定区的其它区域因受力不均而断裂。
下面，以第一绝缘层覆盖邦定区的除接触垫所在区域之外的其它所有区域为例，对本公开下述至少一个实施例中的显示基板及其制备方法、显示装 置进行说明。
例如，在本公开至少一个实施例中，位于邦定区中的多条数据引线可以与多个接触垫一一对应，并且每条数据引线的一个端部与与其对应的接触垫连接，另一端部延伸至显示区，从而与显示区中对应的信号线电连接。如此，在执行邦定工艺之后，显示区的元件可以通过柔性电路板与控制芯片等信号连接。
例如，在本公开至少一个实施例中，引线所在层位于接触垫所在层和衬底基板之间，例如，对于彼此电连接的引线和接触垫，引线的与接触垫电连接的端部与接触垫在垂直于衬底基板的方向上重叠，且位于接触垫和衬底基板之间。
例如，在本公开至少一个实施例中，多个接触垫排布为至少两行的情况下，与远离显示区的行的接触垫连接的数据引线位于靠近显示区的行的接触垫之间的间隙。如此，在邦定区的引线都同层的情况下，可以避免与不同行的接触垫连接的引线彼此接触。
示例性的，如图1A、图1B和图1C所示，与位于第一行L1的接触垫200a连接的数据引线400a的位于第二行L2的部分，走线在第二行L2的接触垫200a的间隙中且由第一绝缘层310a覆盖，即，与远离显示区的第一行L1的接触垫200a连接的数据引线400a，从靠近显示区的第二行L2的接触垫200a的间隙穿过，以延伸至显示区以与显示区中的信号线电连接。
例如，在衬底基板100上，数据引线和信号线例如形成在不同层中，例如，二者通过夹置在二者之间的绝缘层中的一个或多个过孔一一对应电连接；或者，数据引线和信号线例如形成同一层中，从而直接电连接。
例如，本公开至少一个实施例提供的显示基板中还包括位于接触垫和数据引线之间的第二绝缘层，其中，第二绝缘层中设置有过孔，每条数据引线通过过孔与对应的接触垫连接。
示例性的，如图1A、图1B、图1C和图1D所示，在邦定区，第二绝缘层320a位于接触垫200a和数据引线400a之间，第二绝缘层320a覆盖数据引线400a。接触垫200a通过设置在第二绝缘层320a中的一个或多个过孔321a与数据引线400a电连接。在第二行L2中，由于第二绝缘层320a将与第一行L1的接触垫连接的数据引线400a覆盖，从而在形成接触垫200a时，只需要考虑接触垫200a之间的间隙可以达到使得接触垫200a彼此间隔即可，在该情况下，接 触垫可以有较大的设计面积。例如，在实际工艺中，在第二行L2中，位于两个接触垫200a之间的数据引线400a可以与第二行L2的接触垫200a部分重叠。
例如，在本公开至少一个实施例中，邦定区中的第一绝缘层、接触垫、第二绝缘层和数据引线可以与显示区的对应的结构层一起形成，从而降低显示基板的制造工艺的流程。
例如，在本公开至少一个实施例中，在数据引线和接触垫位于不同层的情况下，数据引线和接触垫可以分别配置为与显示区的不同导电层同层设置。
上述实施例的显示基板还包括位于显示区中用于子像素的像素结构。该像素结构包括像素驱动电路、平坦化层以及发光元件，平坦化层在像素驱动电路远离衬底基板的一侧以提供平坦化表面且包括第一过孔，发光元件在平坦化表面上且通过第一过孔与像素驱动电路电连接，第一绝缘层与平坦化层同层设置。
该像素驱动电路包括薄膜晶体管，薄膜晶体管包括有源层、栅极绝缘层、栅极、层间介质层、源极和漏极等；该像素驱动电路包括还可以包括存储电容，存储电容包括两个彼此对置的电容电极。
例如，本公开至少一个实施例中，如图2所示，显示基板包括位于显示区101的子像素的薄膜晶体管500和层间介质层600。例如，薄膜晶体管500可以为像素电路中的驱动晶体管或发光控制晶体管，其可以包括依次位于衬底基板100a上的栅极510、栅绝缘层520、有源层530和源漏电极层540。源漏电极层540包括晶体管的源极和漏极，并且源极和漏极之一与发光元件电连接。层间介质层600位于有源层530和源漏电极层540之间。数据引线400a与栅极510同层设置。当然，本实施例不限于薄膜晶体管500为像素电路中的驱动晶体管或发光控制晶体管，也可以为显示基板上的其他晶体管，例如用于实现像素电路的补偿功能的晶体管等。
在本公开的实施例中，“同层设置”为两个结构(例如数据引线400a与栅极510)同层且同材料形成，即，该两个结构由同一个材料层形成，例如，可以由同一个材料层经过构图工艺形成。
例如，在本公开至少一个实施例中，第一导电层包括薄膜晶体管的源漏电极层，例如进一步包括数据线；第二导电层包括薄膜晶体管的栅极，例如进一步包括栅线。示例性的，如图2所示，接触垫200a和源漏电极层540配置 为同层设置，第二绝缘层320a与层间介质层600配置为同层设置。
例如，在本公开至少一个实施例中，在制造显示区的元件的过程中，在形成第二导电层之后，会沉积绝缘材料层，该绝缘材料层可以同时沉积在邦定区以形成如1B所示的第二绝缘层320a。
例如，在本公开至少一个实施例中，显示区设置有平坦化层以平坦化显示基板的表面，第一绝缘层可以配置为与平坦化层同层设置。
示例性的，如图1A、图1B、图1C和图1D所示，在形成源漏电极层540和接触垫200a之后，可以沉积绝缘材料(例如下述实施例中的第一材料层)以平坦化显示基板的表面，该绝缘材料在显示区101的部分形成为平坦化层700，位于邦定区102的部分形成为第一绝缘层310a。
例如，在本公开至少一个实施例中，邦定区的数据引线可以为用于栅线、数据线或其它类型的信号线的数据引线，例如，与数据线电连接到数据引线。
例如，在本公开至少一个实施例中，显示基板中的薄膜晶体管可以为如图2所示的底栅型薄膜晶体管，或者可以设置为顶栅型薄膜晶体管、双栅型薄膜晶体管或其它类型的薄膜晶体管。例如，在如图2所示的薄膜晶体管500为底栅型薄膜晶体管的情况下，第二绝缘层320a也可以与栅绝缘层520配置为同层设置，相应地，邦定区中可以设置或不设置与层间介质层600同层的绝缘层。
在本公开至少一个实施例中，对接触垫、引线和第二绝缘层的厚度不做限制，可以根据具体工艺设计，第一绝缘层的厚度可以根据接触垫、数据引线和第二绝缘层的厚度进行设计。例如，在如图2所示的邦定区中，数据引线400a的厚度可以为2000埃～3000埃，例如2300埃、2500埃、2700埃等；第二绝缘层320a的厚度可以为4000埃～6000埃，例如为5000埃等；接触垫200a的厚度可以为6000埃～7000埃，例如6300埃、6500埃、6700埃等。需要说明的是，在本公开的实施例中，“厚度”可以为该结构(例如接触垫)的背离衬底基板的表面至面向衬底基板的表面的距离。
例如，在本公开至少一个实施例中，如图3所示，显示基板的显示区101设置有发光结构层800，该发光结构层800位于平坦化层700的背离衬底基板100的一侧。发光结构层800可以包括对应于多个阵列排布的子像素的多个发光元件，每个发光元件例如为有机发光二极管(OLED)或量子点发光二极管(QLED)，可以包第一电极、第二电极以及位于第一电极和第二电极之间 的发光层。平坦化层700中可以设置有过孔701，第一电极和第二电极之一通过该过孔701与像素结构中第一导电层(例如薄膜晶体管的漏极)连接。例如，第一电极为阳极，第二电极为阴极。
例如，对于OLED，发光层可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光；并且，根据需要发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。对于QLED，发光层可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
例如，在本公开至少一个实施例中，如图3所示，显示基板还包括覆盖发光结构层800的封装层900，该封装层900可以延伸至邦定区，封装层900未覆盖接触垫200a。
例如，该封装层900可以为单层结构，也可以为至少两层的复合结构。例如，封装层的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。例如，封装层可以包括依次设置在发光结构层上的第一无机封装层、有机封装层和第二无机封装层。例如，第一无机封装层和第二无机封装层的材料可以包括无机材料，例如氮化硅、氧化硅、氮氧化硅等，无机材料的致密性高，可以防止水、氧等的侵入；例如，有机封装层的材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一无机封装层和第二无机封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
本公开至少一个实施例提供一种显示装置，该显示装置可以包括上述任一实施例的显示基板。
例如，在本公开至少一个实施例中，如图4所示，显示装置包括柔性电路板910，柔性电路板910上设置有控制芯片920，柔性电路板910与接触垫200a电连接。
例如，控制芯片可以为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片 还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。
例如，本公开至少一个实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一个实施例还提供了另一种显示基板，如图5A及图5B(1)及图5B(2)所示，该显示基板包括衬底基板，衬底基板包括显示区1101和至少部分围绕显示区1101的周边区1103，该周边区1103进一步包括位于显示区1101至少一侧的至少一个邦定区1102(例如，图中示出了4个邦定区)，多个接触垫1200位于每个邦定区1102中且彼此具有间隙，即，接触垫1200彼此间隔开一定距离。
在该实施例中，显示区1101包括多个子像素沿第一方向(图中X轴方向)延伸的信号线11011(例如栅线G)和沿第二方向(图中Y轴方向)延伸的信号线11012(例如数据线D。显示基板包括位于邦定区1102中的多条数据引线1400。这些信号线延伸或走线到位于显示区1101至少一侧的邦定区，例如，信号线11012与对应的数据引线电连接，由此可以与邦定区的驱动芯片、柔性电路板等电连接。
随着显示基板的像素阵列的分辨率的提高，显示基板周边用于显示区内的信号线的走线变得越来越密集。因此，在该实施例中，为了避免显示基板的周边区中的相邻引线之间产生相互干扰或出现短路，在显示区的周边可以将用于相邻的同一类引线(例如数据引线)的走线设置在不同导电层上。
在本公开的至少一个实施例中，显示基板包括多条引线与多个接触垫一一对应电连接，且多条引线每条的一端部与多个接触垫中对应的一个电连接且另一端部向所述显示区延伸，从而与显示区中对应的信号线电连接。这些引线与对应的信号线可以位于同一层，从而直接电连接，或者位于不同层，从而通过夹置在二者之间的绝缘层中的一个或多个过孔一一对应电连接。
在该实施例的显示基板中，例如，多个接触垫排布为至少两行，第一绝缘层的至少部分位于一行的多个接触垫之间的间隙，或者至少部分位于不同行的接触垫之间的间隙，或者至少部分同时位于一行的多个接触垫之间的间 隙以及位于不同行的接触垫之间的间隙。并且，显示基板还包括多个绝缘层，在垂直于衬底基板的方向上分别位于不同导电层之间，以将这些导电层彼此间隔开。
在本实施例中，如图5A、图5B(1)及图5B(2)所示的示例中，在显示基板的至少一个邦定区中，接触垫1200排布为两行，即第一行L3中的第二组接触垫1200和第二行L4中的第一组接触垫1200’。在第一行L3内的第二组接触垫1200之间的间隙处，或第二行L4内的第一组接触垫1200’之间的间隙处，或第一行L3的第二组接触垫1200与第二行L4的第一组接触垫1200’之间的间隙处，或者上述全部类型的间隙处，设置有第一绝缘层1310。在实际工艺中，因为工艺条件等的限制，不同行的接触垫之间的间隙通常较同一行的接触垫之间的间隙大，在未设置第一绝缘层1310的情况下，显示基板的位于不同行的接触垫之间的间隙处的部分在邦定工艺中更容易发生断裂。设置第一绝缘层1310使得位于不同行的接触垫之间的间隙处的部分在邦定工艺中不容易发生断裂，提高了产率，降低了成本。
如图5A、图5B(1)及图5B(2)所示的示例中，以为与数据线D电连接的数据引线进行说明。多条数据引线包括第一组数据引线和第二组数据引线，第一组数据引线与第一组接触垫一一对应电连接，第二组数据引线与第二组接触垫一一对应电连接，并且相对于衬底基板，第一组数据引线和第二组数据引线分别位于不同层。
图5C为图5A所示显示基板沿线M3-N3的截面图。如图5C所示，图5B中位于第二行L4的接触垫1201、1203和位于第一行L3中的接触垫1202、1204位于同一层中。但是，与第一组接触垫电连接的第一组数据引线和与第二组接触垫电连接的第二组数据引线分别位于不同层。
具体而言，在图中的示例中，多条数据引线1400包括第一组数据引线1401和第二组数据引线1402。第一组数据引线1401设置在第一栅绝缘层1322(即，邦定区第一栅绝缘层)与第二栅绝缘层1323(即，邦定区第二栅绝缘层)之间，第一组数据引线1401在邦定区的端部与接触垫1201通过穿过第二栅绝缘层1323和层间绝缘层1324(邦定区层间栅绝缘层)的一个或多个过孔电连接。第二组数据引线1402设置在第二栅绝缘层1323与层间绝缘层1324之间，第二组数据引线1402在邦定区的端部与接触垫1202通过层间绝缘层1324的一个或多个过孔电连接。第一栅绝缘层1322与衬底基板1100之间设置缓冲 层1321。在垂直于衬底基板1100的方向上，第一组数据引线1401与第二组数据引线1402非同层设置，如此，在同一层中的相邻引线之间的间距可以制备得更大，与此减小或避免引线排布时同层引线之间的干扰。
在本实施例中，图5D为图5B(1)所示显示基板沿线M4-N4在第二行L4上的截面图。如图5D所示，图5B(1)中位于第二行L4的接触垫1201和接触垫1203位于同一层中。第二行L4上的接触垫1201和接触垫1203分别与第一组数据引线1401中两条电连接。并且，位于与第一组数据引线1401不同层上的第二组数据引线1402的一端从靠近显示区1101的第二行L4的接触垫1201与接触垫1203之间的间隙穿过延伸至显示区，以与数据线D电连接，第二组数据引线1402的另一端通过穿过层间绝缘层1324的一个或多个过孔与第二组接触垫1200电连接。因此，上述设置可以避免相邻引线之间的相互干扰或短路。
在本实施例中，图5E为图5B(1)所示显示基板沿线M5-N5第一行L3上的截面图。如图5E所示，图5B(1)中位于第一行L3的接触垫1202和接触垫1204位于同一层中。第一行L3上的接触垫1202和接触垫1204分别与两条第二组数据引线1402电连接。第二行L3上没有排布第一组数据引线1401，使得接触垫具有更大的排列空间。
在本实施例中，第一绝缘层1310的高度大于接触垫1200的高度，从而，第一绝缘层1310的表面高于接触垫1200的表面。需要说明的是，这里的“高度”同样为结构(例如接触垫1200)的背离衬底基板的表面至衬底基板的距离。第一绝缘层1310的高度增大，即第一绝缘层1310的厚度增大，可增加显示基板的位于不同行的接触垫之间的间隙部分的结构强度，从而进一步降低接触垫之间的间隙部分在邦定工艺中发生断裂的风险。
并且，第一绝缘层1310覆盖接触垫1200的边缘且被配置为露出接触垫的背离衬底基板的表面。如图5C-5E所示，在邦定区中，第一绝缘层1310具有多个开口，与多个接触垫一一对应，即每个开口露出一个接触垫的背离衬底基板的表面。
例如，该开口具有围绕对应的接触垫的侧壁，该侧壁至少部分或全部相对于衬底基板具有为锐角的坡度角X1，该坡度角X1的取值范围约为40度至60度例如，也可以将坡度角X1的取值范围选择为45度至55度，或者坡度角X1的取值选择约为50度。这里，需要说明的是，“约”表示数值的范围可以在给定数值的±5％范围内变化。该坡度角X1既能使得第一绝缘层1310具有适 当的厚度以提供足够的结构强度，又能够降低接触垫表面与第一绝缘层1310的表面之间的段差，使得在进行邦定工艺时，各向异性导电胶能够更容易进入开口中与接触垫接触，提高工艺良率。
在上述实施例的一个变型中，如图5F～5H所示，第一绝缘层1310覆盖接触垫1200的边缘且被配置为露出接触垫的背离衬底基板的表面。在邦定区中，第一绝缘层1310具有多个开口，与多个接触垫一一对应，即每个开口露出一个接触垫的背离衬底基板的表面。在第一行L3内的第二组接触垫1200之间的间隙处，第二行L4内的第一组接触垫1200’之间的间隙处，第一行L3的第二组接触垫1200与第二行L4的第一组接触垫1200’之间的间隙处，第一绝缘层1310表面具有凹陷部分C。该凹陷部分防止在邦定工艺中各向异性导电胶的流动，从而提高邦定工艺的良率。
例如，在本实施例的其他一些示例中，接触垫1200的排布也可设置为一行，这样将不存在位于不同行的接触垫之间的间隙，只需要考虑位于同一行的接触垫之间的间隙的问题。本公开的实施例不以邦定区接触垫的所在行的数量为限。
在至少一个示例中，第一组数据引线中至少一条数据引线相对于显示基板的边缘倾斜延伸，或者第二组数据引线中至少一条数据引线相对于显示基板的边缘倾斜延伸。
进一步地，至少一个示例中，第一组数据引线中至少两条数据引线相对于显示基板的边缘倾斜延伸，且第一组数据引线中的至少两条数据引线相对于显示基板的边缘相同旋向的夹角相同或互补；同样地，至少一个示例中，第二组数据引线中至少两条数据引线相对于显示基板的边缘倾斜延伸，且第二组数据引线中的至少两条数据引线相对于显示基板的边缘相同旋向的夹角相同或互补。
在本公开的实施例中，引线(即引线延伸方向)与显示基板边缘之间的夹角为引线顺时钟方向旋转以与显示基板的边缘重合的角度。此外，相同旋向是指顺时钟方向。
参见图5A、图5B(1)及图5B(2)的示例，邦定区中的第一组数据引线1401相对于显示基板的边缘倾斜延伸，第一组数据引线1401与显示基板边缘之间的夹角为第一组数据引线1401沿顺时钟方向S(图5B(2)中示出)旋转以与显示基板的边缘重合的角度。图中左侧的第一组数据引线1401都具有第一引线夹 角α1，图中右侧的第一组数据引线1401都具有第二引线夹角α2。例如，第一引线夹角α1和第二引线夹角α2彼此互补(即彼此相加的和为180度)。类似地，邦定区中的第二组数据引线1402相对于显示基板的边缘倾斜延伸，且图中左侧的第二组数据引线1402都具有第三引线夹角β1，图中右侧的第二组数据引线1402都具有第四引线夹角β2。例如，第三引线夹角β1和第四引线夹角β2彼此互补(即彼此相加的和为180度)。
在至少一个示例中，第一组接触垫至少一个接触垫相对于显示基板的边缘倾斜延伸，或者，第二组接触垫中至少一个相对于显示基板的边缘倾斜延伸。
在至少一个示例中，第一组接触垫至少两个接触垫相对于显示基板的边缘倾斜延伸，且第一组接触垫中至少两个接触垫相对于显示基板的边缘相同旋向的夹角相同或互补；例如，在至少一个示例中，第二组接触垫至少两个接触垫相对于显示基板的边缘倾斜延伸，且第二组接触垫中至少两个接触垫相对于显示基板的边缘相同旋向的夹角相同或互补。
参见图5A、图5B(1)及图5B(2)的示例，邦定区的L4行中的第一接触垫相对于显示基板的边缘倾斜延伸，且图中左侧的第一组接触都具有第一接触垫夹角A1，图中右侧的第一组接触垫都具有第二接触垫夹角A2。例如，第一接触垫夹角A1和第二接触垫夹角A2彼此互补(即彼此相加的和为180度)。类似地，邦定区的L3行中的第二组接触垫相对于显示基板的边缘倾斜延伸，且图中左侧的第二组接触垫都具有第三接触垫夹角B1，图中右侧的第二组接触垫都具有第四接触垫夹角B2。例如，第三接触垫夹角B1和第四接触垫夹角B2彼此互补(即彼此相加的和为180度)。
例如，在至少一个示例中，如图5B(2)所示，第一引线夹角α1与第一接触垫夹角A1相等；第三引线夹角β1与第三接触垫夹角B1相等。
例如，如图5B(2)所示，多个接触垫中至少一个具有长度Y1，长度Y1的取值范围约为650微米至750微米，例如，长度Y1的取值范围可以选择约为680微米至720微米，或者长度Y1的取值可以选择约为700微米。多个接触垫中至少一个还具有宽度Z1，宽度Z1的取值范围约为34微米至42微米，例如，宽度Z1的取值范围可以选择约为36微米至40微米，或者宽度Z1的取值可以选择约为38微米。需要说明的是，“约”字表示数值的范围可以在所给定数值的±5％范围内变化。
例如，缓冲层1321的材料可以包括氧化硅、氮化硅、氧氮化硅等绝缘材料。第一栅绝缘层1322、第二栅绝缘层1323可以包括氧化硅、氮化硅等绝缘材料。层间绝缘层1324可以包括氧化硅、氮化硅等绝缘材料。
例如，在本公开的至少一个实施例中，邦定区中的缓冲层、第一栅绝缘层、第二栅绝缘层、层间绝缘层、第一组数据引线和第二组数据引线可以与显示区的对应的结构层一起形成，从而降低显示基板的制作工艺的流程。
例如，本公开至少一个实施例提供的显示基板第一绝缘层1310自邦定区1200继续向四周延伸，使得第一绝缘层1310所覆盖区的范围大于邦定区，例如，第一绝缘层1310覆盖除邦定区外的部分或者全部区域，如图5A中所示，第一绝缘层1310覆盖围绕邦定区的周边区1103。如图5A所述，长度D表示第一绝缘层1310的周边区1103相对于邦定区1200在一个侧边延伸出的距离。例如，长度D可以约为40微米至60微米，例如50微米等。邦定区位于第一绝缘层1310覆盖区中，以使得降低邦定区在邦定工艺中发生断裂、出现裂纹的风险。
例如，如图6所示，显示基板的显示区1101的像素阵列包括多个子像素1110，每个子像素可以包括像素电路、平坦化层以及发光元件，像素电路包括多个薄膜晶体管和存储电容，平坦化层位于薄膜晶体管远离衬底基板一侧，以覆盖薄膜晶体管以及存储电容，发光元件位于平坦化层远离衬底基板一侧，平坦化层包括第一平坦层过孔，薄膜晶体管包括位于衬底基板上的有源层，位于有源层远离所处衬底基板一侧的栅极，以及位于栅极远离衬底基板一侧的源极和漏极，并且源极和漏极中之一通过第一平坦层过孔与发光元件电连接；第一绝缘层与平坦化层为同层设置。
发光元件可以为有机发光二极管(Organic Light-Emitting Diode,OLED)或量子点发光二极管(QLED)。像素电路的类型如上所述，这里不再赘述，且本公开的实施例对此不作限制。
例如，显示区的部分结构与邦定区同层形成且材料相同，从而减少制备工艺流程。
例如，在本公开的至少一个实施例中，如图6的子像素1110的部分结构示意图所示，显示区1101的缓冲层1321设置在衬底基板1100上，以提供用于形成像素电路的平坦表面以及避免衬底基板中可能存在的杂质扩散到像素电路中而不利影响像素电路的性能。显示区的显示区的缓冲层1321与邦定区 的缓冲层1321同层设置。例如，缓冲层1321与衬底基板1100之间还可以设置阻挡层。
例如，缓冲层1321的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。
例如，如图6所示，显示区1101的半导体层121设置在显示区的缓冲层1321上。半导体层121可以包括多晶硅或氧化物半导体，包括氧化物半导体的半导体层121可以由单独的钝化层(未示出)覆盖。半导体层121包括未用杂质掺杂的沟道区以及位于沟道区的相对两侧处并且用杂质掺杂(N型杂质或P型杂质)的源区和漏区。
例如，如图6所示，显示区1101的第一栅绝缘层1322(即，显示区第一栅绝缘层)设置在半导体层121上。显示区的第一栅绝缘层1322与邦定区的第一栅绝缘层1322同层设置。栅极1510和第一电容电极1601设置在第一栅绝缘层1322上。栅极1510与半导体层121的沟道区叠置。栅极1510与第一电容电极1601的材料相同，栅极1510、第一电容电极1601与第一组数据引线1401设置在同一导电层中，该导电层可以称为第二导电层。
例如，如图6所示的示例中，显示区1101的第二栅绝缘层1323(即，显示区第二栅绝缘层)可以设置在栅极1510和第一电容电极1601上，第二电容电极1602设置在第二栅绝缘层1323上。第二电容电极1602与第一电容电极1601叠置，在垂直于衬底基板1100的方向上至少部分重叠，第一电容电极1601和第二电容电极1602使用第二栅绝缘层1323作为介电材料来形成存储电容器。显示区的第二栅绝缘层1323与邦定区的第二栅绝缘层1323同层设置。第二电容电极1602与邦定区的第二组数据引线1402设置在同一导电层中，并且例如与显示基板上的例如除图6示出的晶体管之外的其他晶体管的栅极同层设置，又例如与向像素电路提供电源电压的电源线同层设置，该导电层可以被称为第二栅导电层。
在另一示例中，作为图6所示示例的变型，存储电容器的第一电容电极仍然与栅极1510同层设置，而存储电容器的第二电容电极与薄膜晶体管中的源极1541和漏极1542同层设置。在该示例中，第二组数据引线1402则不再与第二电容电极同层设置。
在再一示例中，作为图6所示示例的变型，存储电容器的第一电容电极不再与栅极1510同层设置，而是位于在第二栅绝缘层1323与层间绝缘层1324 (即，显示区层间绝缘层)之间，而存储电容器的第二电容电极与薄膜晶体管中的漏极1541和源极1542同层设置。在该示例中，第二组数据引线1402则不再与第二电容电极同层设置，而是与第一电容电极同层设置。
例如，在一些实施例中，栅极的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))。第一电容电极、第二电容电极的材料可以包括金、银、铜、镍、铂、铝及钼等中的一种或更多种。
例如，如图6所示，显示区1101的层间绝缘层1324可以设置在第二电容电极1602上，源漏电极层1540设置在层间绝缘层1324上。薄膜晶体管的源漏电极层1540包括漏极1541和源极1542。显示区的层间绝缘层1324与邦定区的层间绝缘层1324同层设置。漏极1541和源极1542可以包括为钼、铝及钛等形成的金属单层或多层。漏极1541和源极1542与邦定区的接触垫同层设置。
本实施例中，显示基板中的薄膜晶体管可以为如图6所示的顶栅型薄膜晶体管，但是也可以设置为底栅型薄膜晶体管、双栅型薄膜晶体管或其它类型的薄膜晶体管，本实施例对此不作限制。
例如，如图6所示，显示区1101的第一绝缘层1310覆盖薄膜晶体管并且在其上形成OLED，显示区1101的第一绝缘层1310作为平坦化层1310。第一绝缘层1310可以包括有机绝缘材料或无机绝缘材料，或者可以由有机绝缘材料和无机绝缘材料的组合形成。显示区的第一绝缘层1310与邦定区的第一绝缘层1310同层形成。
例如，如图6所示，显示区1101的子像素中作为发光元件的OLED包括像素电极127、发光层128以及公共电极129。像素电极127在作为平坦化层的第一绝缘层1310上分开地形成在每个子像素中，并且通过形成在第一绝缘层1310上的过孔1271连接到薄膜晶体管的漏极1542。像素限定层(或分隔壁)113设置在第一绝缘层1310上并且在像素电极127的边缘上。发光层128设置在像素电极127上，公共电极129设置在整个显示区域上。像素电极127可以包括反射层，公共电极129可以包括透明层或半透明层。从发光层128发射的光通过像素电极127反射，并且穿过公共电极129以发射到外界环境中，以实现显示功能。当公共电极129包括半透射层时，由像素电极127反射的一些光通过共电极129再次反射，因此像素电极127和共电极129形成共振结构，从而可以改善光提取效率。
例如，像素电极127的材料可以包括至少一种透明导电氧化物材料，包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)等。此外，像素电极127可以包括具有高反射率的金属作为反射层，诸如银(Ag)。
例如，对于OLED，发光层128可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光；并且，根据需要发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。对于QLED，发光层可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
例如，公共电极129可以包括各种导电材料。例如，公共电极129可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
例如，像素限定层113的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。
例如，如图6所示，显示基板还可以包括封装层190，其覆盖在发光元件和像素电路上。封装层190将OLED密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的OLED的劣化。封装层190可以包括无机层和有机层堆叠的结构，例如，在一个示例中，封装层190可以包括第一无机层191、有机层192和第二无机层193。例如，该封装层190可以延伸至邦定区，但是该封装层未覆盖接触垫。
例如，该封装层的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防止水、氧等的侵入；有机封装层的材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一无机封装层和第二无机封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
在本公开的实施例中，“同层设置”为两个结构(例如接触垫1200与源漏电极层1540)同层且同材料形成，即，该两个结构由同一个材料层形成，例如可以由同一个材料层经过构图工艺形成。
本公开至少一个实施例还提供一种显示装置，该显示装置可以包括上述 图5A～图5E和图6所示的任一实施例的显示基板。并且，该显示装置包括柔性电路板，柔性电路板上设置有控制芯片，该柔性电路板与接触垫1200电连接。
例如，控制芯片可以为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。
本公开至少一个实施例提供了一种显示基板的制备方法，包括：提供衬底基板，其中，所述衬底基板包括显示区和位于所述显示区至少一侧的邦定区；在所述显示区中形成多个子像素以及多条数据线，其中，所述多条数据线配置为所述多个子像素提供数据信号；在所述邦定区中形成多条数据引线；在所述邦定区中形成至少一组接触垫，其中，所述至少一组接触垫包括第一组接触垫和第二组接触垫，所述第一组接触垫和所述第二组接触垫分别包括多个接触垫，所述第二组接触垫位于所述第一组接触垫远离所述显示区的一侧，所述多条数据引线与所述第一组接触垫和所述第二组接触垫一一对应电连接；在所述邦定区中形成第一绝缘层，其中，所述第一绝缘层位于所述邦定区且位于所述多个接触垫之间的间隙并覆盖所述多个接触垫的边缘，且被配置为露出所述多个接触垫的背离所述衬底基板的表面。
例如，在上述实施例的制备方法中，所述第一绝缘层形成为，使得所述第一绝缘层远离所述衬底基板一侧的表面距离所述衬底基板的垂直距离不小于所述多个接触垫远离所述衬底基板一侧的表面距离所述衬底基板的垂直距离。
例如，在上述实施例的制备方法中，在所述邦定区中形成第一绝缘层包括：形成所述多个接触垫之后，在所述衬底基板上沉积第一材料层以平坦化所述显示基板的表面；对所述第一材料层进行构图工艺，以使得所述第一材料层的位于所述显示区的部分形成为平坦化层，去除所述第一材料层的与多个所述接触垫重叠的部分，并且减薄所述第一材料层的位于所述邦定区且位于所述接触垫之间的间隙的部分以形成所述第一绝缘层。
例如，在上述实施例的制备方法中，所述第一绝缘层形成为覆盖所述多个接触垫每个的边缘，且包括多个开口以分别露出所述多个接触垫每个的背离所述衬底基板的表面。
例如，在上述实施例的制备方法中，所述对所述第一材料层进行构图工艺包括：在所述第一材料层上涂覆光刻胶；提供第一掩模板以对所述光刻胶进行曝光、显影，以去除与所述光刻胶的与所述多个接触垫重叠的部分；以剩余的光刻胶为掩模构图所述第一材料层，以去除所述第一材料层的与所述多个接触垫重叠的部分；去除所述邦定区中剩余的光刻胶；以及在所述邦定区，刻蚀所述第一材料层的位于所述多个接触垫之间的间隙且背离所述衬底基板的表面部分，使得剩余的所述第一材料层形成为所述第一绝缘层。
例如，在上述实施例的制备方法中，所述对所述第一材料层进行构图工艺包括：在所述第一材料层上涂覆光刻胶；利用灰色调掩模板或半色调掩模板对所述光刻胶进行曝光，对曝光之后的光刻胶进行显影后，以去除所述光刻胶的与所述多个接触垫重叠的部分并减薄所述光刻胶与所述多个接触垫的间隙重叠的部分；以及在所述邦定区，刻蚀所述第一材料层，以去除所述第一材料层的与所述多个接触垫重叠的部分，进行灰化工艺以去除所述光刻胶与所述多个接触垫的间隙重叠的部分，并去除与所述多个接触垫的间隙重叠的第一材料层的背离所述衬底基板的部分厚度。
例如，在上述实施例的制备方法中，所述第一材料层包括光敏树脂材料，所述对所述第一材料层进行构图工艺包括：使用灰色调掩模板或半色调掩模板对所述第一材料层进行曝光，对曝光之后的光刻胶进行显影后，以使得所述第一材料层的位于所述显示区的部分形成为所述平坦化层，去除所述第一材料层的与所述多个接触垫重叠的部分，并且减薄所述第一材料层的位于所述邦定区且位于所述多个接触垫之间的间隙的部分以形成所述第一绝缘层。
例如，在上述实施例的制备方法中，所述多个接触垫每个包括至少一个金属层，形成所述多个接触垫包括：在所述衬底基板上沉积第一导电材料薄膜并对其进行构图工艺，其中，所述第一导电材料薄膜的位于所述显示区的部分形成为第一导电层，所述第一导电材料薄膜的位于所述邦定区的部分形成为所述多个接触垫的至少一个金属层，其中，所述多个子像素中至少一个包括薄膜晶体管，所述平坦化层位于所述薄膜晶体管远离所述衬底基板一侧，所述薄膜晶体管包括位于所述第一导电层中的源极和漏极。
例如，在上述实施例的制备方法中，所述多条数据引线包括第一组数据引线和第二组数据引线，所述第一组数据引线与所述第一组接触垫一一对应电连接，所述第二组数据引线与所述第二组接触垫一一对应电连接，并且相对于所述衬底基板，所述第一组数据引线和所述第二组数据引线分别位于不同层。在所述邦定区中形成多条数据引线包括：在所述衬底基板上形成第一层间绝缘层；在所述邦定区中在第一层间绝缘层上形成所述第一组数据引线，在所述衬底基板上形成第二层间绝缘层以覆盖所述第一组数据引线，在所述邦定区中在第二层间绝缘层上形成所述第二组数据引线；或者，在所述邦定区中在第一层间绝缘层上形成所述第二组数据引线，在所述衬底基板上形成第二层间绝缘层以覆盖所述第二组数据引线，在所述邦定区中在第二层间绝缘层上形成所述第一组数据引线，其中，所述多个接触垫以及所述第一绝缘层形成在所述第二层间绝缘层上。
例如，在上述实施例的制备方法中，在所述邦定区中形成多条数据引线还包括：形成穿过所述第一层间绝缘层中的多个第一接触垫过孔，以使得所述第一组接触垫通过所述多个第一接触垫过孔与所述第一组数据引线一一对应电连接，形成穿过所述第一层间绝缘层和所述第二层间绝缘层中的多个第二接触垫过孔，以使得所述第二组接触垫通过所述多个第二接触垫过孔与所述第二组数据引线一一对应电连接；或者，形成穿过所述第一层间绝缘层中的多个第二接触垫过孔，以使得所述第二组接触垫通过穿过所述多个第二接触垫过孔与所述第二组数据引线一一对应电连接，形成穿过所述第一层间绝缘层和所述第二层间绝缘层中的多个第一接触垫过孔，以使得所述第一组接触垫通过所述多个第一接触垫过孔与所述第一组数据引线一一对应电连接。
例如，在上述实施例的制备方法中，所述多个子像素中所述至少一个还包括存储电容，所述存储电容包括两个电容电极，所述薄膜晶体管包括栅极，所述制备方法还包括：将所述第一组数据引线与所述栅极同层形成，且将所述第二组数据引线与所述存储电容的两个电容电极之一同层形成；或者，将所述第二组数据引线与所述栅极同层形成，且将所述第一组数据引线与所述存储电容的两个电容电极之一同层形成。
例如，在上述实施例的制备方法中，所述两个电容电极包括第一电容电极和第二电容电极，所述第一电容电极与所述栅极同层设置，在所述显示区 中所述第二电容电极设置在所述第一层间绝缘层与所述第二层间绝缘层之间。
参考上述图5A～图5E和图6所示的任一实施例的显示基板，描述根据本公开至少一实施例的制备方法。
对于图5A～图5E和图6所示的任一实施例的显示基板的制备方法以下将进行详细描述。邦定区中第一绝缘层的高度大于邦定区的高度，其制备过程如图7A至图7L所示。
如图7A所示，提供衬底基板1100并在衬底基板1100上沉积绝缘材料形成缓冲层1321，例如，缓冲层覆盖显示区1101和邦定区1102。显示区的缓冲层上沉积半导体材料了形成半导体层121，其包括中间未用杂质掺杂的沟道区以及位于沟道区的相对侧处并且用杂质掺杂(N型杂质或P型杂质)的源区和漏区。在邦定区1102和显示区1101的缓冲层上沉积绝缘材料11形成第一栅绝缘层。
例如，在本公开的实施例中，衬底基板可以为玻璃板、石英板、金属板或树脂类板件等。例如，衬底基板的材料可以包括有机材料，例如该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。例如，该衬底基板可以由多个材料层形成，例如衬底基板可以包括基底，基底的材料可以由上述的材料构成。基底的表面上可以形成缓冲层以作为过渡层，其即可以防止衬底基板中的有害物质侵入显示基板的内部，又可以增加显示基板中的膜层在衬底基板上的附着力。例如，缓冲层的材料可以为氧化硅、氮化硅、氧氮化硅等。
如图7B所示，在邦定区1102和显示区1101的第一栅绝缘层1322上沉积第一导电材料形成第一导电材料层21。如图7C所示，对第一导电材料层进行构图工艺，第一导电材料层21的位于显示区的部分形成栅极1510和第一电容电极1601，第一导电材料层21的位于邦定区的部分形成第一组数据引线1401。例如，第一导电材料层21可以为金属或金属合金，也可以为其它导电材料。例如，第一导电材料层21可以为单层结构，也可以为多个膜层构成的叠层，例如，Ti-AL-Ti三种金属膜层构成的叠层。
在该步骤中，在一些示例中，可以使用栅极1510进行作为掩膜，通过对有源层进行掺杂以形成导电的源区及漏区，而在源区及漏区之间的沟道区由 于栅极的遮挡作用而未掺杂。
如图7D所示，在显示区和邦定区中沉积绝缘材料以在显示区形成覆盖栅极1510的第二栅绝缘层1323，在邦定区形成覆盖第一组数据引线1401的第二栅绝缘层1323。
如图7E所示，在邦定区1102的第二栅绝缘层1323上沉积第二导电材料形成第二导电材料层22。例如，第二导电材料层22可以为金属或金属合金，也可以为其它导电材料。例如，第二导电材料层22可以为单层结构，也可以为多个膜层构成的叠层，例如，Ti-AL-Ti三种金属膜层构成的叠层。
如图7F所示，对第二导电材料层22进行构图工艺，第二导电材料层22的位于邦定区的部分形成第二组数据引线1402，而第二导电材料层22的位于显示区的部分形成第二电容电极1602。
如图7G所示，显示区和邦定区中沉积绝缘材料以在显示区形成覆盖第二栅绝缘层1323的层间绝缘层1324，在邦定区形成覆盖第二组数据引线1402的层间绝缘层1324。
如图7H所示，对邦定区中与第一组数据引线1401重叠的第二栅绝缘层1323及层间绝缘层1324进行构图工艺，以在第二栅绝缘层1323及层间绝缘层1324中形成一个或多个过孔。并且，对邦定区中与第二组数据线重叠的层间绝缘层1324进行构图，以在层间绝缘层1324中形成一个或多个过孔。对显示区中的第一栅绝缘层1322、第二栅绝缘层1323及层间绝缘层1324进行构图工艺，以在第一栅绝缘层1322、第二栅绝缘层1323及层间绝缘层1324中形成过孔。然后在显示区和邦定区中沉积第三导电材料层23。第三导电材料层23通过过孔分别与有源层121、第一组数据引线1401及第二组数据引线1402连接。例如，第三导电材料层23可以为金属或金属合金，也可以为其它导电材料。例如，第三导电材料层23可以为单层结构，也可以为多个膜层构成的叠层，例如，Ti-AL-Ti三种金属膜层构成的叠层。
如图7I所示，对第三导电材料层23进行构图工艺，第三导电材料层23位于显示区的部分形成为漏极1541和源极1542。第三导电材料层23位于邦定区的部分形成接触垫1200。
如图7J所示，在显示区和邦定区上沉积第一绝缘材料层1710以平坦化显示基板的表面，即，第一绝缘材料层1710覆盖薄膜晶体管且覆盖接触垫1200，并且第一绝缘材料层1710的背离衬底基板1100的表面为平面。例如，第一绝 缘材料层的制备材料可以包括有机材料例如高分子树脂，例如可以包括聚酰亚胺、聚丙烯酸酯、聚丙烯酸酯聚氨酯、聚脲、聚芳香酯类或其它。在第一绝缘材料层1710上覆盖光刻胶1040。提供第三掩模板1042对光刻胶1040进行曝光。在邦定区，第三掩模板1042包括与接触垫1201及接触垫1202重叠的第一透光图案1421和与接触垫1201及接触垫1202的间隙重叠的第二透光图案1422，在显示区，第三掩模板1042包括与平坦化层的过孔重叠的第一透光图案1421及非透光图案1423。即第三掩模板1042为灰色调掩模板或半色调掩模板。光刻胶为正性光刻胶，对应地，第一透光图案1421的透光率大于第二透光图案1422的透光率。在曝光过程可以在使得光刻胶1040中与第一透光图案1421对应的部分被完全曝光的情况下，光刻胶1040中与第二透光图案1422对应的部分被部分曝光，光刻胶1040中与非透光图案1423对应的部分未被曝光。
如图7K所示，对光刻胶1040进行显影，光刻胶1040的被曝光的部分去除，即，在邦定区中，与接触垫1200重叠的光刻胶1040被去除，剩余的光刻胶1040被减薄，在显示区中，与平坦化层的过孔重叠的光刻胶被去除。显影后，光刻胶1040形成为第三光刻胶图案1042。对第一绝缘材料层1710进行刻蚀以去除接触垫重叠的绝缘材料层，以及在显示区中形成过孔1271。
如图7L所示，去除邦定区第三光刻胶图案1042，然后，对邦定区中剩余的第一绝缘材料层1710进行刻蚀并控制刻蚀厚度，去除与所述接触垫的间隙重叠的绝缘材料层的背离所述衬底基板的部分厚度，以形成高度大于接触垫的第一绝缘层1310。然后，去除显示区中的光刻胶1042，通过刻蚀并控制刻蚀厚度形成作为平坦化层的第一绝缘层1310。根据对邦定区中剩余的第一绝缘材料层1710厚度的控制以形成位于邦定区中的第一绝缘层1310，可以得到如图5C所示的实施例的显示基板。为了控制对于第一绝缘材料层1710的刻蚀厚度，可以采用刻蚀终点检测仪等来进行实时监控，或者根据实验数据来调节刻蚀液浓度和/或刻蚀时间。
之后，例如可以在显示区的平坦化层之上继续后续工序，包括形成发光元件、像素限定层、封装层等，这里不再赘述。
在利用上述制备方法获得的显示基板中，第一绝缘层可以降低或者消除接触垫与接触垫之间的间隙的段差，在邦定工艺中，压头施加在第一绝缘层的表面和接触垫的表面上的力分布均匀(例如压强相等)，即，由压头施加 在接触垫以及接触垫之间的间隙处的压力分布均匀，显示基板(其中的邦定区)不会在邦定工艺中因为受力不均而损坏，在实际生产中，提高显示基板的良率。
本公开描述的各个实施例以及技术方案可以描述为如下列出的示例。
一种显示基板，包括：衬底基板，包括显示区和位于所述显示区至少一侧的邦定区；多个接触垫，位于所述邦定区且彼此具有间隙；第一绝缘层，位于所述接触垫之间的间隙，且配置为露出所述接触垫的背离所述衬底基板的表面。
所述第一绝缘层的背离所述衬底基板的表面高于所述接触垫的背离所述衬底基板的表面或与所述接触垫的背离所述衬底基板的表面位于同一平面。
所述多个接触垫排布为至少一行，所述行的方向与所述显示区的面向所述邦定区的侧边的延伸方向平行，所述第一绝缘层的至少部分位于一行的多个所述接触垫之间的间隙。
显示基板还包括多条引线，其中，所述多条引线与所述多个接触垫一一对应电连接，且所述多条引线每条的一端部与所述多个接触垫中对应的一个电连接且另一端部向所述显示区延伸。
所述多个接触垫排布为至少两行，所述第一绝缘层的至少部分位于不同行的所述接触垫之间的间隙。
所述至少两行包括第一行和位于所述第一行和所述显示区之间的第二行，以及与位于所述第一行的所述接触垫连接的引线的位于所述第二行的部分，位于所述第二行的所述接触垫的间隙且由所述第一绝缘层覆盖。
对于彼此电连接的所述引线和所述接触垫，所述引线的与所述接触垫电连接的端部与所述接触垫重叠且位于所述接触垫和所述衬底基板之间。
与位于所述第一行的所述接触垫连接的引线包括彼此相邻的第一组数据引线和第二组数据引线，所述第一组数据引线和所述第二组数据引线相对于所述衬底基板位于不同层中。
显示基板还包括位于所述接触垫和所述引线之间的第二绝缘层，其中，所述第二绝缘层中设置有过孔，所述引线通过所述过孔与对应的所述接触垫连接。
显示基板还包括位于所述显示区的子像素中的薄膜晶体管、发光元件和 层间介质层，其中，所述薄膜晶体管的源极和漏极中之一与所述发光元件电连接；所述层间介质层位于所述薄膜晶体管的有源层和源漏电极层之间，所述第二绝缘层与所述层间介质层配置为同层设置。
显示基板还包括位于显示区的子像素中的薄膜晶体管、发光元件以及覆盖所述薄膜晶体管的平坦化层，其中，所述薄膜晶体管的源极和漏极中之一与所述发光元件电连接；所述第一绝缘层与所述平坦化层配置同层设置。
显示装置包括如上所述的显示基板。
一种显示基板的制备方法，包括：提供衬底基板，所述衬底基板包括显示区和位于所述显示区至少一侧的邦定区；在所述邦定区中形成多个彼此间隔的接触垫；在多个所述接触垫的间隙形成第一绝缘层，其中，所述第一绝缘层形成为露出所述接触垫的背离所述衬底基板的表面。
所述第一绝缘层形成为，使得所述第一绝缘层背离所述衬底的表面高于所述接触垫的背离所述衬底基板的表面或与所述接触垫的背离所述衬底基板的表面基本位于同一平面。
所述在所述接触垫之间形成所述第一绝缘层包括：形成所述接触垫之后，在所述衬底基板上沉积第一材料层以平坦化所述显示基板的表面；对所述第一材料层进行构图工艺，以使得所述第一材料层的位于所述显示区的部分形成为平坦化层，去除所述第一材料层的与所述接触垫重叠的部分，并且减薄所述第一材料层的位于所述邦定区且位于所述接触垫之间的间隙的部分以形成所述第一绝缘层。
所述对所述第一材料层进行构图工艺包括：在所述第一材料层上涂覆光刻胶；提供第一掩模板以对所述光刻胶进行曝光、显影，以去除与所述光刻胶的与所述接触垫重叠的部分；以剩余的光刻胶为掩模构图所述第一材料层，以去除所述第一材料层的与所述接触垫重叠的部分；去除所述邦定区中剩余的光刻胶；以及在所述邦定区，刻蚀所述第一材料层的位于所述接触垫的间隙且背离所述衬底基板的表面部分，剩余的所述第一材料层形成为所述第一绝缘层。
所述对所述第一材料层进行构图工艺包括：在所述第一材料层上涂覆光刻胶；利用灰色调掩模板或半色调掩模板对所述光刻胶进行曝光，对曝光之后的光刻胶进行显影后，以去除所述光刻胶的与所述接触垫重叠的部分并减薄所述光刻胶与所述接触垫的间隙重叠的部分；以及在所述邦定区，刻蚀所 述第一材料层，以去除所述第一材料层的与所述接触垫重叠的部分，进行灰化工艺以去除所述光刻胶与所述接触垫的间隙重叠的部分，并去除与所述接触垫的间隙重叠的第一材料层的背离所述衬底基板的部分厚度。
所述第一材料层包括光敏树脂材料，所述对所述第一材料层进行构图工艺还包括：使用灰色调掩模板或半色调掩模板对所述第一材料层进行曝光，对曝光之后的光刻胶进行显影后，以使得所述第一材料层的位于所述显示区的部分形成为所述平坦化层，去除所述第一材料层的与所述接触垫重叠的部分，并且减薄所述第一材料层的位于所述邦定区且位于所述接触垫之间的间隙的部分以形成所述第一绝缘层。
形成所述接触垫包括：在所述衬底基板上沉积第一导电材料薄膜并对其进行构图工艺，其中，所述第一导电材料薄膜的位于所述显示区的部分形成为第一导电层，所述第一导电材料薄膜的位于所述邦定区的部分形成为所述接触垫。
制备方法还包括：在沉积所述第一导电材料薄膜之前，在所述邦定区的部分形成引线，其中，所述引线的第一端部延伸至所述显示区，并且在形成所述接触垫之后，所述引线的第二端部与所述接触垫重叠且连接。
在所述邦定区的部分形成所述引线包括：在所述邦定区分别形成相对于所述衬底基板分别位于不同层的所述第一组数据引线和第二组数据引线。
制备方法还包括：在形成所述引线之后且沉积所述第一导电材料薄膜之前，在所述衬底基板上沉积绝缘材料薄膜以覆盖所述第二导电层和所述引线；在所述邦定区，构图所述绝缘材料薄膜以形成暴露所述引线的所述第二端部的过孔；以及沉积所述第一导电材料薄膜之后，所述第一导电材料薄膜通过所述过孔与所述引线连接；其中，所述绝缘材料薄膜的位于所述显示区的部分为层间介质层，所述绝缘材料薄膜的位于所述邦定区的部分为第二绝缘层。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互 组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (26)

  1. 一种显示基板，包括：
    衬底基板，包括显示区和位于所述显示区至少一侧的邦定区；
    多个子像素，位于所述显示区中；
    多条数据线，位于所述显示区中，配置为所述多个子像素提供数据信号；
    多条数据引线，位于所述邦定区中且与所述多条数据线电连接；
    至少一组接触垫，位于所述邦定区中，其中，所述至少一组接触垫包括第一组接触垫和第二组接触垫，所述第一组接触垫和所述第二组接触垫分别包括多个接触垫，所述第二组接触垫位于所述第一组接触垫远离所述显示区的一侧，所述多条数据引线与所述第一组接触垫和所述第二组接触垫电连接；
    第一绝缘层，位于所述邦定区，所述第一绝缘层位于所述多个接触垫之间的间隙并覆盖所述多个接触垫的边缘，且被配置为露出所述多个接触垫的背离所述衬底基板的表面。
  2. 根据权利要求1所述的显示基板，其中，所述第一绝缘层远离所述衬底基板一侧的表面距离所述衬底基板的垂直距离不小于所述多个接触垫远离所述衬底基板一侧的表面距离所述衬底基板的垂直距离。
  3. 根据权利要求1-2任一所述的显示基板，其中，所述第一绝缘层的至少部分位于所述第一组接触垫相邻的接触垫之间的间隙中。
  4. 根据权利要求1-2任一所述的显示基板，其中，所述第一绝缘层的至少部分位于所述第二组接触垫中相邻的接触垫之间的间隙中。
  5. 根据权利要求1-4任一所述的显示基板，其中，所述第一绝缘层的至少部分位于所述第一组接触垫中相邻的接触垫之间的间隙中和位于所述第二组接触垫中相邻的接触垫之间的间隙中。
  6. 根据权利要求1-5任一所述的显示基板，其中，所述第一组接触垫的多个接触垫排布为至少第一行，所述第二组接触垫的多个接触垫排布为至少第二行；
    所述第一行和所述第二行的行方向与所述显示区的面向所述邦定区的侧边的延伸方向平行，
    所述第一绝缘层的至少部分位于所述第一行与所述第二行之间的间隙。
  7. 根据权利要求6所述的显示基板，其中，所述第一绝缘层的多个开口每个具有侧壁，且所述多个开口中至少一个的侧壁具有相对于所述衬底基板的坡度角的取值范围为40度至60度。
  8. 根据权利要求6或7所述的显示基板，其中，所述多个接触垫中至少一个具有的长度的取值范围为650微米至750微米及具有的宽度的取值范围为34微米至42微米。
  9. 根据权利要求6-8任一所述的显示基板，其中，所述多个子像素中至少一个包括薄膜晶体管、平坦化层以及发光元件，
    所述平坦化层位于所述薄膜晶体管远离所述衬底基板一侧，以覆盖所述薄膜晶体管，
    所述发光元件位于所述平坦化层远离所述衬底基板一侧，
    所述平坦化层包括第一平坦层过孔，
    所述薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所处衬底基板一侧的栅极，以及位于所述栅极远离所述衬底基板一侧的源极和漏极，并且所述源极和所述漏极中之一通过所述第一平坦层过孔与所述发光元件电连接；
    所述第一绝缘层与所述平坦化层为同层设置。
  10. 根据权利要求9所述的显示基板，其中，相对于所述衬底基板，在所述邦定区中的所述第一绝缘层的厚度小于所述显示区域中的所述平坦化层的厚度。
  11. 根据权利要求9或10所述的显示基板，其中，所述多个接触垫每个包括至少一个金属层，所述至少一个金属层包括第一金属层，所述第一金属层与所述源极和所述漏极同层设置。
  12. 根据权利要求9-11任一所述的显示基板，其中，所述多条数据引线包括第一组数据引线和第二组数据引线，所述第一组数据引线与所述第一组接触垫一一对应电连接，所述第二组数据引线与所述第二组接触垫一一对应电连接，并且相对于所述衬底基板，所述第一组数据引线和所述第二组数据引线分别位于不同层。
  13. 根据权利要求12所述的显示基板，其中，所述多个子像素中所 述至少一个还包括存储电容，所述存储电容包括两个电容电极，
    所述第一组数据引线与所述栅极同层设置，且所述第二组数据引线与所述存储电容的两个电容电极之一同层设置；或者，所述第二组数据引线与所述栅极同层设置，且所述第一组数据引线与所述存储电容的两个电容电极之一同层设置。
  14. 根据权利要求12或13所述的显示基板，还包括：
    邦定区层间绝缘层，位于所述邦定区中，并且位于所述多个接触垫与所述引线之间和所述第一绝缘层与所述衬底基板之间；
    邦定区第一栅绝缘层，位于所述绑定区中，且位于所述邦定区层间绝缘层靠近所述衬底基板的一侧；以及
    邦定区第二栅绝缘层，位于所述邦定区中，且位于所述邦定区第一栅绝缘层及所述邦定区层间绝缘层之间，与所述邦定区层间绝缘层层叠；
    其中，所述第一组接触垫通过穿过所述邦定区层间绝缘层中的多个第一接触垫过孔与所述第一组数据引线一一对应电连接，所述第二组接触垫通过穿过所述邦定区层间绝缘层和所述邦定区第二栅绝缘层中的多个第二接触垫过孔与所述第二组数据引线一一对应电连接；或者，所述第二组接触垫通过穿过所述邦定区层间绝缘层中的多个第二接触垫过孔与所述第二组数据引线一一对应电连接，所述第一组接触垫通过穿过所述邦定区层间绝缘层和所述邦定区第二栅绝缘层中的多个第一接触垫过孔与所述第一组数据引线一一对应电连接。
  15. 根据权利要求14所述的显示基板，其中，所述多个子像素中所述至少一个还包括显示区层间绝缘层、显示区第一栅绝缘层以及显示区第二栅绝缘层，
    所述显示区层间绝缘层、显示区第一栅绝缘层和所述显示区第二栅绝缘层分别与所述邦定区层间绝缘层、邦定区第一栅绝缘层和所述邦定区第二栅绝缘层同层设置；
    所述显示区层间绝缘层位于所述栅极与所述源极和所述漏极之间，所述显示区第一栅绝缘层位于所述显示区层间绝缘层靠近所述衬底基板的一侧，所述显示区第二栅绝缘层位于所述显示区层间绝缘层与所述显示区第一栅绝缘层之间；
    所述两个电容电极包括第一电容电极和第二电容电极，所述第一电容 电极与所述栅极同层设置，所述第二电容电极设置在所述显示区层间绝缘层与所述显示区第二栅绝缘层之间。
  16. 根据权利要求15所述的显示基板，其中，所述第一组数据引线与所述第一电容电极和所述栅极同层设置，且所述第二组数据引线与所述第二电容电极同层设置，或者
    所述第二组数据引线与所述第一电容电极和所述栅极同层设置，且所述第一组数据引线与所述第二电容电极同层设置。
  17. 根据权利要求15所述的显示基板，其中，所述第一绝缘层位于所述第一组接触垫和所述第二组接触垫中相邻的接触垫之间的间隙中的表面具有凹陷部分，或者
    所述第一绝缘层位于所述第一行与所述第二行之间的间隙中的表面具有凹陷部分。
  18. 根据权利要求1-17任一所述的显示基板，其中，与所述第二组接触垫中至少一个接触垫电连接的数据引线的经过所述第一组接触垫的部分，位于所述第一组接触垫中相邻的接触垫的间隙中且由所述第一绝缘层覆盖。
  19. 根据权利要求1-18任一所述的显示基板，其中，所述第一组数据引线中至少一条数据引线相对于所述显示基板的边缘倾斜延伸，或者
    所述第二组数据引线中至少一条数据引线相对于所述显示基板的所述边缘倾斜延伸。
  20. 根据权利要求19所述的显示基板，其中，所述第一组数据引线中至少两条数据引线相对于所述显示基板的边缘倾斜延伸，且所述第一组数据引线中的所述至少两条数据引线相对于所述显示基板的边缘相同旋向的夹角相同或互补。
  21. 根据权利要求19或20所述的显示基板，其中，所述第二组数据引线中至少两条数据引线相对于所述显示基板的所述边缘倾斜延伸，且所述第二组数据引线中的所述至少两条数据引线相对于所述显示基板的边缘相同旋向的夹角相同或互补。
  22. 根据权利要求1-21任一所述的显示基板，其中，所述第一组接触垫至少一个接触垫相对于所述显示基板的边缘倾斜延伸，或者
    所述第二组接触垫中至少一个相对于所述显示基板的所述边缘倾斜 延伸。
  23. 根据权利要求22所述的显示基板，其中，所述第一组接触垫至少两个接触垫相对于所述显示基板的边缘倾斜延伸，且所述第一组接触垫中所述至少两个接触垫相对于所述显示基板的边缘相同旋向的夹角相同或互补。
  24. 根据权利要求22或23所述的显示基板，其中，所述第二组接触垫至少两个接触垫相对于所述显示基板的边缘倾斜延伸，且所述第二组接触垫中所述至少两个接触垫相对于所述显示基板的边缘相同旋向的夹角相同或互补。
  25. 一种显示装置，包括如权利要求1-24中任一项所述的显示基板。
  26. 一种显示基板的制备方法，包括：
    提供衬底基板，其中，所述衬底基板包括显示区和位于所述显示区至少一侧的邦定区；
    在所述显示区中形成多个子像素以及多条数据线，其中，所述多条数据线配置为所述多个子像素提供数据信号；
    在所述邦定区中形成多条数据引线；
    在所述邦定区中形成至少一组接触垫，其中，所述至少一组接触垫包括第一组接触垫和第二组接触垫，所述第一组接触垫和所述第二组接触垫分别包括多个接触垫，所述第二组接触垫位于所述第一组接触垫远离所述显示区的一侧，所述多条数据引线与所述第一组接触垫和所述第二组接触垫一一对应电连接；
    在所述邦定区中形成第一绝缘层，其中，所述第一绝缘层位于所述邦定区且位于所述多个接触垫之间的间隙并覆盖所述多个接触垫的边缘，且被配置为露出所述多个接触垫的背离所述衬底基板的表面。
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