WO2021189232A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2021189232A1
WO2021189232A1 PCT/CN2020/080830 CN2020080830W WO2021189232A1 WO 2021189232 A1 WO2021189232 A1 WO 2021189232A1 CN 2020080830 W CN2020080830 W CN 2020080830W WO 2021189232 A1 WO2021189232 A1 WO 2021189232A1
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WIPO (PCT)
Prior art keywords
sub
strip
conductive
conductive strip
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/080830
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English (en)
French (fr)
Inventor
张波
董向丹
王蓉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP20926999.2A priority Critical patent/EP4131371A4/en
Priority to CN202080000350.1A priority patent/CN113728429B/zh
Priority to PCT/CN2020/080830 priority patent/WO2021189232A1/zh
Priority to US17/433,020 priority patent/US12471455B2/en
Publication of WO2021189232A1 publication Critical patent/WO2021189232A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate and a display device.
  • the organic light emitting diode display device can realize a narrow frame by adopting technologies such as Chip On Film (COF) or COP (Chip On Plastic).
  • COF Chip On Film
  • COP Chip On Plastic
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • An embodiment of the present disclosure provides a display substrate, including: a base substrate including a display area and a bonding area located on at least one side of the display area; a plurality of sub-pixels located in the display area; a plurality of data lines, Are located in the display area and connected to the plurality of sub-pixels to provide data signals to the plurality of sub-pixels; a plurality of data leads are located in the bonding area and are electrically connected to the plurality of data lines; at least A set of conductive bars located in the bonding area and on a side of the plurality of data leads away from the display area, the at least one set of conductive bars includes a plurality of conductive bars, and at least of the plurality of conductive bars One includes a first sub-conducting strip and a second sub-conducting strip.
  • the second sub-conducting strip is located on the side of the first sub-conducting strip away from the base substrate; an interlayer insulating layer is located in the first sub-conducting strip. Between the conductive strip and the second sub-conductive strip.
  • the first sub-conductive strip is electrically connected to one of the plurality of data leads;
  • the interlayer insulating layer includes a strip-shaped hole extending along the extending direction of the plurality of conductive strips, and the strip-shaped hole is covered by It is configured to expose the first sub-conductive strip, so that the second sub-conductive strip is electrically connected to the first sub-conductive strip.
  • the aspect ratio of the strip-shaped hole is not less than 5.
  • the width of the strip-shaped hole is in the range of 3 to 5 microns.
  • the slope angle between the inner side surface of the strip hole and the base substrate ranges from 30° to 40°.
  • the length of the strip-shaped hole is 1-10 micrometers smaller than the length of the second sub-conductive strip in the extending direction.
  • the strip-shaped hole is a continuous strip-shaped hole extending along an extension direction of at least one of the plurality of conductive strips.
  • the strip-shaped hole includes a plurality of sub-strip-shaped holes arranged along the extension direction of at least one of the plurality of conductive strips, and two adjacent sub-strips in the plurality of sub-strip-shaped holes There is an interval between the shaped holes, and the length of at least one of the plurality of sub-strip shaped holes is in the range of 15-30 microns.
  • the plurality of sub-strip-shaped holes are uniformly arranged along the extension direction of at least one of the plurality of conductive strips.
  • the second sub-conductive strip includes a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence.
  • the material of the first conductive layer and the third conductive layer includes titanium, and the material of the second conductive layer includes aluminum.
  • the at least one set of conductive stripes includes two sets of conductive stripes, and the two sets of conductive stripes are arranged in a direction away from the display area.
  • At least one of the plurality of sub-pixels includes a pixel circuit and a light-emitting element, and the pixel circuit is located between the base substrate and the light-emitting element;
  • the light-emitting element includes sequentially stacked The first electrode, the light-emitting layer and the second electrode are provided, the second electrode is located on the side of the light-emitting layer facing the base substrate;
  • the pixel circuit includes at least one thin film transistor, and the thin film transistor includes The gate on the base substrate, the source and the drain located on the side of the gate away from the base substrate, the source or the drain of the thin film transistor is electrically connected to the second electrode; the gate The pole and the first sub-conductive strip are arranged in the same layer.
  • the plurality of data lines extend in a first direction
  • the display substrate further includes: a plurality of gate lines extending in a second direction, and the plurality of data lines are located in the plurality of gate lines.
  • the gate line is away from the side of the base substrate, and the first direction and the second direction intersect.
  • the second sub-conductive strip is arranged in the same layer as the plurality of data lines, the source electrode or the drain electrode.
  • At least one of the plurality of sub-pixels further includes a storage capacitor
  • the storage capacitor includes two capacitor electrodes, at least one of the plurality of data leads, and two of the storage capacitors One of the capacitor electrodes is arranged on the same layer as the gate electrode.
  • the extending direction of at least one of the plurality of conductive strips is not parallel to the first direction and the second direction.
  • the maximum width of the first sub-conductive strip is smaller than the maximum width of the second sub-conductive strip, and the strip-shaped hole is in the second direction.
  • the maximum width in the direction is smaller than the maximum width of the first sub-conductive strip.
  • the two groups of conductive strips include a first conductive strip group and a second conductive strip group, and both the first conductive strip group and the second conductive strip group include A row of conductive strips arranged in two directions, the first conductive strip group is located on a side of the second conductive strip group close to the display area.
  • the plurality of data leads includes a plurality of first data leads connected to the first conductive strip group and a plurality of second data leads connected to the second conductive strip group ,
  • the plurality of first data leads and the plurality of second data leads are alternately arranged, and each of the plurality of second data leads passes through between adjacent conductive strips in the first conductive strip group interval.
  • An embodiment of the present disclosure provides a display device including a circuit structure and the above-mentioned display substrate.
  • the circuit structure includes a third sub-conductive strip, and the third sub-conductive strip is electrically connected to the second sub-conductive strip through a conductive glue to write a signal to the second sub-conductive strip.
  • FIG. 1 is a schematic diagram showing a partial planar structure of a strip electrode in a bonding area of a substrate
  • Fig. 2 is a schematic diagram of a partial cross-sectional structure taken along the line AA' shown in Fig. 1;
  • FIG. 3 is a schematic diagram of a planar structure of a display substrate provided by an embodiment of the disclosure.
  • FIG. 4 is a partial enlarged schematic view of the bonding area in the display substrate shown in FIG. 3;
  • FIG. 5 is an enlarged view of part C shown in FIG. 4 in an example
  • Fig. 6 is a partial cross-sectional structural diagram taken along BB' shown in Fig. 5;
  • FIG. 7 is a schematic diagram of a partial cross-sectional structure of a display area in the display substrate shown in FIG. 3;
  • Fig. 8 is an enlarged view of the part C shown in Fig. 3 in another example.
  • FIG. 9 is a schematic diagram of a partial cross-sectional structure of a display device according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram showing a partial planar structure of a strip electrode in a bonding area in a substrate
  • FIG. 2 is a schematic diagram of a partial cross-sectional structure taken along the line AA' shown in FIG. 1.
  • the bonding area (non-display area) of the display substrate includes a plurality of strip-shaped electrodes (contact pads), and each strip-shaped electrode includes a first sub-conductive strip 10 and a second sub-conductive strip that are electrically connected.
  • the second sub-conductive strip 20 is located on the side of the first sub-conductive strip 10 away from the base substrate 40, the extension direction of the first sub-conductive strip 10 is the same as the extension direction of the second sub-conductive strip 20, and the first sub-conductive strip 10
  • An interlayer insulating layer 30 is provided between the conductive strip 10 and the second sub-conductive strip 20.
  • the interlayer insulating layer 30 is provided with a via 31 for exposing the first sub-conductive strip 10 so as to be located in the interlayer insulating layer 30 ( Figure 2 only shows the first sub-conductive strip 10 and the second sub-conductive strip 20).
  • the second sub-conductive strip 20 on the interlayer insulating layer 30) is electrically connected to the first sub-conductive strip 10 through the via 31.
  • the side of the second sub-conductive strip 20 away from the first sub-conductive strip 10 is provided with a passivation layer 50 and a flat layer 60.
  • the strip-shaped electrodes are configured to pass an anisotropic conductive adhesive and a chip-on-film (COF) circuit structure. Electrode bonding.
  • the second sub-conductive strip 20 includes a first metal layer 21, a second metal layer 22, and a third metal layer 23 that are stacked, and the materials of the first metal layer 21 and the third metal layer 23 can be Including titanium, the material of the second metal layer 22 may include aluminum.
  • the inventor of the present application found that the size of the via hole 31 parallel to the base substrate 40 is 2.1 ⁇ m to 2.5 ⁇ m, which is relatively small.
  • the inner side surface of the via hole 31 is formed as a slope, and the included angle a1 (shown in FIG. 2) between the inner side surface and the base substrate 40 is greater than 50°, that is, the slope angle a1 of the slope formed by the inner surface of the via hole 31 is greater than 50°, for example, 70°-80°.
  • the second sub-conductive strip 20 deposited in the via hole 31 is at the edge of the via hole 31. Fracture occurred everywhere.
  • the first metal layer 21 farthest from the base substrate 40 in the second sub-conductive strip 20 is prone to breakage at the edge position of the via 31, resulting in the second metal layer 22 being exposed, for example, the metal aluminum layer is exposed.
  • the organic light emitting element is formed on the side of the flat layer 60 away from the base substrate 40
  • the anode film layer is formed in both the display area and the non-display area.
  • the acid etching solution for etching the anode film layer is recycled, and the acid etching solution is There is a large amount of silver ions.
  • the aluminum in the second metal layer 22 will interact with the silver in the acid etching solution.
  • the ions will undergo a displacement reaction and silver will be precipitated.
  • the precipitated silver will flow irregularly, resulting in the formation of silver particles on the display substrate.
  • the silver particles may cause a short circuit between two adjacent strip electrodes, affect the normal lighting of the panel including the above-mentioned display substrate, and also generate a Mura phenomenon, which reduces the yield of the product.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate includes: a base substrate, a plurality of sub-pixels located on the base substrate, a plurality of data lines, a plurality of data leads, at least one set of conductive bars, and an interlayer insulating layer.
  • the base substrate includes a display area and a bonding area located on at least one side of the display area; multiple sub-pixels are located in the display area; multiple data lines are located in the display area and connected to the multiple sub-pixels to provide data signals to the multiple sub-pixels; Multiple data leads are located in the bonding area and electrically connected to multiple data lines; at least one set of conductive bars is located in the bonding area and on the side of the multiple data leads away from the display area, and at least one set of conductive bars includes multiple conductive bars , At least one of the plurality of conductive strips includes a first sub-conductive strip and a second sub-conductive strip.
  • the second sub-conductive strip is located on the side of the first sub-conductive strip away from the base substrate; the interlayer insulating layer is located in the first sub-conductive strip. Between the conductive strip and the second sub-conductive strip.
  • the first sub-conductive strip is electrically connected to one of the plurality of data leads;
  • the interlayer insulating layer includes a strip-shaped hole extending along the extending direction of the plurality of conductive strips, and the strip-shaped hole is configured to expose the first sub-conductive strip to The second sub-conductive strip is electrically connected to the first sub-conductive strip.
  • the present disclosure by providing a strip hole exposing the first sub-conductive strip in the interlayer insulating layer, it is possible to ensure a larger contact area between the first sub-conductive strip and the second sub-conductive strip, and to reduce the The second sub-conductive strip at the edge of the strip hole has the possibility of breaking, thereby improving the yield of the display substrate.
  • FIG. 3 is a schematic plan view of a display substrate according to an embodiment of the present disclosure
  • FIG. 4 is a partial enlarged schematic view of the bonding area in the display substrate shown in FIG. 3
  • FIG. 5 is an example of the part C shown in FIG. 4
  • Fig. 6 is a partial cross-sectional structural diagram taken along BB' shown in Fig. 5.
  • the display substrate provided by the embodiment of the present disclosure includes a base substrate 100 and a plurality of conductive strips 200 on the base substrate 100, and each conductive strip 200 includes a first sub-conductive strip 210 arranged in a stack.
  • the second sub-conducting strip 220, the second sub-conducting strip 220 is located on the side of the first sub-conducting strip 210 away from the base substrate 100.
  • the first sub-conducting strip 210 and the second sub-conducting strip 220 extend in the same direction.
  • An interlayer insulating layer 301 is provided between the sub-conductive strip 210 and the second sub-conductive strip 220.
  • the base substrate 100 includes a display area 110 and a peripheral area located at the periphery of the display area 110.
  • the peripheral area includes a bonding area 120 for bonding the display substrate and a circuit structure such as a chip on film (COF).
  • COF chip on film
  • the conductive strip 200 including the first sub-conductive strip 210 and the second sub-conductive strip 220 is located in the bonding area 120.
  • the orthographic projection of the second sub-conductive strip 220 on the base substrate 100 and the first sub-conductive strip are on the base substrate 210
  • the orthographic projection on 100 overlaps.
  • the interlayer insulating layer 301 includes a strip hole 310 extending along the extending direction of the conductive strip 200, and the strip hole 310 is configured to expose the first sub-conductive strip 210 so that the second sub-conductive strip 210 is exposed.
  • the conductive strip 220 is electrically connected to the first sub-conductive strip 210.
  • the present disclosure by providing a strip hole exposing the first sub-conductive strip in the interlayer insulating layer, it is possible to ensure a larger contact area between the first sub-conductive strip and the second sub-conductive strip, and to reduce the The second sub-conductive strip at the edge of the strip hole has the possibility of breaking, thereby improving the yield of the display substrate.
  • the planar shape of the above-mentioned conductive strips parallel to the base substrate is a strip shape, and the extension direction of the conductive strips is the extension direction of the long sides in the planar shape.
  • the above-mentioned strip-shaped hole has a strip shape parallel to the plane shape of the base substrate, and the length and width of the subsequent strip-shaped hole refer to the length and width of the plane shape parallel to the base substrate.
  • a plurality of strip-shaped holes are provided in the interlayer insulating layer, and the plurality of strip-shaped holes correspond to the plurality of conductive strips one-to-one, and each strip-shaped hole is used for exposing the first sub-conductive strip in each conductive strip.
  • the material of the interlayer insulating layer 301 may include insulating materials such as silicon oxide or silicon nitride.
  • the display area 110 is provided with a data line 400 extending in a first direction (Y direction) and a gate line 500 extending in a second direction (X direction).
  • the data line 400 is located far away from the gate line 500.
  • An interlayer insulating layer 301 may be provided on one side of the base substrate 100 between the data line 400 and the gate line 500.
  • first direction and the second direction intersect, for example, the first direction and the second direction are perpendicular.
  • first direction and the second direction in the embodiments of the present disclosure may be interchanged.
  • the extending direction of the conductive strip 200 is not parallel to the first direction and the second direction.
  • the extending direction of the conductive strip 200 and the first direction may have an included angle of, for example, 8°-10°.
  • the end of the conductive strip 200 close to the display area 110 is closer to the center line of the display substrate extending in the first direction than the end of the conductive strip 200 away from the display area, thereby facilitating the connection with the data line.
  • the conductive bars 200 located on both sides of the center line extending along the first direction of the display substrate may be symmetrically distributed with respect to the center line.
  • the bonding area 120 is located at one side of the display area 110 and is used to electrically connect the external circuit and the display substrate through the bonding process.
  • the external circuit may include a chip-mounted flexible circuit board (for example, Chip On Film, COF for short), and a control chip or a driving chip, etc., are arranged on the flexible circuit board.
  • the bonding area can also be used for direct electrical connection with the chip.
  • the conductive strip 200 located in the bonding area 120 may be a contact pad that is directly bonded to the driving chip, and the base substrate 100 may be a flexible substrate. Bending away from the back of the data line 400 can achieve a narrow frame.
  • the conductive strip 200 located in the bonding area 120 may also be a contact pad for bonding with the flip chip film.
  • the data line 400 may be connected to a plurality of conductive bars 200 in a one-to-one correspondence through a plurality of data leads 410 located in the bonding area 120, so that the data line 400 is electrically connected to a circuit structure such as a driving chip or a flexible circuit board.
  • the plurality of conductive strips 200 includes a first conductive strip group 2201 and a second conductive strip group 2202, and both the first conductive strip group 2201 and the second conductive strip group 2202 include a
  • the conductive strips 200 are arranged in a row, and the first conductive strip group 2201 is located on the side of the second conductive strip group 2202 close to the display area 110.
  • the conductive strips are arranged in the second direction as an example of two rows, but it is not limited to this, and can also be one or more rows, that is, the conductive strips can be arranged in one or more conductive strip groups.
  • a row of conductive strips that is, a group of conductive strips, can be arranged.
  • each second data lead 412 passes through the adjacent conductive strips in the first conductive strip group 2201.
  • the interval between 200 is connected to the data line 400.
  • two conductive strip groups are provided, and each second data lead passes through the interval between adjacent conductive strips in the first conductive strip group to be connected to the data line, which can reduce the difference between two adjacent data leads. Avoid fan-shaped wiring areas as far as possible to achieve a narrow frame design.
  • the side of the first conductive strip group facing the second conductive strip group can also be provided with a third data lead (not shown in the figure), and the third data lead is away from the conductive strips in the first conductive strip group from the display area.
  • One side extends to pass through the space between two adjacent conductive strips in the second conductive strip group, that is, along the second direction, the third data lead and the second data lead are alternately arranged to ensure that the first conductive strip group and The data leads between the second conductive strip groups are evenly arranged.
  • the aforementioned third data lead is only connected to the conductive strips in the first conductive strip group.
  • the side of each conductive strip away from the display area may be provided with an anti-static part.
  • the anti-static part includes the first conductive strip away from the display area.
  • a part and the active semiconductor layer are connected to the active semiconductor layer to increase resistance and play an anti-static function.
  • the second sub-conductive strip 220 and the data line 400 are in the same layer.
  • the second sub-conductive strip 220 and the data line 400 can be arranged in the same layer and have the same material.
  • the "same layer” here and later refers to the relationship between multiple film layers formed by the same material after the same step (for example, one-step patterning process).
  • the “same layer” here does not always mean that multiple film layers have the same thickness or that multiple film layers have the same height in the cross-sectional view.
  • the first sub-conductive bar 210 and the gate line 500 may be of the same layer and the same material.
  • first data lead 411 may be arranged in the same layer as the first sub-conductive strip 210 of the conductive strip 200 in the first conductive strip group 2201, and at least a part of the second data lead 412 may be the same layer as the second conductive strip group.
  • the first sub-conductive strips 210 of the conductive strips 200 in 2202 are arranged in the same layer. That is, each conductive strip 200 can be connected to the corresponding data line 400 by connecting the first sub-conductive strip 210 to the data lead 410 to realize the circuit structure to provide data signals for the data line.
  • a passivation layer 610 and a flat layer 620 are provided on the side of the second sub-conductive strip 220 away from the base substrate 100.
  • the passivation layer 610 and the planarization layer 620 are provided with openings 621 exposing the second sub-conducting strip 220.
  • the electrode strips in the circuit structure such as a chip on film (COF) realize bonding with the second sub-conducting strip 220 through the opening 621. .
  • COF chip on film
  • the passivation layer 610 and the flat layer 620 cover the peripheral edges of the second sub-conductive strip 220 to prevent the peripheral edges of the second sub-conductive strip 220 from being damaged in the subsequent process of manufacturing the display substrate.
  • the size of the first sub-conductive strip 210 is smaller than the size of the second sub-conductive strip 220, that is, in the second direction, the width of the first sub-conductive strip 210 It is smaller than the width of the second sub-conductive bar 220.
  • the second sub-conductive strip 220 covers the edge of the first sub-conductive strip 210, reducing the overlap between the passivation layer 610 and the flat layer 630 at the edge of the second sub-conductive strip 220 and the first sub-conductive strip 210 This prevents the thickness of the film layer covered by the passivation layer 610 and the flat layer 620 located at the edge of the second sub-conductive strip 220 from being large and affecting the thickness of the display substrate.
  • FIG. 7 is a schematic diagram of a partial cross-sectional structure of the display area in the display substrate shown in FIG. 3.
  • the display substrate further includes a light-emitting element 700 located in the display area 110 of the base substrate 100 and a pixel circuit 1120 that drives the light-emitting element 700.
  • the pixel circuit is located between the light-emitting element and the base substrate.
  • the pixel circuit can include thin film transistors, storage capacitors, etc., and can be implemented in various types, such as 2T1C type (that is, including two thin film transistors and one storage capacitor), and can also include more on the basis of 2T1C type.
  • the transistors and/or capacitors may have functions of compensation, reset, light emission control, detection, etc.
  • the embodiments of the present disclosure do not impose limitations on the pixel circuit.
  • the thin film transistor directly electrically connected to the light-emitting element may be a driving transistor, a light-emitting control transistor, or the like.
  • the display substrate further includes a buffer layer 1121 located on the base substrate 100, and the pixel circuit 1120 includes an active layer 1122 located on the buffer layer 1121, and the active layer 1122 is located away from the base substrate.
  • the first gate insulating layer 1128 on the 100 side, the gate 11211 on the first gate insulating layer 1128, the gate 11211 is the gate of a thin film transistor (such as a driving transistor or a light-emitting control transistor) directly connected to the light-emitting element.
  • the gate and the first sub-conductive strip 210 are arranged in the same layer. Therefore, the gate 11211 and the first sub-conductive strip 210 may be formed in the same manufacturing process, for example, formed by a patterning process using the same material layer.
  • the pixel circuit further includes a second gate insulating layer 302 located on the side of the gate 11211 away from the base substrate 100, an interlayer insulating layer 301 located on the second gate insulating layer 302, and The source electrode 1125 and the drain electrode 1126 on the interlayer insulating layer 301.
  • the buffer layer 1121 in the display area 110 and the bonding area 120 may be an integral structure, or may be a film layer separated from each other and located in the same layer.
  • the first gate insulating layer 1128 in the display area 110 and the bonding area 120 may be an integral structure, or may be a film layer separated from each other and located in the same layer; the second gate insulating layer 302 in the display area 110 and the bonding area 120 may be The interlayer insulating layer 301 in the display area 110 and the bonding area 120 may be an integrated structure, or they may be separated from each other and located on the same layer.
  • the buffer layer 1121 can not only prevent harmful substances in the base substrate from intruding into the interior of the display substrate, but also increase the adhesion of the film layer in the display substrate on the base substrate.
  • the buffer layer 1121 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the interlayer insulating layer 301, the second gate insulating layer 302, and the first gate insulating layer 1128 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the materials of the interlayer insulating layer 301, the second gate insulating layer 302, and the first gate insulating layer 1128 may be the same or different.
  • the active layer 1122 may include a source region 1123 and a drain region 1124, and a trench located between the source region 1123 and the drain region 1124. Road area.
  • the interlayer insulating layer 301, the second gate insulating layer 302, and the first gate insulating layer 1128 have via holes to expose the source region 1123 and the drain region 1124.
  • the source electrode 1125 and the drain electrode 1126 are electrically connected to the source region 1123 and the drain region 1124 through via holes, respectively.
  • the above-mentioned drain electrode 1126 and source electrode 1125 are respectively the first electrode and the second electrode of the thin film transistor directly electrically connected to the light emitting element 700.
  • the drain electrode of the thin film transistor is electrically connected to the light emitting element 700.
  • the part of the drain electrode 1126 and the source electrode 1125 that is located in the interlayer insulating layer 301 away from the base substrate 100 and the second sub-conductive bar 220 are arranged in the same layer.
  • the thin film transistor in the embodiment of the present disclosure may include an oxide semiconductor thin film transistor, an amorphous silicon thin film transistor, a polysilicon thin film transistor, or the like.
  • the source and drain of the thin film transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure.
  • the drains and drains of all or part of the thin film transistors in the embodiments of the present disclosure can be interchanged according to actual needs.
  • the gate 11211 overlaps with the channel region located between the source region 1123 and the drain region 1124 in the active layer 1122 in a direction perpendicular to the base substrate 100.
  • the planarization layer 620 and the passivation layer 610 are located above the source electrode 1125 and the drain electrode 1126, and are used to planarize the surface of the pixel circuit away from the base substrate.
  • a via 1131 is formed in the planarization layer 620 and the passivation layer 610 to expose the source electrode 1125 or the drain electrode 1126 (the case shown in the figure).
  • the passivation layer can protect the source and drain of the pixel circuit from being corroded by water vapor.
  • the material of the active layer 1122 may include polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the material of the gate 11211 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the multi-layer structure may be a multi-metal laminated layer (such as titanium, aluminum and titanium) Layer metal stack (Ti/Al/Ti).
  • the material of the source electrode 1125 and the drain electrode 1126 may include metal materials or alloy materials, such as metal single-layer or multi-layer structures formed of molybdenum, aluminum, and titanium.
  • the embodiment does not specifically limit the material of each functional layer.
  • Figure 7 schematically shows that the active layer 1122 is located on the side of the gate 11211 facing the base substrate, but it is not limited to this, and the active layer may also be located on the gate. The side away from the base substrate.
  • the material of the passivation layer 610 may include an organic insulating material or an inorganic insulating material, for example, silicon nitride material. Because of its high dielectric constant and good hydrophobic function, it can well protect the pixel circuit from being damaged. Corroded by water vapor.
  • the light-emitting element 700 is formed on the planarization layer 620, that is, the light-emitting element 700 is disposed on the side of the planarization layer 620 away from the base substrate 100.
  • the light-emitting element 700 includes a first electrode 710, a light-emitting layer 730, and a second electrode 720 that are sequentially stacked.
  • the second electrode 720 is located on the side of the light-emitting layer 730 facing the base substrate 100 and is configured to be connected to a thin film transistor.
  • the display substrate further includes a pixel defining layer 630. The opening of the pixel defining layer 630 exposes a part of the second electrode 720.
  • the light emitting layer 730 When the light emitting layer 730 is formed in the opening of the pixel defining layer 630, the light emitting layer 730 is in contact with the second electrode 720. Part of the light-emitting layer 730 can be driven to emit light to form an effective light-emitting area.
  • the display substrate further includes a storage capacitor 1160
  • the storage capacitor 1160 may include a first capacitor electrode 1161 and a second capacitor electrode 1162.
  • the first capacitor electrode 1161 is disposed between the first gate insulating layer 1128 and the second gate insulating layer 302, and the second capacitor electrode 1162 is disposed between the second gate insulating layer 302 and the interlayer insulating layer 301.
  • the first capacitor electrode 1161 and the second capacitor electrode 1162 overlap and at least partially overlap in a direction perpendicular to the base substrate 100.
  • the first capacitor electrode 1161 and the second capacitor electrode 1162 use the second gate insulating layer 302 as a dielectric material to form a storage capacitor.
  • the first storage capacitor electrode 1161 is arranged in the same layer as the gate 11211 in the pixel circuit 1120 and the first sub-conductive strip 210 in the bonding region 120.
  • the first storage capacitor electrode 1161 is provided in the same layer as the gate 11211 and at least one of the multiple data leads in the pixel circuit 1120.
  • the embodiments of the present disclosure are not limited to this.
  • the first capacitor electrode and the second capacitor electrode of the storage capacitor may also be located in other layers, so as to obtain sub-pixels with different structures.
  • the first capacitance electrode of the storage capacitor can still be arranged in the same layer as the gate electrode, and the second capacitance electrode of the storage capacitor can be arranged in the same layer as the source and drain electrodes in the thin film transistor, so that the first capacitance electrode and the second capacitance electrode are arranged in the same layer as the gate electrode.
  • the capacitor electrode uses a stack of the second gate insulating layer and the interlayer insulating layer as a dielectric material to form a storage capacitor.
  • the display substrate may further include an encapsulation layer 1150 provided on the light-emitting element 700.
  • the encapsulation layer 1150 seals the light emitting element 700, so that the deterioration of the light emitting element 700 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • the encapsulation layer 1150 may be a single-layer structure or a composite layer structure.
  • the composite layer structure includes a stacked structure of an inorganic layer and an organic layer.
  • the encapsulation layer 1150 may include a first inorganic encapsulation layer 1151 and an organic encapsulation layer arranged in sequence. 1152 and a second inorganic encapsulation layer 1153.
  • the encapsulation layer 1150 may extend to the bonding area. In the above example, the encapsulation layer does not cover the conductive strips.
  • polymer resins are used to flatten the surface of the display substrate, and can relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and can also include water-absorbing materials such as desiccant to absorb water intruding into the interior, Oxygen and other substances.
  • the film layer where the second electrode 720 is located is on the side of the second sub-conductive strip 220 away from the base substrate 100, that is, the second electrode 720 is located on the flat layer 620 away from the second sub-conductive strip. 220 side.
  • the film layer used to form the second electrode 720 of the light-emitting element 700 may be deposited on the side of the flat layer 620 away from the base substrate 100, since the opening 621 of the flat layer 620 exposes the second electrode 720.
  • the acid etching solution to be etched on the film layer to form the second electrode will be recycled. And there are a lot of silver ions in the acid etching solution.
  • the second sub-conductive strip 220 includes three layers of conductive layers stacked, and the material of the second conductive layer 222 in the three layers of conductive layers includes aluminum.
  • the materials of the first conductive layer 221 and the third conductive layer 223 in the three conductive layers include titanium.
  • the laminated structure and the materials of each layer of the second sub-conductive strip 220 in the embodiment of the present disclosure may be the same as the laminated structure and the materials of each layer of the second sub-conductive strip 20 in the display substrate shown in FIGS. 1 to 2.
  • the aspect ratio of the strip hole 310 is not less than 5.
  • the width of the strip hole 310 is in the range of 3 to 5 microns.
  • the "aspect ratio" of the aforementioned bar-shaped hole 310 may refer to the length of the bar-shaped hole 310 in the extending direction of the conductive bar 200 and the width of the bar-shaped hole 310 in the arrangement direction of the conductive bar 200 (for example, the second direction). ratio.
  • the extending direction of the conductive strip is the extending direction of the strip hole and the long side of the conductive strip
  • the second direction is the extending direction of the strip hole and the short side of the conductive strip
  • the strip hole is in the second direction.
  • the size of can also be referred to as the width of the strip hole in the second direction
  • the size of the conductive strip in the second direction can also be referred to as the width of the conductive strip in the second direction.
  • the first sub-conductive strip and the second sub-conductive strip are combined
  • the via holes in the interlayer insulating layer 301 between are arranged as strip-shaped holes 310, and the length-to-width ratio of the strip-shaped holes 310 is not less than 5, and the width of the strip-shaped holes 310 is in the range of 3-5 microns.
  • the length of the strip-shaped hole 310 is smaller than the length of the second sub-conductive strip 220 by 1-10 micrometers.
  • the length of the second sub-conductive strip 220 may be 145 ⁇ m, and the length of the strip hole 310 may be 135 ⁇ m.
  • the length of the second sub-conductive strip 220 may be 650 ⁇ m, and the length of the strip hole 310 may be 640 ⁇ m.
  • the length of the strip-shaped hole 310 is smaller than the length of the second sub-conductive strip 220 by 4-6 micrometers.
  • the size of the via hole 31 in the planarization layer 30 shown in FIGS. 1 to 2 is small, which will cause the second sub-conductive strip 20 formed in the via hole 31 to not be in effective contact with the subsequent circuit structure, so that the second sub-conductor is conductive.
  • the contact area between the strip 20 and the circuit structure is small, the contact resistance is large, and the connectivity is not good.
  • the size of the strip hole 310 in the embodiment of the present disclosure is relatively large, and the second sub-conductive strip 220 located in the strip hole 310 can achieve a better electrical connection effect with the subsequent circuit structure through an anisotropic conductive glue.
  • the strip hole 310 in the embodiment of the present disclosure can contain more anisotropic conductive glue, which increases the contact between the anisotropic conductive glue and the second sub-conductive strip. Therefore, the bonding strength between the anisotropic conductive adhesive and the second sub-conductive strip is increased, thereby ensuring the quality of the display substrate.
  • the included angle a2 (shown in FIG. 6) between the inner surface of the strip hole 310 and the base substrate 100 ranges from 30° to 40°.
  • the inner surface of the strip-shaped hole 310 is formed as a slope, and the slope angle a2 of the slope is in the range of 30°-40°.
  • the cross section of the strip hole 310 cut perpendicular to the surface of the base substrate includes a hypotenuse, and the included angle a2 between the hypotenuse and the base substrate ranges from 30° to 40°.
  • the inner surface of the strip hole 310 may be flat or curved.
  • the above-mentioned hypotenuse When the inner surface of the strip hole is flat, the above-mentioned hypotenuse is a straight side; when the inner surface of the strip hole is a curved surface, the above-mentioned hypotenuse is Is a curved side.
  • the slope of the line connecting the midpoint of the bar-shaped hole with the curve side of the bar-shaped hole and the intersection of the first sub-conductive strip at the position of half the height of the bar-shaped hole is taken as the slope of the hypotenuse of the bar-shaped hole
  • the angle between the above-mentioned connection line and the base substrate is the inclination angle a2 of the inner surface.
  • the embodiment of the present disclosure has The length and width are designed to be larger, which can make the angle between the inner surface of the strip hole 310 and the base substrate 100 smaller, that is, the inclination angle of the inner surface of the strip hole 310 becomes smaller, and the inner surface of the strip hole 310 becomes smaller.
  • the slope formed on the side surface becomes slower, which can prevent the second sub-conductive strip 220 formed in the strip hole 310 from breaking at the edge position of the strip hole 310, thereby improving the yield of the display substrate.
  • the strip hole 310 is a continuous strip hole extending along the extending direction of the first sub-conductive strip 210. That is, each first sub-conductive strip 210 corresponds to a continuous strip-shaped hole 310, and the first sub-conductive strip 210 is electrically connected to the second sub-conductive strip 220 through the continuous strip-shaped hole 310.
  • the orthographic projection of the strip hole 310 on the base substrate 100 is located within the orthographic projection of the first sub-conductive bar 210 on the base substrate 100.
  • the orthographic projection of the strip hole 310 on the base substrate 100 is located in the middle of the orthographic projection of the second sub-conductive strip 220 on the base substrate 100, so that the second sub-conductive strip 220 located in the strip hole 310 and The first sub-conductive strip 210 may have a good electrical connection relationship.
  • Fig. 8 is an enlarged view of the part C shown in Fig. 3 in another example.
  • the example shown in FIG. 8 is different from the example shown in FIG. 5 in that the strip hole 310 shown in FIG. There are intervals between the sub-strip-shaped holes 311, and the length of at least one sub-strip-shaped hole 311 is in the range of 15-30 microns.
  • the multiple sub-strip-shaped holes provided in the flat layer in the embodiment of the present disclosure can increase the size of the first sub-conductive strip and the second sub-conductive strip.
  • the contact area of the sub-conductive strips can reduce the impedance of the conductive strips, and can also reduce the probability of the first conductive layer of the second sub-conductive strips from breaking at the edge of the sub-strip-shaped hole, and prevent the second conductive layer from connecting with subsequent acid etching solutions.
  • the silver ions are replaced.
  • the angle between the inner surface of the sub-strip hole 311 and the base substrate 100 ranges from 30° to 40°, that is, the inclination angle of the inner surface of the sub-strip hole 311 is 30° to 40°.
  • the length of the sub-strip hole is set in the range of 15-30 microns, which can make the angle between the inner side of the sub-strip hole and the base substrate smaller, that is, the inner side of the sub-strip hole The smaller the inclination angle can prevent the second sub-conductive strip subsequently formed in the sub-strip-shaped hole from breaking at the edge of the sub-strip-shaped hole, and improve the yield of the display substrate.
  • the size of the sub-strip-shaped hole is relatively large, and the second sub-conductive strip located in the sub-strip-shaped hole can achieve a better electrical connection effect with the circuit structure through an anisotropic conductive glue.
  • each sub-strip-shaped hole in the embodiment of the present disclosure can contain more anisotropic conductive glue, which increases the contact area between the anisotropic conductive glue and the second sub-conductive strip, thereby increasing the anisotropic conductive glue The bonding strength with the second sub-conductive strip ensures the quality of the display substrate.
  • a plurality of sub-strip-shaped holes 311 are uniformly arranged along the extending direction of the first sub-conductive strip 210, so that the uniformity of electrical connection between the electrode strips of the circuit structure and the second sub-conductive strip can be ensured.
  • FIG. 9 is a schematic diagram of a partial cross-sectional structure of a display device according to an embodiment of the present disclosure.
  • the display device includes the above-mentioned display substrate and a circuit structure 800.
  • the circuit structure 800 includes a third sub-conductive strip 810.
  • the third sub-conductive strip 810 is electrically connected to the second sub-conductive strip 220 through a conductive adhesive 900 to be The two sub-conductive bars 220 write signals.
  • the circuit structure 800 includes a plurality of third sub-conductive bars 810, and the plurality of third sub-conductive bars 810 and the plurality of second sub-conductive bars 220 are connected in a one-to-one correspondence.
  • FIG. 9 only schematically shows the electrical connection between one third sub-conductive strip 810 and one second sub-conductive strip 220.
  • the third sub-conductive strip 810 of the circuit structure 800 extends into the opening defined by the flat layer 620 to achieve electrical connection with the second sub-conductive strip 220 through the anisotropic conductive glue 900.
  • the circuit structure 800 may include a flexible circuit board.
  • the flexible circuit board can be bonded to the bonding area of the display substrate, and the control chip can be mounted on the flexible circuit board, thereby electrically connecting with the display area.
  • the circuit structure may include a flip chip film.
  • the display device may adopt COP (Chip On Plastic) technology
  • the circuit structure 800 may include a control chip, and the control chip may be directly bonded to the bonding area, thereby being electrically connected to the display area.
  • the base substrate may be a flexible substrate.
  • control chip may be a central processing unit, a digital signal processor, a system chip (SoC), etc.
  • the control chip may also include a memory, and may also include a power supply module, etc., and the functions of power supply and signal input and output are realized through separately provided wires and signal lines.
  • the control chip may also include hardware circuits and computer executable codes.
  • Hardware circuits can include conventional very large-scale integration (VLSI) circuits or gate arrays, and existing semiconductors such as logic chips, transistors, or other discrete components; hardware circuits can also include field programmable gate arrays, programmable array logic, Programmable logic equipment, etc.
  • VLSI very large-scale integration
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种显示基板以及显示装置。显示基板包括：衬底基板、导电条以及层间绝缘层。衬底基板包括邦定区；多个导电条位于衬底基板上的邦定区，各导电条包括层叠设置的第一子导电条和第二子导电条，第二子导电条位于第一子导电条远离衬底基板的一侧；层间绝缘层位于第一子导电条与第二子导电条之间。层间绝缘层包括沿导电条的延伸方向延伸的条形孔，且条形孔被配置为暴露第一子导电条，以使第二子导电条与第一子导电条电连接。通过在层间绝缘层中设置暴露第一子导电条的条形孔，既可以保证第一子导电条与第二子导电条之间具有较大的接触面积，还可以降低位于条形孔边缘位置处的第二子导电条发生断裂的几率，从而提高显示基板的良率。

Description

显示基板以及显示装置 技术领域
本公开至少一个实施例涉及一种显示基板以及显示装置。
背景技术
目前，超薄、超窄边框甚至无边框的显示器越来越受到广泛的关注，因此很多厂家向制作超窄边框甚至无边框的显示器的方向发展。有机发光二极管显示装置可以通过采用覆晶薄膜(Chip On Film，COF)或者COP(Chip On Plastic)等技术实现窄边框。
发明内容
本公开的实施例提供一种显示基板以及显示装置。
本公开的实施例提供一种显示基板，包括：衬底基板，包括显示区和位于所述显示区至少一侧的邦定区；多个子像素，位于所述显示区中；多条数据线，位于所述显示区中，且与所述多个子像素连接以向所述多个子像素提供数据信号；多条数据引线，位于所述邦定区中且与所述多条数据线电连接；至少一组导电条，位于所述邦定区且位于所述多条数据引线远离所述显示区的一侧，所述至少一组导电条包括多个导电条，所述多个导电条中的至少一个包括第一子导电条和第二子导电条，所述第二子导电条位于所述第一子导电条远离所述衬底基板的一侧；层间绝缘层，位于所述第一子导电条与所述第二子导电条之间。所述第一子导电条与所述多条数据引线中的一条电连接；所述层间绝缘层包括沿所述多个导电条的延伸方向延伸的条形孔，且所述条形孔被配置为暴露所述第一子导电条，以使所述第二子导电条与所述第一子导电条电连接。
例如，在本公开的实施例中，所述条形孔的长宽比不小于5。
例如，在本公开的实施例中，所述条形孔的宽度在3～5微米范围内。
例如，在本公开的实施例中，所述条形孔的内侧表面与所述衬底基板之间的坡度角的范围为30°～40°。
例如，在本公开的实施例中，沿所述多个导电条的至少一个的延伸方向，所述条形孔的长度比所述第二子导电条延伸方向的长度小1～10微米。
例如，在本公开的实施例中，所述条形孔为沿所述多个导电条的至少一个的延伸方向延伸的连续的条形孔。
例如，在本公开的实施例中，所述条形孔包括沿所述多个导电条中至少一个的延伸方向排列的多个子条形孔，所述多个子条形孔中相邻两个子条形孔之间具有间隔，且所述多个子条形孔的至少一个的长度在15～30微米范围内。
例如，在本公开的实施例中，所述多个子条形孔沿所述多个导电条中至少一个的延 伸方向均匀设置。
例如，在本公开的实施例中，所述第二子导电条包括依次层叠设置的第一导电层、第二导电层以及第三导电层。
例如，在本公开的实施例中，所述第一导电层和所述第三导电层的材料包括钛，所述第二导电层的材料包括铝。
例如，在本公开的实施例中，所述至少一组导电条包括两组导电条，且所述两组导电条沿远离所述显示区的方向排列。
例如，在本公开的实施例中，所述多个子像素中至少一个包括像素电路和发光元件，所述像素电路位于所述衬底基板和所述发光元件之间；所述发光元件包括依次层叠设置的第一电极、发光层以及第二电极，所述第二电极位于所述发光层面向所述衬底基板的一侧；所述像素电路包括至少一个薄膜晶体管，所述薄膜晶体管包括位于所述衬底基板上栅极、位于所述栅极远离所述衬底基板一侧的源极和漏极，所述薄膜晶体管的源极或漏极与所述第二电极电连接；所述栅极与所述第一子导电条同层设置。
例如，在本公开的实施例中，所述多条数据线沿第一方向延伸，所述显示基板还包括：沿第二方向延伸的多条栅线，所述多条数据线位于所述多条栅线远离所述衬底基板的一侧，所述第一方向和所述第二方向相交。所述第二子导电条与所述多条数据线、所述源极或所述漏极同层设置。
例如，在本公开的实施例中，所述多个子像素中至少一个还包括存储电容，所述存储电容包括两个电容电极，所述多条数据引线中至少一条、所述存储电容的两个电容电极之一与所述栅极同层设置。
例如，在本公开的实施例中，所述多个导电条的至少一个的延伸方向与所述第一方向和所述第二方向均不平行。
例如，在本公开的实施例中，沿所述第二方向，所述第一子导电条的最大宽度小于所述第二子导电条的最大宽度，且所述条形孔在所述第二方向上的最大宽度小于所述第一子导电条的最大宽度。
例如，在本公开的实施例中，所述两组导电条包括第一导电条组和第二导电条组，所述第一导电条组和所述第二导电条组均包括沿所述第二方向排列的一行导电条，所述第一导电条组位于所述第二导电条组靠近所述显示区的一侧。
例如，在本公开的实施例中，所述多条数据引线包括与所述第一导电条组连接的多条第一数据引线以及与所述第二导电条组连接的多条第二数据引线，所述多条第一数据引线和所述多条第二数据引线交替排列，且所述多条第二数据引线的每条穿过所述第一导电条组中相邻导电条之间的间隔。
本公开的实施例提供一种显示装置，包括电路结构以及上述显示基板。所述电路结构包括第三子导电条，所述第三子导电条通过导电胶与所述第二子导电条电连接以对所述第二子导电条写入信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示基板中的邦定区内的条状电极的局部平面结构示意图；
图2为沿图1所示的AA’线所截的局部截面结构示意图；
图3为本公开实施例提供的显示基板的平面结构示意图；
图4为图3所示的显示基板中的邦定区的局部放大示意图；
图5为图4所示的局部C在一示例中的放大图；
图6为沿图5所示的BB’所截的局部截面结构示意图；
图7为图3所示的显示基板中的显示区的局部截面结构示意图；
图8为图3所示的局部C在另一示例中的放大图；以及
图9为根据本公开实施例提供的显示装置的局部截面结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
图1为一种显示基板中的邦定区内的条状电极的局部平面结构示意图，图2为沿图1所示的AA’线所截的局部截面结构示意图。如图1和图2所示，显示基板的邦定区(非显示区)包括多个条状电极(接触垫)，各条状电极包括电连接的第一子导电条10和第二子导电条20，第二子导电条20位于第一子导电条10远离衬底基板40的一侧，第一子导电条10的延伸方向与第二子导电条20的延伸方向相同，且第一子导电条10和第二子导电条20之间设置有层间绝缘层30。层间绝缘层30中设置有用于暴露第一子导电条10的过孔31以使位于层间绝缘层30(图2仅示出了第一子导电条10与第二子导电条20之间的层间绝缘层30)上的第二子导电条20通过过孔31与第一子导电条10电连接。第二子导电条20远离第一子导电条10的一侧设置有钝化层50以及平坦层60，条状电极被配置为通过各向异性导电胶与覆晶薄膜(COF)等电路结构的电极邦定。
例如，如图2所示，第二子导电条20包括层叠设置的第一金属层21、第二金属层22以及第三金属层23，第一金属层21和第三金属层23的材料可以包括钛，第二金属层 22的材料可以包括铝。
在研究中，本申请的发明人发现：过孔31的平行于衬底基板40尺寸为2.1微米～2.5微米，该尺寸较小。由此，在通过刻蚀、曝光等工艺形成过孔31的过程中，过孔31的内侧面形成为斜坡，该内侧面与衬底基板40之间的夹角a1(图2所示)大于50°，也就是，过孔31内侧面形成的斜坡的坡度角a1大于50°，例如70°～80°。在一定应力作用下，上述尺寸较小的过孔31由于其斜坡的坡度角较大，也就是斜坡较陡，容易导致沉积在过孔31内的第二子导电条20在过孔31边缘位置处发生断裂。例如，第二子导电条20中距离衬底基板40最远的第一金属层21在过孔31边缘位置处容易发生断裂，导致第二金属层22被暴露，例如金属铝层被暴露。
在图1-图2所示的显示基板的制作工艺中，图案化平坦层60形成暴露第二子导电条20的开口61以后，在平坦层60远离衬底基板40的一侧形成机发光元件的阳极膜层，该阳极膜层既形成在显示区，也形成在非显示区。采用湿刻工艺对位于非显示区的阳极膜层进行刻蚀以形成位于显示区的阳极图案的过程中，刻蚀阳极膜层的酸性刻蚀液会进行循环使用，且该酸性刻蚀液中存在大量的银离子。当过孔31边缘位置处的第二子导电条20中的第一金属层21发生断裂而暴露第二金属层22后，第二金属层22中的铝会与上述酸性刻蚀液中的银离子会发生置换反应，析出银。在后续清洗过程中，析出的银会发生不规则流动，造成显示基板上形成银颗粒。该银颗粒可能会造成相邻两个条状电极发生短路，影响包括上述显示基板的面板正常点亮，也会产生Mura现象，降低产品的良率。
本公开的实施例提供一种显示基板以及显示装置。显示基板包括：衬底基板、位于衬底基板上的多个子像素、多条数据线、多条数据引线、至少一组导电条以及层间绝缘层。衬底基板包括显示区和位于显示区至少一侧的邦定区；多个子像素位于显示区中；多条数据线位于显示区中，且与多个子像素连接以向多个子像素提供数据信号；多条数据引线位于邦定区中且与多条数据线电连接；至少一组导电条位于邦定区且位于多条数据引线远离显示区的一侧，至少一组导电条包括多个导电条，多个导电条中的至少一个包括第一子导电条和第二子导电条，第二子导电条位于第一子导电条远离衬底基板的一侧；层间绝缘层，位于第一子导电条与第二子导电条之间。第一子导电条与多条数据引线中的一条电连接；层间绝缘层包括沿多个导电条的延伸方向延伸的条形孔，且条形孔被配置为暴露第一子导电条，以使第二子导电条与第一子导电条电连接。本公开实施例通过在层间绝缘层中设置暴露第一子导电条的条形孔，既可以保证第一子导电条与第二子导电条之间具有较大的接触面积，还可以降低位于条形孔边缘位置处的第二子导电条发生断裂的几率，从而提高显示基板的良率。
下面结合附图对本公开实施例提供的显示基板以及显示装置进行描述。
图3为根据本公开实施例提供的显示基板的平面结构示意图，图4为图3所示的显示基板中的邦定区的局部放大示意图，图5为图4所示的局部C在一示例中的放大图，图6为沿图5所示的BB’所截的局部截面结构示意图。如图3-图6所示，本公开实施例提供的显示基板包括衬底基板100、位于衬底基板100上的多个导电条200，各导电条200 包括层叠设置的第一子导电条210和第二子导电条220，第二子导电条220位于第一子导电条210远离衬底基板100的一侧，第一子导电条210和第二子导电条220的延伸方向相同，第一子导电条210和第二子导电条220之间设置有层间绝缘层301。衬底基板100包括显示区110以及位于显示区110周边的周边区，周边区包括将显示基板与覆晶薄膜(COF)等电路结构邦定的邦定区120。包括第一子导电条210和第二子导电条220的导电条200位于邦定区120，第二子导电条220在衬底基板100上的正投影与第一子导电条在210衬底基板100上的正投影有交叠。如图3-图6所示，层间绝缘层301包括沿导电条200的延伸方向延伸的条形孔310，且条形孔310被配置为暴露第一子导电条210，以使第二子导电条220与第一子导电条210电连接。本公开实施例通过在层间绝缘层中设置暴露第一子导电条的条形孔，既可以保证第一子导电条与第二子导电条之间具有较大的接触面积，还可以降低位于条形孔边缘位置处的第二子导电条发生断裂的几率，从而提高显示基板的良率。
上述导电条的平行于衬底基板的平面形状为条状，导电条的延伸方向即为平面形状中长边的延伸方向。上述条形孔的平行于衬底基板的平面形状为条状，后续条形孔的长和宽指平行于衬底基板的平面形状的长和宽。
上述层间绝缘层中设置有多个条形孔，多个条形孔与多个导电条一一对应，各条形孔用于暴露每个导电条中的第一子导电条。
例如，层间绝缘层301的材料可以包括硅氧化物或硅氮化物等绝缘材料。
例如，如图3所示，显示区110设置有沿第一方向(Y方向)延伸的数据线400和沿第二方向(X方向)延伸的栅线500，数据线400位于栅线500远离衬底基板100的一侧，数据线400与栅线500之间可以设置有层间绝缘层301。
例如，第一方向和第二方向相交，例如，第一方向和第二方向垂直。本公开实施例中的第一方向和第二方向可以互换。
例如，如图3-图6所示，导电条200的延伸方向与第一方向和第二方向均不平行。例如，导电条200的延伸方向与第一方向可以具有例如8°～10°的夹角。例如，导电条200靠近显示区110的一端相对于导电条200远离显示区的一端更靠近显示基板的沿第一方向延伸的中心线，从而方便与数据线进行连接。例如，位于显示基板的沿第一方向延伸的中心线两侧的导电条200可以相对于该中心线对称分布。
例如，邦定区120位于显示区110的一侧，用于通过邦定工艺将外部电路与显示基板电连接。例如，外部电路可以包括安装芯片的柔性电路板(例如，Chip On Film,简称COF)，该柔性电路板上设置控制芯片或驱动芯片等。该邦定区也可以用于直接与芯片电连接。
例如，位于邦定区120的导电条200可以为与驱动芯片直接邦定的接触垫，衬底基板100可以为柔性衬底，通过将邦定区120位置处的柔性衬底向该柔性衬底远离数据线400的背面弯折，可以实现窄边框。例如，位于邦定区120的导电条200也可以为用于与覆晶薄膜邦定的接触垫。
例如，数据线400可以通过位于邦定区120的多条数据引线410与多个导电条200一一对应连接，以使数据线400与驱动芯片或者柔性电路板等电路结构电连接。
例如，如图3-图4所示，多个导电条200包括第一导电条组2201和第二导电条组2202，第一导电条组2201和第二导电条组2202均包括沿第二方向排列的一行导电条200，第一导电条组2201位于第二导电条组2202靠近显示区110的一侧。本公开实施例以导电条沿第二方向排列为两行为例，但不限于此，还可以是一行或者更多行，即导电条可以排列为一个或更多个导电条组。
例如，为了减小邦定区沿Y方向的尺寸，可以设置一行导电条，即一个导电条组。
例如，如图3-图4所示，多条数据引线410包括与第一导电条组2201连接的多条第一数据引线411以及与第二导电条组2202连接的多条第二数据引线412，多条第一数据引线411和多条第二数据引线412沿第二方向交替排列，即，第一数据引线411可以与奇数条数据线400连接，第二数据引线412可以与偶数条数据线400连接。本公开实施例不限于此，还可以第一数据引线与偶数条数据线连接，第二数据引线与奇数条数据线连接。
例如，如图3-图4所示，各导电条组中的相邻两个导电条200之间设置有间隔，且各第二数据引线412穿过第一导电条组2201中相邻导电条200之间的间隔以与数据线400连接。本公开实施例通过设置两个导电条组，且各第二数据引线穿过第一导电条组中相邻导电条之间的间隔以与数据线连接，可以减小相邻两条数据引线之间的距离，尽量避免出现扇形布线区，以实现窄边框设计。
例如，第一导电条组面向第二导电条组的一侧也可以设置第三数据引线(图中未示出)，该第三数据引线从第一导电条组中的导电条远离显示区的一侧延伸至穿过第二导电条组中的相邻两个导电条之间的间隔，即沿第二方向，第三数据引线与第二数据引线交替设置，以保证第一导电条组与第二导电条组之间的数据引线均匀设置。上述第三数据引线仅与第一导电条组中的导电条连接。
例如，在第一导电条远离衬底基板的一侧设置有源半导体层时，各导电条远离显示区的一侧可以设置防静电部，该防静电部中包括第一导电条远离显示区的一部分以及有源半导体层，该部分与有源半导体层连接以增加电阻，起到防静电的作用。
例如，如图3-图6所示，第二子导电条220与数据线400同层，例如，第二子导电条220与数据线400可以同层设置且材料相同。这里以及后续出现的“同层”指同一材料在经过同一步骤(例如一步图案化工艺)后形成的多个膜层之间的关系。这里的“同层”并不总是指多个膜层的厚度相同或者多个膜层在截面图中的高度相同。
例如，第一子导电条210与栅线500可以同层且材料相同。
例如，第一数据引线411中的至少一部分可以与第一导电条组2201中的导电条200的第一子导电条210同层设置，第二数据引线412的至少一部分可以与第二导电条组2202中的导电条200的第一子导电条210同层设置。也就是，各导电条200可以通过第一子导电条210与数据引线410相连而实现与相应的数据线400相连，以实现电路结构为数 据线提供数据信号。
例如，如图3-图6所示，第二子导电条220远离衬底基板100的一侧设置有钝化层610以及平坦层620。钝化层610和平坦层620中设置有暴露第二子导电条220的开口621，覆晶薄膜(COF)等电路结构中的电极条通过上述开口621实现与第二子导电条220的邦定。
例如，钝化层610以及平坦层620覆盖第二子导电条220的四周边缘，以防止第二子导电条220的四周边缘在后续制作显示基板的工艺中受到损伤。
例如，如图5-图6所示，沿第二方向，第一子导电条210的尺寸小于第二子导电条220的尺寸，也就是，沿第二方向，第一子导电条210的宽度小于第二子导电条220的宽度。沿第二方向，第二子导电条220覆盖了第一子导电条210的边缘，减少位于第二子导电条220边缘的钝化层610和平坦层630与第一子导电条210的交叠面积，从而防止位于第二子导电条220边缘的钝化层610和平坦层620覆盖的膜层厚度较大而影响显示基板的厚度。
例如，图7为图3所示的显示基板中的显示区的局部截面结构示意图。如图7所示，显示基板还包括位于衬底基板100的显示区110的发光元件700以及驱动发光元件700的像素电路1120。例如，像素电路位于发光元件与衬底基板之间。例如，像素电路可以包括薄膜晶体管、存储电容等，可以实现为各种不同类型，例如为2T1C型(即包括两个薄膜晶体管和一个存储电容)，还可以在2T1C型的基础上进一步包括更多的晶体管和/或电容以具有补偿、复位、发光控制、检测等功能，本公开的实施例对于像素电路不作限制。例如，在一些实施例中，与发光元件直接电连接的薄膜晶体管可以为驱动晶体管或发光控制晶体管等。
例如，如图6-图7所示，显示基板还包括位于衬底基板100上的缓冲层1121，像素电路1120包括位于缓冲层1121上的有源层1122、位于有源层1122远离衬底基板100一侧的第一栅绝缘层1128、位于第一栅绝缘层1128上的栅极11211，该栅极11211为与发光元件直接连接薄膜晶体管(例如驱动晶体管或者发光控制晶体管)的栅极，该栅极与第一子导电条210同层设置。因此，栅极11211和第一子导电条210可以在同一制备工艺中形成，例如采用同一材料层通过构图工艺形成。
例如，如图6-图7所示，像素电路还包括位于栅极11211远离衬底基板100一侧的第二栅绝缘层302，位于第二栅绝缘层302上的层间绝缘层301以及位于层间绝缘层301上的源极1125及漏极1126。显示区110与邦定区120中的缓冲层1121可以为一体结构，也可以为彼此分离且位于同层的膜层。显示区110与邦定区120中第一栅绝缘层1128可以为一体结构，也可以为彼此分离且位于同层的膜层；显示区110与邦定区120中的第二栅绝缘层302可以为一体结构，也可以为彼此分离且位于同层的膜层；显示区110与邦定区120中的层间绝缘层301可以为一体结构，也可以为彼此分离且位于同层的膜层。缓冲层1121作为过渡层，既可以防止衬底基板中的有害物质侵入显示基板的内部，又可以增加显示基板中的膜层在衬底基板上的附着力。
例如，缓冲层1121可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。层间绝缘层301、第二栅绝缘层302以及第一栅绝缘层1128可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。层间绝缘层301、第二栅绝缘层302以及第一栅绝缘层1128的材料可以相同也可以不相同。
例如，在本公开上述实施例一些示例中，如图7所示，有源层1122可以包括源极区1123和漏极区1124，以及包括位于源极区1123和漏极区1124之间的沟道区。层间绝缘层301、第二栅绝缘层302以及第一栅绝缘层1128具有过孔，以暴露源极区1123和漏极区1124。源极1125及漏极1126分别通过过孔与源极区1123和漏极区1124电连接。上述漏极1126和源极1125分别为与发光元件700直接电连接的薄膜晶体管的第一极和第二极，例如，薄膜晶体管的漏极与发光元件700电连接。上述漏极1126和源极1125中位于层间绝缘层301远离衬底基板100的部分与第二子导电条220同层设置。
本公开的实施例中的薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。薄膜晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。本公开的实施例中全部或部分薄膜晶体管的漏极和漏极可以根据实际需要而互换。
例如，如图7所示，栅极11211在垂直于衬底基板100的方向上与有源层1122中位于源极区1123和漏极区1124之间的沟道区重叠。平坦层620和钝化层610位于源极1125及漏极1126的上方，用于平坦化像素电路远离衬底基板一侧的表面。平坦层620和钝化层610中形成过孔1131，以暴露源极1125或漏极1126(图中示出的情况)。钝化层可以保护像素电路的源极和漏极不被水汽腐蚀。
例如，有源层1122的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)。栅极11211的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构可以为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti)。源极1125及漏极1126的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构。本公开的实施例对各功能层的材料不做具体限定。图7示意性的示出有源层1122位于栅极11211面向衬底基板的一侧，但不限于此，还可以是有源层位于栅极远离衬底基板的一侧。
例如，钝化层610的材料可以包括有机绝缘材料或无机绝缘材料，例如，氮化硅材料，由于其具有较高的介电常数且具有很好的疏水功能，能够很好的保护像素电路不被水汽腐蚀。
例如，如图6-图7所示，在平坦化层620上形成发光元件700，即发光元件700设置在平坦化层620远离衬底基板100一侧。发光元件700包括依次层叠设置的第一电极710、发光层730以及第二电极720，第二电极720位于发光层730面向衬底基板100的一侧，且被配置为于薄膜晶体管连接。显示基板还包括像素限定层630，像素限定层630的开口暴露部分第二电极720，当发光层730形成在上述像素限定层630的开口中时，发光层730与第二电极720接触，从而这部分能够驱动发光层730进行发光以形成有效发 光区。
此外，显示基板还包括存储电容器1160，存储电容器1160可以包括第一电容电极1161和第二电容电极1162。第一电容电极1161设置在第一栅绝缘层1128与第二栅绝缘层302之间，第二电容电极1162设置在第二栅绝缘层302与层间绝缘层301之间。第一电容电极1161和第二电容电极1162叠置，在垂直于衬底基板100的方向上至少部分重叠。第一电容电极1161和第二电容电极1162以第二栅绝缘层302作为介电材料来形成存储电容器。第一存储电容电极1161与像素电路1120中的栅极11211、邦定区120中的第一子导电条210同层设置。例如，第一存储电容电极1161与像素电路1120中的栅极11211、多条数据引线中的至少一条同层设置。本公开实施例不限于此，例如，存储电容器的第一电容电极和第二电容电极还可以位于其他层中，从而得到不同结构的子像素。例如，存储电容器的第一电容电极可以仍然与栅极同层设置，而存储电容器的第二电容电极可以与薄膜晶体管中的源极和漏极同层设置，由此第一电容电极和第二电容电极以第二栅绝缘层以及层间绝缘层的叠层来作为介电材料来形成存储电容器。
例如，如图7所示，显示基板还可以包括设置在发光元件700上的封装层1150。封装层1150将发光元件700密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的发光元件700的劣化。封装层1150可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构，例如，封装层1150可以包括依次设置的第一无机封装层1151、有机封装层1152以及第二无机封装层1153。封装层1150可以延伸至邦定区，在上述示例中，该封装层未覆盖导电条。
例如，该封装层的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防止水、氧等的侵入；有机封装层的材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一无机封装层和第二无机封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
例如，如图6-图7所示，第二电极720所在膜层位于第二子导电条220远离衬底基板100的一侧，即，第二电极720位于平坦层620远离第二子导电条220的一侧。
例如，如图6-图7所示，用于形成发光元件700的第二电极720的膜层可以沉积在平坦层620远离衬底基板100的一侧，由于平坦层620的开口621暴露了第二子导电条220，所以用于形成第二电极的膜层包括沉积在显示区和非显示区的部分，位于非显示区的部分包括位于第二子导电条220上的部分。在采用湿刻工艺对用于形成第二电极的膜层进行刻蚀以形成位于显示区的阳极图案的过程中，对待形成第二电极的膜层刻蚀的酸性刻蚀液会进行循环使用，且该酸性刻蚀液中存在大量的银离子。
例如，如图3-图6所示，第二子导电条220包括层叠设置的三层导电层，三层导电层中的第二导电层222的材料包括铝。例如，三层导电层中的第一导电层221和第三导电层223的材料包括钛。本公开实施例中的第二子导电条220的层叠结构以及各层材料可以与图1-图2所示的显示基板中的第二子导电条20的层叠结构以及各层材料均相同。
例如，如图3-图6所示，条形孔310的长宽比不小于5。例如，条形孔310的宽度在3～5微米范围内。上述条形孔310的“长宽比”可以指条形孔310的沿导电条200的延伸方向的长度与条形孔310的沿导电条200的排列方向(例如，第二方向)的宽度的比值。本公开实施例以导电条的延伸方向为条形孔以及导电条的长边的延伸方向，第二方向为条形孔以及导电条的短边的延伸方向，则条形孔在第二方向上的尺寸也可以称为条形孔在第二方向上的宽度，导电条在第二方向上的尺寸也可以称为导电条在第二方向上的宽度。
相对于图2所示的显示基板中位于两层导电条之间的层间绝缘层30中尺寸较小的过孔31，本公开实施例中，将第一子导电条和第二子导电条之间的层间绝缘层301中的过孔设置为条形孔310，且条形孔310的长宽比不小于5，条形孔310的宽度在3～5微米范围内。由此，在增大第一子导电条210与第二子导电条220的接触面积以减小导电条阻抗的同时，还可以降低第一导电层221在条形孔310边缘位置处发生断裂的几率，防止第二导电层222与后续酸性刻蚀液中的银离子发生置换，影响显示基板的良率。
例如，如图3-图6所示，沿第二子导电条220的延伸方向，条形孔310的长度比第二子导电条220的长度小1～10微米。例如，第二子导电条220的长度可以为145微米，则条形孔310的长度可以为135微米。例如，第二子导电条220的长度可以为650微米，则条形孔310的长度可以为640微米。例如沿第二子导电条210的延伸方向，条形孔310的长度比第二子导电条220的长度小4～6微米。
图1-图2所示的平坦层30中的过孔31的尺寸较小，会导致形成在过孔31内的第二子导电条20不能与后续电路结构有效接触，从而，第二子导电条20与电路结构的接触面积小，接触电阻大，连接性不好。本公开实施例中的条形孔310的尺寸较大，位于条形孔310内的第二子导电条220可以通过各向异性导电胶实现与后续电路结构的较好的电连接效果。此外，相对于图2所示的过孔31，本公开实施例中的条形孔310内可以容纳较多的各向异性导电胶，增加了各向异性导电胶与第二子导电条的接触面积，因而增加了各向异性导电胶与第二子导电条之间的结合强度，从而保证了显示基板的品质。
例如，如图3-图6所示，条形孔310的内侧表面与衬底基板100之间的夹角a2(图6所示)的范围为30°～40°。例如，通过刻蚀、曝光等工艺形成条形孔310的过程中，条形孔310的内侧表面形成为斜坡，该斜坡的坡度角a2的范围为30°～40°。例如，条形孔310被垂直于衬底基板的表面所截的截面包括斜边，该斜边与衬底基板之间的夹角a2的范围为30°～40°。条形孔310的内侧表面可以为平面，也可以为曲面，当条形孔的内侧表面为平面时，上述斜边即为直边；当条形孔的内侧表面为曲面时，上述斜边即为曲线边，此时，以条形孔的高度的一半的位置处中点与条形孔的曲线边与第一子导电条的交点的连线的斜率作为条形孔的斜边的斜率为例，则上述连线与衬底基板的夹角为内侧面的倾斜角度a2。相对于图2所示的层间绝缘层30中的过孔31的内侧面与衬底基板40之间的夹角在70°～80°范围的情况，本公开实施例将条形孔310的长度和宽度设计的较大，可以使得条形孔310的内侧面与衬底基板100之间的夹角变小，即条形孔310的内侧面的倾 斜角度变小，条形孔310的内侧面形成的斜坡变缓，可以防止后续形成在条形孔310内的第二子导电条220在条形孔310的边缘位置处发生断裂，提高显示基板的良率。
例如，如图3-图6所示，条形孔310为沿第一子导电条210的延伸方向延伸的连续的条形孔。也就是，每个第一子导电条210对应一个连续的条形孔310，第一子导电条210通过该连续的条形孔310实现与第二子导电条220的电连接。
例如，如图3-图6所示，条形孔310在衬底基板100上的正投影位于第一子导电条210在衬底基板100上的正投影内。例如，条形孔310在衬底基板100上的正投影位于第二子导电条220在衬底基板100上的正投影的中部，从而，位于条形孔310内的第二子导电条220与第一子导电条210可以具有良好的电连接关系。
图8为图3所示的局部C在另一示例中的放大图。图8所示的示例与图5所示的示例的不同之处在于，图8所示的条形孔310包括沿第一子导电条210的延伸方向排列的多个子条形孔311，相邻子条形孔311之间具有间隔，且至少一个子条形孔311的长度在15～30微米范围内。相对于图2所示的显示基板的平坦层中设置多个小尺寸过孔的情况，本公开实施例在平坦层中设置的多个子条形孔既可以增大第一子导电条与第二子导电条的接触面积以减小导电条阻抗，还可以降低第二子导电条的第一导电层在子条形孔边缘位置处发生断裂的几率，防止第二导电层与后续酸性刻蚀液中的银离子发生置换。
例如，子条形孔311的内侧表面与衬底基板100之间的夹角的范围为30°～40°，即子条形孔311的内侧表面的倾斜角度为30°～40°。本公开实施例将子条形孔的长度设置在15～30微米范围内，可以使得子条形孔的内侧面与衬底基板之间的夹角变小，即子条形孔的内侧面的倾斜角度变小，可以防止后续形成在子条形孔内的第二子导电条在子条形孔的边缘位置处发生断裂，提高显示基板的良率。
本公开实施例中，子条形孔的尺寸较大，位于子条形孔内的第二子导电条可以通过各向异性导电胶实现与电路结构的较好的电连接效果。此外，本公开实施例中的各子条形孔内可以容纳较多的各向异性导电胶，增加了各向异性导电胶与第二子导电条的接触面积，因而增加了各向异性导电胶与第二子导电条之间的结合强度，从而保证了显示基板的品质。
例如，如图8所示，多个子条形孔311沿第一子导电条210的延伸方向均匀设置，从而可以保证电路结构的电极条与第二子导电条的电连接的均匀性。
本公开另一实施例提供一种显示装置，该显示装置可以包括上述任一实施例的显示基板。图9为根据本公开实施例提供的显示装置的局部截面结构示意图。如图9所示，显示装置包括上述显示基板以及电路结构800，电路结构800包括第三子导电条810，第三子导电条810通过导电胶900与第二子导电条220电连接以对第二子导电条220写入信号。
例如，如图9所示，电路结构800包括多个第三子导电条810，且多个第三子导电条810与多个第二子导电条220一一对应连接。图9仅示意性示出一个第三子导电条810与一个第二子导电条220的电连接。
例如，如图9所示，电路结构800的第三子导电条810伸入平坦层620限定的开口中，以通过各向异性导电胶900实现与第二子导电条220的电连接。
例如，电路结构800可以包括柔性电路板。例如，柔性电路板可以邦定到显示基板的邦定区，控制芯片可以安装在柔性电路板上，由此与显示区电连接。例如，电路结构可以包括覆晶薄膜。
例如，显示装置可以采用COP(Chip On Plastic)技术，电路结构800可以包括控制芯片，控制芯片可以直接邦定到邦定区，由此与显示区电连接。例如，衬底基板可以为柔性衬底，通过将邦定区位置处的柔性衬底向该柔性衬底远离数据线的一侧弯折，即将柔性衬底向背面弯折，可以最大限度减少显示装置对“下巴”空间的占用，从而实现窄边框。
例如，控制芯片可以为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。
例如，本公开至少一个实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (19)

  1. 一种显示基板，包括：
    衬底基板，包括显示区和位于所述显示区至少一侧的邦定区；
    多个子像素，位于所述显示区中；
    多条数据线，位于所述显示区中，且与所述多个子像素连接以向所述多个子像素提供数据信号；
    多条数据引线，位于所述邦定区中且与所述多条数据线电连接；
    至少一组导电条，位于所述邦定区且位于所述多条数据引线远离所述显示区的一侧，所述至少一组导电条包括多个导电条，所述多个导电条中的至少一个包括第一子导电条和第二子导电条，所述第二子导电条位于所述第一子导电条远离所述衬底基板的一侧；
    层间绝缘层，位于所述第一子导电条与所述第二子导电条之间；
    其中，所述第一子导电条与所述多条数据引线中的一条电连接；
    所述层间绝缘层包括沿所述多个导电条的延伸方向延伸的条形孔，且所述条形孔被配置为暴露所述第一子导电条，以使所述第二子导电条与所述第一子导电条电连接。
  2. 根据权利要求1所述的显示基板，其中，所述条形孔的长宽比不小于5。
  3. 根据权利要求2所述的显示基板，其中，所述条形孔的宽度在3～5微米范围内。
  4. 根据权利要求1-3任一项所述的显示基板，其中，所述条形孔的内侧表面与所述衬底基板之间的坡度角的范围为30°～40°。
  5. 根据权利要求1-4任一项所述的显示基板，其中，沿所述多个导电条的至少一个的延伸方向，所述条形孔的长度比所述第二子导电条延伸方向的长度小1～10微米。
  6. 根据权利要求5所述的显示基板，其中，所述条形孔为沿所述多个导电条的至少一个的延伸方向延伸的连续的条形孔。
  7. 根据权利要求1-4任一项所述的显示基板，其中，所述条形孔包括沿所述多个导电条中至少一个的延伸方向排列的多个子条形孔，所述多个子条形孔中相邻两个子条形孔之间具有间隔，且所述多个子条形孔的至少一个的长度在15～30微米范围内。
  8. 根据权利要求7所述的显示基板，其中，所述多个子条形孔沿所述多个导电条中至少一个的延伸方向均匀设置。
  9. 根据权利要求1-8任一项所述的显示基板，其中，所述第二子导电条包括依次层叠设置的第一导电层、第二导电层以及第三导电层。
  10. 根据权利要求9所述的显示基板，其中，所述第一导电层和所述第三导电层的材料包括钛，所述第二导电层的材料包括铝。
  11. 根据权利要求9或10所述的显示基板，其中，所述至少一组导电条包括两组导电条，且所述两组导电条沿远离所述显示区的方向排列。
  12. 根据权利要求11所述的显示基板，其中，所述多个子像素中至少一个包括像素电路和发光元件，所述像素电路位于所述衬底基板和所述发光元件之间；
    所述发光元件包括依次层叠设置的第一电极、发光层以及第二电极，所述第二电极位于所述发光层面向所述衬底基板的一侧；
    所述像素电路包括至少一个薄膜晶体管，所述薄膜晶体管包括位于所述衬底基板上栅极、位于所述栅极远离所述衬底基板一侧的源极和漏极，所述薄膜晶体管的源极或漏极与所述第二电极电连接；
    所述栅极与所述第一子导电条同层设置。
  13. 根据权利要求12所述的显示基板，其中，所述多条数据线沿第一方向延伸，所述显示基板还包括：
    沿第二方向延伸的多条栅线，所述多条数据线位于所述多条栅线远离所述衬底基板的一侧，所述第一方向和所述第二方向相交，
    其中，所述第二子导电条与所述多条数据线、所述源极或所述漏极同层设置。
  14. 根据权利要求13所述的显示基板，其中，所述多个子像素中至少一个还包括存储电容，所述存储电容包括两个电容电极，
    所述多条数据引线中至少一条、所述存储电容的两个电容电极之一与所述栅极同层设置。
  15. 根据权利要求13或14所述的显示基板，其中，所述多个导电条的至少一个的延伸方向与所述第一方向和所述第二方向均不平行。
  16. 根据权利要求13-15任一项所述的显示基板，其中，沿所述第二方向，所述第一子导电条的最大宽度小于所述第二子导电条的最大宽度，且所述条形孔在所述第二方向上的最大宽度小于所述第一子导电条的最大宽度。
  17. 根据权利要求11-16任一项所述的显示基板，其中，所述两组导电条包括第一导电条组和第二导电条组，所述第一导电条组和所述第二导电条组均包括沿所述第二方向排列的一行导电条，所述第一导电条组位于所述第二导电条组靠近所述显示区的一侧。
  18. 根据权利要求17所述的显示基板，其中，所述多条数据引线包括与所述第一导电条组连接的多条第一数据引线以及与所述第二导电条组连接的多条第二数据引线，所述多条第一数据引线和所述多条第二数据引线交替排列，且所述多条第二数据引线的每条穿过所述第一导电条组中相邻导电条之间的间隔。
  19. 一种显示装置，包括电路结构以及权利要求1-18任一项所述的显示基板，
    其中，所述电路结构包括第三子导电条，所述第三子导电条通过导电胶与所述第二子导电条电连接以对所述第二子导电条写入信号。
PCT/CN2020/080830 2020-03-24 2020-03-24 显示基板以及显示装置 Ceased WO2021189232A1 (zh)

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