WO2021190055A1 - Substrat d'affichage et son procédé de préparation, panneau d'affichage et dispositif d'affichage - Google Patents

Substrat d'affichage et son procédé de préparation, panneau d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2021190055A1
WO2021190055A1 PCT/CN2020/141653 CN2020141653W WO2021190055A1 WO 2021190055 A1 WO2021190055 A1 WO 2021190055A1 CN 2020141653 W CN2020141653 W CN 2020141653W WO 2021190055 A1 WO2021190055 A1 WO 2021190055A1
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Prior art keywords
layer
base substrate
conductor layer
metal layer
protective conductor
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PCT/CN2020/141653
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English (en)
Chinese (zh)
Inventor
田春光
李小龙
邹佳滨
文娜
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Publication of WO2021190055A1 publication Critical patent/WO2021190055A1/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a preparation method of the display substrate, a display panel including the display substrate, and a display device including the display panel.
  • the present disclosure provides a display substrate and a preparation method of the display substrate, a display panel including the display substrate, and a display device including the display panel.
  • a display substrate including a base substrate provided with a display area and a non-display area, and the display substrate in the non-display area further includes:
  • the data line metal layer is arranged on one side of the base substrate
  • the first protective conductor layer is arranged on the side of the data line metal layer away from the base substrate, and the orthographic projection of the first protective conductor layer on the base substrate is in line with the data line metal layer
  • the orthographic projections on the base substrate at least partially overlap;
  • the passivation layer is provided on a side of the first protective conductor layer away from the base substrate, and a first via is provided on the passivation layer;
  • the connecting conductor layer is provided on the side of the passivation layer away from the base substrate, and the connecting conductor layer is connected to the first protective conductor layer through the first via hole so that the data line metal
  • the layer is conductively connected to the connecting conductor layer.
  • the display substrate in the non-display area further includes:
  • the gate metal layer is provided on one side of the base substrate, and the orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the data line metal layer on the base substrate do not cross each other Stack
  • the gate insulating layer is disposed on the side of the gate metal layer away from the base substrate, the gate insulating layer is provided with a third via hole, and the data line metal layer is located far from the gate insulating layer. Said one side of the base substrate;
  • the passivation layer is provided on a side of the gate insulating layer away from the base substrate, a second via is provided on the passivation layer, and the connecting conductor layer passes through the second via and the The third via hole is connected to the gate metal layer.
  • the display substrate in the non-display area further includes:
  • the gate metal layer is provided on one side of the base substrate, and the orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the data line metal layer on the base substrate do not cross each other Stack
  • the gate insulating layer is disposed on the side of the gate metal layer away from the base substrate, the gate insulating layer is provided with a third via hole, and the data line metal layer is located far from the gate insulating layer. Said one side of the base substrate;
  • the first protective conductor layer extends to a side of the gate insulating layer away from the base substrate, and the first protective conductor layer is connected to the gate metal layer through the third via hole.
  • the display substrate in the non-display area further includes:
  • the gate metal layer is provided on one side of the base substrate, and the orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the data line metal layer on the base substrate do not cross each other Stack
  • the gate insulating layer is disposed on the side of the gate metal layer away from the base substrate, the gate insulating layer is provided with a third via hole, and the data line metal layer is located far from the gate insulating layer. Said one side of the base substrate;
  • the second protective conductor layer is provided on a side of the gate insulating layer away from the base substrate, and the second protective conductor layer is connected to the gate metal layer through the third via;
  • the passivation layer is provided on a side of the second protective conductor layer away from the base substrate, a second via is provided on the passivation layer, and the connecting conductor layer passes through the second via It is connected to the second protective conductor layer to make the gate metal layer and the connection conductor layer conductively connected.
  • the first protective conductor layer and the second protective conductor layer are formed of the same layer and the same material, and the first protective conductor layer is connected to the second protective conductor layer As one; or
  • the first protective conductor layer and the second protective conductor layer are formed of the same layer and the same material, and a space is provided between the first protective conductor layer and the second protective conductor layer.
  • the display substrate in the display area includes:
  • the first electrode is provided on one side of the base substrate, and the side of the first electrode away from the base substrate is provided with the passivation layer;
  • the second electrode is provided on the side of the passivation layer away from the base substrate;
  • first electrode and the first protective conductor layer are formed of the same layer and the same material
  • second electrode and the connecting conductor layer are formed of the same layer and the same material
  • the first electrode is a pixel electrode
  • the second electrode is a slit electrode, and is used to form a multi-dimensional electric field with the first electrode.
  • the display substrate in the display area further includes:
  • the gate is provided on one side of the base substrate, and the gate insulating layer is provided on the side of the gate away from the base substrate;
  • the active layer is provided on the side of the gate insulating layer away from the base substrate;
  • the source and drain are provided on the side of the active layer away from the base substrate and on the side of the first electrode close to the base substrate.
  • the source and drain include a source and a drain. Electrode, the source electrode is directly connected to the first electrode;
  • the source and drain electrodes are formed of the same layer and the same material as the data line metal layer; the gate and the gate metal layer are formed of the same layer and the same material.
  • the material of the data line metal layer and the gate metal layer is metallic copper.
  • a method for manufacturing a display substrate including:
  • a first protective conductor layer is formed on the side of the data line metal layer away from the base substrate, and the orthographic projection of the first protective conductor layer on the base substrate is at the same position as the data line metal layer.
  • the orthographic projections on the base substrate at least partially overlap;
  • a connecting conductor layer is formed on the side of the passivation layer away from the base substrate, and the connecting conductor layer is connected to the first protective conductor layer through the first via hole so that the data line metal layer Conductive connection with the connecting conductor layer.
  • the preparation method before forming the data line metal layer, the preparation method further includes:
  • a gate metal layer is formed in the non-display area of the base substrate, and the orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the data line metal layer on the base substrate do not cross each other Stack
  • a gate insulating layer is formed on a side of the gate metal layer away from the base substrate, and the data line metal layer is formed on a side of the gate insulating layer away from the base substrate.
  • the passivation layer is further formed on a side of the gate insulating layer away from the base substrate; while the first via is formed, the A second via is formed on the passivation layer and a third via is formed on the gate insulating layer, so that the connecting conductor layer is connected to the gate metal layer through the second via and the third via.
  • the preparation method further includes:
  • a second protective conductor layer is formed on the side of the gate insulating layer away from the base substrate, and the second protective conductor layer passes through the third via hole and The gate metal layer connection;
  • the passivation layer is also formed on a side of the second protective conductor layer away from the base substrate; while forming the first via hole, a second via hole is formed on the passivation layer, The connecting conductor layer is connected to the second protective conductor layer through the second via hole.
  • the first protective conductor layer and the second protective conductor layer are connected as a whole, or the first protective conductor layer and the second protective conductor layer are arranged between There are compartments.
  • the preparation method further includes:
  • the first protective conductor layer is also formed on a side of the gate insulating layer away from the base substrate, and the first protective conductor layer is connected to the gate metal layer through the third via hole.
  • a first electrode is formed on one side of the display area of the base substrate, and the first electrode is a pixel electrode, And the passivation layer is formed on the side of the first electrode away from the base substrate;
  • a second electrode is formed on the side of the passivation layer of the display area away from the base substrate, and the second electrode is a common electrode.
  • a display panel including the display substrate described in any one of the above.
  • a display device including the display panel described in any one of the above.
  • FIG. 1 is a schematic diagram of the structure of a non-display area of a display substrate in the related art
  • FIG. 2 is a schematic structural diagram of an exemplary embodiment of a non-display area of a display substrate of the present disclosure
  • FIG. 3 is a schematic diagram of the structure in FIG. 2 when the connecting conductor layer and the alignment film have not been formed;
  • FIG. 4 is a schematic structural diagram of another exemplary embodiment of a non-display area of a display substrate of the present disclosure
  • FIG. 5 is a schematic structural diagram of another exemplary embodiment of a non-display area of a display substrate of the present disclosure
  • FIG. 6 is a schematic structural view of still another exemplary embodiment of a non-display area of a display substrate of the present disclosure
  • FIG. 7 is a schematic structural diagram of an exemplary embodiment of a display area of a display substrate of the present disclosure.
  • FIG. 8 is a schematic block diagram of the flow of an exemplary embodiment of a method for preparing a substrate according to the present disclosure.
  • FIG. 1 shows a schematic diagram of the structure of the non-display area of the display substrate in the related art shown in FIG. 1; a gate metal layer 61 is provided on one side of the base substrate 1, and a side of the gate metal layer 61 away from the base substrate 1 is provided
  • the gate insulating layer 7 is provided with a third via 71 on the gate insulating layer 7, a data line metal layer 21 is provided on the side of the gate insulating layer 7 away from the base substrate 1, and the data line metal layer 21 is on the base substrate
  • the orthographic projection on 1 and the orthographic projection of the gate metal layer 61 on the base substrate 1 do not overlap each other.
  • a passivation layer 4 is provided on the side of the data line metal layer 21 and the gate insulating layer 7 away from the base substrate 1, and a first via 41 and a second via are provided on the passivation layer 4.
  • a connecting conductor layer 51 is provided on the side of the passivation layer 4 away from the base substrate 1. The connecting conductor layer 51 is connected to the data line metal layer 21 through the first via 41, and the connecting conductor layer 51 passes through the second via and the first via. The three vias are connected to the gate metal layer 61.
  • the third via 71 on the gate insulating layer 7 in the non-display area and the second via 42 on the passivation layer 4 can be formed by one photolithography process. Therefore, in this process, the gate metal layer 61 There is always the protection of the gate insulating layer 7, which reduces the possibility of oxidation and corrosion of the gate metal layer. Since the data line metal layer 21 is exposed to the air on the surface away from the base substrate 1, the probability of oxidation is significantly increased, and the lotion used when forming other film layers in this process can directly contact the data line metal layer. This increases the risk of the data line metal layer 21 being corroded, resulting in an abnormal increase in the contact resistance between the data line metal layer 21 and the connecting conductor layer 51, which affects the subsequent bridging performance with the gate metal layer 61.
  • a display substrate is provided. Refer to the structural schematic diagrams of an exemplary embodiment of the non-display area of the display substrate of the present disclosure shown in FIGS. 2-6; the display substrate may include a base substrate 1, a data The wire metal layer 21, the first protective conductor layer 31, the passivation layer 4, and the connecting conductor layer 51; the data wire metal layer 21 is provided on one side of the base substrate 1; the first protective conductor layer 31 is provided on the data On the side of the wire metal layer 21 away from the base substrate 1, the orthographic projection of the first protective conductor layer 31 on the base substrate 1 and the orthographic projection of the data wire metal layer 21 on the base substrate 1 at least partially overlap
  • the passivation layer 4 is provided on the side of the first protective conductor layer 31 away from the base substrate 1, the passivation layer 4 is provided with a first via 41; the connecting conductor layer 51 is provided on the On the side of the passivation layer 4 away from the base substrate 1, the connecting conductor layer 51 is connected to the first protective conductor layer 31 through
  • FIG. 2 and FIG. 3 structural schematic diagrams of an exemplary embodiment of the non-display area of the display substrate of the present disclosure.
  • a gate metal layer 61 is provided on the base substrate 1, a gate insulating layer 7 is provided on the side of the gate metal layer 61 away from the base substrate 1, and a gate insulating layer 7 is provided on the gate insulating layer 7.
  • the three vias 71 are provided with a data line metal layer 21 on the side of the gate insulating layer 7 away from the base substrate 1.
  • the orthographic projection of the data line metal layer 21 on the base substrate 1 and the gate metal layer 61 on the base substrate The orthographic projections on 1 do not overlap each other.
  • a first protective conductor layer 31 is provided on the side of the data line metal layer 21 away from the base substrate 1.
  • the orthographic projection of the first protective conductor layer 31 on the base substrate 1 and the data line metal layer 21 on the base substrate 1 overlap at least partially, that is, the first protective conductor layer 31 at least partially covers the area of the data line metal layer 21 exposed by the first via 41. Further, the first protective conductor layer 31 may completely cover the data line metal layer. The area of the layer 21 exposed by the first via 41.
  • a passivation layer 4 is provided on the side of the first protective conductor layer 31 and the gate insulating layer 7 away from the base substrate 1, and a first via 41 and a second via 43 are provided on the passivation layer 4.
  • the second via 42 and the third via 71 are in communication.
  • a connecting conductor layer 51 is provided on the side of the passivation layer 4 away from the base substrate 1.
  • the connecting conductor layer 51 is connected to the first protective conductor layer 31 through the first via 41, and the first protective conductor layer 31 can conduct electricity, thereby
  • the connection conductor layer 51 and the data line metal layer 21 can be electrically connected.
  • the connecting conductor layer 51 is connected to the gate metal layer 61 through the second via 42 and the third via 71.
  • the gate insulating layer 7 and the passivation layer 4 can be made of materials with similar properties, and the materials with similar properties can be patterned by etching with the same etching solution, so that only one photolithography can be used.
  • the process forms a second via 42 on the passivation layer 4 and a third via 71 on the gate insulating layer 7. Therefore, before the second via 42 is formed, the surface of the gate metal layer 61 away from the base substrate 1 is covered by the gate insulating layer 7, so there is no need to provide a protective conductor layer to protect the gate metal layer 61, that is, the first protective conductor.
  • the orthographic projection of the layer 31 on the base substrate 1 and the orthographic projection of the gate metal layer 61 on the base substrate 1 do not overlap.
  • the above-mentioned similar properties means that the same etching agent can be used for etching.
  • silicon oxide, silicon nitride, a mixture of silicon oxide and silicon nitride are all materials with similar properties.
  • the material properties for forming the gate insulating layer 7 and the passivation layer 4 are quite different, and cannot be etched by the same etchant, that is, the gate cannot be etched by only one photolithography process.
  • the third via 71 is formed on the insulating layer 7 and the second via 42 is formed on the passivation layer 4. It is necessary to form the third via 71 on the gate insulating layer 7 and then form the second via on the passivation layer 4. Two through holes 44. At this time, the part of the surface of the gate insulating layer 7 away from the base substrate 1 is exposed to the air because the third via 71 has been formed, and may be oxidized and corroded. It is necessary to introduce a protective conductor layer on the gate metal layer 61. Protect it.
  • the following three example embodiments are specific descriptions of the structure of the non-display area of the display substrate in this case.
  • FIG. 4 for a schematic structural view of another exemplary embodiment of the non-display area of the display substrate of the present disclosure.
  • a gate metal layer 61 is provided on the base substrate 1, a gate insulating layer 7 is provided on the side of the gate metal layer 61 away from the base substrate 1, and a gate insulating layer 7 is provided on the gate insulating layer 7.
  • the three vias 71 are provided with a data line metal layer 21 on the side of the gate insulating layer 7 away from the base substrate 1.
  • the orthographic projection of the data line metal layer 21 on the base substrate 1 and the gate metal layer 61 on the base substrate The orthographic projections on 1 do not overlap each other.
  • a first protective conductor layer 31 is provided on the side of the data line metal layer 21 away from the base substrate 1.
  • the orthographic projection of the first protective conductor layer 31 on the base substrate 1 and the data line metal layer 21 on the base substrate 1 The orthographic projection on the base substrate at least partially overlaps, and a first protective conductor layer 31 is also provided on the side of the gate insulating layer 7 away from the base substrate 1, and the orthographic projection of the first protective conductor layer 31 on the base substrate 1 and The orthographic projection of the gate metal layer 61 on the base substrate 1 at least partially overlaps, that is, the first protective conductor layer 31 at least partially covers the area of the gate metal layer 61 exposed by the third via 71, and the first protective conductor layer 31 It is connected to the gate metal layer 61 through the third via 71. Further, the first protective conductor layer 31 may also completely cover the area of the gate metal layer 61 exposed by the third via 71.
  • the data line metal layer 21 and the gate metal layer 61 are connected through the first protective conductor layer 31.
  • a passivation layer 4 is provided on the side of the first protective conductor layer 31 away from the base substrate 1, and a first via 41 is provided on the passivation layer 4.
  • a connecting conductor layer 51 is provided on the side of the passivation layer 4 away from the base substrate 1. The connecting conductor layer 51 is connected to the first protective conductor layer 31 through the first via 41, and the first protective conductor layer 31 can conduct electricity, thereby
  • the data line metal layer 21 and the gate metal layer 61 are electrically connected through the connecting conductor layer 51 and the first protective conductor layer 31.
  • a second via 42 is provided on the passivation layer 4, and the connecting conductor layer 51 is connected to the first protective conductor layer 31 through the second via 42 to realize multiple overlapping modes , Reduce the lap resistance and improve the reliability of the lap.
  • FIG. 6 for a schematic structural view of another exemplary embodiment of the non-display area of the display substrate of the present disclosure.
  • a gate metal layer 61 is provided on the base substrate 1, a gate insulating layer 7 is provided on the side of the gate metal layer 61 away from the base substrate 1, and a gate insulating layer 7 is provided on the gate insulating layer 7.
  • the three vias 71 are provided with a data line metal layer 21 on the side of the gate insulating layer 7 away from the base substrate 1.
  • the orthographic projection of the data line metal layer 21 on the base substrate 1 and the gate metal layer 61 on the base substrate The orthographic projections on 1 do not overlap each other.
  • a first protective conductor layer 31 is provided on the side of the data line metal layer 21 away from the base substrate 1.
  • a second protective conductor layer 32 is provided on the side of the gate insulating layer 7 away from the base substrate 1, and the second protective conductor layer 32 is connected to the gate metal layer 61 through a third via 71, and the second protective conductor layer 32 is The orthographic projection on the base substrate 1 and the orthographic projection of the gate metal layer 61 on the base substrate 1 at least partially overlap, that is, the second protective conductor layer 32 at least partially covers the gate metal layer 61 exposed by the third via 71 Furthermore, the second protective conductor layer 32 may also completely cover the area of the gate metal layer 61 exposed by the third via 71.
  • the first protective conductor layer 31 and the second protective conductor layer 32 are formed by the same patterning process.
  • a passivation layer 4 is provided on the side of the first protective conductor layer 31 and the second protective conductor away from the base substrate 1, and a first via 41 and a second via 42 are provided on the passivation layer 4.
  • a connecting conductor layer 51 is provided on the side of the passivation layer 4 away from the base substrate 1.
  • the connecting conductor layer 51 is connected to the first protective conductor layer 31 through the first via 41, and the first protective conductor layer 31 can conduct electricity, thereby
  • the connection conductor layer 51 and the data line metal layer 21 can be electrically connected.
  • the connecting conductor layer 51 is connected to the second protective conductor layer 32 through the second via hole 42, and the second protective conductor layer 32 can conduct electricity, so that the connecting conductor layer 51 and the gate metal layer 61 can be electrically connected.
  • the alignment film 9 is provided on the side of the connecting conductor layer 51 away from the base substrate 1.
  • FIG. 7 for a schematic structural diagram of an exemplary embodiment of the display area of the display substrate of the present disclosure.
  • the display substrate in the display area may include a gate 62, a gate insulating layer 7, an active layer 8, a source electrode 221, a drain electrode 222, a first electrode 33, a passivation layer 4, and a second electrode 52.
  • a gate 62 is provided on one side of the base substrate 1
  • a gate insulating layer 7 is provided on the side of the gate 62 away from the base substrate 1 and the side of the base substrate 1
  • the gate insulating layer 7 is far away from the base substrate 1.
  • An active layer 8 is provided on one side of the base substrate 1
  • a source electrode 221 and a drain electrode 222 are provided on the side of the active layer 8 away from the base substrate 1.
  • the source electrode 221 and the drain electrode 222 are electrically connected to the active layer respectively .
  • a first electrode 33 is provided on the side of the source electrode 221 away from the base substrate 1, the source electrode 221 and the first electrode 33 are directly overlapped, and the drain electrode 222 is electrically connected to the data line (not shown in the figure) to input to the pixel unit Pixel signal.
  • a passivation layer 4 is provided on the side of the first electrode 33 away from the base substrate 1, and a second electrode 52 is provided on the side of the passivation layer 4 away from the base substrate 1.
  • An alignment film 9 is provided on one side of one surface of the substrate 1. It should be noted that the source electrode 221 and the first electrode 33 directly overlap, which means that at least part of the first electrode 33 is formed on the surface of the source electrode 221 away from the base substrate 1.
  • the display substrate is used for a liquid crystal display panel, and the display mode is Advanced Super Dimension Switch (ADS), where the first electrode 33 may be a slit electrode or a plate shape.
  • the second electrode 52 can be a slit electrode.
  • the electric field generated by the edge of the slit electrode in the same plane and the electric field between the slit electrode layer and the plate electrode layer form a multi-dimensional electric field, so that the gap between the slit electrodes in the liquid crystal cell , All oriented liquid crystal molecules directly above the electrode can be rotated to achieve display.
  • the source electrode 221 and the drain electrode 222 are formed of the same layer and the same material as the data line metal layer 21, and the gate 62 and the gate metal layer 61 are formed of the same layer and the same material.
  • the first electrode 33 may be a pixel electrode, and the second electrode 52 may be a common electrode. In order to reduce the space occupied by signal connection, the first electrode 33 and the source electrode 221 may be directly connected, as shown in FIG. 7, for example, The first electrode 33 at least partially covers the surface of the source electrode 221 away from the base substrate 1 to achieve an effective electrical connection between the two, and at the same time can optimize the pixel aperture ratio, thereby improving the transmittance of the display product.
  • the first electrode 33 and the first protective conductor may be formed of the same layer and the same material.
  • the second electrode 52 and the connecting conductor layer 51 may also be formed of the same layer and the same material. It should be noted that the formation of the same layer and the same material mentioned here refers to the formation of patterns by using the same material in the same patterning process. Multiple structures with different functions can be formed through the same patterning process, and various functional requirements of the product can be met without increasing the process flow, which not only saves manpower and material resources, but also improves product performance.
  • the material of the gate 62, the source 221, the drain 222, the data line metal layer 21, and the gate metal layer 61 may be metallic copper.
  • the data line metal layer 21 and the gate metal layer 61 can increase the refresh rate; but because the nature of copper is more active, when exposed to the air Or when it is in direct contact with other etching agents, poor metal corrosion will occur.
  • the first protective conductor layer 31, the gate insulating layer 7, and the second protective conductor layer 32 can protect the metal copper from exposure to the air or direct contact with other etching agents, and prevent the conductor layer 51 from being connected to the data line.
  • the contact resistance between the metal layer 21 and the gate metal layer 61 is abnormally increased, which improves the metal bridge performance.
  • a method for preparing a display substrate is also provided. Referring to the schematic flow diagram of an exemplary embodiment of the method for preparing a display substrate of the present disclosure shown in FIG. 8, the preparation method includes the following steps:
  • Step S10 providing a base substrate 1 with a display area and a non-display area
  • Step S20 forming a data line metal layer 21 on the non-display area of the base substrate 1;
  • a first protective conductor layer 31 is formed on the side of the data line metal layer 21 away from the base substrate 1.
  • the orthographic projection of the first protective conductor layer on the base substrate and the The orthographic projection of the data line metal layer on the base substrate at least partially overlaps;
  • Step S40 forming a passivation layer 4 on the side of the first protective conductor layer 31 away from the base substrate 1, and patterning the passivation layer 4 to form a first via 41;
  • a connecting conductor layer 51 is formed on the side of the passivation layer 4 away from the base substrate 1, and the connecting conductor layer 51 passes through the first via 41 and the first protective conductor layer 31 It is connected to make the data line metal layer 21 and the connecting conductor layer 51 conductively connected.
  • a base substrate 1 is provided, and the base substrate 1 may be a glass substrate.
  • the base substrate 1 is provided with a display area and a non-display area; a display structure is formed in the display area, and a binding structure, various circuits, etc. are formed in the non-display area.
  • a gate material layer is formed on the base substrate 1 through processes such as evaporation or sputtering, and the gate material layer is patterned so that the gate material layer forms a gate 62 in the display area and a gate 62 in the non-display area.
  • Metal layer 61 is formed on the base substrate 1 through processes such as evaporation or sputtering, and the gate material layer is patterned so that the gate material layer forms a gate 62 in the display area and a gate 62 in the non-display area.
  • a gate insulating layer 7 is formed on the side of the gate 62 and the gate metal layer 61 away from the base substrate 1. Among them, if the material for forming the gate insulating layer 7 and the material properties of the passivation layer 4 to be formed later are quite different and cannot be etched by the same etchant, it is necessary to pattern the part of the gate insulating layer 7 in the non-display area Chemical treatment to form a third via 71.
  • An active layer 8 is formed on the side of the gate insulating layer 7 away from the base substrate 1, and a source and drain material layer is formed on the side of the active layer 8 away from the base substrate 1 through evaporation or sputtering processes, and the source
  • the drain material layer is patterned to form a source electrode 221 and a drain electrode 222 in the display area, wherein the source electrode 221 and the drain electrode 222 are electrically connected to the active layer, respectively.
  • a data line metal layer 21 is formed on the side of the gate insulating layer 7 away from the base substrate 1.
  • the data line metal layer 21 and the source electrode 221 and the drain electrode 222 can also be formed of the same layer and the same material, that is, in the display area and the non-display area.
  • the first conductive material layer is formed in all regions, and then the first conductive material layer is patterned once to form the source electrode 221, the drain electrode 222 and the data line metal layer 21 at the same time.
  • a first electrode material layer is formed on the side of the source electrode 221 and the drain electrode 222 away from the base substrate 1, and the first electrode material layer is patterned to form the first electrode 33 in the display area.
  • the source electrode 221 and the first electrode 33 are directly connected, and the drain electrode 222 is electrically connected to a data line (not shown in the figure) to input pixel signals to the pixel unit.
  • a first protective conductor layer 31 is formed on the side of the data line metal layer 21 away from the base substrate 1, or a first protective conductor layer 31 and a second protective conductor are formed on the side of the data line metal layer 21 away from the base substrate 1.
  • Layer 32 is formed on the side of the data line metal layer 21 away from the base substrate 1.
  • first electrode 33, the first protective conductor layer 31, and the second protective conductor layer 32 can also be formed of the same layer and the same material, that is, the first electrode material layer is formed in the display area and the non-display area, and then the first electrode material layer is formed in the display area and the non-display area.
  • An electrode material layer is subjected to a patterning process once to form the first electrode 33 in the display area, and at the same time to form the first protective conductor layer 31 and the second protective conductor layer 32 in the non-display area.
  • the first protective conductor layer 31 is provided only on the side of the data line metal layer 21 away from the base substrate 1, namely The orthographic projection of the first protective conductor layer 31 on the base substrate 1 and the orthographic projection of the data line metal layer 21 on the base substrate 1 at least partially overlap, and the first protective conductor layer 31 at least partially covers the data line metal layer 21
  • the area exposed by the first via 41, further, the first protective conductor layer 31 may also completely cover the area exposed by the first via 41 of the data line metal layer 21.
  • the first protective conductor layer 31 also extends to the area where the gate metal layer 61 is located, that is, the orthographic projection of the first protective conductor layer 31 on the base substrate 1 and the data line metal layer 21 on the base substrate 1 While the orthographic projections at least partially overlap, the orthographic projection of the first protective conductor layer 31 on the base substrate 1 also at least partially overlaps the orthographic projection of the gate metal layer 61 on the base substrate 1.
  • the first protective conductor The layer 31 at least partially covers the area of the data line metal layer 21 exposed by the first via 41, and at least partially covers the area of the gate metal layer 61 exposed by the third via 71. Further, the first protective conductor layer 31 can also completely cover the area of the data line metal layer 21 exposed by the first via 41. Similarly, the first protective conductor layer 31 can also completely cover the third area of the gate metal layer 61. The exposed area of the via 71.
  • first protective conductor layer 31 is provided on the side of the data line metal layer 21 away from the base substrate 1
  • second protective conductor layer 32 is provided on the side of the gate metal layer 61 away from the base substrate 1.
  • the first protective conductor layer 31 and the second protective conductor layer 32 are not connected to each other, that is, a space is provided between the two.
  • the orthographic projection of the first protective conductor layer 31 on the base substrate 1 At least partially overlaps with the orthographic projection of the data line metal layer 21 on the base substrate 1, that is, the first protective conductor layer 31 at least partially covers the area of the data line metal layer 21 exposed by the first via 41, and further, the first A protective conductor layer 31 can also completely cover the area exposed by the first via 41 of the data line metal layer 21; the orthographic projection of the second protective conductor layer 32 on the base substrate 1 and the gate metal layer 61 on the base substrate 1
  • the orthographic projections above overlap at least partially, that is, the second protective conductor layer 32 at least partially covers the area of the gate metal layer 61 exposed by the third via 71.
  • the second protective conductor layer 32 may also completely cover the gate metal layer 61. The area exposed by the third via 71.
  • the passivation layer 4 is formed on the side of the first protective conductor layer 31 away from the base substrate 1, or on the side of the first protective conductor layer 31 and the second protective conductor layer 32 away from the base substrate 1. 4 Perform a patterning process to form the first via 41, or perform a patterning process on the passivation layer 4 to form the first via 41 and the second via 42 respectively.
  • a number of exemplary embodiments corresponding to the structure of the non-display area of the display substrate described above, one is that only one side of the data line metal layer 21 is provided with the first protective conductor layer 31.
  • the other is to provide a first protective conductor layer 31 on one side of the data line metal layer 21 and a second protective conductor layer 32 on one side of the gate metal layer 61.
  • the first via 41 and the second via 42 can be formed on the passivation layer 4.
  • the first via 41 is connected to the first protective conductor layer 31, and the second via 42 is connected to the second protective conductor.
  • the first protective conductor layer 31 also extends to the area where the gate metal layer 61 is located.
  • first via 41 or the second via 42 may be formed on the passivation layer 4.
  • the via 41 or the second via 42 is connected to the first protective conductor layer 31.
  • the first via 41 and the second via 42, and the first via 41 and the second via can also be formed at the same time. 42 are all connected to the first protective conductor layer 31, thereby realizing multiple overlapping modes, reducing the overlapping resistance, and improving the reliability of the overlapping.
  • the material for forming the gate insulating layer 7 is similar to the material for forming the passivation layer 4, while the first via 41 and the second via 42 are formed on the passivation layer 4, A third via hole needs to be formed on the gate insulating layer 7.
  • a second electrode material layer is formed on the side of the passivation layer 4 away from the base substrate 1, and the second electrode material layer is patterned to form a second electrode in the display area and a connecting conductor layer 51 in the non-display area .
  • the connecting conductor layer 51 is connected to the first protective conductor layer 31 through the first via 41, and the connecting conductor layer 51 is connected to the gate metal layer 61 through the second via 42 and the third via 71 .
  • the connecting conductor layer 51 is connected to the first protective conductor layer 31 through the first via 41.
  • the connecting conductor layer 51 is connected to the first protective conductor layer 31 through the first via 41, and the connecting conductor layer 51 is connected to the second protective conductor layer 32 through the second via 42.
  • the connecting conductor layer 51 may also be connected to the first protective conductor layer 31 through the first via 41 and the second via 42 respectively.
  • the present disclosure also provides a display panel, which includes the above-mentioned display substrate.
  • the specific structure of the display substrate has been described in detail above, so it will not be repeated here.
  • the beneficial effects of the display panel provided by the embodiments of the present disclosure are the same as the beneficial effects of the display substrate provided by the above-mentioned embodiments, and will not be repeated here.
  • the present disclosure also provides a display device, which includes the above-mentioned display panel.
  • the specific type of the display device is not particularly limited.
  • the types of display devices commonly used in the field can be used, such as liquid crystal displays, OLED displays, mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc. The personnel can make a corresponding selection according to the specific purpose of the display device, which will not be repeated here.
  • the display device also includes other necessary components and components. Taking the display as an example, specific examples include a housing, a circuit board, a power cord, etc. The specific usage requirements shall be supplemented accordingly, which will not be repeated here.
  • the beneficial effects of the display device provided by the embodiments of the present disclosure are the same as the beneficial effects of the display substrate provided by the above-mentioned embodiments, and will not be repeated here.
  • the terms “a”, “a”, “the” and “said” are used to indicate the presence of one or more elements/components/etc.; the terms “including”, “including” and “have” are used to It means open-ended inclusion and means that in addition to the listed elements/components/etc., there may be other elements/components/etc.; the terms “first”, “second” and “third” “, etc. are only used as markers, not as a restriction on the number of objects.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne un substrat d'affichage et son procédé de préparation, ainsi qu'un panneau d'affichage et un dispositif d'affichage. Le substrat d'affichage comprend un substrat de base (1), le substrat de base étant pourvu d'une région d'affichage et d'une région de non-affichage et le substrat d'affichage comprenant en outre une couche métallique de ligne de données (21), une première couche conductrice de protection (31), une couche de passivation (4) et une couche conductrice de connexion (51) dans la région de non-affichage ; la couche métallique de ligne de données est disposée sur un côté du substrat de base ; la première couche conductrice de protection est disposée sur le côté de la couche métallique de ligne de données à l'opposé du substrat de base ; la couche de passivation est disposée sur le côté de la première couche conductrice de protection à l'opposé du substrat de base et un premier trou traversant (41) est disposé sur la couche de passivation ; la couche conductrice de connexion est disposée sur le côté de la couche de passivation à l'opposé du substrat de base et la couche conductrice de connexion est connectée à la première couche conductrice de protection au moyen du premier trou traversant de telle sorte que la couche métallique de ligne de données soit connectée de manière conductrice à la couche conductrice de connexion. La couche métallique de ligne de données peut être protégée par la première couche conductrice de protection et empêchée d'être exposée à l'air et d'être en contact direct avec d'autres agents de gravure qui pourraient provoquer une oxydation et une corrosion nocives. Les performances de pontage métallique sont ainsi améliorées.
PCT/CN2020/141653 2020-03-27 2020-12-30 Substrat d'affichage et son procédé de préparation, panneau d'affichage et dispositif d'affichage Ceased WO2021190055A1 (fr)

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CN114823728A (zh) * 2022-04-19 2022-07-29 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN114843302A (zh) * 2022-05-06 2022-08-02 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示装置
CN115172433A (zh) * 2022-08-12 2022-10-11 北京京东方显示技术有限公司 显示基板及其制备方法、显示面板、显示装置
CN115274702A (zh) * 2022-07-28 2022-11-01 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN115343890A (zh) * 2022-08-22 2022-11-15 合肥京东方光电科技有限公司 阵列基板和显示面板
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CN111403423B (zh) * 2020-03-27 2023-04-14 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板和显示装置
CN111999947A (zh) * 2020-08-11 2020-11-27 深圳市华星光电半导体显示技术有限公司 一种显示面板及显示装置
CN113363304B (zh) * 2021-06-03 2022-09-13 武汉天马微电子有限公司 一种显示面板和显示装置
CN117215106A (zh) * 2023-09-08 2023-12-12 京东方科技集团股份有限公司 显示面板和显示装置

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US12130981B2 (en) 2021-04-30 2024-10-29 Chengdu Boe Optoelectronics Technology Co., Ltd. Display device and display apparatus including the same
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CN114823728A (zh) * 2022-04-19 2022-07-29 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
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CN115172433A (zh) * 2022-08-12 2022-10-11 北京京东方显示技术有限公司 显示基板及其制备方法、显示面板、显示装置
CN115343890A (zh) * 2022-08-22 2022-11-15 合肥京东方光电科技有限公司 阵列基板和显示面板

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