WO2021237509A1 - Clock and data recovery circuit, processing chip and electronic device - Google Patents

Abstract

A clock and data recovery circuit, a processing chip and an electronic device. The clock and data recovery circuit comprises an edge detector, a flip circuit (2), a delay chain (3), a delay control module (4) and a clock delay module (5), wherein the delay control module (4) is used for adjusting a delay time of the delay chain (3) according to the phase of a first clock signal and the phase of a second clock signal until the phase of the first clock signal is consistent with the phase of the second clock signal, and the second clock signal is a first clock signal delayed by the delay chain (3); and the flip circuit (2) is used for resetting the first clock signal when detecting that a reset signal, which is obtained after the first clock signal is delayed by the delay chain (3), is at a high level. For digital signals of different rates, a delay time of a delay chain is adaptively adjusted, so as to obtain clock signals that match the rates of the digital signals, such that adaptation to the recovery of the digital signals of various rates can be realized.

Description

Clock data recovery circuit, processing chip and electronic equipment Technical field

This application relates to the field of signal processing technology, and in particular to a clock data recovery circuit, processing chip and electronic equipment.

Background technique

The Mobile Industry Processor Interface (MIPI) alliance is an open standard and a specification formulated for mobile application processors, serving to effectively increase bandwidth and reduce power consumption. The MIPI Alliance has self-defined three circuit specifications: D-physical layer protocol (referred to as D-PHY), M-physical layer protocol (referred to as M-PHY) and C-physical layer protocol (referred to as C-PHY). Among them, in D-PHY, the transmitting side device directly sends a clock signal to the receiving side device through a clock channel, so that the receiving side device can recover the data, while C-PHY uses three-phase signal technology by embedding in the transmitted data The clock transfers data. Compared with D-PHY, C-PHY can transmit 2.28 times the data at the same symbol rate. It can be seen that C-PHY can achieve high data throughput under the premise of low power consumption. .

Existing cameras, display screens, mobile communications, storage, etc. are on the physical layer of the connection. The requirements for data line rate are getting higher and higher, and the number of data lines used is decreasing. Each Trio group of C-PHY The line includes three lines. When C-PHY is used as the physical layer of the connection, it has the advantages of high speed and few lines.

For two devices connected with the C-PHY MIPI interface, the transmitting side device has three signal voltage strengths: high, medium, and low. The receiving side device calculates the difference between the three signals and uses the developed codec conversion chart to perform Decode and restore the signal clock at the same time.

Summary of the invention

The purpose of the embodiments of the present application is to provide a clock data recovery circuit, processing chip, and electronic equipment that adaptively adjust the delay time of the delay chain for digital signals of different rates to obtain a clock signal that matches the rate of the digital signal. , So as to be able to adapt to the recovery of multiple rates of digital signals.

The embodiment of the application provides a clock data recovery circuit, including: an edge detector, a flip circuit, a delay chain, a delay control module, and a clock delay module; the edge detector is used to obtain the rising edge of a set of input digital signals to obtain a Group of pulse signals; the flip circuit is used to generate a corresponding rising edge on the output first clock signal when the rising edge of any pulse signal in a group of pulse signals is detected; the delay control module is used to generate a corresponding rising edge on the first clock signal according to the first clock signal. Phase and the phase of the second clock signal, adjust the delay time of the delay chain until the phase of the first clock signal is consistent with the phase of the second clock signal, where the second clock signal is the first clock signal delayed by the delay chain; The flip circuit is used to detect that the reset signal obtained after the first clock signal is delayed by the delay chain is at a high level, and the first clock signal is set to zero; the clock delay module is used to delay the first clock signal according to the delay time of the delay chain Through processing, the third clock signal is obtained, and the third clock signal is input to the collector, so that the collector can recover a group of digital signals according to the third clock signal.

The embodiment of the present application also provides a processing chip including the above-mentioned clock data recovery circuit.

An embodiment of the present application also provides an electronic device including the above-mentioned processing chip.

The embodiment of the application is now based on the prior art, the edge detector can obtain the rising edge of each digital signal in a set of input digital signals, and generate a set of pulse signals. After the inversion circuit receives the set of pulse signals, it can detect When the rising edge of any pulse signal in the group of pulse signals is reached, the corresponding rising edge is generated on the output first clock signal, the second clock signal obtained after the first clock signal is delayed by the delay chain, the delay control module The delay time of the delay chain can be adjusted according to the phase of the first clock signal and the phase of the second clock signal, until the phase of the first clock signal is consistent with the phase of the second clock signal, and the first clock signal is delayed by the delay chain The obtained reset signal is input to the flip circuit. When the flip circuit detects that the reset signal is at a high level, it sets the first clock signal to zero. After the above process, the first clock signal is also input to the clock delay module, which is then The first clock signal can be delayed according to the delay time of the delay chain, and the third clock signal can be obtained and input to the collector, so that the collector can recover the data signal according to the third clock signal. Signal, adaptively adjust the delay time of the delay chain to obtain a clock signal that matches the rate of the digital signal, so as to be able to adapt to the recovery of multiple rates of digital signals.

For example, the delay chain includes a first half delay chain and a second half delay chain, and the delay time of the first half delay chain is equal to the delay time of the second half delay chain; the delay control module is used to compare the phase of the first clock signal with the The phase of the second clock signal, adjust the delay time of the first half of the delay chain and the delay time of the second half of the delay chain; the flip circuit is used to detect the reset of the first clock signal after the delay of the first half of the delay chain in the delay chain When the signal is at a high level, the first clock signal is set to zero; the clock delay module is used to delay the first clock signal according to the delay time of the first half of the delay chain or the delay time of the second half of the delay chain to obtain the third Clock signal. In this embodiment, the delay chain is divided into two identical half-delay chains to facilitate the output of the reset signal from the half-delay position of the delay chain, which is more convenient.

For example, the first half-delay chain and the second half-delay chain have the same structure; each half-delay chain includes N delay units, and N is an integer greater than 0; the delay control module is used to compare the phase of the first clock signal with The phase of the second clock signal is adjusted to the N value of each half of the delay chain. This embodiment provides specific structures of the first half-delay chain and the second half-delay chain, and a specific manner for adjusting the delay time of each half-delay chain.

For example, the first half-delay chain is used to determine the Mth delay unit to the Nth delay unit as the tap interval according to the value of N, and select a delay unit from the tap interval as the tap delay connection point, and The signal output from the tap delay contact point is used as the reset signal, and M is the difference of N minus the preset value. This embodiment provides an implementation method for generating a reset signal, which can reduce the transmission delay of the line, the delay caused by the process and the temperature to a certain extent, and make the output clock signal more accurate.

For example, the first half-delay chain is used to select the N-1th delay unit from the N delay units as the tap-delay connection point.

For example, each half-delay chain also includes a NOR circuit; the first half-delay chain is used to receive the first clock signal through the included NOR circuit; the second half-delay chain is connected to the first through the included NOR circuit Half-delay chain, the second half-delay chain is also used to be closed when the closing control signal is received through the included NOR circuit. In this embodiment, the second half of the delay chain can be turned off when the turn-off control signal is received through the NOR circuit to reduce power consumption.

For example, the delay control module includes a phase comparator and a detector; the phase comparator is used to obtain a phase difference value according to the phase of the first clock signal and the phase of the second clock signal; the detector is used to generate a delay adjustment according to the phase difference value Time delay control signal, and send the delay control signal to the delay chain. In this embodiment, a specific structure of the delay air module is provided.

For example, the phase comparator is used to obtain multiple phase difference values based on the phase of the first clock signal and the phases of multiple second clock signals output from the delay chain taps; the detector is used to obtain multiple phase difference values based on the average cumulative value of the multiple phase difference values, Generate a delay control signal for adjusting the delay time, and send the delay control signal to the delay chain; the detector is used to determine the first clock signal and the second clock signal when the average cumulative value of multiple phase difference values is less than a preset threshold value The phases are the same. In this embodiment, the phase comparison can calculate multiple phase difference values, and the detector can calculate an average cumulative value based on the multiple phase difference values, and generate a delay control signal for adjusting the delay time according to the average cumulative value. A more accurate delay control signal can be obtained.

For example, the detector is used to generate a delay control signal for increasing the delay time when the average cumulative value is positive; the detector is used to generate a delay control signal for reducing the delay time when the average cumulative value is negative.

For example, a set of digital signals includes three digital signals; the edge detector includes three edge detector circuits corresponding to the three digital signals; each edge detector circuit includes an exclusive OR circuit and a delay module; each exclusive OR circuit The first input terminal of each XOR circuit is used to receive the corresponding digital signal, the second input terminal of each XOR circuit is used to receive the corresponding digital signal delayed by the delay module, and the XOR circuit is used to output and receive through the output terminal. The digital signal corresponds to a pulse signal. This embodiment provides a specific structure of the edge detector.

For example, the flip circuit includes a first XOR gate circuit, a second XOR gate circuit, a NAND gate circuit, a first PMOS tube, a second PMOS tube, an NMOS tube, a first inverter, a second inverter, and a first inverter. Three inverters; the input terminal of the first exclusive OR circuit is used to receive a set of pulse signals, and the output terminal of the first exclusive OR circuit is respectively connected to the first input terminal of the second exclusive OR circuit and the NAND circuit The first input terminal of the first inverter is used to receive the reset signal, the output terminal of the first inverter is connected to the second input terminal of the NAND circuit through the second inverter, and the second XOR The second input terminal of the gate circuit is used to receive the reset signal passing through the first inverter; the output terminal of the second exclusive OR circuit is connected to the gate of the first PMOS transistor, the source of the first PMOS transistor and the second PMOS The source of the tube is connected to the power supply terminal, the drain of the first PMOS tube is connected to the drain of the NMOS tube and the input terminal of the third inverter, and the gate of the second PMOS tube is used to receive the For the reset signal of the inverter, the drain of the second PMOS tube is connected to the input terminal of the third inverter, and the source of the NMOS tube is connected to the reference potential terminal; the output terminal of the third inverter is used to output the first clock signal. This embodiment provides a specific structure of the flip circuit.

For example, each half-delay chain also includes a register corresponding to each delay unit; the delay control module is used to adjust the value of each register according to the phase of the first clock signal and the phase of the second clock signal for the connection of the register The delay unit is turned on or off based on the value of the register. This embodiment provides a specific implementation manner for controlling the number of access delay units in a half-delay chain.

For example, a group of digital signals includes: three digital signals obtained by decoding the C-PHY signal.

Description of the drawings

One or more embodiments are exemplified by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. The elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the attached drawings do not constitute a scale limitation.

Fig. 1 is a schematic diagram of a clock data recovery circuit according to the first embodiment of the present application;

2 is a schematic diagram of a third clock signal obtained after a set of pulse signals pass through a clock data recovery circuit in the first embodiment of the present application;

Fig. 3 is a schematic diagram of a clock data recovery circuit according to a second embodiment of the present application;

4 is a schematic diagram of the first half-delay chain and the second half-delay chain in the third embodiment of the present application;

FIG. 5 is a schematic diagram of a semi-delay chain according to a third embodiment of the present application;

6 is a schematic diagram of the first half-delay chain and the second half-delay chain according to the third embodiment of the present application, wherein each half-delay chain further includes a NOR circuit;

FIG. 7 is a schematic diagram of a clock data recovery circuit in a fourth embodiment of the present application;

FIG. 8 is a specific implementation manner of outputting multiple second clock signals to a phase comparator according to the delay chain in the fourth embodiment of the present application;

Fig. 9 is a schematic diagram of a flip circuit in a clock data recovery circuit according to a fifth embodiment of the present application.

Specific embodiment

In order to make the objectives, technical solutions, and advantages of the present application clearer, the following describes the embodiments of the present application in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not used to limit the present application.

At present, when the receiving side device recovers the clock of the data signal of the sending side device, a fixed delay is generally set, but the same delay is used for data signals of different rates, which will cause the recovered clock signal to be inaccurate. Based on this, the inventor proposed the technical solution of this application.

The first embodiment of this application relates to a clock and data recovery (Clock and Data Recovery, CDR) circuit, which can be applied to a processing chip in an electronic device. For example, it can be used as a part of a processor chip and connected to the C of the processor chip. -PHY type MIPI interface to obtain the signal containing the clock, and recover the clock and data from the signal. The CDR can be a low-voltage CDR circuit. The electronic device can include both a receiving side device and a sending side device. The sending side device can be an image sensor, display screen, memory, etc. in the electronic device, and the receiving side device can be the above The processing chip, the transmitting side device and the receiving side device can be connected through the C-PHY type MIPI interface.

Please refer to FIG. 1, the clock data recovery circuit of this embodiment includes an edge detector, a flip circuit 2, a delay chain 3, a delay control module 4, and a clock delay module 5. In an example, the clock data recovery circuit further includes a collector 6.

In this example, the input to the clock data recovery circuit is a set of digital signals, including three digital signals, which are the A signal, the B signal, and the C signal in the figure. In one example, the edge detector includes the A signal and the B signal. And three edge discrimination circuits corresponding to the three digital signals of the C signal one-to-one. Each edge discrimination circuit includes an exclusive OR circuit and a delay module 12. The three exclusive OR gates are the exclusive OR gates XOR1 and XOR in the figure. Gate XOR2 and exclusive OR gate XOR3.

It should be noted that the set of digital signals in this example are three digital signals obtained by the C-PHY signal from the transmitting-side device after the signal processing in the processing chip. Specifically, the transmitting-side device and the receiving-side device pass When the C-PHY MIPI interface is connected, there are three connecting lines between the transmitting side device and the receiving side device. The C-PHY signal received by the receiving side device includes x signal, y signal, z signal, x signal, y signal, z The signal includes three voltages: high, medium and low. The processing chip calculates the difference between the two voltages in the x signal, y signal, and z signal, and obtains three digital signals based on the codec conversion diagram of C-PHY, which is this implementation In the example, the A signal, B signal, and C signal are input to the CDR.

The edge detector is used to obtain the rising edge of a set of input digital signals to obtain a set of pulse signals; specifically, for the edge detector circuit in the edge detector, the first input terminal of each XOR gate is used to receive For corresponding digital signals, the second input terminal of each XOR gate is used to receive the corresponding digital signal delayed by the delay module, and the XOR gate circuit is used to output a pulse signal corresponding to the received digital signal through the output terminal. Take the A signal as an example. The A signal is directly input to the first input terminal of the XOR gate XOR1, and the A signal is delayed by the delay module 12 and then input to the second input terminal of the XOR gate XOR1. The delay time of the delay module 12 is the preset value. Set the value, that is, the A signal and the A signal are input to the two input terminals of the exclusive OR gate XOR1 after being delayed, so that the rising edge of the A signal can be obtained, and the pulse signal A_pluse signal corresponding to the A signal can be obtained; similarly, the B signal can be obtained The corresponding pulse signal B_pluse signal, the pulse signal C_pluse signal corresponding to the C signal, the A_pluse signal, the B_pluse signal, and the C_pluse signal form a set of pulse signals corresponding to a set of digital signals. For the three edge detection circuits, the delay times of the delay modules 12 included in them are generally set equal, for example, 50 picoseconds. The flip circuit 2 is used to generate a corresponding rising edge on the output first clock signal when the rising edge of any pulse signal in a set of pulse signals is detected, specifically, the output terminal of the XOR gate XOR1, the XOR gate The output terminal of XOR2 and the output terminal of XOR gate XOR3 are respectively connected to the three input terminals of flip circuit 2, that is, A_pluse signal, B_pluse signal and C_pluse signal are simultaneously input to flip circuit 2. For each group of pulse signals, flip circuit 2 is When the rising edge of any one of the A_pluse, B_pluse, and C_pluse signals in the group of pulse signals is detected, a rising edge from 0 to 1 is generated on the output first clock signal C_CLK.

The output ends of the flip circuit 2 are respectively connected to the delay chain 3, the delay control module 4, and the clock delay module 5, so that the first clock signal C_CLK can be input to the delay chain 3, the delay control module 4, and the clock delay module 5, respectively. One output terminal of 3 is connected to the first input terminal of the delay control module 4, the output terminal of the flip circuit 2 is connected to the second input terminal of the delay control module 4, and the other output terminal of the delay chain 3 is connected to the flip circuit 2. The output terminal of the control module 4 is connected to the delay chain 3.

After the first clock signal C_CLK is delayed by the delay chain 3, the second clock signal D_CLK is obtained. The first input terminal of the delay control module 4 receives the second clock signal D_CLK, and the second input terminal of the delay control module 4 receives the second clock signal D_CLK. Flip the first clock signal C_CLK output by the circuit 2, at this time, the delay control module 4 can adjust the delay time T1 of the delay chain 3 according to the phase of the first clock signal C_CLK and the phase of the second clock signal D_CLK, until the first clock signal C_CLK The phase of is consistent with the phase of the second clock signal D_CLK.

The delay chain 3 is connected to the output terminal of the flipping circuit 2. After the first clock signal C_CLK is delayed by the first half delay chain 31, the reset signal RST_EN is obtained. The reset signal RST_EN is output to the flipping circuit 2, and the flipping circuit 2 is also used for When detecting that the reset signal RST_EN is at a high level, the first clock signal is set to zero, that is, the flip circuit 2 receives the reset signal RST_EN output by the delay chain 3, and when the reset signal RST_EN is 1, the first clock signal C_CLK is set to zero , So that the next rising edge can be obtained; and due to the delay of the delay chain 3, if there are multiple rising edges in the A_pluse signal, B_pluse signal, and C_pluse signal during the delay period, only one of the first clock signal C_CLK can be set The rising edge can prevent the flip circuit 2 from repeatedly setting multiple rising edges in the first clock signal C_CLK.

The clock delay module 5 is used to delay the first clock signal C_CLK according to the delay time T1 of the delay chain 3 to obtain the third clock signal CDR_CLK, and input the third clock signal CDR_CLK to the collector 6 for the collector 6 according to The third clock signal CDR_CLK restores the data signal. Specifically, the clock delay module 5 can obtain the delay time T1 of the delay chain 3, and then adjust its own delay time T2 according to the delay time T1 of the delay chain 3 to obtain a delay time greater than the setup time of the collector 6 to ensure that the collector 6Able to recover the clock and signal.

Among them, the time delay module 6 can be connected to the delay chain 3, so that the delay time T1 of the delay chain 3 can be read. The clock delay module 5 is provided with a calculation formula for the delay time T2 of the time delay module 6 so as to be based on the delay Time T1 obtains its own delay time T2. For example, T1 represents the delay time of the delay chain 3, and T2 represents the delay time of the time delay module 6. The calculation formula of the delay time T2 is: T2=(K+a) *T1/2, K is a positive integer, 0<a<0.2.

In this embodiment, the collector 6 can collect the A signal, the B signal, and the C signal according to the third clock signal CDR_CLK, and then recover the corresponding RA signal, RB signal, and RC signal. Specifically, it is delayed by the first clock signal C_CLK. When the third clock signal CDR_CLK is obtained, it can include all the rising edges of any of the three digital signals of A signal, B signal, and C signal. The A signal, the B signal and the C signal are sequentially input to the collector 6, the collector 6 Based on each rising edge of the third clock signal CDR_CLK, the signal is recovered once to obtain a signal including the clock, so that the RA signal, the RB signal and the RC signal corresponding to the A signal, the B signal, and the C signal can be obtained. Please refer to FIG. 2, which is a schematic diagram of a third clock signal CDR_CLK obtained after a group of pulse signals pass through the clock data recovery circuit in this embodiment.

Compared with the prior art, in this embodiment, the edge detector can obtain the rising edge of each digital signal in a set of input digital signals to generate a set of pulse signals. After receiving the set of pulse signals, the flipping circuit can detect When the rising edge of any pulse signal in the group of pulse signals, the corresponding rising edge is generated on the output first clock signal. The second clock signal obtained after the first clock signal is delayed by the delay chain, the delay control module can According to the phase of the first clock signal and the phase of the second clock signal, adjust the delay time of the delay chain until the phase of the first clock signal is consistent with the phase of the second clock signal, and the first clock signal is delayed by the delay chain. The reset signal is input to the flip circuit. When the flip circuit detects that the reset signal is at a high level, it sets the first clock signal to zero. After the above process, the first clock signal is also input to the clock delay module. The clock delay module can The first clock signal is delayed according to the delay time of the delay chain, and the third clock signal is obtained and input to the collector for the collector to recover the data signal according to the third clock signal. In this embodiment, for digital signals of different rates , Adaptively adjust the delay time of the delay chain to obtain a clock signal that matches the rate of the digital signal, so as to adapt to the recovery of digital signals at multiple rates.

The second embodiment of the present application relates to a clock data recovery circuit. Compared with the first embodiment, the main difference of this embodiment is that the delay chain is divided into two identical sub-delay chains.

In this embodiment, referring to FIG. 3, the delay chain 3 includes a first half delay chain 311 and a second half delay chain 32. One output terminal of the first half delay chain 31 is connected to the input terminal of the second half delay chain 32. The other output terminal of the first half delay chain 31 is connected to the flip circuit 2, the output terminal of the second half delay chain 32 is connected to the first input terminal of the delay control module 4, and the output terminals of the delay control module 4 are respectively connected to the first input terminal. The half-delay chain 31 and the second half-delay chain 32. The delay time of the first half-delay chain 311 is equal to the delay time of the second half-delay chain 32.

The delay control module 4 is configured to adjust the delay time T11 of the first half delay chain 31 and the delay time T12 of the second half delay chain 32 according to the phase of the first clock signal C_CLK and the phase of the second clock signal D_CLK.

After the first clock signal C_CLK passes through the first half delay chain 31 and the second half delay chain 32 in turn, the second clock signal D_CLK is obtained. The delay control module 4 receives the second clock signal D_CLK through the first input terminal and passes the second clock signal D_CLK. The second input terminal receives the first clock signal C_CLK, the delay control module 4 can adjust the delay time of the first half delay chain 31 and the delay time of the second half delay chain 32 according to the first clock signal C_CLK and the second clock signal D_CLK, Until the phase of the first clock signal C_CLK is consistent with the phase of the second clock signal D_CLK.

In this embodiment, when the phase of the first clock signal C_CLK is consistent with the phase of the second clock signal D_CLK, it means that the first clock signal C_CLK and the second clock signal D_CLK can be considered to be two clock signals with the same frequency and phase. At this time, the delay time T11 of the first half delay chain 31 is half of the clock period of the third clock signal output, and then the first clock signal C_CLK is delayed by the first half delay chain 31 to obtain the reset signal RST_EN, and the reset signal RST_EN can be The first clock signal C_CLK output by the flip circuit 2 generates a rising edge and resets it to zero, which can ensure that the flip circuit 2 detects the next rising edge in the pulse signal, and at the same time, due to the delay of the first half delay chain 31 to avoid flipping Circuit 2 flips multiple rising edges in a group of pulse signals within the delay time.

Since the output terminal of the first half delay chain 31 is connected to the flip circuit 2, when the first half delay chain 31 receives the first clock signal C_CLK through the input terminal, the first clock signal C_CLK is delayed by the first half delay chain 31 Then get the reset signal RST_EN, and output the reset signal RST_EN to the flip circuit 2. After the flip circuit 2 receives the reset signal RST_EN, if the reset signal RST_EN is 1, the first clock signal C_CLK is set to zero, so that the next clock signal C_CLK is set to zero. The rising edge is acquired, and due to the delay of the first half delay chain 31, if there are multiple rising edges in the A_pluse signal, B_pluse signal, and C_pluse signal during the delay period, only one rising edge can be set in the first clock signal C_CLK, It can be avoided that the flip circuit 2 repeatedly sets multiple rising edges in the first clock signal C_CLK.

In this embodiment, when the phase of the first clock signal C_CLK is consistent with the phase of the second clock signal D_CLK, it means that the first clock signal C_CLK and the second clock signal D_CLK can be considered to be two clock signals with the same frequency and phase. At this time, the delay time of the first half delay chain 31 is half of the clock period of the output third clock signal CDR_CLK, and then the first clock signal C_CLK is delayed by the first half delay chain 31 to obtain the reset signal RST_EN, and the reset signal RST_EN can be in The first clock signal C_CLK output by the flip circuit 2 generates a rising edge and resets it to zero, which can ensure that the flip circuit 2 detects the next rising edge in the pulse signal, and at the same time, due to the delay of the first half delay chain 31 to avoid flipping Circuit 2 flips multiple rising edges in a group of pulse signals within the delay time.

The clock delay module 5 is used to delay the first clock signal C_CLK according to the delay time T11 of the first half delay chain 31 or the delay time T12 of the second half delay chain 32 to obtain the third clock signal CDR_CLK; where the clock delay The module 5 is connected to the first half-delay chain 31 or the second half-delay chain 32 (not shown in the figure). The clock delay module 5 is provided with a calculation formula for the delay time T2 of the time delay module 6, so that it can be based on the first half The delay time T11 of the delay chain 31 or the delay time T12 of the second half delay chain 32 is substituted into the calculation formula to obtain the own delay time T2. For example, the calculation formula of the delay time T2 of the clock delay module 5 is T2=(K+a)*T11, K is a positive integer, 0<a<0.2.

Compared with the prior art, this embodiment divides the delay chain into two identical half-delay chains to facilitate the output of the reset signal from the half-delay position of the delay chain, which is more convenient.

The third embodiment of the present application relates to a clock data recovery circuit. Compared with the second embodiment, the main difference of this embodiment is that the specific structure of the half-delay chain and its delay time adjustment method are provided.

In this embodiment, the first half-delay chain 31 and the second half-delay chain 32 have the same structure. Please refer to FIG. 4. Each half-delay chain includes N delay units connected in series in sequence, and each delay unit has one The preset delay time T3, the delay time of each delay unit in each half-delay chain can be set equal, at this time the delay time of the half-delay chain is N*T3; among them, the delay unit can be a buffer The N delay units are the buffer BUF1 to the buffer BUFN in Fig. 4, N is an integer greater than 0, and the N buffers BUF are connected in series in sequence.

In this embodiment, N buffers BUF are connected in series to form a first half delay chain 31, and N buffers BUF are connected in series to form a second half delay chain 32. The first half delay chain 31 and the second half delay chain 31 are connected in series. The chain 32 can form a delay chain 3 containing 2N buffers BUF, the first half-delay chain 31 includes the first N buffers, the second half-delay chain 32 includes the last N buffers, and the buffer of the first half-delay chain 31 The BUFN is connected to the BUF1 of the second half-delay chain 32, and the first half-delay chain 31 and the second half-delay chain 32 are respectively connected to the delay control module 4.

The delay control module 4 is used for adjusting the N value of each half of the delay chain according to the phase of the first clock signal C_CLK and the phase of the second clock signal D_CLK. Specifically, taking the maximum length value of the first half-delay chain 31 as an example, the N value of the buffer BUF currently accessed by the first half-delay chain 31 is b, that is, the output tap of the b-th buffer BUF is taken as the first half-delay chain 31. Half of the output of the delay chain 31, the delay control module 4 adjusts the N value of the buffer BUF connected to the first half delay chain 31 according to the phase of the first clock signal C_CLK and the phase of the second clock signal D_CLK, until the first half of the delay chain 31 The phase of the clock signal C_CLK is consistent with the phase of the second clock signal D_CLK, and c represents the adjusted N value, that is, the N value of the buffer BUF connected to the first half-delay chain 31 is c, and the c-th buffer The output tap of the BUF is used as the output of the first half-delay chain 31, that is, the delay time of the first half-delay chain 31 is controlled. The control method of the second half-delay chain 32 is similar to that of the first half-delay chain 31, and will not be repeated here.

In this embodiment, each half-delay chain also includes a register corresponding to each delay unit, so the delay control module 4 can control the opening or closing of the delay unit connected to it by adjusting the value of the register. Specifically, the delay control module 4 adjusts the value of each register according to the phase of the first clock signal and the phase of the second clock signal, so that the delay unit connected to the register turns on or off based on the value of the register, and controls the connection in the half-delay chain. The number of incoming delay units. Specifically, when the value of the register is 1, the delay unit connected to the register is in the on state; when the value of the register is 0, the delay unit connected to the register is in the off state. Taking the maximum length of a half-delay chain as an example, if the number of delay units currently connected to the half-delay chain is k, it means that the value of the register connected to the first k delay units in the half-delay chain is 1. The value of the register connected to the last ak delay units is 0. If the number of delay units connected to the half-delay link is controlled to be L, the value of the register connected to the first L delay units in the half-delay chain is controlled to 1, The value of the register connected to the last aL delay units is 0. At this time, the number of delay units connected to the half-delay link is L.

In this embodiment, the delay unit used to output the reset signal RST_EN to the flip circuit 2 in the first half delay chain 31 is called the tap delay contact point, and a preset value X is set in the first half delay chain 31, when After the N value of the first half of the delay chain 31 is determined, the difference M of N minus the preset value X is calculated, and the M-th delay unit to the N-th delay unit are used as the tap interval, and the tap interval is selected A delay unit is used as the tap delay connection point, and the signal output from the tap delay connection point is input to the flip circuit 2 as the reset signal RST_EN, that is, the first clock signal C_CLK passes through the first delay unit to the tap delay connection point The reset signal RST_EN obtained by the delay generated by the delay unit is input to the flip circuit 2. Taking FIG. 5 as an example, the buffer BUFM to the buffer BUFN of the first half delay chain 31 forms a tap interval, and a buffer is selected from the buffer BUFM to the buffer BUFN included in the tap interval as the tap delay output point, and The delay signal output from the tap delay contact point is input to the flip circuit 2 as the reset signal RST_EN, which can reduce the transmission delay of the line, the delay caused by the process and the temperature to a certain extent, so that the first clock signal is output more precise.

In an example, the N-1th delay unit from the N delay units of the first half-delay chain 31 is selected as the tap delay connection point, and the signal output from the tap delay connection point is used as the reset signal, namely The first clock signal C_CLK is delayed by the first N-1 buffers to obtain the reset signal RST_EN, and the reset signal RST_EN is input to the flip circuit 2.

In an example, each half-delay chain further includes a NOR circuit; please refer to FIG. 6, the first half-delay chain 31 includes a NOR gate NOR31, and the second half-delay chain 32 includes a NOR gate NOR41.

The first half of the delay chain 31 receives the first clock signal C_CLK through the input terminal of the NOR gate NOR31, the output terminal of the NOR gate NOR31 is connected to the buffer BUF1, the buffer BUF1 to the buffer BUFN are connected in series in sequence, and the second half delay chain 32 One input terminal of the NOR gate NOR41 is connected to the buffer BUFN of the first delay chain 3, the output terminal of the NOR gate NOR41 is connected in series with the BUF1 to BUFN of the second half delay chain 32, and the other of the NOR gate NOR41 The input terminal is connected to a controller (not shown in the figure) in the processing chip, and the controller is used to output a closing control signal to the NOR gate NOR41, which is closed when receiving the closing control signal.

Exemplarily, the controller of the processing chip is connected to the clock control module 4, so that when the phase of the first clock signal C_CLK is consistent with the phase of the second clock signal D_CLK, it can output the shutdown control signal to the second half of the delay chain 32. The NOR gate NOR41 is used to close the second half delay chain 32 to reduce power consumption. The controller of the processing chip controls the second half-delay chain 32 to remain closed during the current input time of the data signal, and re-controls the second half-delay chain 32 to open when a new data signal is input.

It should be noted that this embodiment can also set multiple delay chains in the clock data recovery circuit according to data signals of different rates, and each delay chain corresponds to a data signal of one rate, and the delay unit contained in each delay chain Each delay chain includes a first half-delay chain 31 and a second half-delay chain 32.

It should be noted that this embodiment can also set multiple delay chains in the clock data recovery circuit according to data signals of different rates, and each delay chain corresponds to a data signal of one rate, and the delay unit contained in each delay chain Each delay chain includes a first half-delay chain 31 and a second half-delay chain 32.

Compared with the second embodiment, this embodiment provides the specific structure of the half-delay chain and its delay time adjustment method.

The fourth embodiment of the present application relates to a clock data recovery circuit. Compared with the second embodiment, the main difference of this embodiment is: please refer to FIG. 7, the delay control module 4 includes a phase comparator 41 and a detector 42 . Wherein, the phase comparator 41 is a phase detector, and the detector 42 may be a digital filter, for example, an average counter.

The first input terminal of the phase comparator 41 forms the first input terminal of the delay control module 4, the second input terminal of the phase comparator 41 forms the second input terminal of the delay control module 4, and the output terminal of the second half-delay chain 32 is connected At the first input terminal of the phase comparator 41 to receive the second clock signal D_CLK, the second input terminal of the phase comparator 41 is connected to the flip circuit 2 to receive the first clock signal C_CLK, and the output terminal of the phase comparator 41 is connected At the input end of the detector 42, the output end of the detector 42 is respectively connected to the first half-delay chain 31 and the second half-delay chain 32.

The phase comparator 41 is used to obtain the phase difference value according to the phase of the first clock signal C_CLK and the phase of the second clock signal D_CLK; specifically, the phase comparator 41 calculates the phase of the first clock signal C_CLK minus the second clock signal D_CLK The phase difference value of the phase.

The detector 42 is used to generate a delay control signal for adjusting the delay time according to the phase difference value, and send the delay control signal to the delay chain, that is, to send the delay control signal to the first half-delay chain 31 and the second half-delay respectively Chain 32 to adjust the delay time T11 of the first half-delay chain 31 and the delay time T12 of the second half-delay chain 32.

In an example, the phase comparator 41 is used to obtain multiple phase difference values according to the phase of the first clock signal C_CLK and the phases of the multiple second clock signals output from the delay chain taps. For details, please refer to FIG. 8. Take a delay chain including 2N delay units as an example, that is, select multiple delay units from 2N delay units as tap points, and input the signals output from these multiple tap points as the second clock signal D_CLK to the phase comparison. At this time, the phase comparator 41 respectively calculates the phase difference value of the first clock signal C_CLK minus the phase of each second clock signal D_CLK, so as to obtain multiple phase difference values.

The detector 42 is used to generate a delay control signal for adjusting the delay time according to the average cumulative value of a plurality of phase difference values, and send the delay control signal to the delay chain, that is, to send the delay control signal to the first half of the delay chain respectively 31 and the second half-delay chain 32 to adjust the delay time T11 of the first half-delay chain 31 and the delay time T12 of the second half-delay chain 32.

The detector 42 is also used for determining that the phase of the first clock signal C_CLK is consistent with the phase of the second clock signal D_CLK when the absolute value of the average cumulative value of the plurality of phase difference values is less than or equal to the preset threshold, and there is no need to continue to check the first clock signal C_CLK. The delay time T11 of the half-delay chain 31 and the delay time T12 of the second half-delay chain 32 are adjusted. Wherein, the preset threshold is greater than or equal to zero.

In this embodiment, the detector 42 adjusts the delay time of the delay chain when the absolute value of the average cumulative value of the multiple phase difference values is greater than the preset threshold. When the average cumulative value is positive, it generates A delay control signal with a large delay time; when the average cumulative value is negative, a delay control signal for reducing the delay time is generated.

Specifically, when the detector 42 receives multiple phase difference values sent by the phase comparator 41, it can calculate an average cumulative value based on the multiple phase difference values. If the average cumulative value is positive and greater than the preset value Threshold, it means that the phase of the second clock signal D_CLK is too early, the detector 42 generates a delay control signal for increasing the delay time, and outputs it to the first half delay chain 31 and the second half delay chain 32, respectively, and waits for a new second clock signal D_CLK. The second clock signal D_CLK is input to the phase comparator 41, and the above judgment process is repeated; if the average cumulative value is negative and the absolute value of the average cumulative value is greater than the preset threshold, it means that the phase of the second clock signal D_CLK is too late. The detector 42 generates a delay control signal for reducing the delay time and outputs it to the first half-delay chain 31 and the second half-delay chain 32 respectively, and waits for a new second clock signal D_CLK to be input to the phase comparator 41, and repeats the above judgment Process; until the absolute value of the average cumulative value is less than or equal to the preset threshold, it is determined that the phase of the first clock signal C_CLK is consistent with the phase of the second clock signal D_CLK.

The method of controlling the delay time of the delay chain by the delay control signal will be described in detail below in conjunction with the delay chain structure of FIG. 4 in the third embodiment.

Taking the N value of the buffer BUF currently accessed by the first half-delay chain 31 as an example, when the detector 42 generates a delay control signal for increasing the delay time, it controls the buffer that the first half-delay chain 31 accesses. The number of BUF increases, and the increased number can be the preset step value z, that is, when the detector 42 needs to increase the delay time of the first delay chain 3, it assigns a value of b+z to N, that is, the first delay chain is controlled. The number of buffers BUF connected to the half-delay chain 31 is increased to b+z, and the output tap of the b+z-th buffer BUF is used as the output of the first half-delay chain 31; otherwise, the detector 42 generates When the delay control signal is used to reduce the delay time, the number of buffers BUF connected in the first half-delay chain 31 is reduced. The reduced number can be a preset step value z, that is, the detector 42 is in need When reducing the delay time of the first delay chain 3, N is assigned to bz, that is, the number of buffers BUF connected in the first half-delay chain 31 is reduced to bz, at this time the output of the bz-th buffer BUF The tap is used as the output of the first half delay chain 31. Wherein, the first half delay chain 31 may include an adjustment amount register for controlling the value of N, and the adjustment amount register stores the value of N to control the number of buffers BUF connected to the first half delay chain 31, namely , The detector 42 assigns the value of N in the adjustment register based on the need to adjust the delay time of the first half-delay chain 31, so as to control the output of the Nth buffer BUF in the first half-delay chain 31 The tap is used as the output of the first half delay chain 31, that is, the delay time of the first half delay chain 31 is controlled. The control method of the second half-delay chain 32 is similar to that of the first half-delay chain 31, and will not be repeated here.

In this example, the controller of the processing chip can also send the shutdown control signal to the phase comparator 41 and the detector 42 at the same time to turn off the phase comparator 41 and the detector 42, thereby further reducing power consumption. Among them, the controller of the processing chip controls the phase comparator 41 and the detector 42 to remain closed during the current data signal input time, and re-controls the phase comparator 41 and the detector 42 to turn on when a new data signal is input.

Compared with the first embodiment, this embodiment provides a specific structure of the delay control module.

The fifth embodiment of the present application relates to a clock data recovery circuit. Compared with the first embodiment, the main difference of this embodiment is: please refer to FIG. 9, the flip circuit 2 includes a first exclusive OR circuit NOR1 and a second The two exclusive OR circuit NOR2, the NAND circuit NAND, the first PMOS tube PM1, the second PMOS tube PM2, the NMOS tube NM1, the first inverter INV1, the second inverter INV2, and the third inverter INV3.

The input terminal of the first exclusive OR circuit NOR1 is used to receive pulse signals. Specifically, the first exclusive OR circuit NOR1 has three input terminals, and the three input terminals of the first exclusive OR circuit NOR1 simultaneously receive three pulse signals : A_pluse signal, B_pluse signal and C_pluse signal, the output terminal of the first exclusive OR circuit NOR1 is respectively connected to the first input terminal of the second exclusive OR circuit NOR2 and the first input terminal of the NAND circuit NAND, the first reverse The input terminal of the inverter is used to receive the reset signal RST_EN. The reset signal RST_EN passes through the first inverter INV1 to obtain the inverted signal RST_EN_b of the reset signal RST_EN. The output terminal of the first inverter INV1 is connected to the second inverter INV2. The second input terminal of the NAND circuit NAND and the second input terminal of the second exclusive OR circuit NOR2 are used to receive the reset signal through the first inverter INV1, that is, the inverted signal RST_EN_b; the second exclusive OR circuit NOR2 The output terminal of the first PMOS tube PM1 is connected to the gate of the first PMOS tube PM1, the source of the first PMOS tube PM1 and the source of the second PMOS tube PM2 are respectively connected to the power supply terminal VDD, and the drain of the first PMOS tube PM1 is respectively connected to the NMOS The drain of the tube NM1 is connected to the input terminal of the third inverter INV3, and the gate of the second PMOS tube PM2 is used to receive the reset signal RST_EN (not shown in the figure) passing through the first inverter INV1, that is, the inverted signal RST_EN_b is input to the gate of the second PMOS tube PM2; the drain of the second PMOS PM2 tube is connected to the input terminal of the third inverter INV3, and the source of the NMOS tube NM1 is connected to the reference potential terminal. In this embodiment, GND is used as the reference potential terminal, and the output terminal of the third inverter INV3 is used to output the first clock signal, that is, the third inverter INV3 is connected to the first half delay chain 31, the delay control module 4, and the clock delay module 5, respectively.

It should be noted that in FIG. 9, the inverted signal RST_EN_b of the reset signal RST_EN is obtained by the reset signal RST_EN through the first inverter INV1, and then restored through the second inverter INV2 to obtain the reset signal RST_EN input to the NAND circuit NAND. Take the second input terminal and input the inverted signal RST_EN_b of the reset signal RST_EN obtained by the first inverter INV1 to the gate of the second PMOS transistor PM2 as an example, but it is not limited to this, and the reset signal RST_EN can also be directly input to The second input terminal of the NAND circuit NAND, at the same time, the reset signal RST_EN is connected to the gate of the second PMOS transistor PM2 through an inverter, that is, the inverted signal RST_EN_b of the reset signal RST_EN is input to the gate of the second PMOS transistor PM2 pole.

Compared with the first embodiment, this embodiment provides a specific structure of the flip circuit.

The sixth embodiment of the present application relates to a processing chip, including the clock data recovery circuit of any one of the first to fifth embodiments. The processing chip is applied to an electronic device, and the electronic device can be a receiving-side device and a sending-side device. , The sending-side device may be a camera, display screen, memory, etc. in an electronic device, and the receiving-side device may be the aforementioned processing chip.

The seventh embodiment of the present application relates to an electronic device, including the processing chip of the sixth embodiment. The electronic device can be a receiving-side device and a sending-side device respectively, and the sending-side device can be a camera, a display screen, a memory, etc. in the electronic device. , The receiving device can be the above-mentioned processing chip.

Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific embodiments for realizing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and spirit of the present application. Scope.

Claims (15)

A clock data recovery circuit, which is characterized by comprising: an edge detector, a flip circuit, a delay chain, a delay control module, and a clock delay module; The edge detector is used to obtain the rising edge of a set of input digital signals to obtain a set of pulse signals; The flip circuit is configured to generate a corresponding rising edge on the output first clock signal when the rising edge of any pulse signal in the set of pulse signals is detected; The delay control module is configured to adjust the delay time of the delay chain according to the phase of the first clock signal and the phase of the second clock signal until the phase of the first clock signal and the phase of the second clock signal Consistent, wherein the second clock signal is the first clock signal delayed by the delay chain; The flip circuit is configured to set the first clock signal to zero when detecting that the reset signal obtained after the first clock signal is delayed by the delay chain is at a high level; The clock delay module is configured to delay processing the first clock signal according to the delay time of the delay chain to obtain a third clock signal, and input the third clock signal to a collector for the collection The device recovers the set of digital signals according to the third clock signal. The clock data recovery circuit of claim 1, wherein the delay chain includes a first half delay chain and a second half delay chain, and the delay time of the first half delay chain is the same as that of the second half delay chain. The delay time of the chain is equal; The delay control module is configured to adjust the delay time of the first half delay chain and the delay time of the second half delay chain according to the phase of the first clock signal and the phase of the second clock signal; The flip circuit is configured to detect that the reset signal obtained after the first clock signal is delayed by the first half delay chain in the delay chain is at a high level, and then set the first clock signal to zero; The clock delay module is configured to delay the first clock signal according to the delay time of the first half delay chain or the delay time of the second half delay chain to obtain a third clock signal. 3. The clock data recovery circuit according to claim 2, wherein the structure of the first half-delay chain and the second half-delay chain are the same; each half-delay chain includes N delay units, N is an integer greater than 0; The delay control module is configured to adjust the N value of each half-delay chain according to the phase of the first clock signal and the phase of the second clock signal. The clock data recovery circuit of claim 3, wherein the first half-delay chain is used to determine the M-th delay unit to the N-th delay unit as taps according to the value of N Interval, and select one of the delay units from the tap interval as the tap delay tap-out point, and use the signal output from the tap-delay tap-out point as the reset signal, where M is N minus a preset value Difference. The clock data recovery circuit according to claim 4, wherein the first half-delay chain is used to select the N-1th delay unit from the N delay units as a tap delay connection point. 4. The clock data recovery circuit of claim 3, wherein each half-delay chain further comprises a NOR circuit; The first half delay chain is used for receiving the first clock signal through the included NOR circuit; The second half-delay chain is connected to the first half-delay chain through the included NOR circuit, and the second half-delay chain is also used for receiving a turn-off control through the included NOR circuit When the signal is turned off. 3. The clock data recovery circuit of claim 1, wherein the delay control module comprises a phase comparator and a detector; The phase comparator is used to obtain a phase difference value according to the phase of the first clock signal and the phase of the second clock signal; The detector is used to generate a delay control signal for adjusting the delay time according to the phase difference value, and send the delay control signal to the delay chain. 7. The clock data recovery circuit of claim 7, wherein the phase comparator is used to determine the phase of the second clock signal output from the delay chain taps according to the phase of the first clock signal. , Get multiple phase difference values; The detector is configured to generate a delay control signal for adjusting the delay time according to the average cumulative value of the plurality of phase difference values, and send the delay control signal to the delay chain; The detector is used for determining that the phases of the first clock signal and the second clock signal are consistent when the average cumulative value of the plurality of phase difference values is less than a preset threshold. 8. The clock data recovery circuit according to claim 8, wherein the detector is configured to generate the delay control signal for increasing the delay time when the average cumulative value is positive; The detector is used for generating the delay control signal for reducing the delay time when the average cumulative value is negative. The adaptive clock data recovery circuit of claim 1, wherein the set of digital signals includes three digital signals; The edge discriminator includes three edge discriminating circuits respectively corresponding to the three digital signals; each of the edge discriminating circuits includes an exclusive OR circuit and a delay module; The first input terminal of each XOR gate circuit is used to receive the corresponding digital signal, and the second input terminal of each XOR gate circuit is used to receive the corresponding all signal delayed by the delay module. For the digital signal, the exclusive OR circuit is used to output the pulse signal corresponding to the received digital signal through an output terminal. The adaptive clock data recovery circuit of claim 1, wherein the flip circuit includes a first exclusive OR circuit, a second exclusive OR circuit, a NAND circuit, a first PMOS transistor, a second PMOS tube, NMOS tube, first inverter, second inverter and third inverter; The input terminal of the first XOR gate circuit is used to receive the set of pulse signals, and the output terminal of the first XOR gate circuit is connected to the first input terminal and the second XOR gate circuit respectively. The first input terminal of the NAND gate circuit, the input terminal of the first inverter is used to receive the reset signal, and the output terminal of the first inverter is connected to all the terminals through the second inverter. The second input terminal of the NAND gate circuit, the second input terminal of the second XOR circuit is used to receive the reset signal through the first inverter; the second XOR circuit The output terminal is connected to the gate of the first PMOS tube, the source of the first PMOS tube and the source of the second PMOS tube are respectively connected to the power terminal, and the drain of the first PMOS tube is respectively connected to At the drain of the NMOS transistor and the input terminal of the third inverter, the gate of the second PMOS transistor is used to receive the reset signal passing through the first inverter, and the second The drain of the PMOS tube is connected to the input terminal of the third inverter, and the source of the NMOS tube is connected to the reference potential terminal; The output terminal of the third inverter is used to output the first clock signal. 4. The adaptive clock data recovery circuit of claim 3, wherein each half-delay chain further comprises a register corresponding to each of the delay units; The delay control module is configured to adjust the value of each register according to the phase of the first clock signal and the phase of the second clock signal, so that the delay unit connected to the register is based on the value of the register Turn on or off. The adaptive clock data recovery circuit of claim 1, wherein the set of digital signals includes three digital signals decoded from C-PHY signals. A processing chip, characterized by comprising: the clock data recovery circuit according to any one of claims 1 to 14. An electronic device, characterized by comprising the processing chip of claim 14.

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