WO2022005292A1 - Décodage hybride de codes de produit et d'escalier à l'aide d'un décodage de distance limitée et d'un décodage d'erreur et d'effacement - Google Patents

Décodage hybride de codes de produit et d'escalier à l'aide d'un décodage de distance limitée et d'un décodage d'erreur et d'effacement Download PDF

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WO2022005292A1
WO2022005292A1 PCT/NL2021/050423 NL2021050423W WO2022005292A1 WO 2022005292 A1 WO2022005292 A1 WO 2022005292A1 NL 2021050423 W NL2021050423 W NL 2021050423W WO 2022005292 A1 WO2022005292 A1 WO 2022005292A1
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decoding
ibdd
bdd
hard decision
code
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Alireza SHEIKH
Alex Enrique ALVARADO SEGOVIA
Alexandre Graell I Amat
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Eindhoven Technical University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2909—Product codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H03M13/293—Decoding strategies with erasure setting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2948—Iterative decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45—Soft decoding, i.e. using symbol reliability information
    • H03M13/451—Soft decoding, i.e. using symbol reliability information using a set of candidate code words, e.g. ordered statistics decoding [OSD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • the present disclosure relates to decoding. Particular embodiments relate to a method for decoding received data encoded using an error correction code, and a related computer program, a related computer program product, and a related device.
  • the measure of reliability is calculated during the first decoding step.
  • the reliability may be obtained during, and preferably as a by-product of, the first decoding step.
  • the measure of reliability is calculated by determining a density evolution at constraint nodes of a Tanner graph of an ensemble comprising a class of the error correction code.
  • the hard decision is extended by one extra bit in each of its dimensions, wherein the one extra bit is 1 if either or both of the BDD decoding and the EED decoding were successful and is 0 if both of the BDD decoding and the EED decoding failed.
  • a computer program comprising instructions configured for, when executed by a processor, causing the processor to perform the method of any previously described embodiment.
  • a computer program product storing the computer program according to the above-described embodiment on a storage device.
  • a device preferably an optical transport network device or a wireless network device, comprising:
  • the device comprises a comparison circuit configured for comparing the first distance metric and the second distance metric, outputting one of the BDD decoded data and the EED decoded data based on an outcome of the comparing, and for updating the hard decision using the returned decoded data.
  • Figure 6 schematically illustrates a graph showing a comparison of performance expressed as a bit error rate, BER, or transmission reach improvement of one or more embodiments according to the present disclosure with respect to known techniques;
  • Figure 8 schematically illustrates operation of an embodiment of a method according to the present disclosure on a staircase code, SCC;
  • Figure 13 schematically illustrates an embodiment of a method according to the present disclosure.
  • Figures 3 and 4 show respectively a schematic of iBDD-CR [16] for decision on code bit at iteration I by ith row decoding with input ; and a schematic of iBDD-CR [16] for decision on code bit at iteration I by ith row decoding with input ; and a schematic of iBDD-CR [16] for decision on code bit at iteration I by ith row decoding with input ; and a schematic of iBDD-
  • Figure 5 schematically illustrates a graph showing a comparison of performance expressed as a bit error rate, BER, of one or more embodiments according to the present disclosure with respect to known techniques for PC with component code Ci;
  • Figure 6 schematically illustrates a graph showing a comparison of performance expressed as a bit error rate, BER, or transmission reach improvement of one or more embodiments according to the present disclosure with respect to known techniques.
  • the performance is of iBDD, ideal iBDD, iBDD-SR, iBDD-CR, and BEE-PC for PC with component code C2 in the BICM with (a) 4-QAM, (b) 16-QAM, (c) 64-QAM, and (d) 256-QAM modulation (e)
  • Figures 9, 10, 11 and 12 schematically illustrate graphs showing a comparison of performance expressed as a bit error rate, BER, or spectral efficiency, SE, of one or more embodiments according to the present disclosure with respect to known techniques.
  • Figure 9 shows a comparison between the simulation results of iBDD-CR for SCC and PC as well as the DE analysis of iBDD-CR for SC-GLDPC and GLDPC ensembles for (a) component code C 2 (b) component code C3.
  • Figure 11 shows a performance comparison of iBDD, AD, iBDD-SR, iBDD-CR, and BEE-SCC for SCC with component code C3.
  • the method 100 further comprises in a second decoding step 106 determining 107 at least two least reliable bits of the hard decision received data, based on the calculated measure of reliability; decoding 108 the received data, using error and erasure decoding, EED, wherein the determined at least two least reliable bits are considered to be erased; and determining 109 a second distance metric between the EED decoded data and the hard decision.
  • the method 100 further comprises comparing 110 the first distance metric and the second distance metric; and, based on an outcome of the comparing 110, outputting 111, i.e. returning an output as a result of the method to an entity or process that executed the method, e.g. called for execution of the method it in a device such as device 200 of Figure 14, one of the BDD decoded data and the EED decoded data.
  • method 100 and further developed embodiments thereof allow implementations wherein only so-called hard messages are exchanged between component codes, which improves overall efficiency, and thus allows for improved data rates.
  • Figure 14 schematically illustrates an embodiment of a device 200 according to the present disclosure.
  • the device 200 may preferably be an optical transport network device or a wireless network device, or may be a device coupled to a memory bank and adapted to correct storage errors of data stored on the memory bank.
  • the device 200 comprises at least one processor 201 and at least one memory 202.
  • the memory 202 stores a computer program according to any above-described embodiment.
  • the processor 201 is operatively coupled to the memory 202, such that it can execute instructions of the computer program in order to perform the method according to any above-described embodiment.
  • PCs Product codes
  • SCCs staircase codes
  • iBDD low-complex iterative bounded distance decoding
  • the performance of iBDD can be improved using soft-aided (hybrid) algorithms.
  • the latest algorithm in this class of decoders is called iBDD with combined reliability (iBDD- CR), recently proposed for PCs.
  • iBDD-CR we generalize iBDD-CR and improve on its performance, and thus, the contributions of the present disclosure are two.
  • iBDD-CR we extend iBDD-CR to SCCs, where the reliability of BDD outbound messages is estimated through density evolution analysis of the underlying spatially- coupled low-density parity check ensemble.
  • the second contribution is to propose two novel decoding algorithms for PCs and SCCs which improve upon iBDD-CR.
  • the new algorithms use an extra decoding attempt based on error and erasure decoding of the component codes.
  • the proposed algorithms can be efficiently implemented because only the exchange of hard messages between the component decoders is required, making them an attractive solution for high throughput fiber-optic systems.
  • algorithm may refer to a method, and should not be construed to be limited to a strict computer-science interpretation.
  • an algorithm may refer to a practical method, executed on real data stemming from a physical origin, and e.g. executed in a physical device.
  • next-generation optical line cards target data rate of 1 Tb/s/l and beyond.
  • Reliable transmission at such high data rates cannot be achieved using off-the-shelf digital signal processing (DSP) nor by exclusively relying on the improvement of integrated circuits (due to the end of Moore’s law [3]).
  • FEC Forward error correction
  • Designing high-performance FEC decoders for ultra high-speeds is very challenging due to the strict latency and power constraints.
  • PCs Product codes
  • SCCs staircase codes
  • SDD Soft-decision decoding
  • TPD turbo product decoding
  • HDD hard decision decoding
  • hybrid decoding architectures have been proposed for both PCs and SCCs, which provide a suitable performance-complexity trade-off between SDD and HDD [11]-[16]
  • the idea of hybrid schemes is to employ HDD as the decoding core, while exploiting the channel log-likelihood ratios (LLRs) to improve the overall decoder performance.2
  • LLRs channel log-likelihood ratios
  • the soft-aided bit-marking (SABM) decoder was proposed for PCs and SCCs based on flipping the least reliable bits and a heuristic miscorrection detection procedure.
  • the performance of SABM was further improved for PCs based by combining SABM with SR principle [15]
  • iBDD-CR iterative bounded distance decoding with combined reliability
  • iBDD-CR we extend to SCCs.
  • preferred embodiments perform density evolution (DE) analysis for iBDD-CR employing the spatially-coupled GLDPC (SCGLDPC) ensemble, as the code ensemble containing the SCCs.
  • the derived DE may provide an accurate estimate of the reliability of HDD outputs for SCCs, which is exploited in iBDD-CR.
  • decoding algorithms for PCs and SCCs are proposed based on improving the iBDD- CR architecture with error and erasure decoding (EDD) of the component codes.
  • EDD error and erasure decoding
  • Product-like codes is a family of codes constructed by serial concatenation of component codes.
  • binary PCs and SCCs we briefly review the structure of PCs and SCCs and also explain the channel model considered in the present disclosure. The last part of this section describes the recently introduced iBDD-CR algorithm.
  • C be a Bose-Chaudhuri-Hocquenghem (BCH) code constructed over the Galois field GF(2 V ).
  • a PC with (n; k) component codes is defined as the set of all arrays such that each row and column of C is a valid codeword of C.
  • Fig. 1(a) shows the schematic of a PC code array encompassing , as a code bit corresponding to the second row and second column component codes of a PC.
  • PCs are conventionally decoded based on BDD of component codes.
  • BDD corrects all error patterns with maximum Hamming weight t. If the weight of the error pattern is larger than t and there exists another codeword with Hamming distance less than t to the received codeword, BDD introduces miscorrections. Otherwise, BDD fails, where conventionally it is considered that BDD outputs its input.
  • iBDD iterative applying the BDD on row and column codes
  • Fig. 1(b) shows an schematic of the SCC comprising the blocks , and as a code bit corresponding to the second row and second column of
  • Bo is an all-zeros matrix which initializes the decoding procedure of the SCCs.
  • SCCs are decoded in a windowed-decoding fashion, i.e. , each row of for staircase blocks within a decoding window is decoded based on BDD [5]
  • BDD BDD
  • BICM bit-interleaved coded modulation
  • M 2 -QAM
  • BRGC binary reflected Gray code
  • the AWGN channel output at time instant i corresponding to transmitted symbol x, X is given by where n C h is the number of channel uses corresponding to a PC or SCC block,
  • the log likelihood ratio (LLR) of the k-th bit level of is given as where are sets of size 2 m symbols with 0 and 1 as the kth bit of the corresponding BRGC label, respectively.
  • LLR log likelihood ratio
  • BEE binary message passing based on error and erasure decoding
  • the LLR on the code bit ci;j after BDD at iteration ‘ is given as [16, Eq. (9)] where is the channel LLR and can be computed using a look-up table
  • GD generalized distance
  • FIG. 2 shows the block diagram of the proposed BEE algorithm for PCs. Without loss of generality, we explain the BEEPC decision corresponding to the ith row decoding of PC at iteration ‘. BEE-PC encompasses two decoding attempts, each corresponding to a branch, or also decoding step, in Fig. 2. First, we explain the upper branch of Fig.
  • Comparing the candidate codeword with the minimum score is chosen as the BEE-PC decision and the corresponding BDD outcome is used for updating the input for column decoding in the next iteration, i.e. ,
  • the channel LLRs are employed as the input LLRs of both BDD and EED blocks, i.e., .
  • the BEE-PC decoding output yields from the branch with lowest score, i.e., the decoding output is
  • Fig. 5 we show the bit error rate (BER) performance of BEE-PC for a PC with component code Ci and transmission over the bi-AWGN channel.
  • BER bit error rate
  • BEE-PC outperforms all other algorithms where the performance gain of BEE-PC over conventional iBDD is 0.68 dB. Furthermore, the gap between BEE-PC and TPD is 0.43 dB. Therefore, BEE-PC can close 0.62% of the gap between (full hard) iBDD and (full soft) TPD. We highlight that the performance of iGMDD-SR, SABM-SR, and BMP-GMDD is close to BEE-PC.
  • BMP-GMDD requires up to 30% more message exchanging between component codes than BEE-PC
  • iGMDD-SR and SABM-SR require exchanging soft messages between component decoders, which yields significantly higher decoder data flow than BEE-PC (see Sec. V-B and Table III for high level complexity discussion of different algorithms).
  • Fig. 6(a)-(d) the performance of iBDD, ideal iBDD, iBDD-SR, iBDD-CR, and BEE- PC for a PC with component code C2 are shown for transmission in a BICM (employing random interleaver) with 4-QAM, 16-QAM, 64-QAM, and 256-QAM, respectively.
  • BICM deployment random interleaver
  • BEE-PC outperforms all other decoders and the gain with respect to iBDD increases using higher order modulation.
  • the performance gain of BEE-PC over iBDD is 0.46 dB, 0.7 dB, 0.79 dB, and 0.88 dB for 4-QAM, 16-QAM, 64- QAM, and 256-QAM, respectively.
  • Fig. 6(e) shows the spectral efficiency (SE) versus the optical reach improvement of BEE-PC over iBDD as well as the original optical reach of iBDD, for transmission on a BICM employing PC with the same component code considered in Fig. 6(a)-(d).
  • SE spectral efficiency
  • reach efficiency h defined as the reach improvement of BEE-PC over iBDD normalized to the original reach of iBDD.
  • reach efficiency h defined as the reach improvement of BEE-PC over iBDD normalized to the original reach of iBDD.
  • increasing the spectral efficiency results in a smaller reach enhancement and larger h.
  • the reach increase for 4-QAM, 16-QAM, 64- QAM, and 256-QAM are 1600 km, 640 km, 240 km, and 80 km, respectively.
  • Fig. 4 a schematic of the iBDD-CR decision for the code bit corresponding to the decoding iteration I is shown.
  • the core of iBDD-CR is to compute .
  • the components of this LUT are optimized for an GLDPC ensemble using DE analysis and used for implementing the iBDD-CR for PCs, as a code contained in the GLDPC ensemble.
  • this DE analysis we extend this DE analysis to SC-GLDPC ensemble, which allows to find the LUT for SCCs and implement the iBDD-CR.
  • Fig. 7 shows the Tanner graph of a SC-GLDPC ensemble with n 2 /4 degree-2 variable nodes (VNs) and n/2 constraint nodes (CNs) of degree-n.
  • the coupling memory of this SCGLDPC ensemble is 2. Therefore, the VNs at spatial position i are randomly connected to CNs at spatial position i and i + 1. This randomness is denoted in Fig. 7 by the edge interleavers t .
  • CNs at spatial position i are randomly (denoted in Fig. 7 by the edge interleavers t ') connected to VNs at spatial position i - 1 and i. Comparing Fig. 1 (b) with Fig.
  • SCCs can be constructed as a particular instance of SC-GLDPC ensemble, where n/2 BCH component code corresponds to CNs and n 2 /4 code bits of B, corresponds to VNs in spatial position i.
  • SCCs are deterministic codes (see [27]), i.e. , the connections of VNs and CNs are determined by the SCC structure, which is not random.
  • the reason for analyzing the SC-GLDPC ensemble instead of the Tanner graph of SCCs is that the randomization in the SC-GLDPC ensemble significantly simplifies the DE analysis. Under other assumptions such as extrinsic message passing [28, Sec. 11— B], BICM channel mixing [29, Sec. IV-A], and employing channel adapters in BICM [30], in what follows we generalize the DE analysis of iBDD-CR originally derived for GLDPC ensemble in [16, Sec. IV], to SC-GLDPC ensemble.
  • BCH codes as the CNs.
  • iBDD-CR for the GLDPC ensemble [16, Sec. IV]
  • M and noise variance o 2 the output message error probability of the iBDD-CR at CNs and iteration I is given by where g( ) is defined by [16, Eq. (15)] and denotes the input message error probability of CNs.
  • pch defined as the channel output error probability yielded by employing hard detection on channel LLRs.
  • the difference between the Tanner graph of GLDPC codes and SC-GLDPC ensembles is the existence of coupling memory in the Tanner graph of the SC-GLPDC ensemble.
  • BEE-SCC is inspired by iBDD-CR and utilizes the GD metric (5).
  • Fig. 8 shows the schematic of BEE-SCC in making a decision for the jth row of . Similar to Sec. IV, we denote by the hard decision input of BEE-SCC corresponding to .
  • the lower branch of Fig. 8 serves as a second decoding attempt.
  • the 2 least reliable bits of according to reliability vector are erased and passed to the algebraic EED [25, Sec. 6.6], although a greater number of least reliable bits may also be erased - in that case, it is preferred to erase an even number of bits, as erasing an odd number of bits does not contribute extra to the EED decoding.
  • EED algebraic EED
  • iBDD-CR and BEE-SCC are compared with iBDD, ideal iBDD, AD, and iBDD-SR for SCCs with C 2 and C3 component codes, and transmission over the bi-AWGN channel.
  • BEE-SCC and iBDD-CR outperform all other algorithms.
  • the gain of iBDD-CR and BEE-SCC over iBDD is 0.41 dB and 0.55 dB for SCC with C 2
  • the same gains are 0.33 dB and 0.44 dB for SCC with C 3 .
  • BEE-PC and BEE-SCC Two algorithms employ an erasure attempt to improve the performance of iBDD-CR.
  • the EED is successful if , where d m m is the minimum Hamming distance of the component code [25, Sec. 6]
  • the second attempt can correct more errors if the least reliable bits corresponds to error bits.
  • BEE-PC The main difference between BEE-PC and BEE-SCC is that each algorithm exploits different soft information values for the erasure attempt. In order to efficiently perform the erasure attempt one needs a reliability measure. In BEEPC, is used to find the two least reliable bits of (see Fig. 2). If we use the architecture of iBDDCR to implement BEE-PC, we have to exchange soft values between component decoders, yielding a significantly higher internal decoder data flow compared to iBDD-CR. To avoid exchanging of the soft values between component codes, BEE-PC modified the iBDD-CR architecture such that the
  • BDD/EED decisions i.e., are exchanged (c.f. Fig. 3 and the first branch of Fig. 2).
  • both (hard) decisions and LLRs used in BEE-PC can be computed internally in the decoder using , channel LLRs, and iBDD-CR LUT.
  • BEE-PC outputs with ternary components , and send it to the column decoder. Therefore, it may seem that the contribution of message exchanging of BEE-PC in decoder data flow is higher than that of iBDD-CR and iBDD, which both exchange only binary messages. However, in what follows, we will show that we can implement BEEPC more efficiently than a plain ternary message passing between component codes.
  • BDD/EDD decoding 1 ⁇ using the mapping according to . Furthermore, we assume that the extra bit is 0, corresponds to BDD/EDD failure. In this case the other n are 0. With this simple bit extension and mapping, become binary, at the cost of sending only one extra bit per component code. As the component code of a PC is typically long to reduce the error floor, the contribution of exchanging this extra bit on decoder data flow is negligible. For instance, BEE-PC decoding of a PC with BCH component length of 255 and 511, requires only an extra message exchanging of 0.4% and 0.2%, respectively, compared to iBDD-CR and conventional iBDD. As shown in Sec.
  • BEE-SCC only exchanges (binary) hard decisions between component decoders (see (18) and Fig. 8), hence, the contribution of message exchanging of BEE-PC in decoder data flow is the same as iBDD-CR and conventional iBDD.
  • Two other implementation aspects we consider here are decoding complexity of EDD and LLR calculations.
  • BDD is usually implemented based on Berlekamp-Massey decoding of BCH codes [32].
  • EED can also be implemented by modifying the Berlekamp-Massey algorithm, hence, the complexities of EED decoding and BDD are roughly similar [33]
  • BEE-PC and BEE-SCC require to compute channel LLRs for the code bits, store channel LLRs, and a sorting algorithm to find the two least reliable bits per component code.
  • the memory required for BEE-PC and BEE- SCC is static, as the LLRs are not updated during the decoding iterations. It is known that static memory is significantly less costly than dynamic memory in hardware implementation [10].
  • Ciena “Waveserver 5,” https://media.ciena.com/documents/ Waveserver _- 5_DS.pdf.

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Abstract

La présente invention concerne un procédé de décodage hybride de données reçues codées à l'aide d'un code de correction d'erreur, le procédé comprenant des étapes de mappage (101) des données reçues avec une décision dure à l'aide d'une table de mappage prédéfinie, le décodage (102) des données reçues à l'aide d'un décodage de distance limitée, BDD, la détermination (102) d'une première mesure de distance entre les données décodées BDD et la décision dure, le calcul (105) d'une mesure de fiabilité de bits de la décision dure, la détermination (107) d'au moins deux bits les moins fiables des données reçues de décision dure, sur la base de la fiabilité calculée, le décodage (108) des données reçues, à l'aide d'un décodage d'erreur et d'effacement, EED, dans lequel les au moins deux bits les moins fiables déterminés sont considérés comme étant effacés, la détermination (109) d'une seconde mesure de distance entre les données décodées EED et la décision dure, la comparaison (110) de la première mesure de distance et de la seconde mesure de distance, et sur la base d'un résultat de la comparaison, la sortie (111) de l'une des données décodées BDD et des données décodées EED. Ce procédé de décodage hybride peut être appliqué au décodage de codes de produits ou de codes d'escalier.
PCT/NL2021/050423 2020-07-02 2021-07-02 Décodage hybride de codes de produit et d'escalier à l'aide d'un décodage de distance limitée et d'un décodage d'erreur et d'effacement Ceased WO2022005292A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1028533A1 (fr) * 1999-02-09 2000-08-16 Tandberg Television ASA Décodage d'un signal d'entrée numérique
WO2003103152A2 (fr) * 2002-05-31 2003-12-11 Koninklijke Philips Electronics N.V. Decodage pondere de codes de bloc lineaire

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1028533A1 (fr) * 1999-02-09 2000-08-16 Tandberg Television ASA Décodage d'un signal d'entrée numérique
WO2003103152A2 (fr) * 2002-05-31 2003-12-11 Koninklijke Philips Electronics N.V. Decodage pondere de codes de bloc lineaire

Non-Patent Citations (9)

* Cited by examiner, † Cited by third party
Title
A. SHEIKHA. GRAELL I AMATG. LIVAC. HAGERH. D. PFISTER: "On low-complexity decoding of product codes for high-throughput fiberoptic systems", PROC. IEEE INT. SYMP. ON TURBO CODES & ITERATIVE
C. FOUGSTEDTP. LARSSON-EDEFORS: "Energy-efficient high-throughput VLSI architectures for product-like codes", J. LIGHTW. TECHNOL., vol. 37, no. 2, January 2019 (2019-01-01), pages 477 - 485, XP011710939, DOI: 10.1109/JLT.2019.2893039
J. HOUP. H. SIEGELL. B. MILSTEINH. D. PFISTER: "Capacityapproaching bandwidth-efficient coded modulation schemes based on low-density parity-check codes", IEEE TRANS. INF. THEORY, vol. 49, no. 9, September 2003 (2003-09-01), pages 2141 - 2155
Q. XIEZ. WANGZ. YANG, SIMPLIFIED SOFT DEMAPPER FOR APSK WITH PRODUCT CONSTELLATION LABELING, vol. 11, no. 7, 2012, pages 2649 - 2657
R. M. PYNDIAH: "Near-optimum decoding of product codes: block turbo codes", IEEE TRANS. COMMUN., vol. 46, no. 8, pages 1003 - 1010, XP000782280, DOI: 10.1109/26.705396
ROBERT MORELOS-ZARAGOZA: "The Art of Error Correcting Coding. Chapters 5 and 7.", 1 January 2006 (2006-01-01), XP055123297, Retrieved from the Internet <URL:NA> [retrieved on 20140613] *
SHEIKH ALIREZA ET AL: "Binary Message Passing Decoding of Product-Like Codes", IEEE TRANSACTIONS ON COMMUNICATIONS, IEEE SERVICE CENTER, PISCATAWAY, NJ. USA, vol. 67, no. 12, 1 December 2019 (2019-12-01), pages 8167 - 8178, XP011762240, ISSN: 0090-6778, [retrieved on 20191216], DOI: 10.1109/TCOMM.2019.2940180 *
SHEIKH ALIREZA ET AL: "Novel High-Throughput Decoding Algorithms for Product and Staircase Codes Based on Error-and-Erasure Decoding", JOURNAL OF LIGHTWAVE TECHNOLOGY, IEEE, USA, vol. 39, no. 15, 7 May 2021 (2021-05-07), pages 4909 - 4922, XP011866496, ISSN: 0733-8724, [retrieved on 20210715], DOI: 10.1109/JLT.2021.3078172 *
SHEIKH ALIREZA ET AL: "On Low-Complexity Decoding of Product Codes for High-Throughput Fiber-Optic Systems", PROC. 2018 IEEE 10TH INTERNATIONAL SYMPOSIUM ON TURBO CODES & ITERATIVE INFORMATION PROCESSING (ISTC), IEEE, 3 December 2018 (2018-12-03), pages 1 - 5, XP033506478, DOI: 10.1109/ISTC.2018.8625279 *

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