WO2022032995A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2022032995A1
WO2022032995A1 PCT/CN2021/074295 CN2021074295W WO2022032995A1 WO 2022032995 A1 WO2022032995 A1 WO 2022032995A1 CN 2021074295 W CN2021074295 W CN 2021074295W WO 2022032995 A1 WO2022032995 A1 WO 2022032995A1
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Prior art keywords
layer
conductive layer
semiconductor substrate
bit line
conductive
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PCT/CN2021/074295
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English (en)
French (fr)
Inventor
卢经文
朱柄宇
白世杰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to JP2022538408A priority Critical patent/JP7513720B2/ja
Priority to KR1020227020833A priority patent/KR102711683B1/ko
Priority to EP21855052.3A priority patent/EP4024456A4/en
Priority to US17/370,503 priority patent/US12108594B2/en
Publication of WO2022032995A1 publication Critical patent/WO2022032995A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a preparation method thereof.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers, and its memory array area is composed of many repeated memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the bit line structure, one of the drain or source is connected to the bit line structure, and one of the drain or source is connected to the capacitor. On the bit line structure The voltage signal can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line structure, or write the data information into the capacitor through the bit line structure for storage.
  • DRAM Dynamic Random Access Memory
  • the contact resistance of each wire connection position in the DRAM becomes more and more important.
  • the contact resistance of the conductive connection position of the capacitor in the array area and the transistor of the DRAM and the contact resistance of the wire connection position of the MOS transistor source-drain area in the peripheral circuit area are particularly important.
  • a transition layer is deposited before the metal wire is deposited, so as to reduce the contact resistance and increase the connection performance between the layers.
  • the thicknesses of the transition layers of the array area and the peripheral circuit area are the same.
  • the thicker the transition layer the greater the on-current, and the better the performance of the wire.
  • the thicker the transition layer will cause excessive on-current, which may cause Breakdown effect, resulting in increased leakage.
  • the technical problem to be solved by the present invention is to provide a semiconductor structure and a preparation method thereof, which can form transition layers of different thicknesses in the array area and the peripheral circuit area, so as to improve the conductivity of the wires in the array area, and avoid peripheral circuits The area leaks due to the thick transition layer.
  • the present invention provides a method for preparing a semiconductor structure, which includes the following steps: providing a semiconductor substrate, the semiconductor substrate includes an array area and a peripheral circuit area, and in the array area, the semiconductor substrate There are a plurality of capacitor contact holes on the bottom, a first conductive layer is deposited on the bottom of the capacitor contact holes, and a device layer is arranged on the semiconductor substrate in the peripheral circuit area; the first conductive layer is processed to increasing the roughness of the first conductive layer; forming wire contact holes in the peripheral circuit region, the wire contact holes exposing the semiconductor substrate; forming a transition layer covering at least the first conductive layer layer surface and the surface of the semiconductor substrate exposed by the wire contact hole; forming a second conductive layer, the second conductive layer covering the transition layer, and filling the capacitor contact hole and the wire contact hole.
  • bit line structures are formed on the semiconductor substrate, the capacitor contact holes are arranged between the bit line structures, and before the step of processing the first conductive layer, the The bit line structure in the array area and the device layer in the peripheral circuit area are thinned.
  • the bit line structure includes a bit line contact island and a bit line, the bit line contact island is in contact with the semiconductor substrate, the bit line is arranged on the bit line contact island, and the bit line includes a conductive layer and the dielectric layer disposed on the conductive layer, the dielectric layer is thinned in the thinning process step.
  • the step of processing the first conductive layer further includes: performing ion implantation on the first conductive layer to destroy the surface flatness of the first conductive layer and increase the roughness of the first conductive layer.
  • the first conductive layer is a polysilicon layer
  • the step of implanting ions into the first conductive layer is to implant germanium ions, carbon ions or arsenic ions into the first conductive layer.
  • a deposition layer is also formed on the surface of the device layer in the peripheral circuit region.
  • the step of processing the first conductive layer further includes the following steps: forming an isolation layer, the isolation layer covering the surface of the array area and the peripheral circuit area; forming wires in the peripheral circuit area After the step of contacting the holes, the isolation layer is removed.
  • the step of forming the transition layer further includes: depositing a cobalt layer, and at the bottom of the capacitor contact hole and the bottom of the wire contact hole, cobalt reacts with the first conductive layer and the semiconductor substrate respectively to form the transition layer; rapid heat treatment.
  • the thickness of the transition layer located in the array region is greater than the thickness of the transition layer located in the peripheral circuit region.
  • the second conductive layer includes an adhesion layer and a metal conductive layer
  • the step of forming the second conductive layer further includes the following steps: forming an adhesion layer on the surface of the transition layer;
  • a metal conductive layer is formed on the surface of the adhesive layer, and the metal conductive layer fills the capacitor contact hole and the wire contact hole.
  • the present invention also provides a semiconductor structure, which includes: a semiconductor substrate, including an array area and a peripheral circuit area, in the array area, the semiconductor substrate has a plurality of capacitor contact holes, the capacitor contact holes are exposed
  • the semiconductor substrate, in the peripheral circuit region has a plurality of wire contact holes on the semiconductor substrate, and the wire contact holes expose the semiconductor substrate;
  • a plurality of capacitor conductive structures are arranged on the capacitor In the contact hole, the capacitive conductive structure includes a first conductive layer filling part of the capacitive contact hole, a transition layer covering at least the first conductive layer, and a second conductive layer covering the transition layer and filling the capacitive contact hole a conductive layer, the first conductive layer is in contact with the semiconductor substrate;
  • a plurality of wire structures are arranged in the conductive contact holes, the wire structures include a transition layer covering the surface of the semiconductor substrate, covering the a transition layer and fills the second conductive layer of the wire contact hole, the transition layer is in contact with the semiconductor substrate; where
  • a structure layer is provided on the semiconductor substrate, and the wire contact hole penetrates the structure layer.
  • the capacitive conductive structure further includes an ion implantation layer, and the ion implantation layer is located in the first conductive layer.
  • the structure layer further includes a device layer and is located on the device layer.
  • the deposition layer is the same material layer as the ion implantation layer.
  • bit line structures there are a plurality of discretely arranged bit line structures on the semiconductor substrate, and the capacitor contact holes are arranged between the bit line structures.
  • bit line structure includes a bit line contact island and a bit line, the bit line contact island is in contact with the semiconductor substrate, the bit line is arranged on the bit line contact island, and the bit line includes a conductive layer and a dielectric layer disposed on the conductive layer.
  • the second conductive layer includes an adhesive layer and a metal conductive layer, the adhesive layer at least covers the surface of the transition layer, the metal conductive layer covers the adhesive layer, and fills the capacitor contact hole and the Wire contact holes.
  • the advantage of the present invention is that in the array area, the surface of the first conductive layer is roughened, so that in the same step, the thicknesses of the transition layers formed in the array area and the peripheral circuit area are different, which satisfies the requirements of the array area and the peripheral circuit area.
  • the requirements for the thickness of the transition layer in the area can improve the conductivity of the wires in the array area, and can avoid the leakage of electricity in the peripheral circuit area due to the excessive thickness of the transition layer, which greatly improves the performance of the semiconductor structure, and the preparation process is simple, and no additional cumbersome is added. process steps.
  • FIG. 1 is a schematic diagram of steps of an embodiment of a method for fabricating a semiconductor structure of the present invention
  • FIGS. 2 to 9 are process flow diagrams of an embodiment of a method for fabricating a semiconductor structure of the present invention.
  • FIG. 1 is a schematic diagram of steps of an embodiment of a method for fabricating a semiconductor structure of the present invention.
  • the method for preparing the semiconductor structure includes the following steps: Step S10 , providing a semiconductor substrate, the semiconductor substrate includes an array area and a peripheral circuit area, and in the array area, the semiconductor substrate has A plurality of capacitor contact holes, a first conductive layer is deposited at the bottom of the capacitor contact holes, and a device layer is provided on the semiconductor substrate in the peripheral circuit region; step S11, the first conductive layer is processed to increasing the roughness of the first conductive layer; step S12, forming a wire contact hole in the peripheral circuit region, the wire contact hole exposing the semiconductor substrate; step S13, forming a transition layer, the transition layer at least Cover the surface of the first conductive layer and the surface of the semiconductor substrate exposed by the wire contact holes; step S14, form a second conductive layer, the second conductive layer covers the transition layer, and fills the capacitive contact hole and the wire contact hole.
  • FIGS. 2 to 9 are process flow diagrams of an embodiment of a method for fabricating a semiconductor structure of the present invention.
  • a semiconductor substrate 200 is provided.
  • the semiconductor substrate 200 includes an array area A and a peripheral circuit area B.
  • the semiconductor substrate 200 has a plurality of capacitor contact holes. 210 , a first conductive layer 220 is deposited on the bottom of the capacitor contact hole 210 , and a device layer 230 is formed on the semiconductor substrate 200 in the peripheral circuit region B.
  • the semiconductor substrate 200 includes, but is not limited to, a silicon substrate or a germanium substrate.
  • a shallow trench isolation structure 201 and an active region 202 separated by the shallow trench isolation structure 201 are disposed in the semiconductor substrate 200 .
  • the capacitor contact hole 210 exposes a part of the active region 202 .
  • the first conductive layer 220 is deposited on the bottom of the capacitor contact hole 210 and can be electrically connected to the active region 202 .
  • the first conductive layer 220 is a polysilicon layer.
  • bit line structure 203 extends in a predetermined direction, for example, in this embodiment, the bit line structure 203 extends in a direction perpendicular to the paper surface.
  • the bit line structure 203 includes a bit line contact island 203A and a bit line disposed on the bit line contact island 203A.
  • the bit line contact islands 203A are distributed on the semiconductor substrate 200 at intervals. For example, in the present embodiment, in the extending direction of the bit line 203, the bit line contact islands 203A are arranged in sequence.
  • the bit line contact island 203A is in contact with the active region 202 in the semiconductor substrate 200 , thereby electrically connecting the bit line with the active region 202 .
  • bit line contact island 203A there is a region of the bit line contact island 203A, and the bit line is electrically connected to the active region 202 through the bit line contact island 203A, and the bit line contact island 203A does not exist in the region.
  • the bit line contact islands 203A may be formed of materials such as polysilicon.
  • the bit line can be composed of multiple conductive layers 2031.
  • the bit line is composed of conductive layers such as a polysilicon layer, a TiN layer, and a metal tungsten layer.
  • a dielectric layer 2032 is disposed on the conductive layer 2031 to protect the conductive layer, and the dielectric layer 2032 includes but is not limited to a silicon nitride layer.
  • bit line structure 203 further includes a protective layer 2033 disposed on the sidewalls of the conductive layer 2031 and the dielectric layer 2032 , and the protective layer 2033 may be a silicon nitride layer.
  • the semiconductor substrate 200 includes a shallow trench isolation structure 201 , an active region 202 separated by the shallow trench isolation structure 201 , and the semiconductor substrate 200 .
  • Device layer 230 includes a conductive structure layer 231 and an insulating layer 232 disposed on the surface of the semiconductor substrate.
  • a conductive structure is disposed in the conductive structure layer 231 , and the conductive structure corresponds to the active region 202 .
  • the conductive structure can act as a gate of a transistor.
  • the insulating layer 232 covers the conductive structure layer 231 to protect the conductive structure layer 231 .
  • a thinning step is also included. Specifically, referring to FIG. 3 , the bit line structure 203 of the array region A and the device layer 230 of the peripheral circuit region B are thinned. In this step, in the array area A, the dielectric layer 2032 and the protective layer 2033 on the sidewall thereof are thinned, and the conductive layer 2031 of the bit line is not exposed; in the peripheral circuit area B, the device layer The insulating layer 232 of the device layer 230 is thinned, and the conductive structures in the conductive structure layer 231 of the device layer 230 are not exposed. Further, the dielectric layer 2032 , the protective layer 2033 and the insulating layer 232 may be thinned by means of etching or the like.
  • the first conductive layer 220 is processed to increase the roughness of the first conductive layer 220 .
  • the roughness of the surface of the first conductive layer 220 increases, and the surface area of the surface increases, which is beneficial to the subsequent process of forming the transition layer 250 (shown in FIG. 8 ), the transition layer and the first conductive layer
  • the contact area of the conductive layer 220 is increased, so that the thickness of the transition layer can be increased.
  • ion implantation is performed on the first conductive layer 220 to destroy the surface flatness of the first conductive layer 220 and increase the roughness of the first conductive layer 220 , which is shown by hatching in FIG. 4 .
  • the affected area 220A on the surface of the first conductive layer 220 ions will bombard the surface of the first conductive layer 220, break the chemical bonds of the first conductive layer 220, destroy the flatness of the surface of the first conductive layer 220, and make the first conductive layer 220 conductive.
  • the surface roughness of layer 220 is increased.
  • the ion implantation will break the Si-Si chemical bond of the polysilicon, destroy the flatness of the polysilicon surface, increase the surface roughness of the polysilicon, and further increase the reaction area between the subsequent transition layer and the polysilicon. Increase the thickness of the transition layer.
  • ions with larger atomic radius such as germanium ions, carbon ions or arsenic ions, can be used for ion implantation to further break the chemical bonds of the first conductive layer 220 and further increase the roughness of the first conductive layer 220 .
  • an ion implantation layer 400 is formed in the first conductive layer 220 .
  • the peripheral circuit region B due to the blocking effect of the device layer 230, specifically, due to the blocking effect of the insulating layer 232, ions are not implanted into the device layer 230, but are deposited on the surface of the device layer 230 to form a deposition layer 410.
  • the depth of the ion implantation can be determined according to the actual situation, and the position of the ion implantation layer 400 formed after the ion implantation may not affect the subsequent formation of the transition layer 250 .
  • an isolation layer 500 is formed, and the isolation layer 500 covers the surfaces of the array region A and the peripheral circuit region B.
  • the isolation layer 500 is a silicon nitride layer, and in the array region A, it covers the surface of the bit line structure 203 and the surface of the first conductive layer 220, and in the peripheral circuit region B, so The isolation layer 500 covers the surface of the deposition layer 410 .
  • a wire contact hole 240 is formed, and the wire contact hole 240 exposes the semiconductor substrate 200 .
  • the wire contact holes 240 are formed by photolithography and etching processes.
  • the wire contact hole 240 penetrates through the deposition layer 410 and the device layer 230 and exposes the active region 202 of the semiconductor substrate 200 .
  • the wire contact holes 240 are disposed on both sides of the conductive structure of the conductive structure layer 231 .
  • step S12 after the wire contact holes are formed, the following step is further included: referring to FIG. 7 , the isolation layer 500 is removed to expose the first conductive layer 220 .
  • the isolation layer 500 may be removed by an etching method.
  • a transition layer 250 is formed, and the transition layer 250 at least covers the surface of the first conductive layer 220 and the surface of the semiconductor substrate 200 exposed by the wire contact holes 240 .
  • the method of forming the transition layer 250 is to deposit cobalt in the array region A and the peripheral circuit region B, and at the bottom of the capacitor contact hole 210 and the bottom of the wire contact hole 240 , cobalt and the The semiconductor substrate 200 reacts with the first conductive layer 220 to form a transition layer 250.
  • cobalt is deposited to form a cobalt layer.
  • the cobalt layer on the side wall of the capacitor contact hole 210 and the side wall of the wire contact hole 240 is cleaned and removed by means of pickling and the like, and the transition layer 250 is retained.
  • the semiconductor substrate is a silicon substrate and the first conductive layer 220 is a polysilicon layer
  • cobalt reacts with silicon at the bottom of the capacitor contact hole 210 and the bottom of the wire contact hole 240 to form A cobalt silicide (CoSix) layer
  • the cobalt silicide layer is the transition layer
  • cobalt is deposited to form a cobalt layer.
  • the cobalt layer is removed by cleaning.
  • FIG. 8 in order to clearly show the structure of the transition layer 250 , the size of the transition layer 250 is appropriately exaggerated.
  • a rapid thermal process is performed in an inert gas environment, for example, in a temperature environment with a manufacturing process temperature ranging from 700°C to 850°C.
  • RTP rapid thermal process
  • step S13 the first conductive layer 220 has been roughened, and the semiconductor substrate 200 exposed by the wire contact holes 240 has not been roughened, and its surface is a flat surface.
  • the roughness is greater than the roughness of the semiconductor substrate 200 exposed by the wire contact holes 240, so that when cobalt is deposited, the contact area of the cobalt with the first conductive layer 220 is larger than the contact area of the cobalt with the semiconductor substrate 200 exposed by the wire contact holes 240,
  • the thickness of the transition layer 250 formed in the capacitor contact hole 210 is much larger than that of the transition layer 250 formed in the wire contact hole 240 .
  • the thickness of the transition layer 250 is thick enough, the on-current is large, and the wire performance is good, while for the peripheral circuit area B, the transition layer 250 is not too thick, and thus will not cause excessive conduction current, avoid breakdown effect, and avoid increasing leakage.
  • a second conductive layer 260 is formed.
  • the second conductive layer 260 covers the transition layer 250 and fills the capacitor contact hole 210 and the wire contact hole 240 .
  • the second conductive layer 260 includes an adhesive layer 261 and a metal conductive layer 262 .
  • the step of forming the second conductive layer 260 further includes the following steps: forming an adhesive layer 261 on the surface of the transition layer 250, the sidewall of the capacitor contact hole 210 and the sidewall of the wire contact hole 240, the adhesive layer 261 including but not limited to a TiN layer;
  • a metal conductive layer 262 is formed on the surface of the adhesive layer 261 , and the metal conductive layer 262 fills the capacitor contact hole 210 and the wire contact hole 240 .
  • the metal conductive layer 262 may be a metal tungsten layer.
  • the first conductive layer 220 , the transition layer 250 and the second conductive layer 260 form a capacitive conductive structure, and the transition layer 250 can reduce the amount of the first conductive layer 220 and the second conductive layer.
  • Contact resistance between layers 260 is not limited to
  • the transition layer 250 and the second conductive layer 260 form a wire structure, and the transition layer 250 connects the semiconductor substrate 200 and the second conductive layer 260 respectively, which can reduce the The contact resistance between the semiconductor substrate 200 and the second conductive layer 260 increases the connection performance between layers.
  • the wire structure is in contact with the source and drain regions of the transistor in the semiconductor substrate 200 to lead out the source and drain regions, and the conductive structure in the conductive structure layer 231 of the device layer 230 serves as the gate of the transistor pole, used to control the conduction of the transistor.
  • the transistors are mainly used as control circuits.
  • the preparation method of the semiconductor structure of the present invention can form a thicker transition layer in the array area A and a thin transition layer in the peripheral circuit area B in the same step, which satisfies the requirements of the array area A and the peripheral circuit area B.
  • the requirement for the thickness of the transition layer greatly improves the performance of the semiconductor structure.
  • the present invention also provides a semiconductor structure prepared by the above-mentioned preparation method.
  • the semiconductor structure includes a semiconductor substrate 200 , a plurality of capacitive conductive structures and a plurality of wire structures.
  • the semiconductor substrate 200 includes an array area A and a peripheral circuit area B.
  • the semiconductor substrate 200 has a plurality of capacitor contact holes 210 , and the capacitor contact holes 210 expose the semiconductor substrate 200
  • the semiconductor substrate 200 in the peripheral circuit area B, has a plurality of wire contact holes 240 , and the wire contact holes 240 expose the semiconductor substrate 200 .
  • a plurality of capacitive conductive structures are disposed in the capacitive contact holes 210 .
  • the capacitive conductive structure includes a first conductive layer 220 filling part of the capacitive contact hole 210 , a transition layer 250 covering at least the first conductive layer 220 , and a transition layer 250 covering the transition layer 250 and filling the capacitive contact hole 220 .
  • the second conductive layer 260 , the first conductive layer 220 is in contact with the semiconductor substrate 200 , and the transition layer 250 is formed on the first conductive layer 220 .
  • the transition layer 250 can reduce the contact resistance between the first conductive layer 220 and the second conductive layer 260 and improve the performance of the capacitive conductive structure.
  • bit line structure 203 includes a bit line contact island 203A and a bit line, the bit line contact island 203A is in contact with the semiconductor substrate 200 , and the bit line is disposed on the bit line contact island 203A. Further, the bit line includes a conductive layer 2031 and a dielectric layer 2032 disposed on the conductive layer 2031 .
  • the capacitive conductive structure further includes an ion implantation layer 400 , and the ion implantation layer 400 is located in the first conductive layer 220 .
  • a plurality of wire structures are disposed in the conductive contact holes 240 , and the wire structures include a transition layer 250 covering the surface of the semiconductor substrate 200 , a second conductive layer covering the transition layer 250 and filling the wire contact holes 240 .
  • layer 260 the transition layer 250 is in contact with the semiconductor substrate 200 .
  • the semiconductor substrate 200 has a structure layer, and the wire contact hole 240 penetrates the structure layer.
  • the structural layers include a device layer 230 and a deposition layer 410 on the device layer 230 .
  • the deposition layer 410 and the ion implantation layer 400 are of the same material layer, for example, both are a germanium material layer, a carbon material layer or an arsenic material layer.
  • the second conductive layer 260 includes an adhesive layer 261 and a metal conductive layer 262, the adhesive layer 261 covers at least the surface of the transition layer 250, the metal conductive layer 262 covers the adhesive layer 261, and fills the The capacitor contact hole 210 and the wire contact hole 240 are formed.
  • the thickness of the transition layer 250 of the capacitive conductive structure is greater than the thickness of the transition layer 250 of the wire structure, which satisfies the requirements for the thickness of the transition layer in the array area A and the peripheral circuit area B, and greatly improves the performance of the semiconductor structure.

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Abstract

本发明提供一种半导体结构及其制备方法，制备方法包括如下步骤：提供半导体衬底，半导体衬底包括阵列区及外围电路区，在阵列区，半导体衬底上具有多个电容接触孔，电容接触孔底部沉积有第一导电层，在外围电路区，半导体衬底上具有器件层；对第一导电层进行处理，以增大第一导电层的粗糙度；在外围电路区形成导线接触孔，导线接触孔暴露半导体衬底；形成过渡层，过渡层至少覆盖第一导电层表面及导线接触孔暴露的半导体衬底表面；形成第二导电层，第二导电层覆盖过渡层，且填充电容接触孔及导线接触孔。本发明能够在阵列区及外围电路区形成不同厚度的过渡层，大大提高了半导体结构的性能。

Description

半导体结构及其制备方法
相关申请引用说明
本申请要求于2020年08月14日递交的中国专利申请号202010816754.X，申请名为“半导体结构及其制备方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体结构及其制备方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，其存储阵列区由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与位线结构相连、漏极或源极其中之一与位线结构相连、漏极或源极其中之一与电容器相连，位线结构上的电压信号能够控制晶体管的打开或关闭，进而通过位线结构读取存储在电容器中的数据信息，或者通过位线结构将数据信息写入到电容器中进行存储。
随着制程的微缩，动态随机存取存储器中各个导线连接位置的接触电阻显得越发重要。其中，阵列区的电容器与DRAM的晶体管的导电连接位置的接触电阻及外围电路区的MOS管源漏区导线连接位置的接触电阻尤为重要。目前，在制作导线结构时，在沉积金属导线之前先沉积一层过渡层，以减小接触电阻，增加层与层之间的连接性能。
由于阵列区及外围电路区的过渡层是在同一步骤中形成，则阵列区及外围电路区的过渡层的厚度相同。对于阵列区而言，过渡层越厚，其导通电流越大，导线性能越好，而对于外围电路区而言，过渡层太厚，则会引起过高的导通电流，就可能会引起击穿效应，导致漏电增大。
因此，如何在阵列区及外围电路区形成不同厚度的过渡层，成为目前亟需解决的问题。
发明内容
本发明所要解决的技术问题是，提供一种半导体结构及其制备方法，其能够在阵列区及外围电路区形成不同厚度的过渡层，从而能够提高阵列区导线的 导电性能，且能够避免外围电路区由于过渡层过厚而漏电。
为了解决上述问题，本发明提供了一种半导体结构的制备方法，其包括如下步骤：提供半导体衬底，所述半导体衬底包括阵列区及外围电路区，在所述阵列区，所述半导体衬底上具有多个电容接触孔，所述电容接触孔底部沉积有第一导电层，在所述外围电路区，所述半导体衬底上具有器件层；对所述第一导电层进行处理，以增大所述第一导电层的粗糙度；在所述外围电路区形成导线接触孔，所述导线接触孔暴露所述半导体衬底；形成过渡层，所述过渡层至少覆盖所述第一导电层表面及所述导线接触孔暴露的所述半导体衬底表面；形成第二导电层，所述第二导电层覆盖所述过渡层，且填充所述电容接触孔及所述导线接触孔。
进一步，在所述半导体衬底上形成多个分立设置的位线结构，所述电容接触孔设置在所述位线结构之间，对所述第一导电层进行处理的步骤之前，对所述阵列区的位线结构及所述外围电路区的器件层进行减薄处理。
进一步，所述位线结构包括位线接触岛及位线，所述位线接触岛与所述半导体衬底接触，所述位线设置在所述位线接触岛上，所述位线包括导电层及设置在所述导电层上的介质层，在减薄处理步骤中，所述介质层被减薄。
进一步，对所述第一导电层进行处理的步骤进一步包括：对所述第一导电层进行离子注入，以破坏第一导电层表面平整度，增大所述第一导电层的粗糙度。
进一步，所述第一导电层为多晶硅层，对所述第一导电层进行离子注入的步骤为，对所述第一导电层进行锗离子、碳离子或者砷离子注入。
进一步，对所述第一导电层进行离子注入的步骤中，在所述外围电路区的器件层表面也形成沉积层。
进一步，对所述第一导电层进行处理的步骤之后，进一步包括如下步骤：形成隔离层，所述隔离层覆盖所述阵列区及所述外围电路区的表面；在所述外围电路区形成导线接触孔的步骤之后，去除所述隔离层。
进一步，形成过渡层的步骤进一步包括：沉积钴层，在所述电容接触孔底部及所述导线接触孔底部，钴分别与所述第一导电层及所述半导体衬底反应，形成所述过渡层；进行快速热处理。
进一步，位于所述阵列区的过渡层的厚度大于位于所述外围电路区的过渡层的厚度。
进一步，所述第二导电层包括黏附层及金属导电层，形成第二导电层的步骤进一步包括如下步骤：在过渡层表面形成黏附层；
在所述黏附层表面形成金属导电层，且所述金属导电层填充所述电容接触孔及所述导线接触孔。
本发明还提供一种半导体结构，其包括：半导体衬底，包括阵列区及外围电路区，在所述阵列区，所述半导体衬底上具有多个电容接触孔，所述电容接触孔暴露出所述半导体衬底，在所述外围电路区，所述半导体衬底上具有多个导线接触孔，所述导线接触孔暴露出所述半导体衬底；多个电容导电结构，设置在所述电容接触孔内，所述电容导电结构包括填充部分所述电容接触孔的第一导电层、至少覆盖所述第一导电层的过渡层及覆盖所述过渡层且填充所述电容接触孔的第二导电层，所述第一导电层与所述半导体衬底接触；多个导线结构，设置在所述导电接触孔内，所述导线结构包括覆盖所述半导体衬底表面的过渡层、覆盖所述过渡层且填充所述导线接触孔的第二导电层，所述过渡层与所述半导体衬底接触；其中，所述电容导电结构的过渡层的厚度大于所述导线结构的过渡层的厚度。
进一步，在所述外围电路区，所述半导体衬底上具有结构层，所述导线接触孔贯穿所述结构层。
进一步，所述电容导电结构还包括一离子注入层，所述离子注入层位于所述第一导电层内，在所述外围电路区，所述结构层还包括器件层及位于所述器件层上的沉积层，所述沉积层与所述离子注入层为同种材料层。
进一步，在阵列区，在所述半导体衬底上具有多个分立设置的位线结构，所述电容接触孔设置在所述位线结构之间。
进一步，所述位线结构包括位线接触岛及位线，所述位线接触岛与所述半导体衬底接触，所述位线设置在所述位线接触岛上，所述位线包括导电层及设置在所述导电层上的介质层。
进一步，所述第二导电层包括黏附层及金属导电层，所述黏附层至少覆盖所述过渡层表面，所述金属导电层覆盖所述黏附层，且分别填充所述电容接触 孔及所述导线接触孔。
本发明的优点在于，在阵列区，对第一导电层表面进行粗糙化处理，使得在同一步骤中，在阵列区及在外围电路区形成的过渡层的厚度不同，满足了阵列区及外围电路区对过渡层厚度的要求，能够提高阵列区导线的导电性能，且能够避免外围电路区由于过渡层过厚而漏电，大大提高了半导体结构的性能，且制备工艺简单，不会额外增加繁琐的工艺步骤。
附图说明
图1是本发明半导体结构的制备方法的一实施例的步骤示意图；
图2～图9是本发明半导体结构的制备方法的一实施例的工艺流程图。
具体实施方式
下面结合附图对本发明提供的半导体结构及其制备方法的具体实施方式做详细说明。
图1是本发明半导体结构的制备方法的一实施例的步骤示意图。请参阅图1，所述半导体结构的制备方法包括如下步骤：步骤S10，提供半导体衬底，所述半导体衬底包括阵列区及外围电路区，在所述阵列区，所述半导体衬底上具有多个电容接触孔，所述电容接触孔底部沉积有第一导电层，在所述外围电路区，所述半导体衬底上具有器件层；步骤S11，对所述第一导电层进行处理，以增大所述第一导电层的粗糙度；步骤S12，在所述外围电路区形成导线接触孔，所述导线接触孔暴露所述半导体衬底；步骤S13，形成过渡层，所述过渡层至少覆盖所述第一导电层表面及所述导线接触孔暴露的所述半导体衬底表面；步骤S14，形成第二导电层，所述第二导电层覆盖所述过渡层，且填充所述电容接触孔及所述导线接触孔。
图2～图9是本发明半导体结构的制备方法的一实施例的工艺流程图。
请参阅步骤S10及图2，提供半导体衬底200，所述半导体衬底200包括阵列区A及外围电路区B，在所述阵列区A，所述半导体衬底200上具有多个电容接触孔210，所述电容接触孔210底部沉积有第一导电层220，在所述外围电路区B，所述半导体衬底200上具有器件层230。
所述半导体衬底200包括但不限于硅衬底或者锗衬底。
在所述阵列区A，所述半导体衬底200内设置有浅沟槽隔离结构201及被 所述浅沟槽隔离结构201分隔的有源区202。所述电容接触孔210暴露出部分所述有源区202。所述第一导电层220沉积在所述电容接触孔210的底部，并能够与所述有源区202电连接。在本实施例中，所述第一导电层220为多晶硅层。
进一步，在所述半导体衬底200上形成多个分立设置的位线结构203，相邻的位线结构203之间具有间隔，所述电容接触孔210设置在相邻的所述位线结构203之间间隔的区域。所述位线结构203沿一设定方向延伸，例如，在该实施例中，所述位线结构203沿垂直纸面的方向延伸。
所述位线结构203包括位线接触岛203A及设置在所述位线接触岛203A上的位线。所述位线接触岛203A间隔分布在所述半导体衬底200上，例如，在本实施例中，在所述位线203的延伸方向上，所述位线接触岛203A依次排布。所述位线接触岛203A与半导体衬底200中的有源区202接触，进而将位线与有源区202电连接。具体地说，在如图2所示的截面示意图中，存在位线接触岛203A的区域，位线通过所述位线接触岛203A与有源区202电连接，在不存在位线接触岛203A的区域，位线与有源区之间具有绝缘层，即位线不与有源区202电连接。所述位线接触岛203A可由多晶硅等材料形成。所述位线可由多层导电层2031构成，例如，在一实施例中，所述位线由多晶硅层、TiN层及金属钨层等导电层构成。在所述导电层2031上设置有介质层2032，以保护所述导电层，所述介质层2032包括但不限于氮化硅层。
进一步，所述位线结构203还包括设置在所述导电层2031及所述介质层2032侧壁的保护层2033，所述保护层2033可为氮化硅层。
在所述外围电路区B，所述半导体衬底200包括浅沟槽隔离结构201、被所述浅沟槽隔离结构201分隔的有源区202、设置在所述半导体衬底200上的所述器件层230。所述器件层230包括设置在半导体衬底表面的导电结构层231及绝缘层232。所述导电结构层231内设置有导电结构，且所述导电结构与所述有源区202对应。所述导电结构可作为晶体管的栅极。所述绝缘层232覆盖所述导电结构层231，以保护所述导电结构层231。
进一步，为了便于后续工艺的进行，例如，为了便于后续第二导电层(绘示于图9中)的填充，在步骤S10之后，还包括减薄步骤。具体地说，请参阅 图3，对所述阵列区A的位线结构203及所述外围电路区B的器件层230进行减薄处理。在该步骤中，在阵列区A，所述介质层2032及其侧壁的保护层2033被减薄，所述位线的导电层2031未暴露；在所述外围电路区B，所述器件层230的绝缘层232被减薄，所述器件层230的导电结构层231中的导电结构未被暴露。进一步，可采用刻蚀等方式减薄所述介质层2032、所述保护层2033及所述绝缘层232。
请参阅步骤S11及图4，对所述第一导电层220进行处理，以增大所述第一导电层220的粗糙度。在该步骤中，所述第一导电层220表面的粗糙度增加，则其表面的表面积增大，有利于后续形成过渡层250(绘示于图8中)的工艺中，过渡层与第一导电层220的接触面积增大，进而能够增大过渡层的厚度。
在本实施例中，对所述第一导电层220进行离子注入，以破坏第一导电层220表面平整度，增大所述第一导电层220的粗糙度，在图4中采用阴影绘示第一导电层220表面被影响的区域220A。在对所述第一导电层220进行离子注入时，离子会轰击第一导电层220的表面，打断第一导电层220的化学键，破坏第一导电层220表面的平整度，使第一导电层220表面粗糙度增加。例如，当所述第一导电层220为多晶硅时，离子注入会打断多晶硅的Si-Si化学键，破坏多晶硅表面的平整度，使多晶硅表面粗糙度增加，进而增加后续过渡层与多晶硅反应面积，增大过渡层的厚度。
其中，可采用原子半径较大的离子进行离子注入，例如锗离子、碳离子或者砷离子，以进一步打断第一导电层220的化学键，进一步增加第一导电层220的粗糙度。
如图4所示，在进行离子注入后，在阵列区A，在所述第一导电层220中形成了一层离子注入层400。而在外围电路区B，由于所述器件层230的阻挡作用，具体地说，由于绝缘层232的阻挡，离子并未注入所述器件层230，而是沉积在器件层230表面，形成沉积层410。离子注入的深度可根据实际情况确定，离子注入后形成的所述离子注入层400的位置不影响后续过渡层250的形成即可。
进一步，为了避免在后续工艺中第一导电层被氧化，在步骤S11后，还包括一形成隔离层的步骤。具体地说，请参阅图5，形成隔离层500，所述隔离 层500覆盖所述阵列区A及所述外围电路区B的表面。在该实施例中，所述隔离层500为氮化硅层，在阵列区A，其覆盖所述位线结构203的表面、所述第一导电层220的表面，在外围电路区B，所述隔离层500覆盖所述沉积层410的表面。
请参阅步骤S12及图6，在所述外围电路区B，形成导线接触孔240，所述导线接触孔240暴露所述半导体衬底200。具体地说，在本实施例中，采用光刻及刻蚀工艺形成所述导线接触孔240。所述导线接触孔240贯穿所述沉积层410及所述器件层230，并暴露出所述半导体衬底200的有源区202。其中，所述导线接触孔240设置在所述导电结构层231的导电结构的两侧。
可以理解的是，在形成所述导线接触孔240时，所述阵列区A被掩膜遮挡，以避免被刻蚀。
进一步，在步骤S12，形成导线接触孔后，还包括如下步骤：请参阅图7，去除所述隔离层500，以暴露出所述第一导电层220。在该步骤中，可采用刻蚀的方法去除所述隔离层500。
请参阅步骤S13及图8，形成过渡层250，所述过渡层250至少覆盖所述第一导电层220表面及所述导线接触孔240暴露的所述半导体衬底200表面。
在本实施例中，形成所述过渡层250的方法是，在阵列区A及外围电路区B沉积钴，在所述电容接触孔210底部及所述导线接触孔240底部，钴分别与所述半导体衬底200及所述第一导电层220反应，形成过渡层250，在其它区域，例如，所述电容接触孔210侧壁及所述导线接触孔240的侧壁，钴沉积形成钴层。在沉积钴后，采用酸洗等方法清洗去除所述电容接触孔210侧壁及所述导线接触孔240侧壁的钴层，保留所述过渡层250。具体地说，当所述半导体衬底为硅衬底，所述第一导电层220为多晶硅层时，在所述电容接触孔210底部及所述导线接触孔240底部，钴与硅反应，形成硅化钴(CoSix)层，所述硅化钴层为所述过渡层，在其他区域，钴沉积形成钴层。沉积钴后，清洗去除所述钴层。在图8中为了清楚显示过渡层250的结构，适当夸大了过渡层250的尺寸。
进一步，在形成过渡层250后，接着在惰性气体的环境下进行一快速热处理(rapid thermal process，RTP)，例如在制作工艺温度介于700℃～850℃的温 度环境。如此，电容接触孔210及导线接触孔240尚未反应的钴以及未完全反应的CoSi相硅化物会完全反应形成一完整的硅化钴层，进一步降低其阻值。
在步骤S13中，第一导电层220进行过粗糙化处理，而导线接触孔240暴露的半导体衬底200并未进行过粗糙化处理，其表面为平整的表面，则第一导电层220表面的粗糙度大于导线接触孔240暴露的半导体衬底200的粗糙度，使得在沉积钴时，钴与第一导电层220的接触面积大于钴与导线接触孔240暴露的半导体衬底200的接触面积，在电容接触孔210中形成的过渡层250的厚度远大于在导线接触孔240中形成的过渡层250的厚度。对于阵列区A而言，过渡层250厚度足够厚，其导通电流大，导线性能好，而对于外围电路区B而言，过渡层250不会太厚，进而不会引起过高的导通电流，避免击穿效应，避免增大漏电。
请参阅步骤S14及图9，形成第二导电层260，所述第二导电层260覆盖所述过渡层250，且填充所述电容接触孔210及所述导线接触孔240。
在本实施例中，所述第二导电层260包括黏附层261及金属导电层262。形成第二导电层260的步骤进一步包括如下步骤：在过渡层250表面、电容接触孔210侧壁及导线接触孔240侧壁形成黏附层261，所述黏附层261包括但不限于TiN层；在所述黏附层261表面形成金属导电层262，且所述金属导电层262填充所述电容接触孔210及所述导线接触孔240，所述金属导电层262可为金属钨层。
在所述阵列区A，所述第一导电层220、所述过渡层250及所述第二导电层260形成电容导电结构，所述过渡层250能够减小第一导电层220与第二导电层260之间的接触电阻。
在所述外围电路区B，所述过渡层250与所述第二导电层260形成导线结构，所述过渡层250分别连接所述半导体衬底200与第二导电层260，其能够降低所述半导体衬底200与第二导电层260之间的接触电阻，增加层与层之间的连接性能。在所述外围电路区，所述导线结构与半导体衬底200中晶体管的源漏区接触，用于将源漏区引出，所述器件层230的导电结构层231中的导电结构作为晶体管的栅极，用于控制晶体管的导通。所述晶体管主要用作控制电路。
本发明半导体结构的制备方法能够在同一步骤中在阵列区A能够形成厚度较厚的过渡层，而在外围电路区B能够形成厚度较薄的过渡层，满足了阵列区A及外围电路区B对过渡层厚度的要求，大大提高了半导体结构的性能。
本发明还提供一种采用上述制备方法制备的半导体结构。请参阅图9，所述半导体结构包括半导体衬底200、多个电容导电结构及多个导线结构。
所述半导体衬底200包括阵列区A及外围电路区B。在所述阵列区A，所述半导体衬底200上具有多个电容接触孔210，所述电容接触孔210暴露出所述半导体衬底200，在所述外围电路区B，所述半导体衬底200上具有多个导线接触孔240，所述导线接触孔240暴露出所述半导体衬底200。多个电容导电结构设置在所述电容接触孔210内。所述电容导电结构包括填充部分所述电容接触孔210的第一导电层220、至少覆盖所述第一导电层220的过渡层250及覆盖所述过渡层250且填充所述电容接触孔220的第二导电层260，所述第一导电层220与所述半导体衬底200接触，所述过渡层250形成在所述第一导电层220上。所述过渡层250能够降低所述第一导电层220与所述第二导电层260的接触电阻，提高电容导电结构的性能。
进一步，在阵列区A，在所述半导体衬底200上具有多个分立设置的位线结构203，所述电容接触孔210设置在所述位线结构203之间，则所述电容导电结构也位于所述位线结构203之间。所述位线结构203包括位线接触岛203A及位线，所述位线接触岛203A与所述半导体衬底200接触，所述位线设置在所述位线接触岛203A上。进一步，所述位线包括导电层2031及设置在所述导电层2031上的介质层2032。
进一步，所述电容导电结构还包括一离子注入层400，所述离子注入层400位于所述第一导电层220内。
多个导线结构设置在所述导电接触孔240内，所述导线结构包括覆盖所述半导体衬底200表面的过渡层250、覆盖所述过渡层250且填充所述导线接触孔240的第二导电层260，所述过渡层250与所述半导体衬底200接触。进一步，在所述外围电路区B，所述半导体衬底200上具有结构层，所述导线接触孔240贯穿所述结构层。所述结构层包括器件层230及位于所述器件层230上的沉积层410。所述沉积层410与所述离子注入层400为同种材料层，例如， 均为锗材料层、碳材料层或砷材料层。
进一步，所述第二导电层260包括黏附层261及金属导电层262，所述黏附层261至少覆盖所述过渡层250表面，所述金属导电层262覆盖所述黏附层261，且分别填充所述电容接触孔210及所述导线接触孔240。
所述电容导电结构的过渡层250的厚度大于所述导线结构的过渡层250的厚度，满足了阵列区A及外围电路区B对过渡层厚度的要求，大大提高了半导体结构的性能。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (16)

  1. 一种半导体结构的制备方法，其特征在于，包括如下步骤：
    提供半导体衬底，所述半导体衬底包括阵列区及外围电路区，在所述阵列区，所述半导体衬底上具有多个电容接触孔，所述电容接触孔底部沉积有第一导电层，在所述外围电路区，所述半导体衬底上具有器件层；
    对所述第一导电层进行处理，以增大所述第一导电层的粗糙度；
    在所述外围电路区形成导线接触孔，所述导线接触孔暴露所述半导体衬底；
    形成过渡层，所述过渡层至少覆盖所述第一导电层表面及所述导线接触孔暴露的所述半导体衬底表面；
    形成第二导电层，所述第二导电层覆盖所述过渡层，且填充所述电容接触孔及所述导线接触孔。
  2. 根据权利要求1所述的半导体结构的制备方法，其特征在于，在所述半导体衬底上形成多个分立设置的位线结构，所述电容接触孔设置在所述位线结构之间，对所述第一导电层进行处理的步骤之前，对所述阵列区的位线结构及所述外围电路区的器件层进行减薄处理。
  3. 根据权利要求2所述的半导体结构的制备方法，其特征在于，所述位线结构包括位线接触岛及位线，所述位线接触岛与所述半导体衬底接触，所述位线设置在所述位线接触岛上，所述位线包括导电层及设置在所述导电层上的介质层，在减薄处理步骤中，所述介质层被减薄。
  4. 根据权利要求1所述的半导体结构的制备方法，其特征在于，对所述第一导电层进行处理的步骤进一步包括：对所述第一导电层进行离子注入，以破坏第一导电层表面平整度，增大所述第一导电层的粗糙度。
  5. 根据权利要求4所述的半导体结构的制备方法，其特征在于，所述第一导电层为多晶硅层，对所述第一导电层进行离子注入的步骤为，对所述第一导电层进行锗离子、碳离子或者砷离子注入。
  6. 根据权利要求4所述的半导体结构的制备方法，其特征在于，对所述第一导电层进行离子注入的步骤中，在所述外围电路区的器件层表面也形成沉积层。
  7. 根据权利要求1所述的半导体结构的制备方法，其特征在于，对所述第一 导电层进行处理的步骤之后，进一步包括如下步骤：形成隔离层，所述隔离层覆盖所述阵列区及所述外围电路区的表面；在所述外围电路区形成导线接触孔的步骤之后，去除所述隔离层。
  8. 根据权利要求1所述的半导体结构的制备方法，其特征在于，形成过渡层的步骤进一步包括：
    沉积钴层，在所述电容接触孔底部及所述导线接触孔底部，钴分别与所述第一导电层及所述半导体衬底反应，形成所述过渡层；
    进行快速热处理。
  9. 根据权利要求1所述的半导体结构的制备方法，其特征在于，位于所述阵列区的过渡层的厚度大于位于所述外围电路区的过渡层的厚度。
  10. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述第二导电层包括黏附层及金属导电层，形成第二导电层的步骤进一步包括如下步骤：
    在过渡层表面形成黏附层；
    在所述黏附层表面形成金属导电层，且所述金属导电层填充所述电容接触孔及所述导线接触孔。
  11. 一种半导体结构，其特征在于，包括：
    半导体衬底，包括阵列区及外围电路区，在所述阵列区，所述半导体衬底上具有多个电容接触孔，所述电容接触孔暴露出所述半导体衬底，在所述外围电路区，所述半导体衬底上具有多个导线接触孔，所述导线接触孔暴露出所述半导体衬底；
    多个电容导电结构，设置在所述电容接触孔内，所述电容导电结构包括填充部分所述电容接触孔的第一导电层、至少覆盖所述第一导电层的过渡层及覆盖所述过渡层且填充所述电容接触孔的第二导电层，所述第一导电层与所述半导体衬底接触；
    多个导线结构，设置在所述导电接触孔内，所述导线结构包括覆盖所述半导体衬底表面的过渡层、覆盖所述过渡层且填充所述导线接触孔的第二导电层，所述过渡层与所述半导体衬底接触；
    其中，所述电容导电结构的过渡层的厚度大于所述导线结构的过渡层的厚度。
  12. 根据权利要求11所述的半导体结构，其特征在于，在所述外围电路区，所述半导体衬底上具有结构层，所述导线接触孔贯穿所述结构层。
  13. 根据权利要求12所述的半导体结构，其特征在于，所述电容导电结构还包括一离子注入层，所述离子注入层位于所述第一导电层内，在所述外围电路区，所述结构层还包括器件层及位于所述器件层上的沉积层，所述沉积层与所述离子注入层为同种材料层。
  14. 根据权利要求11所述的半导体结构，其特征在于，在阵列区，在所述半导体衬底上具有多个分立设置的位线结构，所述电容接触孔设置在所述位线结构之间。
  15. 根据权利要求14所述的半导体结构，其特征在于，所述位线结构包括位线接触岛及位线，所述位线接触岛与所述半导体衬底接触，所述位线设置在所述位线接触岛上，所述位线包括导电层及设置在所述导电层上的介质层。
  16. 根据权利要求11所述的半导体结构，其特征在于，所述第二导电层包括黏附层及金属导电层，所述黏附层至少覆盖所述过渡层表面，所述金属导电层覆盖所述黏附层，且分别填充所述电容接触孔及所述导线接触孔。
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