WO2022041960A1 - 测试电路、测试装置及其测试方法 - Google Patents

测试电路、测试装置及其测试方法 Download PDF

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Publication number
WO2022041960A1
WO2022041960A1 PCT/CN2021/100759 CN2021100759W WO2022041960A1 WO 2022041960 A1 WO2022041960 A1 WO 2022041960A1 CN 2021100759 W CN2021100759 W CN 2021100759W WO 2022041960 A1 WO2022041960 A1 WO 2022041960A1
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Prior art keywords
signal
pulse
sampling
temporary storage
storage unit
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English (en)
French (fr)
Inventor
张良
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to EP21859804.3A priority Critical patent/EP4089966B1/en
Priority to JP2022550121A priority patent/JP7450050B2/ja
Priority to KR1020227027189A priority patent/KR102684998B1/ko
Priority to US17/467,570 priority patent/US12033709B2/en
Publication of WO2022041960A1 publication Critical patent/WO2022041960A1/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56016—Apparatus features
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/0082—Monitoring; Testing using service channels; using auxiliary channels
    • H04B17/0085—Monitoring; Testing using service channels; using auxiliary channels using test signal generators

Definitions

  • the embodiments of the present application relate to the technical field of memory, and in particular, to a test circuit, a test device, and a test method thereof.
  • a memory is a device used to store data.
  • the memory usually includes multiple storage arrays, and each storage array includes multiple storage units.
  • the storage unit is used as a basic unit structure for storing data, and each storage unit has the function of data storage.
  • the pulse signal can be used to control the turn-on and turn-off of the transistor pair connected to the word line.
  • the memory cell performs a read or write operation, and when the pulse signal is invalid, the memory cell keeps the original state. data.
  • higher requirements are placed on the test circuit and the test device of the pulse width, and the current test circuit can no longer accurately test the continuously narrowed pulse width.
  • test circuit including:
  • the signal processing module is used to receive the pulse signal to be tested and output the processed signal under the control of the control signal;
  • a sampling module connected to the output end of the signal processing module, for receiving the processing signal, and generating a sampling signal according to the processing signal;
  • the sampling signal includes a first sampling pulse and a second sampling pulse, the first sampling pulse and the second sampling pulse have a pulse width difference, and the pulse width difference is equal to the pulse width of the pulse signal.
  • test device comprising:
  • an analysis module connected to the sampling module, and configured to acquire the width of the pulse in the pulse signal according to the first sampling pulse and the second sampling pulse.
  • test method based on the above-mentioned test device, the method comprising:
  • the sampling signal including a first sampling pulse and a second sampling pulse
  • the first sampling pulse and the second sampling pulse have a pulse width difference, and the pulse width difference is equal to the pulse width of the pulse signal.
  • 1 is a schematic structural diagram of a test circuit of the first embodiment
  • FIG. 2 is an exemplary signal timing diagram corresponding to the embodiment of FIG. 1;
  • FIG. 3 is another exemplary signal timing diagram corresponding to the embodiment of FIG. 1;
  • Fig. 4 is another exemplary signal timing diagram corresponding to the embodiment of Fig. 1;
  • FIG. 5 is a schematic structural diagram of a test circuit of the second embodiment
  • FIG. 6 is an exemplary signal timing diagram corresponding to the embodiment of FIG. 5;
  • Fig. 7 is the structural schematic diagram of the test circuit of the third embodiment.
  • FIG. 9 is an exemplary signal timing diagram corresponding to the embodiment of FIG. 8;
  • FIG. 10 is a schematic structural diagram of a test circuit of the fifth embodiment
  • FIG. 11 is a schematic structural diagram of a test circuit of the sixth embodiment.
  • FIG. 12 is a schematic structural diagram of a testing device according to an embodiment
  • FIG. 13 is a flowchart of a testing method according to an embodiment.
  • FIG. 1 is a schematic structural diagram of a test circuit 10 according to a first embodiment.
  • the test circuit 10 includes a signal processing module 100 and a sampling module 200 .
  • the pulse signal to be tested is generated by the pulse generator 30 and is divided into at least two paths, one pulse signal is transmitted to the test circuit 10 for testing, and the other pulse signal is transmitted to the storage array to control the data of the storage array read and write.
  • the pulse signal includes multiple pulses, and the pulse width refers to the duration of the high level of each pulse, that is, the time interval between the rising edge moment and the falling edge moment of a pulse is the pulse width.
  • the signal processing module 100 is configured to receive a pulse signal to be tested, and output a processed signal under the control of a control signal, where the processed signal is the pulse signal or the inverted pulse signal in time division.
  • the time-division of the processed signal as the pulse signal or the inverted pulse signal means that in a part of the time period of the processed signal, the waveform of the processed signal is consistent with the waveform of the pulse signal, and in the remaining time period of the processed signal, the waveform of the processed signal matches the waveform of the pulse signal.
  • the waveform of the processed signal coincides with the waveform of the inverted pulse signal.
  • the processed signal is used to transmit to the clock driving end of the sampling module 200 to be used as a clock to sample the signal input by the sampling module 200.
  • the signal input by the sampling module 200 is processed according to the edge of the processed signal sampling.
  • a sampling module 200 usually only samples one kind of edge, that is, only sampling the rising edge or only sampling the falling edge. Therefore, if the sampling module 200 needs to sample different edges, multiple flip-flops with complex structures need to be arranged in the sampling module 200 , so the internal structure and control circuit of the sampling module 200 are complicated.
  • the sampling module 200 by controlling the time-division of the processing signal to be a pulse signal or an inverted pulse signal, the sampling module 200 only needs to sample one kind of edge, that is, by inverting the pulse signal, so as to realize the sampling of different edges. edge for sampling.
  • the sampling module 200 is sampling on the rising edge, and part of the edge of the sampling signal is generated based on the falling edge of the pulse signal, the target falling edge of the pulse signal can be inverted, so as to convert the falling edge of the pulse signal.
  • simple and accurate sampling of the sampling module 200 can be implemented, thereby simplifying the internal structure of the sampling module 200 .
  • the control logic and circuit required to realize the time-sharing control of the inversion function are simpler. Therefore, the signal processing module 100 of this embodiment further simplifies the test circuit 10 the overall circuit structure.
  • the sampling module 200 connected to the output end of the signal processing module 100, is used for receiving the processing signal, and generating a sampling signal according to the processing signal, wherein the sampling signal includes a first sampling pulse and a second sampling pulse , the first sampling pulse and the second sampling pulse have a pulse width difference, and the pulse width difference is equal to the pulse width of the pulse signal.
  • the pulse width difference refers to the difference between the pulse width of the first sampling pulse and the pulse width of the second sampling pulse.
  • the sampling module 200 generates the sampling signal in response to the edge of the processed signal. Therefore, each rising edge in the sampling signal and each falling edge corresponds to an edge in the processed signal, that is, each rising edge and each falling edge in the sampled signal also corresponds to an edge in the pulse signal.
  • the test circuit 10 includes: a signal processing module 100, configured to receive a pulse signal to be tested, and output a processed signal under the control of a control signal, where the processed signal is time-divisionally the pulse signal or inverted the pulse signal; the sampling module 200, connected to the output end of the signal processing module 100, is used for receiving the processing signal, and generating a sampling signal according to the processing signal; wherein, the sampling signal includes the first sampling The pulse and the second sampling pulse, the first sampling pulse and the second sampling pulse have a pulse width difference, and the pulse width difference is equal to the pulse width of the pulse signal.
  • the input pulse signal is processed by the signal processing module 100, and the sampling module 200 with a relatively simple structure can be used to sample different edges of the pulse signal, thereby simplifying the hardware structure of the test circuit 10, and further through The sampling module 200 samples the processed signal to generate the first sampling pulse and the second sampling pulse, that is, the pulse width can be obtained through the first sampling pulse and the second sampling pulse, that is, a test circuit 10 with higher test accuracy is realized. .
  • the sampling module 200 may be configured to generate the first sampling pulse in response to the same edges of the first two pulses in timing, and generate the first sampling pulse in response to different edges of the last two pulses in timing the second sampling pulse.
  • FIG. 2 is an exemplary signal timing diagram corresponding to the embodiment of FIG. 1. Referring to FIG. 1, in this embodiment, the pulse signal includes four pulses, and the sampling module 200 responds to one of the rising edge and the falling edge of each pulse.
  • the first rising edge of the sampling signal is generated in response to the falling edge of the first pulse
  • the first falling edge of the sampling signal is generated in response to the rising edge of the second pulse
  • the second The rising edge is generated in response to the rising edge of the third pulse
  • the second falling edge of the sampled signal is generated in response to the rising edge of the fourth pulse.
  • the time interval between the first rising edge time t1 and the first falling edge time t2 is the width A of the first sampling pulse
  • the second sampling pulse may be generated in response to the falling edge of the third pulse and the falling edge of the fourth pulse as shown in FIG. 3 .
  • the first sampling pulse may also be generated in response to three or more pulses, and the second sampling pulse may be generated in response to another three or more pulses, as shown in FIG. 4 . It is also possible that five or more pulses are included in the pulsed signal, the first sampling pulse is generated in response to the first pulse and the second pulse, and the second sampling pulse is generated in response to the fourth pulse and the fifth pulse. It should be noted that the generation methods of the sampling signals in the embodiments of FIG. 2 to FIG.
  • FIG. 5 is a schematic structural diagram of the test circuit 10 according to the second embodiment.
  • the sampling module 200 includes: a first temporary storage unit 210 , which is driven by a clock of the first temporary storage unit 210 The terminal is connected to the signal processing module 100, and the first temporary storage unit 210 is used for sampling the to-be-sampled signal in response to the processing signal, so as to generate a first temporary storage signal, the edge of the sampling signal and the first corresponding to the edge of the temporary signal.
  • the input terminal of the first temporary storage unit 210 is connected to the signal source to be sampled, and the signal source to be sampled is used to output the signal to be sampled. level switching signal.
  • FIG. 6 is an exemplary signal timing diagram corresponding to the embodiment of FIG. 5 .
  • the pulse signal may include four pulses that are adjacent in timing, and the signal processing module 100 is used for In response to the control signal, the first one of the pulses in the pulse signal is inverted in time sequence, and the rest of the pulses are not inverted.
  • the sampling module 200 is configured to generate the first sampling pulse in response to the first two pulses in the time sequence, and generate the second sampling pulse in response to the last two pulses in the time sequence.
  • the signal to be sampled The period is twice the period of the pulse signal, and the edge of the signal to be sampled is staggered from the edge of the pulse signal, thereby ensuring the accuracy of sampling the signal to be sampled according to the edge of the processed signal. It can be understood that accurate sampling can be performed only if the signal to be sampled corresponding to the edge moment of the processing signal is in a stable state. Therefore, in this embodiment, the test circuit 10 has a lower requirement on the timing accuracy of the signal to be sampled. , that is, the timing window is larger and has higher timing reliability.
  • the first temporary storage unit 210 includes one or more of flip-flops, latches, and registers.
  • the first temporary storage unit 210 includes a D flip-flop, the clock drive terminal of the D flip-flop is connected to the output terminal of the signal processing module 100 , and the input terminal of the D flip-flop is connected to the signal to be sampled , the signal output by the output terminal of the D flip-flop can be used as the sampling signal.
  • the set terminal or reset terminal of the D flip-flop can also be connected to an external circuit, so that the initial state of the D flip-flop can be determined by means of set or reset, thereby improving the reliability of the test circuit 10 .
  • the first temporary storage unit 210 can sample and latch the edge of the processed signal, so as to output the sampled signal accurately and stably.
  • FIG. 7 is a schematic structural diagram of the test circuit 10 according to the third embodiment.
  • the sampling module 200 further includes: a first inverter 220 , which is common with the first temporary storage unit 210 A feedback loop is formed for generating a feedback signal in response to the processed signal, the edge of the feedback signal corresponding to the edge of the processed signal.
  • the sampled signal can be output only through the signal source to be sampled of the peripheral device.
  • the signal at the input end of the first temporary storage unit 210 can be made to follow the feedback signal output by the first inverter 220 , thereby simplifying the test circuit 10 and improving the flexibility of the test circuit 10 sturdiness and reliability.
  • the input terminal of the first inverter 220 is connected to the output terminal of the first temporary storage unit 210 , and the output terminal of the first inverter 220 is connected to the input terminal of the first temporary storage unit 210 . terminal is connected, and the first inverter 220 is used for inverting the first temporary storage signal to generate a feedback signal.
  • the first temporary storage signal output by the first temporary storage unit 210 is in the 0 state, and the feedback signal outputted through the inversion of the first inverter 220 is in the 1 state, then The signal at the input terminal of the first temporary storage unit 210 is also in the 1 state.
  • the first temporary storage signal will switch to the 1 state, thereby automatically updating the input terminal of the first temporary storage unit 210.
  • the feedback signal is realized, that is, the test circuit 10 with simpler structure and automatic sampling is realized.
  • the sampling module 200 further includes: a second inverter 230 , an input end of the second inverter 230 and an output end of the first inverter 220 connected, the second inverter 230 is configured to receive the feedback signal and generate the sampling signal according to the feedback signal.
  • the signal output by the sampling module 200 can be matched with the signal output by the first temporary storage unit 210.
  • FIG. 8 is a schematic structural diagram of the test circuit 10 according to the fourth embodiment.
  • the test circuit 10 further includes: a control module 300 , respectively connected to the sampling module 200 and the signal processing module 100 is used to generate the control signal in response to the sampling signal, and the edge of the control signal corresponds to the edge of the sampling signal.
  • the control module 300 can generate a corresponding control signal according to the signal output by the sampling module 200, so as to realize the control of the output signal of the signal processing module 100, that is, control the processing signal output by the signal processing module 100 according to the level state of the control signal .
  • FIG. 9 is an exemplary signal timing diagram corresponding to the embodiment of FIG. 8 .
  • the signal processing module 100 when the level state of the control signal is a high level, the signal processing module 100 outputs a pulse signal; When the level state of the control signal is a low level, the signal processing module 100 outputs an inverted pulse signal.
  • the control module 300 may include a second temporary storage unit 310 , the clock drive terminal of the second temporary storage unit 310 is connected to the output terminal of the sampling module 200 , and the input of the second temporary storage unit 310
  • the output terminal of the second temporary storage unit 310 is connected to the signal processing module 100, and the second temporary storage unit 310 is used to respond to the signal processing module 100.
  • the sampling signal samples a preset level signal to generate a second temporary storage signal, and an edge of the control signal corresponds to an edge of the second temporary storage signal. That is, the preset level signal generator outputs a signal with a constant level state, for example, a high level signal.
  • the second temporary storage unit 310 can be reset first, so that the second temporary storage unit 310 can be reset.
  • the unit 310 outputs a 0 state, and disconnects the enable signal of the reset terminal at the target time, and samples the high-level signal output by the preset level signal generator according to the sampling signal, so that the control output of the second temporary storage unit 310
  • the state of the signal Q is switched to the 1 state, so as to achieve the purpose of inverting part of the pulse signal and outputting the remaining pulse signal in the state.
  • the target time can be controlled by the number of inverters connected to the output end of the first temporary storage unit 210 .
  • FIG. 10 is a schematic structural diagram of the test circuit 10 according to the fifth embodiment.
  • the control module 300 further includes: a third inverter 320 , and the input of the third inverter 320 is The terminal is connected to the output terminal of the second temporary storage unit 310 , and the third inverter 320 is configured to receive the second temporary storage signal and generate the control signal according to the second temporary storage signal.
  • the control signal Q and the control signal QN can be generated by the third inverter 320 , that is, the signal processing module 100 can be controlled based on the two control signals, thereby improving the control reliability of the signal processing module 100 .
  • FIG. 11 is a schematic structural diagram of the test circuit 10 according to the sixth embodiment.
  • the signal processing module 100 includes a fourth inverter 110 and a multiplexer 120 .
  • the multiplexer 120 The first input terminal of the multiplexer 120 is connected to the output terminal of the fourth inverter 110, the second input terminal of the multiplexer 120 is connected to the pulse signal, and the output terminal of the multiplexer 120 is connected to the pulse signal.
  • the first temporary storage unit 210 is connected, and the multiplexer 120 is used for receiving the control signal, and under the control of the control signal, selectively turns on the first input terminal or the second input terminal and path between the outputs.
  • the structure of the multiplexer 120 is not limited to the structure in the embodiment of the figure, and other multiplexers 120 that can realize the multiplexing function also belong to the protection scope of the present application.
  • FIG. 12 is a schematic structural diagram of a test device according to an embodiment.
  • the test device includes: the above-mentioned test circuit 10; The first sampling pulse and the second sampling pulse obtain the width of the pulse in the pulse signal.
  • the testing circuit 10 For the specific limitations of the testing circuit 10, reference may be made to the limitations above, which will not be repeated here.
  • a test device for accurate pulse width test is realized through the test circuit 10 and the analysis module 20 .
  • FIG. 13 is a flowchart of a testing method according to an embodiment.
  • the testing method in this embodiment is based on the above-mentioned testing device.
  • the method includes S100 to S400 .
  • S300 Generate a sampling signal according to the processing signal, where the sampling signal includes a first sampling pulse and a second sampling pulse;
  • S400 Acquire the width of the pulse in the pulse signal according to the first sampling pulse and the second sampling pulse.

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  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
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  • Tests Of Electronic Circuits (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

一种测试电路、测试装置及其测试方法，测试电路包括：信号处理模块，用于接收待测试的脉冲信号，并在控制信号的控制下输出处理信号；采样模块，与信号处理模块的输出端连接，用于接收处理信号，并根据处理信号生成采样信号；其中，采样信号包括第一采样脉冲和第二采样脉冲，第一采样脉冲和第二采样脉冲具有一脉冲宽度差，脉冲宽度差等于脉冲信号的脉冲宽度。

Description

测试电路、测试装置及其测试方法
本申请要求于2020年8月31日提交的申请号为202010893028.8、名称为“测试电路、测试装置及其测试方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及存储器技术领域，特别是涉及一种测试电路、测试装置及其测试方法。
背景技术
存储器是用于存储数据的器件，存储器通常包括多个存储阵列，每个存储阵列中包括多个存储单元，存储单元作为存储数据的基本单元结构，每个存储单元都具有数据存储的功能。
在对存储器进行读写操作时，需要由脉冲信号进行控制。示例性地，脉冲信号可以用于控制字线连接的晶体管对导通和断开，具体地，当脉冲信号有效时，存储单元进行读或写操作，当脉冲信号失效时，存储单元保持原来的数据。随着对存储器对读写速度对要求对不断提高，需要进一步提高脉冲信号的发送频率并减小脉冲宽度。为了保证脉冲信号对可靠性，需要通过测试电路对脉冲宽度进行测试，以确保生成对脉冲信号与设计的信号相同。但是，随着脉冲宽度的不断缩窄，对脉冲宽度的测试电路和测试装置提出了更高的要求，目前的测试电路已经无法准确地测试不断缩窄的脉冲宽度。
发明内容
本申请一方面提供一种测试电路，包括：
信号处理模块，用于接收待测试的脉冲信号，并在控制信号的控制下输出处理信号；
采样模块，与所述信号处理模块的输出端连接，用于接收所述处理信号，并根据所述处理信号生成采样信号；
其中，所述采样信号包括第一采样脉冲和第二采样脉冲，所述第一采样脉冲和所述第二采样脉冲具有一脉冲宽度差，所述脉冲宽度差等于所述脉冲信号的脉冲宽度。
本申请另一方面提供一种测试装置，包括：
如上述的测试电路；
分析模块，与所述采样模块连接，用于根据所述第一采样脉冲和所述第二采样脉冲获取所述脉冲信号中所述脉冲的宽度。
本申请另一方面提供一种测试方法，基于如上述的测试装置，所述方法包括：
接收待测试的脉冲信号；
在控制信号的控制下输出处理信号；
根据所述处理信号生成采样信号，所述采样信号包括第一采样脉冲和第二采样脉冲；
根据所述第一采样脉冲和所述第二采样脉冲获取所述脉冲信号中所述脉冲的宽度；
其中，所述第一采样脉冲和所述第二采样脉冲具有一脉冲宽度差，所述脉冲宽度差等于所述脉冲信号的脉冲宽度。
本发明的各个实施例的细节将在下面的附图和描述中进行说明。根据说明 书、附图以及权利要求书的记载，本领域技术人员将容易理解本发明的其它特征、解决的问题以及有益效果。
附图说明
为了更好地描述和说明本申请的实施例，可参考一幅或多幅附图，但用于描述附图的附加细节或示例不应当被认为是对本申请的发明创造、目前所描述的实施例或优选方式中任何一者的范围的限制。
图1为第一实施例的测试电路的结构示意图；
图2为图1实施例对应的一示例性的信号时序图；
图3为图1实施例对应的另一示例性的信号时序图；
图4为图1实施例对应的又一示例性的信号时序图；
图5为第二实施例的测试电路的结构示意图；
图6为图5实施例对应的一示例性的信号时序图；
图7为第三实施例的测试电路的结构示意图；
图8为第四实施例的测试电路的结构示意图；
图9为图8实施例对应的一示例性的信号时序图；
图10为第五实施例的测试电路的结构示意图；
图11为第六实施例的测试电路的结构示意图；
图12为一实施例的测试装置的结构示意图；
图13为一实施例的测试方法的流程图。
具体实施方式
为了便于理解本申请实施例，下面将参照相关附图对本申请实施例进行更 全面的描述。附图中给出了本申请实施例的首选实施例。但是，本申请实施例可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请实施例的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请实施例的技术领域的技术人员通常理解的含义相同。本文中在本申请实施例的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请实施例。本文可能使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本申请实施例的描述中，需要理解的是，可能存在的术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本申请实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请实施例的限制。
图1为第一实施例的测试电路10的结构示意图，参考图1，在本实施例中，测试电路10包括信号处理模块100和采样模块200。
其中，待测试的脉冲信号由脉冲发生器30产生，并被划分为至少两路，一路脉冲信号传输至测试电路10，以进行测试，另一路脉冲信号传输至存储阵列，以控制存储阵列的数据读写。在本申请实施例中，脉冲信号中包括多个脉冲，脉冲宽度是指每个脉冲的高电平的持续时间，即，一个脉冲的上升沿时刻和下降沿时刻的时间间隔为脉冲宽度。
信号处理模块100，用于接收待测试的脉冲信号，并在控制信号的控制下输出处理信号，所述处理信号分时为所述脉冲信号或反相的所述脉冲信号。
其中，处理信号分时为所述脉冲信号或反相的所述脉冲信号是指，在处理信 号的部分时间段内，处理信号的波形与脉冲信号的波形相吻合，在处理信号的剩余时间段内，处理信号的波形与反相的脉冲信号的波形相吻合。在本实施例中，处理信号用于传输至采样模块200的时钟驱动端，以作为时钟对采样模块200输入的信号进行采样，具体地，是根据处理信号的边沿对采样模块200输入的信号进行采样。
可以理解的是，一个采样模块200通常只对一种边沿进行采样，即只对上升沿进行采样或只对下降沿进行采样。因此，若需要采样模块200对不同的边沿进行采样，需要在采样模块200中设置结构复杂的多个触发器等结构，因此会造成采样模块200的内部结构和控制电路较为复杂。在本实施例中，通过控制处理信号分时为脉冲信号或反相的脉冲信号，可以使采样模块200只需对一种边沿进行采样，即通过对脉冲信号进行反相，以实现对不同的边沿进行采样。示例性地，若采样模块200为上升沿采样，而采样信号的部分边沿是基于脉冲信号的下降沿生成的，则可以对脉冲信号的目标下降沿进行反相，从而将脉冲信号的下降沿转化为处理信号的上升沿，即可以实现采样模块200的简单、准确地采样，从而简化了采样模块200的内部结构。而且，相比多个触发器等结构的采样模块200，实现反相功能的分时控制所需要的控制逻辑和电路都更加简单，因此，本实施例的信号处理模块100进而简化了测试电路10的整体电路结构。
采样模块200，与所述信号处理模块100的输出端连接，用于接收所述处理信号，并根据所述处理信号生成采样信号，其中，所述采样信号包括第一采样脉冲和第二采样脉冲，所述第一采样脉冲和所述第二采样脉冲具有一脉冲宽度差，所述脉冲宽度差等于所述脉冲信号的脉冲宽度。其中，脉冲宽度差是指第一采样脉冲的脉冲宽度与第二采样脉冲的脉冲宽度之间的差值，采样模块200响应处理信号的边沿生成采样信号，因此，采样信号中的每个上升沿和每个下降沿都会 与处理信号中的一个边沿相对应，即，采样信号中的每个上升沿和每个下降沿也都会与脉冲信号中的一个边沿相对应。
在本实施例中，测试电路10包括：信号处理模块100，用于接收待测试的脉冲信号，并在控制信号的控制下输出处理信号，所述处理信号分时为所述脉冲信号或反相的所述脉冲信号；采样模块200，与所述信号处理模块100的输出端连接，用于接收所述处理信号，并根据所述处理信号生成采样信号；其中，所述采样信号包括第一采样脉冲和第二采样脉冲，所述第一采样脉冲和所述第二采样脉冲具有一脉冲宽度差，所述脉冲宽度差等于所述脉冲信号的脉冲宽度。在本实施例中，通过信号处理模块100对输入的脉冲信号进行处理，可以以结构较简单的采样模块200对脉冲信号的不同边沿进行采样，从而简化了测试电路10的硬件结构，并进一步通过采样模块200对处理信号进行采样，以生成第一采样脉冲和第二采样脉冲，即可通过第一采样脉冲和第二采样脉冲获取脉冲宽度，即实现了一种测试精度更高的测试电路10。
在一些实施例中，所述采样模块200可以用于响应时序上的前两个所述脉冲的相同边沿生成所述第一采样脉冲，并响应时序上的后两个所述脉冲的不同边沿生成所述第二采样脉冲。图2为图1实施例对应的一示例性的信号时序图，参考图1，在本实施例中，脉冲信号包括四个脉冲，采样模块200响应每个脉冲的上升沿和下降沿中的一个生成相应的边沿，具体地，采样信号的第一个上升沿响应第一个脉冲的下降沿生成，采样信号的第一个下降沿响应第二个脉冲的上升沿生成，采样信号的第二个上升沿响应第三个脉冲的上升沿生成，采样信号的第二个下降沿响应第四个脉冲的上升沿生成。第一个上升沿时刻t1和第一个下降沿时刻t2之间的时间间隔即为第一采样脉冲的宽度A，第二个上升沿时刻t3和第二个下降沿时刻t4之间的时间间隔即为第二采样脉冲的宽度B。因此，基 于本实施例的测试电路10，只需对每个脉冲的一个边沿进行采样，即可获取输入的脉冲信号的脉冲宽度，从而降低了采样模块200的采样难度，从而提高了测试电路10的测试精度。
在其他实施例中，可以如图3所示的响应第三个脉冲的下降沿和第四个脉冲的下降沿生成第二采样脉冲。也可以如图4所示响应三个或三个以上脉冲生成第一采样脉冲，并响应另外的三个或三个以上脉冲生成第二采样脉冲。还可以脉冲信号中包括五个或五个以上脉冲，响应第一个脉冲和第二个脉冲生成第一采样脉冲，并响应第四个脉冲和第五个脉冲生成第二采样脉冲。需要说明的是，图2至图4实施例中的采样信号的生成方式仅用于示例性说明，而不用于限定本申请的保护范围，只要生成的第一采样脉冲的脉冲宽度和第二采样脉冲的脉冲宽度之差等于待测试的脉冲信号的脉冲宽度，都属于本申请的保护范围。
图5为第二实施例的测试电路10的结构示意图，参考图5，在本实施例中，所述采样模块200包括：第一暂存单元210，所述第一暂存单元210的时钟驱动端与所述信号处理模块100连接，所述第一暂存单元210用于响应所述处理信号对待采样信号进行采样，以生成第一暂存信号，所述采样信号的边沿与所述第一暂存信号的边沿相对应。其中，第一暂存单元210的输入端与待采样信号源连接，待采样信号源用于输出待采样信号，示例性地，待采样信号可以是一个以预设时间间隔进行高电平和低电平切换的信号。
图6为图5实施例对应的一示例性的信号时序图，参考图5，在本实施例中，所述脉冲信号可以包括时序上相邻的四个脉冲，所述信号处理模块100用于响应控制信号，对所述脉冲信号中时序上的首个所述脉冲进行反相，并对其余所述脉冲不进行反相。所述采样模块200用于响应时序上的前两个所述脉冲生成所述第一采样脉冲，并响应时序上的后两个所述脉冲生成所述第二采样脉冲， 具体地，待采样信号的周期为脉冲信号的周期的两倍，且待采样信号的边沿与脉冲信号的边沿相错开，从而确保根据处理信号的边沿对待采样信号进行采样的准确性。可以理解的是，只需处理信号的边沿时刻对应的待采样信号为稳定状态，即可进行准确的采样，因此，在本实施例中，测试电路10对待采样信号的时序准确度要求也较低，即时序窗口较大，具有较高的时序可靠性。
进一步地，所述第一暂存单元210包括触发器、锁存器、寄存器中的一种或多种。在图5所示的实施例中，第一暂存单元210包括一个D触发器，D触发器的时钟驱动端与信号处理模块100的输出端连接，D触发器的输入端与待采样信号连接，D触发器的输出端输出的信号即可作为采样信号。再进一步地，D触发器的置位端或复位端也可以连接至外部的电路，从而通过置位或复位的方式确定D触发器的初始状态，从而提升测试电路10的可靠性。在本实施例中，第一暂存单元210可以对处理信号的边沿进行采样和锁存，从而准确、稳定地输出采样信号。
图7为第三实施例的测试电路10的结构示意图，参考图7，在本实施例中，所述采样模块200还包括：第一反相器220，与所述第一暂存单元210共同构成反馈环路，所述反馈环路用于响应所述处理信号生成反馈信号，所述反馈信号的边沿与所述处理信号的边沿相对应。可以理解的是，在前述实施例中，需要通过外设的待采样信号源，才能输出采样信号。在本实施例中，通过形成反馈环路，可以使第一暂存单元210的输入端的信号跟随于第一反相器220输出的反馈信号，从而简化测试电路10，并提高测试电路10的灵活性和可靠性。
具体地，所述第一反相器220的输入端与所述第一暂存单元210的输出端连接，所述第一反相器220的输出端与所述第一暂存单元210的输入端连接，所述第一反相器220用于对所述第一暂存信号进行反相，以生成反馈信号。示 例性地，当前处理信号周期的上升沿到达后，第一暂存单元210输出的第一暂存信号为0状态，经过第一反相器220的反相输出的反馈信号为1状态，则第一暂存单元210的输入端的信号也为1状态，在下一处理信号周期的上升沿到达后，第一暂存信号会切换为1状态，从而自动更新第一暂存单元210的输入端输入的反馈信号，即实现了结构更加简单、且能够自动采样的测试电路10。
继续参考图7，在其中一个实施例中，所述采样模块200还包括：第二反相器230，所述第二反相器230的输入端与所述第一反相器220的输出端连接，所述第二反相器230用于接收所述反馈信号，并根据所述反馈信号生成所述采样信号。通过设置第二反相器230可以使采样模块200输出的信号与第一暂存单元210输出的信号相吻合。
图8为第四实施例的测试电路10的结构示意图，参考图8，在本实施例中，测试电路10还包括：控制模块300，分别与所述采样模块200和所述信号处理模块100连接，用于响应所述采样信号生成所述控制信号，所述控制信号的边沿与所述采样信号的边沿相对应。
具体地，控制模块300可以根据采样模块200输出的信号生成响应的控制信号，以实现对信号处理模块100的输出信号的控制，即根据控制信号的电平状态控制信号处理模块100输出的处理信号。例如，图9为图8实施例对应的一示例性的信号时序图，参考图9，在本实施例中，当控制信号的电平状态为高电平时，信号处理模块100输出脉冲信号；当控制信号的电平状态为低电平时，信号处理模块100输出反相的脉冲信号。
继续参考图8，控制模块300可以包括第二暂存单元310，所述第二暂存单元310的时钟驱动端与所述采样模块200的输出端连接，所述第二暂存单元310的输入端与预设电平信号发生器连接，以获取预设电平信号，所述第二暂存单元 310的输出端与所述信号处理模块100连接，所述第二暂存单元310用于响应所述采样信号对预设电平信号进行采样，以生成第二暂存信号，所述控制信号的边沿与所述第二暂存信号的边沿相对应。即预设电平信号发生器输出一恒定电平状态的信号，例如可以为高电平信号，在采样模块200运行前，可以先对第二暂存单元310进行复位，以使第二暂存单元310输出0状态，并在目标时刻断开复位端的使能信号，并根据采样信号对预设电平信号发生器输出的高电平信号进行采样，以使第二暂存单元310输出的控制信号Q的状态切换为1状态，从而实现对部分脉冲信号进行反相，并保持剩余的脉冲信号的状态进行输出的目的。其中，目标时刻可以通过第一暂存单元210的输出端连接的反相器的数量进行控制。
图10为第五实施例的测试电路10的结构示意图，参考图10，在本实施例中，所述控制模块300还包括：第三反相器320，所述第三反相器320的输入端与所述第二暂存单元310的输出端连接，所述第三反相器320用于接收所述第二暂存信号，并根据所述第二暂存信号生成所述控制信号。在本实施例中，通过第三反相器320可以生成控制信号Q和控制信号QN，即可以基于两个控制信号对信号处理模块100进行控制，从而提高信号处理模块100的控制可靠性。
图11为第六实施例的测试电路10的结构示意图，参考图11，在本实施例中，信号处理模块100包括第四反相器110和多路选择器120，所述多路选择器120的第一输入端与所述第四反相器110的输出端连接，所述多路选择器120的第二输入端与所述脉冲信号连接，所述多路选择器120的输出端与所述第一暂存单元210连接，所述多路选择器120用于接收所述控制信号，并在所述控制信号的控制下选择导通所述第一输入端或所述第二输入端与所述输出端之间的通路。需要说明的是，多路选择器120的结构不局限于图实施例中的结构，其他 可以实现多路选择功能的多路选择器120也属于本申请的保护范围。
图12为一实施例的测试装置的结构示意图，参考图12，在本实施例中，测试装置包括：如上述的测试电路10；分析模块20，与所述采样模块200连接，用于根据所述第一采样脉冲和所述第二采样脉冲获取所述脉冲信号中所述脉冲的宽度。关于测试电路10的具体限定可以参见上文中对于的限定，在此不再赘述。在本实施例中，通过测试电路10和分析模块20实现了一种脉冲宽度测试准确的测试装置。
图13为一实施例的测试方法的流程图，本实施例的测试方法基于如上述的测试装置，参考图13，在本实施例中，所述方法包括S100至S400。
S100：接收待测试的脉冲信号；
S200：在控制信号的控制下输出处理信号；
S300：根据所述处理信号生成采样信号，所述采样信号包括第一采样脉冲和第二采样脉冲；
S400：根据所述第一采样脉冲和所述第二采样脉冲获取所述脉冲信号中所述脉冲的宽度。
需要说明的是，关于测试方法的具体限定可以参见上文中对于测试装置的限定，在此不再赘述。应该理解的是，虽然图13的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图13中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请实施例的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请实施例构思的前提下，还可以做出若干变形和改进，这些都属于本申请实施例的保护范围。因此，本申请实施例专利的保护范围应以所附权利要求为准。

Claims (13)

  1. 一种测试电路，包括：
    信号处理模块，用于接收待测试的脉冲信号，并在控制信号的控制下输出处理信号；
    采样模块，与所述信号处理模块的输出端连接，用于接收所述处理信号，并根据所述处理信号生成采样信号；
    其中，所述采样信号包括第一采样脉冲和第二采样脉冲，所述第一采样脉冲和所述第二采样脉冲具有一脉冲宽度差，所述脉冲宽度差等于所述脉冲信号的脉冲宽度。
  2. 根据权利要求1所述的测试电路，其中，所述采样模块包括：
    第一暂存单元，所述第一暂存单元的时钟驱动端与所述信号处理模块连接，所述第一暂存单元用于响应所述处理信号对待采样信号进行采样，以生成第一暂存信号，所述采样信号的边沿与所述第一暂存信号的边沿相对应。
  3. 根据权利要求2所述的测试电路，其中，所述第一暂存单元包括触发器、锁存器、寄存器中的一种或多种。
  4. 根据权利要求2所述的测试电路，其中，所述采样模块还包括：
    第一反相器，与所述第一暂存单元共同构成反馈环路，所述反馈环路用于响应所述处理信号生成反馈信号，所述反馈信号的边沿与所述处理信号的边沿相对应。
  5. 根据权利要求4所述的测试电路，其中，所述第一反相器的输入端与所述第一暂存单元的输出端连接，所述第一反相器的输出端与所述第一暂存单元的输入端连接，所述第一反相器用于对所述第一暂存信号进行反相，以生成反馈信号。
  6. 根据权利要求5所述的测试电路，其中，所述采样模块还包括：
    第二反相器，所述第二反相器的输入端与所述第一反相器的输出端连接，所述第二反相器用于接收所述反馈信号，并根据所述反馈信号生成所述采样信号。
  7. 根据权利要求1所述的测试电路，其中，所述脉冲信号包括时序上相邻的四个脉冲，所述信号处理模块用于响应所述控制信号，对所述脉冲信号中时序上的首个所述脉冲进行反相，并对其余所述脉冲不进行反相；
    其中，所述采样模块用于响应时序上的前两个所述脉冲生成所述第一采样脉冲，并响应时序上的后两个所述脉冲生成所述第二采样脉冲。
  8. 根据权利要求7所述的测试电路，其中，所述采样模块用于响应时序上的前两个所述脉冲的相同边沿生成所述第一采样脉冲，并响应时序上的后两个所述脉冲的不同边沿生成所述第二采样脉冲。
  9. 根据权利要求1所述的测试电路，其中，还包括：
    控制模块，分别与所述采样模块和所述信号处理模块连接，用于响应所述采样信号生成所述控制信号，所述控制信号的边沿与所述采样信号的边沿相对应。
  10. 根据权利要求9所述的测试电路，其中，所述控制模块包括：
    第二暂存单元，所述第二暂存单元的时钟驱动端与所述采样模块的输出端连接，所述第二暂存单元的输入端与预设电平信号连接，所述第二暂存单元的输出端与所述信号处理模块连接，所述第二暂存单元用于响应所述采样信号对预设电平信号进行采样，以生成第二暂存信号，所述控制信号的边沿与所述第二暂存信号的边沿相对应。
  11. 根据权利要求10所述的测试电路，其中，所述控制模块还包括：
    第三反相器，所述第三反相器的输入端与所述第二暂存单元的输出端连接，所述第三反相器用于接收所述第二暂存信号，并根据所述第二暂存信号生成所 述控制信号。
  12. 一种测试装置，包括：
    如权利要求1至11任一项所述的测试电路；
    分析模块，与所述采样模块连接，用于根据所述第一采样脉冲和所述第二采样脉冲获取所述脉冲信号中所述脉冲的宽度。
  13. 一种测试方法，基于如权利要求12所述的测试装置，所述方法包括：
    接收待测试的脉冲信号；
    在控制信号的控制下输出处理信号；
    根据所述处理信号生成采样信号，所述采样信号包括第一采样脉冲和第二采样脉冲；
    根据所述第一采样脉冲和所述第二采样脉冲获取所述脉冲信号中所述脉冲的宽度；
    其中，所述第一采样脉冲和所述第二采样脉冲具有一脉冲宽度差，所述脉冲宽度差等于所述脉冲信号的脉冲宽度。
PCT/CN2021/100759 2020-08-31 2021-06-18 测试电路、测试装置及其测试方法 Ceased WO2022041960A1 (zh)

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