WO2022042333A1 - 时延补偿值确定方法、装置、设备和存储介质 - Google Patents

时延补偿值确定方法、装置、设备和存储介质 Download PDF

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Publication number
WO2022042333A1
WO2022042333A1 PCT/CN2021/112458 CN2021112458W WO2022042333A1 WO 2022042333 A1 WO2022042333 A1 WO 2022042333A1 CN 2021112458 W CN2021112458 W CN 2021112458W WO 2022042333 A1 WO2022042333 A1 WO 2022042333A1
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Prior art keywords
impulse response
frequency domain
domain impulse
channel frequency
compensation value
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PCT/CN2021/112458
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English (en)
French (fr)
Inventor
陈诗军
李俊强
陈大伟
张诗壮
李刚
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ZTE Corp
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ZTE Corp
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Priority to JP2023504795A priority Critical patent/JP7529890B2/ja
Priority to US18/021,419 priority patent/US12362968B2/en
Priority to EP21860172.2A priority patent/EP4207887B1/en
Priority to KR1020237005561A priority patent/KR20230040363A/ko
Publication of WO2022042333A1 publication Critical patent/WO2022042333A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/0055—Synchronisation arrangements determining timing error of reception due to propagation delay
    • H04W56/0095—Synchronisation arrangements determining timing error of reception due to propagation delay estimated based on signal strength
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0475—Circuits with means for limiting noise, interference or distortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/101—Monitoring; Testing of transmitters for measurement of specific parameters of the transmitter or components thereof
    • H04B17/104—Monitoring; Testing of transmitters for measurement of specific parameters of the transmitter or components thereof of other parameters, e.g. DC offset, delay or propagation times
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/30—Monitoring; Testing of propagation channels
    • H04B17/309—Measuring or estimating channel quality parameters
    • H04B17/364—Delay profiles
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/0212—Channel estimation of impulse response
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/022—Channel estimation of frequency response
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/004—Synchronisation arrangements compensating for timing error of reception due to propagation delay
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present application relates to the field of wireless communication technologies, for example, to a method, apparatus, device, and storage medium for determining a delay compensation value.
  • Time-based positioning methods such as TDOA and RTT are usually used for high-precision positioning.
  • the time-based positioning method requires the transmitter to have high-precision synchronization performance, or to be able to measure and compensate for synchronization errors.
  • the hardware link needs to go through a series of hardware modules and links from the baseband signal to the antenna port, including the baseband module, digital-to-analog conversion, in-phase quadrature modulation, video graphics array, power amplifier, power amplifier, ring device + switch, antenna vibrator. These links cause delay errors, which in turn affect signal synchronization accuracy and ultimately positioning accuracy.
  • the embodiments of the present application propose a method, apparatus, device, and storage medium for determining a delay compensation value, which aim to determine the channel frequency domain impulse response of a transmission link by combining hardware modules, and then determine the delay compensation of the transmission link value to achieve high-precision delay compensation for complex hardware links.
  • the embodiment of the present application provides a method for determining a delay compensation value, the method includes:
  • the transmit chain is obtained by combining at least two hardware modules in the transmit circuit;
  • the delay compensation value of the transmit link is determined according to the preset conditions and the time domain impulse response.
  • An embodiment of the present application provides an apparatus for determining a delay compensation value, and the apparatus includes:
  • a determination module configured to obtain a channel frequency domain impulse response of a transmission chain, wherein the transmission chain is obtained by combining at least two hardware modules in the transmission circuit;
  • the conversion module is set to obtain the time domain impulse response according to the channel frequency domain impulse response
  • the determining module is further configured to determine the delay compensation value of the transmission link according to the preset condition and the time domain impulse response.
  • An embodiment of the present application provides a device, including: a memory, a processor, and a computer program stored in the memory and running on the processor.
  • the processor executes the computer program, the delay as provided in the embodiment of the present application is implemented. Compensation value determination method.
  • Embodiments of the present application provide a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method for determining a delay compensation value provided by the embodiments of the present application is implemented.
  • FIG. 1 is a schematic diagram of a wireless signal transmission chain in the related art.
  • FIG. 2 is a schematic diagram of the compensation principle of the averaging method in the related art.
  • FIG. 3 is a flowchart of a method for determining a delay compensation value provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of a method for determining a delay compensation value provided by another embodiment of the present application.
  • FIG. 5 is a flowchart of a method for determining a delay compensation value provided by another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a time domain impulse response corresponding to a module used in a combined transmit chain provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of estimating the average delay of multiple subcarriers in the related art.
  • FIG. 8 is a schematic diagram of the mean time delay of the integration of estimation modules in the related art.
  • FIG. 9 is a schematic diagram of a time domain impulse response corresponding to a combination module provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of an apparatus for determining a delay compensation value provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a device provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of a method for determining a delay compensation value provided by an embodiment of the present application.
  • the method can be applied to a hardware transmitting circuit. As shown in FIG. 3 , the method can include the following steps:
  • the hardware transmission circuit may include hardware chips, switches, modules, lines, etc., and the combination of the transmission link in this step can be understood as the basis for the hardware chips, switches, modules, lines, etc. in the hardware transmission circuit.
  • a set of hardware modules is obtained, and multiple modules in the set of hardware modules constitute a transmission chain, and then the channel frequency domain impulse response is determined according to the transmission chain obtained by the combination.
  • Convert the obtained channel frequency domain impulse response of the transmit link to obtain the time domain impulse response for example, convert the channel frequency domain impulse response to the time domain impulse response through Inverse Fast Fourier Transform (IFFT). excited response.
  • IFFT Inverse Fast Fourier Transform
  • a time-domain impulse response that satisfies the conditions can be selected based on a preset condition, and the delay compensation value of the transmit link is determined according to the selected time-domain impulse response, wherein the time-domain impulse response
  • the impulse response can be a radial signal or a shock pulse.
  • the above preset condition may be exceeding the preset threshold, that is, determining the pulse signal whose signal strength exceeds the preset threshold, and then determining the delay compensation value of the transmission link according to the delay of the pulse signal exceeding the preset threshold.
  • An embodiment of the present application provides a method for determining a time delay compensation value, to obtain a channel frequency domain impulse response of a transmit link, where the transmit link is obtained by combining at least two hardware modules in a transmit circuit, and according to the channel frequency domain
  • the time domain impulse response is obtained from the impulse response, and then the delay compensation value of the transmission link is determined according to the preset condition and the time domain impulse response.
  • the implementation manner of obtaining the channel frequency domain impulse response of the transmit link in the foregoing step S301 may include but not be limited to the following steps:
  • S401 Determine the wideband channel frequency domain impulse responses of multiple hardware modules in the transmitting circuit.
  • the implementation of this step may include the following processes:
  • Step 1 Input all subcarriers of different frequencies divided in the set frequency band into the current module in turn, and use the output of the current module to all subcarriers as the wideband channel frequency domain impulse response of the current module.
  • Step 2 Take the next module in the transmitting circuit as the current module.
  • each divided sub-carrier After dividing the set frequency band into multiple sub-carriers with different frequencies, input each divided sub-carrier into all hardware modules in the hardware transmitting circuit, and obtain the channel frequency domain impulse response of each hardware module to each sub-carrier .
  • S402. Combine at least two modules in the multiple hardware modules in the transmission circuit used by the transmission chain.
  • the module used in the transmission chain can be any module in the hardware module, for example, a switch, a hardware chip, etc., according to the situation, the required module can be selected from the hardware modules in the transmission circuit to combine the modules selected by the transmission chain.
  • S403. Determine the channel frequency domain impulse response of the transmit link according to the combined broadband channel frequency domain impulse responses of the at least two modules.
  • the channel frequency domain of the transmit link can be determined according to the wideband channel frequency domain impulse responses of at least two modules combined above. impulse response.
  • the frequency domain impulse responses of the wideband channels of at least two modules in the combination are multiplied to obtain the channel frequency domain impulse responses of the transmit link.
  • the implementation manner of obtaining the channel frequency domain impulse response of the transmit link in the foregoing step S301 may include but is not limited to the following steps:
  • the modules used in the transmission chain are selected from the hardware transmission circuit, and the modules used in the transmission chain are combined to obtain an integral module, which is determined as a combination module.
  • module used in the transmission chain can be any module in the transmission circuit.
  • the time domain output signal output by the combination module is the time domain output signal of the transmission link.
  • the time-domain output signal can be converted to a frequency-domain output signal by a Fast Fourier Transform (FFT).
  • FFT Fast Fourier Transform
  • an FFT can be used to convert the wideband time-domain signal input to the combining block to a frequency-domain input signal.
  • the implementation manner of determining the delay compensation value of the transmission link according to the delay of the pulse signal exceeding the preset threshold may be: Determined as the delay compensation value of the transmit chain.
  • the obtained multiple pulse signals are sorted according to the time delay, that is, P it ⁇ P i+1.t , if P xa is greater than the preset threshold, and P xa >P Ya , P xt >P Yt , then the determined The delay of the transmit link is P xt .
  • P xa represents the intensity of the x-th pulse signal
  • P xt represents the time delay of the x-th pulse signal
  • the frequency-domain impulse responses of the broadband channels of the three modules are measured separately, and the frequency-domain impulse responses of the channels of the entire transmit chain are obtained by combined calculation, and the obtained channel frequency-domain impulse responses are transformed into time-domain impulse responses, as shown in Figure 6. shown.
  • the first pulse signal The time position corresponding to the estimated delay is 65684, that is, the delay compensation value of the corresponding transmit chain is (65684-65537)/16 ⁇ 9.1875Ts.
  • the delay of each sub-carrier is obtained, and the average value of each sub-carrier is obtained as the delay compensation value.
  • the final average delay compensation value is about 5.9183*10 - 8 , which is 59.183ns, which is about 7.3979Ts, as shown in Figure 7.
  • the method provided by the embodiment of the present application can increase the error of 1.7896Ts compared with the time delay compensation value estimated in the related art.
  • Another way is to combine the modules as an integrated module, that is, a combined module, pass the channel impulse response through a system composed of all modules in the entire link, and take the impulse response output from the link as the entire transmission link.
  • the frequency domain impulse response of the channel is obtained, and then the time delay compensation value is obtained.
  • the received integrated output data is changed to the frequency domain, the delay of each sub-carrier is obtained, and the average value is determined, which is the delay compensation value of the entire transmission chain.
  • the obtained average delay compensation value is about 2.6164*10 -8 , that is, 26.164ns, which is about 3.2705Ts.
  • the time delay estimation is performed on the obtained integrated time domain impulse response, and the time delay of the first pulse signal satisfying the preset condition is used as the time delay compensation value, as shown in FIG. 9 ,
  • the position corresponding to the estimated time delay of the first pulse signal is 65570, that is, the corresponding time delay compensation value is (65570-65537)/16 ⁇ 2.0625Ts.
  • FIG. 10 is an apparatus for determining a delay compensation value provided by an embodiment of the present application. As shown in FIG. 10 , the apparatus includes a determination module 1001 and a conversion module 1002 .
  • the determining module is configured to obtain the channel frequency domain impulse response of the transmission link, wherein the transmission link is obtained by combining at least two hardware modules in the transmission circuit;
  • the conversion module is set to obtain the time domain impulse response according to the channel frequency domain impulse response
  • the determining module is further configured to determine the delay compensation value of the transmission link according to the preset condition and the time domain impulse response.
  • the above determining module is configured to determine the wideband channel frequency domain impulse responses of multiple hardware modules in the transmitting circuit, and combine at least two modules used in the transmitting link, according to the wideband channel of the combined at least two modules.
  • Frequency domain impulse response which determines the channel frequency domain impulse response of the transmit link.
  • the module used in the transmission chain is any module in the hardware module.
  • the determination by the determining module of the wideband channel frequency domain impulse responses of the above multiple hardware modules may be implemented in the following manner:
  • Step 1 Input all subcarriers of different frequencies divided in the set frequency band into the current module in turn, and use the output of the current module to all subcarriers as the wideband channel frequency domain impulse response of the current module;
  • Step 2 Take the next module in the transmitting circuit as the current module
  • the above determining module may be further configured to multiply the frequency domain impulse responses of the wideband channels of the at least two modules to determine the channel frequency domain impulse responses of the transmit link.
  • the above determination module may include a conversion unit and a calculation unit
  • the determining module is set to combine the modules used by the transmission link in the transmission circuit to obtain the combination module, and input the broadband time domain signal into the combination module to obtain the time domain output signal of the transmission link, wherein the module used in the transmission link is Any module in the transmitter circuit;
  • a conversion unit configured to convert the time-domain output signal into a frequency-domain output signal, and convert the broadband time-domain signal into a frequency-domain input signal
  • the calculation unit is configured to divide the frequency domain output signal by the frequency domain input signal to obtain the frequency domain impulse response of the wideband channel of the transmitting link.
  • the above determining module may be further configured to determine a pulse signal whose signal strength exceeds a preset threshold in the time domain impulse response, and determine the delay compensation value of the transmission link according to the time delay of the pulse signal.
  • an implementation manner in which the determining module determines the delay compensation value of the transmission link may include determining the delay of the first pulse signal in the pulse signals as the delay compensation value of the transmission link.
  • the apparatus for determining a delay compensation value provided in this embodiment is configured to implement the methods for determining a delay compensation value in the embodiments shown in FIG. 3 , FIG. 4 , and FIG.
  • FIG. 11 is a schematic structural diagram of a device provided by an embodiment of the application. As shown in FIG. 11 , the device includes a processor 1101 and a memory 1102; the number of processors 1101 in the device may be one or more. A processor 1101 is taken as an example; the processor 1101 and the memory 1102 in the device may be connected by a bus or in other ways, and the connection by a bus is taken as an example in FIG. 11 .
  • the memory 1102 can be configured to store software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the methods in the embodiments of FIG. 1 , FIG. 2 , and FIG. 3 of the present application (for example, The determination module 1001 and the conversion module 1002 in FIG. 10 ).
  • the processor 1101 implements the above-mentioned methods in the embodiments of FIG. 3 , FIG. 4 and FIG. 5 by running the software programs, instructions and modules stored in the memory 1102 .
  • the memory 1102 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the set-top box, and the like. Additionally, memory 1102 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device.
  • the processor in the above-mentioned node may also implement the above-mentioned method for determining the delay compensation value through hardware circuits such as logic circuits and gate circuits inside the processor.
  • the embodiments of the present application also provide a readable and writable storage medium, which is set to be stored by a computer, and the storage medium stores one or more programs.
  • the one or more programs can be executed by one or more processors, the following can be achieved: Methods provided by the embodiments of FIG. 3 , FIG. 4 , and FIG. 5 .
  • the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components Components execute cooperatively.
  • Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit .
  • Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • Computer storage media includes both volatile and nonvolatile implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules or other data flexible, removable and non-removable media.
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or may Any other medium used to store desired information and which can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media, as is well known to those of ordinary skill in the art .

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Abstract

本申请公开一种时延补偿值确定方法、装置、设备及计算机可读存储介质，该方法包括得到发射链路的信道频域冲激响应，其中所述发射链路由发射电路中的至少两个硬件模块组合得到；根据信道频域冲激响应得到时域冲激响应，进而根据预设条件和时域冲激响应确定发射链路的时延补偿值。

Description

时延补偿值确定方法、装置、设备和存储介质 技术领域
本申请涉及无线通信技术领域，例如涉及一种时延补偿值确定方法、装置、设备和存储介质。
背景技术
在第五代移动通信技术(5th generation wireless systems，5G)领域，通常采用接收信号强度指示(Received Signal Strength Indication，RSSI)、到达时间差(Time Difference of Arrival，TDOA)、信号到达角(Angle of Arrival，AOA)、往返时间(Round-Trip Time，RTT)等方法进行5G通信系统中的定位，其中，TDOA、RTT等基于时间的定位方法通常用于高精度定位。而基于时间的定位方法要求发射设备具有高精度同步性能，或者能够对同步误差进行测量补偿。如图1所示，硬件链路从基带信号到天线口发射需要经过一系列硬件模块和链路，包括基带模块，数模转换，同相正交调制，视频图形阵列，功率放大器，功率放大器，环形器+开关，天线振子。这些链路会导致时延误差，进而影响信号同步精度和最终的定位精度。
相关技术中是输入多个测试信号测试多个模块的时延，然后取多个模块时延的平均值作为补偿值，如图2所示。但是，这种方式存在较大的误差，多个硬件模块叠加之后会进一步扩大时延误差，难以实现高精度的时延补偿。
发明内容
本申请实施例提出一种时延补偿值确定方法、装置、设备和存储介质，旨在通过组合硬件模块的方式确定发射链路的信道频域冲激响应，进而确定发射链路的时延补偿值，以实现复杂硬件链路的高精度时延补偿。
本申请实施例提供了一种时延补偿值确定方法，该方法包括：
得到发射链路的信道频域冲激响应，其中所述发射链路由发射电路中的至少两个硬件模块组合得到；
根据信道频域冲激响应得到时域冲激响应；
根据预设条件和时域冲激响应确定发射链路的时延补偿值。
本申请实施例提供了一种时延补偿值确定装置，该装置包括：
确定模块，设置为得到发射链路的信道频域冲激响应，其中所述发射链路由发射电路中的至少两个硬件模块组合得到；
转换模块，设置为根据信道频域冲激响应得到时域冲激响应；
确定模块，还设置为根据预设条件和时域冲激响应确定发射链路的时延补偿值。
本申请实施例提供了一种设备，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，在处理器执行计算机程序时，实现如本申请实施例提供的时延补偿值确定方法。
本申请实施例提供了一种计算机可读存储介质，计算机可读存储介质存储有计算机程序，计算机程序被处理器执行时实现如本申请实施例提供的时延补偿值确定方法。
附图说明
图1是相关技术中的无线信号发射链路示意图。
图2是相关技术中平均方法补偿原理示意图。
图3是本申请实施例提供的一种时延补偿值确定方法的流程图。
图4是本申请另一实施例提供的一种时延补偿值确定方法的流程图。
图5是本申请另一实施例提供的一种时延补偿值确定方法的流程图。
图6是本申请实施例提供的组合发射链路使用的模块对应的时域冲激响应示意图。
图7是相关技术中估计多个子载波平均时延的示意图。
图8是相关技术中估计模块一体化的时延均值示意图。
图9是本申请实施例提供的组合模块对应的时域冲激响应示意图。
图10是本申请实施例提供的一种时延补偿值确定装置结构示意图。
图11是本申请实施例提供的一种设备的结构示意图。
具体实施方式
下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
图3为本申请实施例提供的一种时延补偿值确定方法的流程图，该方法可以应用于硬件发射电路中，如图3所示，该方法可以包括以下步骤：
S301、得到发射链路的信道频域冲激响应，其中所述发射链路由发射电路中的至少两个硬件模块组合得到。
示例性地，硬件发射电路中可以包括硬件芯片、开关、模组、线路等，本步骤中组合得到发射链路即可理解为对硬件发射电路中的硬件芯片、开关、模组、线路等根据实际需求进行组合，从而得到硬件模块集合，该硬件模块集合中的多个模块即构成了发射链路，进而，根据组合得到的发射链路确定其信道频域冲激响应。
S302、根据信道频域冲激响应得到时域冲激响应。
将得到的发射链路的信道频域冲激响应换算得到时域冲激响应，例如，通过快速傅里叶反变换(Inverse Fast Fourier Transform，IFFT)将信道频域冲激响应转换为时域冲激响应。
S303、根据预设条件和时域冲激响应确定发射链路的时延补偿值。
由于存在多个时域冲激响应，那么可以基于预设条件选择满足条件的时域冲激响应，并根据选择的时域冲激响应确定发射链路的时延补偿值，其中，该时域冲激响应可以为径信号 或者冲击脉冲。
示例性地，上述预设条件可以为超过预设门限，即确定信号强度超过预设门限的脉冲信号，进而根据超过预设门限的脉冲信号的时延确定发射链路的时延补偿值。
本申请实施例提供了一种时延补偿值确定方法，得到发射链路的信道频域冲激响应，其中所述发射链路由发射电路中的至少两个硬件模块组合得到，根据信道频域冲激响应得到时域冲激响应，进而根据预设条件和时域冲激响应确定发射链路的时延补偿值。这样可以实现复杂硬件链路的高精度时延补偿，进而提高基于该时延补偿值得到的定位精度。
如图4所示，在一种实施例中，上述步骤S301中得到发射链路的信道频域冲激响应的实现方式可以包括但不限于以下步骤：
S401、确定发射电路中多个硬件模块的宽带信道频域冲激响应。
示例性地，本步骤的实现方式可以包括以下过程：
步骤一：将设定频带内划分的不同频率的所有子载波依次输入当前模块，将当前模块对所有子载波的输出作为当前模块的宽带信道频域冲激响应。
步骤二：将发射电路中的下一个模块作为当前模块。
重复上述步骤一至步骤二，直至确定发射电路中所有模块的宽带信道频率冲激响应。
即将设定频带划分为多个不同频率的子载波后，将划分后的每个子载波输入到硬件发射电路中的所有硬件模块中，得到每个硬件模块对每个子载波的信道频域冲激响应。
S402、组合发射链路使用的发射电路中多个硬件模块中的至少两个模块。
发射链路使用的模块可以为硬件模块中的任意模块，例如，开关、硬件芯片等等，可以根据情况在发射电路中的硬件模块中选择需要的模块对发射链路选择的模块进行组合。
S403、根据组合的至少两个模块的宽带信道频域冲激响应，确定发射链路的信道频域冲激响应。
由于步骤S401中确定了硬件发射电路中所有硬件模块的宽带信道频域冲激响应，因此，可以根据上述组合的至少两个模块的宽带信道频域冲激响应，确定发射链路的信道频域冲激响应。
例如，将组合中的至少两个模块的宽带信道频域冲激响应相乘，得到发射链路的信道频域冲激响应。
如图5所示，在一种实施例中，上述步骤S301中得到发射链路的信道频域冲激响应的实现方式可以包括但不限于以下步骤：
S501、组合发射电路中发射链路使用的模块得到组合模块。
即从硬件发射电路中选取发射链路使用的模块，并对发射链路使用的模块进行组合，得到一个整体模块，将该整体模块确定为组合模块。
可以理解的是，发射链路使用的模块可以为发射电路中的任意模块。
S502、将宽带时域信号输入组合模块，得到发射链路的时域输出信号。
由于将得到的组合模块看做一个整体，那么将宽带时域信号输入组合模块后，组合模块输出的时域输出信号即为发射链路的时域输出信号。
S503、将时域输出信号转换为频域输出信号。
例如，可以通过快速傅里叶变换(Fast Fourier Transformation，FFT)将时域输出信号转 换为频域输出信号。
S504、将宽带时域信号转换为频域输入信号。
同样地，可以采用FFT将输入组合模块的宽带时域信号转换为频域输入信号。
S505、将频域输出信号除以频域输入信号，得到发射链路的宽带信道频域冲激响应。
在一种示例中，上述步骤S303中，根据超过预设门限的脉冲信号的时延确定发射链路的时延补偿值的实现方式可以为，将脉冲信号中的第一个脉冲信号的时延确定为发射链路的时延补偿值。
例如，对得到的多个脉冲信号按照时延进行排序，即P i.t＜P i+1.t，若P x.a大于预设门限，并且P x.a＞P Y.a，P x.t＞P Y.t，则确定的发射链路的时延即为P x.t。
其中，P x.a表示第x个脉冲信号的强度，P x.t表示第x个脉冲信号的时延。
下面以具体示例对上述过程进行详细描述。例如，假设存在三个模块，分别为模块a、模块b、模块c，对这三个模块输入宽带时域信号，其采样周期Ts＝8ns，过采样倍数为16，第一个脉冲信号时延所对应的时间位置为65537。对模块a构造一个脉冲信号的时域信道，该信号无衰减，时延为1Ts；对模块b构造两个脉冲信号的时域信道，衰减分别为0.5和1，时延分别为2Ts和4Ts；对模块c构造两个脉冲信号的时域信道，衰减分别为0.7和1，时延分别为6Ts和8Ts。单独测量三个模块的宽带信道频域冲激响应，并组合计算得到整个发射链路的信道频域冲激响应，将得到的信道频域冲激响应变换为时域冲激响应，如图6所示。对发射链路的时域冲激响应进行时延估计，将超过预设门限的第一个脉冲信号的时延作为发射链路的时延补偿值，如图6所示，第一个脉冲信号的估计时延对应的时间位置为65684，即对应的发射链路的时延补偿值为(65684-65537)/16≈9.1875Ts。而相关技术中通过接收数据变化到频域，求出每个子载波的时延，并求取每个子载波的平均值作为时延补偿值，最终得到的平均时延补偿值约为5.9183*10 -8，即59.183ns，约为7.3979Ts，如图7所示。相比之下，本申请实施例提供的方法可以比相关技术中估计得到的时延补偿值提高1.7896Ts的误差。
另一种方式是将模块组合后看作一个一体化的模块，即组合模块，将信道冲激响应通过整个链路的所有模块构成的系统，将链路输出的冲激响应作为整个发射链路的信道频域冲激响应，进而得到时延补偿值。
如图8所示，相关技术中是将接收到的一体化输出数据变化到频域，求出每个子载波的时延，确定其平均值，即为整个发射链路的时延补偿值，计算得到的平均时延补偿值约为2.6164*10 -8，即26.164ns，约为3.2705Ts。
基于本申请实施例提供的方法，对得到的一体化时域冲激响应进行时延估计，将满足预设条件的第一个脉冲信号的时延作为时延补偿值，如图9所示，第一个脉冲信号的估计时延对应的位置为65570，即对应的时延补偿值为(65570-65537)/16≈2.0625Ts。
图10为本申请实施例提供的一种时延补偿值确定装置，如图10所示，该装置包括确定模块1001、转换模块1002。
其中，确定模块，设置为得到发射链路的信道频域冲激响应，其中所述发射链路由发射电路中的至少两个硬件模块组合得到；
转换模块，设置为根据信道频域冲激响应得到时域冲激响应；
确定模块，还设置为根据预设条件和时域冲激响应确定发射链路的时延补偿值。
在一种示例中，上述确定模块设置为确定发射电路中多个硬件模块的宽带信道频域冲激响应，并组合发射链路使用的至少两个模块，根据组合的至少两个模块的宽带信道频域冲激响应，确定发射链路的信道频域冲激响应。其中，发射链路使用的模块为硬件模块中的任意模块。
示例性地，确定模块确定上述多个硬件模块的宽带信道频域冲激响应可以通过以下方式实现：
步骤一：将设定频带内划分的不同频率的所有子载波依次输入当前模块，将当前模块对所有子载波的输出作为当前模块的宽带信道频域冲激响应；
步骤二：将发射电路中的下一个模块作为当前模块；
重复上述步骤一至步骤二，直至确定发射电路中所有模块的宽带信道频率冲激响应。
在一种示例中，上述确定模块还可以设置为将至少两个模块的宽带信道频域冲激响应相乘，确定发射链路的信道频域冲激响应。
在一种示例中，上述确定模块可以包括转换单元和计算单元；
其中，确定模块设置为组合发射电路中发射链路使用的模块得到组合模块，以及，将宽带时域信号输入组合模块，得到发射链路的时域输出信号，其中，发射链路使用的模块为发射电路中的任意模块；
转换单元，设置为将时域输出信号转换为频域输出信号，以及将宽带时域信号转换为频域输入信号；
计算单元，设置为将频域输出信号除以频域输入信号，得到发射链路的宽带信道频域冲激响应。
在一种示例中，上述确定模块还可以设置为确定时域冲激响应中信号强度超过预设门限的脉冲信号，并根据脉冲信号的时延确定发射链路的时延补偿值。
示例性地，确定模块确定发射链路的时延补偿值的实现方式可以包括将脉冲信号中的第一个脉冲信号的时延确定为发射链路的时延补偿值。
本实施例提供的时延补偿值确定装置设置为实现图3、图4、图5所示实施例的时延补偿值确定方法，其实现原理和技术效果类似，此处不再赘述。
图11为本申请实施例提供的一种设备的结构示意图，如图11所示，该设备包括处理器1101和存储器1102；设备中处理器1101的数量可以是一个或多个，图11中以一个处理器1101为例；设备中的处理器1101和存储器1102可以通过总线或其他方式连接，图11中以通过总线连接为例。
存储器1102作为一种计算机可读存储介质，可设置为存储软件程序、计算机可执行程序以及模块，如本申请图1、图2、图3实施例中的方法对应的程序指令/模块(例如，图10中的确定模块1001、转换模块1002)。处理器1101通过运行存储在存储器1102中的软件程序、指令以及模块实现上述的图3、图4、图5实施例中的方法。
存储器1102可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据机顶盒的使用所创建的数据等。此外，存储器1102可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。
在一种示例中，在可能的情况下，上述节点中的处理器也可以通过其内部的逻辑电路、门电路等硬件电路实现上述的时延补偿值确定方法。
本申请实施例还提供了一种可读写存储介质，设置为计算机存储，存储介质存储有一个或者多个程序，在一个或者多个程序可被一个或者多个处理器执行时，可以实现如图3、图4、图5实施例所提供的方法。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、设备中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。
在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。

Claims (10)

  1. 一种时延补偿值确定方法，包括：
    得到发射链路的信道频域冲激响应，其中所述发射链路由发射电路中的至少两个硬件模块组合得到；
    根据所述信道频域冲激响应得到时域冲激响应；
    根据预设条件和所述时域冲激响应确定所述发射链路的时延补偿值。
  2. 根据权利要求1所述的方法，其中，所述得到发射链路的信道频域冲激响应，包括：
    确定发射电路中多个硬件模块的宽带信道频域冲激响应；
    组合所述发射链路使用的所述多个硬件模块中的至少两个模块；
    根据组合的所述至少两个模块的宽带信道频域冲激响应，确定所述发射链路的信道频域冲激响应。
  3. 根据权利要求2所述的方法，其中，所述确定发射电路中多个硬件模块的宽带信道频域冲激响应，包括：
    将设定频带内划分的不同频率的所有子载波依次输入当前模块，将所述当前模块对所有子载波的输出作为所述当前模块的宽带信道频域冲激响应；
    将所述发射电路中的下一个模块作为当前模块；
    重复执行所述将设定频带内划分的不同频率的所有子载波依次输入当前模块，将所述当前模块对所有子载波的输出作为所述当前模块的宽带信道频域冲激响应，将所述发射电路中的下一个模块作为当前模块的步骤，直至确定所述发射电路中所有模块的宽带信道频率冲激响应。
  4. 根据权利要求1所述的方法，其中，所述得到发射链路的信道频域冲激响应，包括：
    组合所述发射电路中发射链路使用的至少两个模块得到组合模块；
    将宽带时域信号输入所述组合模块，得到所述发射链路的时域输出信号；
    将所述时域输出信号转换为频域输出信号；
    将所述宽带时域信号转换为频域输入信号；
    将所述频域输出信号除以所述频域输入信号，得到所述发射链路的宽带信道频域冲激响应。
  5. 根据权利要求2所述的方法，其中，所述根据组合的所述至少两个模块的宽带信道频域冲激响应，确定所述发射链路的信道频域冲激响应，包括：
    将所述至少两个模块的宽带信道频域冲激响应相乘，确定所述发射链路的信道频域冲激响应。
  6. 根据权利要求1-5任一项所述的方法，其中，所述根据预设条件和所述时域冲激响应确定所述发射链路的时延补偿值，包括：
    确定所述时域冲激响应中信号强度超过预设门限的脉冲信号；
    根据所述脉冲信号的时延确定所述发射链路的时延补偿值。
  7. 根据权利要求6所述的方法，其中，所述根据所述脉冲信号的时延确定所述发射链路 的时延补偿值，包括：
    将所述脉冲信号中的第一个脉冲信号的时延确定为所述发射链路的时延补偿值。
  8. 一种时延补偿值确定装置，包括：
    确定模块，设置为得到发射链路的信道频域冲激响应，其中所述发射链路由发射电路中的至少两个硬件模块组合得到；
    转换模块，设置为根据所述信道频域冲激响应得到时域冲激响应；
    所述确定模块，还设置为根据预设条件和所述时域冲激响应确定所述发射链路的时延补偿值。
  9. 一种设备，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时，实现如权利要求1-7任一项所述的时延补偿值确定方法。
  10. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1-7任一项所述的时延补偿值确定方法。
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