WO2022142633A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022142633A1
WO2022142633A1 PCT/CN2021/126056 CN2021126056W WO2022142633A1 WO 2022142633 A1 WO2022142633 A1 WO 2022142633A1 CN 2021126056 W CN2021126056 W CN 2021126056W WO 2022142633 A1 WO2022142633 A1 WO 2022142633A1
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WO
WIPO (PCT)
Prior art keywords
base substrate
trace
wiring
display
orthographic projection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/126056
Other languages
English (en)
French (fr)
Inventor
赵二瑾
蒋志亮
王领然
颜俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US17/800,559 priority Critical patent/US12041814B2/en
Priority to JP2022559787A priority patent/JP7836767B2/ja
Priority to KR1020227034218A priority patent/KR20230124841A/ko
Priority to EP21913378.2A priority patent/EP4095662A4/en
Publication of WO2022142633A1 publication Critical patent/WO2022142633A1/zh
Anticipated expiration legal-status Critical
Priority to US18/673,576 priority patent/US12490583B2/en
Priority to US19/342,822 priority patent/US20260033134A1/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04107—Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04111—Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04112—Electrode mesh in capacitive digitiser: electrode for touch sensing is formed of a mesh of very fine, normally metallic, interconnected lines that are almost invisible to see. This provides a quite large but transparent electrode surface, without need for ITO or similar transparent conductive material

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • An organic electroluminescent (OLED) display device is a display screen based on organic electroluminescent diodes. It has excellent characteristics such as self-luminescence, high contrast, thin thickness, wide viewing angle, fast response speed, can be used for flexible panels, wide operating temperature range, simple structure and process, etc. It has attracted more and more attention and has application prospects. broad.
  • an OLED display module is used to integrate the touch function by embedding the touch structure, so as to realize the integration of the display function and the touch function of the OLED display device.
  • an embodiment of the present disclosure provides a display substrate, including:
  • the base substrate comprising: a display area, and a frame area surrounding the display area;
  • At least one ring of blocking dams is arranged around the display area in the frame area;
  • the touch metal layer is located on the side of the layer where the barrier dam is located away from the base substrate;
  • the touch metal layer includes a plurality of touch electrodes and a plurality of contacts electrically connected to the plurality of touch electrodes control signal lines, wherein the plurality of touch electrodes are at least partially located in the display area, and the plurality of touch signal lines are located in the frame area;
  • the plurality of touch signal lines include: parallel along a first direction A plurality of first wirings and a plurality of second wirings are provided; wherein, the orthographic projection of the plurality of first wirings on the base substrate is located at the front of the blocking dam on the base substrate Between the projection and the display area, the orthographic projection of the plurality of second traces on the base substrate is located on the side away from the display area of the orthographic projection of the barrier dam on the base substrate .
  • the above-mentioned display substrate provided in the embodiment of the present disclosure further includes: an organic insulating layer having a first groove, and the first groove is located at an orthographic projection of the barrier dam on the base substrate and the orthographic projections of the plurality of first traces on the base substrate;
  • N 1 of the plurality of first wirings satisfies the formula: N 1 ⁇ (Dd 1 -d 2 )/(d 3 +d 4 ), and the number N 2 of the plurality of second wirings satisfies the formula: N 2 ⁇ NN 1 ;
  • D is the shortest distance between the boundary of the display area and the barrier dam
  • d 1 is the shortest distance between the first groove and the first trace
  • d 2 is the first groove
  • d 3 is the line width of the first trace L 1
  • d 4 is the distance between the adjacent first traces
  • N is the total number of the plurality of touch signal lines.
  • the number of the plurality of first wirings is less than or equal to 27, and the number of the plurality of second wirings is less than or equal to 23.
  • the plurality of touch signal lines further include: a plurality of third wirings and a plurality of fourth wirings arranged in parallel along the second direction; wherein,
  • the third wiring and the first wiring are in one-to-one correspondence as an integral structure, and the fourth wiring and the second wiring are in a one-to-one correspondence as an integral structure;
  • Orthographic projections of the plurality of third wirings and the plurality of fourth wirings on the base substrate span the orthographic projections of the barrier dams on the base substrate.
  • the frame area includes a bending area located on a side of the barrier dam away from the display area;
  • the orthographic projection of the second trace on the base substrate is located between the orthographic projection of the barrier dam on the base substrate and the bending region;
  • the orthographic projection of the third trace on the base substrate is located between the orthographic projection of the first trace on the base substrate and the bending region;
  • the orthographic projection of the fourth trace on the base substrate is located corresponding to the orthographic projection of the second trace on the base substrate and the orthographic projection of the first trace on the base substrate. between projections.
  • the frame area further includes a pad area located on a side of the bending area away from the barrier dam;
  • the plurality of touch signal lines further include: the plurality of fifth wirings and the plurality of sixth wirings arranged in parallel along the second direction; wherein,
  • the plurality of fifth wires and the plurality of sixth wires are arranged side by side on a side of the second wire adjacent to the central axis of the base substrate in the second direction;
  • the fifth wiring, the third wiring and the first wiring are in one-to-one correspondence as an integral structure, and the fifth wiring is adjacent to the first wiring through the third wiring
  • One end of the central axis of the base substrate in the second direction is connected, and the fifth trace extends to the pad area through the bending area;
  • the sixth wiring, the fourth wiring and the second wiring are in one-to-one correspondence as an integral structure, and the fourth wiring and the second wiring are far away from the base substrate in the first wiring.
  • the other ends of the central axis in the two directions are connected, the sixth trace is connected to one end of the second trace adjacent to the central axis of the base substrate in the second direction, and the sixth trace is connected Lines extend through the bend region to the pad region.
  • one end of the first trace away from the central axis of the base substrate in the second direction, and the fourth trace away from all One end of the second wiring is located in the frame area adjacent to the frame area where the plurality of third wires are located;
  • the orthographic projection of one end of the first trace away from the central axis of the base substrate in the second direction on the base substrate, and the fourth trace away from the second trace is located between the orthographic projection of the blocking dam on the base substrate and the display area.
  • the plurality of touch signal lines further include: a plurality of seventh wirings and a plurality of eighth wirings arranged in parallel along the second direction; in,
  • the seventh wiring and the first wiring are in one-to-one correspondence as an integral structure, and the seventh wiring and the first wiring are far from the central axis of the base substrate in the second direction. connected at one end;
  • the eighth wiring and the fourth wiring are in one-to-one correspondence in an integrated structure, and the eighth wiring is connected to an end of the fourth wiring that is far away from the second wiring.
  • the plurality of touch signal lines are divided into two groups, and the two groups of touch signal lines are in the second direction with respect to the base substrate
  • the central axis of the set is symmetrical.
  • the line widths of the first wiring and the second wiring are smaller than that of the third wiring, the fourth wiring, and the first wiring.
  • the line widths of the fifth line and the sixth line, and the line widths of the first line and the second line are substantially equal to the line widths of the seventh line and the eighth line.
  • the line widths of the first wiring and the second wiring are 3 ⁇ m-20 ⁇ m, and the third wiring and the fourth wiring are ,
  • the line width of the fifth line and the sixth line is 5-20 ⁇ m
  • the line width of the seventh line and the eighth line is 3 ⁇ m-20 ⁇ m.
  • the resistance values of the touch signal lines are approximately the same.
  • the organic insulating layer further includes a second groove, wherein the second groove is located on a side of the barrier dam away from the display area;
  • the orthographic projection of the second trace on the base substrate is located in the second groove.
  • the distance between the orthographic projection of the first trace on the base substrate and the orthographic projection of the barrier dam on the base substrate is The shortest distance is greater than the shortest distance between the orthographic projection of the second trace on the base substrate and the orthographic projection of the blocking dam on the base substrate.
  • the distance between the orthographic projection of the first trace on the base substrate and the orthographic projection of the barrier dam on the base substrate is The shortest distance is 30 ⁇ m-200 ⁇ m, and the shortest distance between the orthographic projection of the second trace on the base substrate and the orthographic projection of the barrier dam on the base substrate is 10 ⁇ m-100 ⁇ m.
  • the width of the first groove is smaller than the width of the second groove.
  • the above-mentioned display substrate provided in the embodiment of the present disclosure further includes: at least one shielding wire;
  • the at least one shielded wire is located on at least one side of the plurality of first wirings in the second direction, and/or is located on at least one of the plurality of second wirings in the second direction. side.
  • the at least one shielded wire is disposed around the touch signal wire including the first trace, and/or the at least one shielded wire surrounds The touch signal line arrangement including the second wiring.
  • the display substrate provided by the embodiment of the present disclosure, it further comprises: a crack detection line located on a side of the shielding line away from the display area;
  • the crack detection line crosses the barrier dam in the frame area where the first trace is located, and is located between the barrier dam and the display area in other frame areas.
  • the above-mentioned display substrate provided in the embodiment of the present disclosure further includes: a ground wire located between the shield wire and the crack detection wire, and the direction of the ground wire is the same as the direction of the shield wire roughly the same.
  • the distance between the first trace and the base substrate is greater than that of the second trace The distance between the line and the base substrate.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned display substrate.
  • FIG. 1 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure
  • Fig. 2 is a kind of enlarged structural schematic diagram of N region in Fig. 1;
  • Fig. 3 is another kind of enlarged structural schematic diagram of N region in Fig. 1;
  • Fig. 4 is a cross-sectional structure schematic diagram along line I-II in Fig. 3;
  • Fig. 5 is the sectional structure schematic diagram along III-IV line in Fig. 3;
  • Fig. 6 is the enlarged structural schematic diagram of M region in Fig. 1;
  • FIG. 7 is another schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is another schematic plan structure diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 9 is another schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is another schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is another schematic plan structure diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 12 is another schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 13 is another schematic plan view of the display substrate provided by the embodiment of the present disclosure.
  • the FMLOC process is to make a metal grid electrode layer on the packaging layer of the display module to realize the touch function, so there is no need for an external touch structure (TSP), which can reduce the thickness of the screen.
  • TSP external touch structure
  • the FMLOC process is mostly made of two layers of metal, one is a metal mesh layer (Metal Mesh, MM), and the other is a bridge metal layer (Bridge Metal, BM).
  • the metal grid is located in the display area, and can be divided into a touch-driven (Tx) metal grid and a touch-sensitive (Rx) metal grid according to the horizontal and vertical directions. Among them, the Rx metal grid and the Tx metal grid One is connected to each other and the other is connected by bridging metal layers.
  • FMLOC products are also provided with barrier dams and multiple touch signal traces located in the frame area; among them, the barrier dams are arranged around the display area to prevent external water vapor or oxygen from entering the display area; multiple touch signals
  • the lines are all arranged between the barrier dam and the display area, and are respectively electrically connected to the Tx metal grid and the Rx metal grid.
  • an embodiment of the present disclosure provides a display substrate, as shown in FIG. 1 and FIG. 2 , including:
  • a base substrate 101, the base substrate 101 includes: a display area AA, and a frame area BB surrounding the display area AA;
  • At least one circle of blocking dams 102 is arranged around the display area AA in the frame area BB;
  • the touch metal layer MM is located on the side of the layer where the barrier dam 102 is located away from the base substrate 101 ;
  • the touch metal layer MM includes a plurality of touch electrodes Tx/Rx, and a plurality of touch signal lines 103, wherein the plurality of touch electrodes Tx/Rx are at least partially located in the display area AA, and the plurality of touch signal lines 103 are located in the frame area BB;
  • the plurality of touch signal lines 103 may include: along the first direction A plurality of first wires L 1 and a plurality of second wires L 2 arranged in parallel; wherein, the orthographic projections of the plurality of first wires L 1 on the base substrate 101 are located on the base substrate 101 of the barrier dam 102 Between the orthographic projection on the base substrate 101 and the display area AA, the orthographic projection of the plurality of second traces L 2 on the base substrate 101 is located on the side away from the display area AA of the orthographic projection of the barrier dam 102 on the base substrate 101
  • a plurality of first wirings L1 are placed in the frame area BB inside the barrier dam 102, and a plurality of second wirings arranged in parallel with the first wirings L1
  • the line L2 is arranged in the border area BB outside the blocking dam 102, so that the space outside the blocking dam 102 can be reasonably utilized, thereby effectively reducing the width of the border area BB inside the blocking dam 102, which is conducive to realizing products with a narrower border design need.
  • a plurality of first wiring lines L 1 and a plurality of second wiring lines L 2 disposed in parallel in the frame area BB on the lower side are separated from the inner and outer sides of the barrier dam 102 for illustration.
  • the touch signal lines 103 are divided into two parts, they are respectively disposed on the inner and outer sides of the blocking dam 102 .
  • an organic insulating layer 104 having a first groove H1 may be further included, and the first groove H1 is used to prevent The intrusion of water and oxygen into the display area AA can be specifically located between the orthographic projection of the barrier dam 102 on the base substrate 101 and the orthographic projection of the first wiring L1 on the base substrate 101, and is in contact with the barrier dam 102 and with The shortest distance between the first traces L 1 is d 1 .
  • an inclined plane may be set between the display area AA and the groove H1 according to actual needs.
  • the shortest distance d1 of the first groove H1 is the shortest distance on a plane parallel to the base substrate , that is, the shortest distance d 1 of the first groove H 1 does not include the slope between the display area AA and the groove H 1 .
  • the area between the display area AA and the groove H1 is an inclined plane, at least part of the plurality of first wirings may be disposed on the inclined plane.
  • the number N 1 of the plurality of first wiring lines L 1 satisfies the formula: N 1 ⁇ (Dd 1 ⁇ d 2 )/(d 3 +d 4 ); wherein, D represents the boundary of the display area AA ( That is, the shortest distance between the boundary line between the display area AA and the border area BB where the first groove H1 is located) and the blocking dam 102, d2 represents the width of the first groove H1 along the second direction Y, and d3 represents the first groove H1.
  • a line width of the wiring L1, d4 represents the spacing of the first wiring L1.
  • the number N 2 of the plurality of second wirings L 2 satisfies the formula: N 2 ⁇ NN 1 ; wherein, N is the total number of all touch signal lines 103 electrically connected to the Tx metal grid and the Rx metal grid.
  • N is the total number of all touch signal lines 103 electrically connected to the Tx metal grid and the Rx metal grid.
  • the number of the plurality of first wirings L 1 is less than or equal to 27, and the number of the plurality of second wirings L 2 is less than or equal to 23.
  • N 1 (Dd 1 -d 2 )/(d 3 +d 4 )
  • N 2 NN 1 , in this case, the border area BB of the display panel is the narrowest and will not interfere Display area AA displays normally.
  • the plurality of touch signal lines 103 may further include: a plurality of third wiring lines L 3 arranged in parallel along the second direction Y and A plurality of fourth routing lines L 4 ; wherein, the second direction Y and the first direction X are crossed and arranged;
  • the second traces L 2 correspond to one-to-one integrated structure; the orthographic projections of the plurality of third traces L 3 and the plurality of fourth traces L 4 on the base substrate 101 cross the barrier dam 102 on the base substrate 101 orthographic projection.
  • the control signal line 103 is connected to an external driving circuit.
  • the external driving circuit may be an electrical connection of a Flexible Print Circuit Board (FPC).
  • the second trace L2 on the outside of the blocking dam 102 can be led out to the inside of the blocking dam 102, which is beneficial to realize the electrical connection between the touch signal line 103 and the Tx or Rx metal grid in the display area AA;
  • the arrangement of the traces L 2 can reasonably utilize the space outside the barrier dam 102 , thereby reducing the width of the frame area BB inside the barrier dam 102 , thereby realizing a further narrowing design of the frame area BB.
  • the orthographic projection of the second wiring L 2 on the base substrate 101 may be located between the orthographic projection of the barrier dam 102 on the base substrate 101 and the bending area BA; the third wiring L 3 is located at The orthographic projection on the base substrate 101 may be located between the orthographic projection of the corresponding first trace L1 on the base substrate 101 and the bending area BA; the orthographic projection of the fourth trace L4 on the base substrate 101 may be It is located between the orthographic projection of the corresponding second wire L 2 on the base substrate 101 and the orthographic projection of the first wire L 1 on the base substrate 101; A wiring line L1 extends toward the bending area BA, and a fourth wiring line L4 extends toward the inner side of the blocking dam 102 from the second wiring line L2 designed in an integrated manner.
  • the frame area BB may further include a pad area PA located on the side of the bending area BA away from the barrier dam 102; a plurality of touch signals
  • the line 103 may further include: a plurality of fifth wiring lines L 5 and a plurality of sixth wiring lines L 6 arranged in parallel along the second direction Y; wherein, a plurality of fifth wiring lines L 5 and a plurality of sixth wiring lines L 6 are arranged side by side on the side of the second wiring L 2 adjacent to the central axis of the base substrate 101 in the second direction Y; the fifth wiring L 5 , the third wiring L 3 and the first wiring L 1 are one-to-one Corresponding to the integrated structure, the fifth wiring L5 is connected to one end of the first wiring L1 adjacent to the central axis of the base substrate 101 in the second direction Y through the third wiring L3, and the fifth wiring L5 Extends to the pad area PA through the
  • the pad area PA has a plurality of contact pads (or called pads, Pads), each of which is configured to electrically connect a fifth trace L 5 or a sixth trace L 6 .
  • the contact pads may be exposed on the surface of the pad area PA, ie not covered by any layer, so as to facilitate electrical connection to the flexible printed circuit board.
  • the flexible printed circuit board is electrically connected to the external controller, and is configured to transmit a signal or power from the external controller to the fifth and sixth wirings L 5 and L 6 .
  • the wiring methods of the common (Com) signal lines, power supply (VDD/VSS) lines, ground (GND) lines, etc. wired in the frame area BB can also adopt the above-mentioned wiring methods of the touch signal lines 103 .
  • the touch signal line 103 may include: a first portion 103 a provided on the same layer as the metal mesh layer MM, and a first portion 103 a provided on the same layer as the bridge metal layer BM and aligned with the first portion 103a is electrically connected to the second portion 103b.
  • the touch signal line 103 As a double-layered line including the first part 103a and the second part 103b, after one layer of the line is partially broken, the metal mesh layer MM can still be connected to the metal mesh layer MM through the other layer of the line Loading the touch signal, thus effectively solving the problem that the single-layer wiring breakage easily leads to touch failure; in addition, compared with the design of the single-layer wiring, the double-layer wiring can also reduce the resistance value of the touch signal line 103 .
  • the first part 103 a and the second part 103 b are electrically connected through via holes penetrating the inorganic insulating layer 105 .
  • the fifth wiring L 5 and the sixth wiring L 6 included in the touch signal line 103 may be in the bending area BA
  • the wiring is performed from the metal mesh layer MM and the bridge metal layer BM to the second source-drain metal layer 106 (SD2), and returns to the metal mesh layer MM and the bridge metal layer BM in the pad area PA for wiring.
  • SD2 second source-drain metal layer 106
  • the display substrate may include a plurality of self-capacitance electrodes disposed in different layers from the plurality of touch traces, and the inorganic insulating layer 105 is located on the layer where the plurality of touch traces are located and the layer where the plurality of self-capacitance electrodes are located. and each touch trace is electrically connected to a self-capacitance electrode through a via hole passing through the inorganic insulating layer 105 .
  • the display side of the display substrate can be defaulted to be the front side, and the side opposite to the display side can be the back side.
  • the bending of the bending area BA makes the pad area PA located on the side of the bending area BA away from the display area DA all on the back of the display substrate, which can improve space utilization and reduce the area occupied by the border area BB.
  • one end of the first wiring L1 away from the central axis of the base substrate 101 in the second direction Y, and the fourth wiring One end of L4 far away from the second wiring L2 is located in the adjacent frame area of the frame area where the plurality of third wirings L3 are located; and the first wiring L1 is far away from the base substrate 101 in the second direction Y
  • the orthographic projection of one end of the central axis of , on the base substrate 101 , and the orthographic projection of the end of the fourth trace L 4 away from the second trace L 2 on the base substrate 101 are located on the base substrate 101 of the barrier dam 102 between the orthographic projection on and the display area AA.
  • the touch signal lines 103 including the first trace L 1 , the third trace L 3 and the fifth trace L 5 in the present disclosure are first folded from the frame area BB on the right side to the bottom side.
  • the border area BB crosses the blocking dam 102, and then extends to the pad area PA through the bending area BA to be electrically connected to the flexible printed circuit board; and includes a second trace L 2 , a fourth trace L 4 and a sixth trace
  • the touch signal line 103 of L6 first crosses the blocking dam 102 from the frame area BB on the right side, then is folded to the frame area BB on the lower side, and then extends to the pad area PA and the flexible printed circuit board through the bending area BA. connect.
  • the arrangement of the second wiring L 2 can reasonably utilize the space outside the barrier dam 102 , thereby reducing the width of the frame area BB inside the barrier dam 102 , thereby realizing a further narrowing design of the frame area BB.
  • the plurality of touch signal lines 103 may further include: a plurality of seventh lines L 7 and A plurality of eighth lines L 8 ; wherein, the seventh line L 7 and the first line L 1 are in one-to-one correspondence as an integral structure, and the seventh line L 7 and the first line L 1 are far away from the base substrate 101 One end of the central axis in the second direction Y is connected; the eighth wiring L8 and the fourth wiring L4 are in one-to-one correspondence as an integral structure, and the eighth wiring L8 and the fourth wiring L4 are far away from the second wiring One end of L2 is connected.
  • the seventh trace L 7 may extend in the second direction Y within the adjacent frame region.
  • the eighth trace L8 may also be located in the frame area.
  • the adjacent frame regions extend along the second direction Y. This arrangement minimizes the wiring length of the touch signal line 103 , so that the resistance value of the touch signal line 103 is small, and the upper signal delay of the touch signal line 103 is avoided.
  • the plurality of touch signal lines 103 may be divided into two groups, and the two groups of touch signal lines 103 are located in the second group with respect to the base substrate 101 .
  • the central axis EF in the direction Y is arranged symmetrically.
  • the wiring method of the touch signal lines 103 on the inner and outer sides of the barrier dam is the same on both sides of the central axis EF of the base substrate 101 in the second direction Y, but the specific number of the two groups of touch signal lines is not limited. That is to say, the number of the two groups of touch signal lines may be the same or different. This arrangement facilitates balanced wiring, improves process stability, and realizes further narrowing design of the frame area.
  • the line widths of the first wiring L 1 and the second wiring L 2 may be set to be smaller than those of the first wiring L 1 and the second wiring L 2 .
  • the line widths of the third line L 3 , the fourth line L 4 , the fifth line L 5 , and the sixth line L 6 , and the line widths of the first line L 1 and the second line L 2 are approximately equal to the line width of the first line L 1 and the second line L 2 .
  • Line widths of the seventh trace L 7 and the eighth trace L 8 are approximately equal to the line width of the first line L 1 and the second line L 2 .
  • the line widths of the first trace L 1 and the second trace L 2 may be 3 ⁇ m-20 ⁇ m, for example, 7.3 ⁇ m;
  • the line widths of the fourth line L 4 , the fifth line L 5 , and the sixth line L 6 may be 5 ⁇ m-20 ⁇ m, for example, 9.2 ⁇ m;
  • the line widths of the seventh line L 7 and the eighth line L 8 may be 3 ⁇ m-20 ⁇ m, eg 7.2 ⁇ m.
  • the display substrate may further include: an organic insulating layer 104 , and the organic insulating layer 104 is provided with a first groove H1 and a first groove H1 and a first groove H1 .
  • Two grooves H 2 wherein the first groove H 1 is located between the blocking dam 102 and the display area AA, and the second groove H 2 is located on the side of the blocking dam 102 away from the display area AA ;
  • the orthographic projection on the base substrate 101 is located between the first groove H1 and the display area AA, and the orthographic projection of the second wiring L2 on the base substrate 101 is located in the second groove H2 .
  • the first groove H 1 is used to cut off the insulating layer 104 to prevent water and oxygen from invading into the display area AA; the second groove H 2 is used to release the bending stress.
  • the distance between the first wiring L 1 and the base substrate 101 is greater than that of the second wiring L 2 The distance from the base substrate 101 .
  • the distance between the first wiring L 1 and the base substrate 101 is greater than that of the second wiring L 2 The distance from the base substrate 101 .
  • the barrier dam 102 there are many film layers under the first trace L1 inside the barrier dam 102 , which are the base substrate 101 , the first source-drain metal layer 107 ( SD1 ), the first source-drain metal layer 107 ( SD1 ), the first Two planarization layers 1042 (PLN2), a pixel definition layer 1043 (PDL), a first inorganic encapsulation layer 108, an organic encapsulation layer 109, a second inorganic encapsulation layer 110 and a second etch barrier layer 111 (BFL2); and the barrier dam 102
  • There are fewer film layers under the second trace L1 on the outside, and from bottom to top are the base substrate 101, the first source-drain metal layer 107, the first inorganic encapsulation layer 108, the second inorganic encapsulation layer 110 and the second Etch the barrier layer 111 ; in some embodiments, it is ensured that the line widths of the first wiring L 1 and the second wiring L 2 on the inner and outer sides of
  • the organic insulating layer 104 may include a first flat layer 1041 ( PLN1 ), a second flat layer 1042 , and a pixel defining layer 1043 ;
  • the barrier dam 102 may include a surrounding display area AA The first barrier dam 1021 and the second barrier dam 1022 surrounding the first barrier dam 1021; wherein, the stacked pattern of the first barrier dam 1021 is located in the second flat layer 1042 and the pixel defining layer 1043, and the second barrier dam 1022 The stacked pattern is located on the first flat layer 1041 , the second flat layer 1042 and the pixel defining layer 1043 .
  • the height of the first barrier dam 1021 relative to the base substrate 101 is higher than that of the second barrier dam 1022 relative to the base substrate
  • the height of 101 is low, so that the path for external water vapor and oxygen to enter the display area AA becomes longer, which increases the difficulty of entering the display area AA, and further improves the blocking ability of the blocking dam 102 .
  • the width of the first barrier dam 1021 , the width of the second barrier dam 1022 , and the distance between the first barrier dam 1021 and the second barrier dam 1022 may be approximately the same, eg, 30 ⁇ m.
  • the cross-sectional shape of the first barrier dam 1021 and the second barrier dam 1022 may be a rectangle as shown in FIG. 4 or a trapezoid as shown in FIG. 5 .
  • the side of the area AA is an inclined plane, which is not limited here.
  • the third and fourth traces L 3 and L 4 may be arranged on the first The line width at the gap between the barrier dam 1021 and the second barrier dam 1022 is narrowed.
  • inside of the barrier dam 102 specifically refers to the side of the first barrier dam 1021 close to the display area AA
  • outside of the barrier dam 102 specifically refers to a side of the second barrier dam 1022 away from the display area AA side.
  • the display substrate may further include: an interlayer dielectric layer 112 (ILD), a gate insulating layer 113 (GI), a first etch barrier layer 114 (BFL1), a buffer layer 115 (BRL) and Spacer layer 116 (PS).
  • ILD interlayer dielectric layer
  • GI gate insulating layer 113
  • BFL1 first etch barrier layer 114
  • BFL1 buffer layer 115
  • PS Spacer layer 116
  • the first wiring L 1 inside the blocking dam 102 can avoid the first groove H 1 , so that the first wiring L 1 inside the blocking dam 102 does not overlap with the first groove H 1 .
  • the shortest distance d between the orthographic projection of the first trace L1 on the base substrate 101 and the orthographic projection of the blocking dam 102 on the base substrate 101 5 can be 30 ⁇ m-200 ⁇ m, such as 48.9 ⁇ m; the shortest distance d 6 between the orthographic projection of the second trace L 2 on the base substrate 101 and the orthographic projection of the blocking dam 102 on the base substrate 101 can be 10 ⁇ m- 100 ⁇ m, eg 29.4 ⁇ m.
  • the first groove H1 in the second direction Y is smaller than the width d 7 of the second groove H 2 in the second direction Y.
  • the width d 2 of the first groove H 1 may be 30 ⁇ m-50 ⁇ m
  • the width d 7 of the second groove H 2 may be greater than or equal to 70 ⁇ m.
  • a dummy line 117 (dummy) extending in the first direction X may be provided between the blocking dam 102 and the first wiring L1 inside the barrier dam 102 , and the dummy line 117
  • the boundary of the first groove H1 does not overlap with each other, that is, the floating line 117 may be disposed between the first groove H1 and the first wiring L1, or may be disposed inside the first groove H1.
  • the area between the barrier dam 102 and the first wiring L1 inside it is a blank area.
  • the wiring of the blank area and the surrounding wiring area can be structured. closer, thereby improving process stability and product stability.
  • At least one shielded wire 118 may be further included; the above-mentioned at least one shielded wire 118 may be located in At least one side of the plurality of first wirings L 1 in the second direction Y, and/or, are located on at least one side of the plurality of second wirings L 2 in the second direction Y.
  • At least one shielded wire 118 may be disposed around the touch signal wire 103 including the first trace L1; in some embodiments, as shown in FIG. 8, at least one shielded wire 118 may be disposed around the touch signal line 103 including the second trace L2; in some embodiments, the number of at least one shielding line 118 is multiple, then as shown in FIG.
  • the touch signal lines 103 of the first wiring L1 and the touch signal lines 103 including the second wiring L2 are disposed. In other embodiments, as shown in FIG.
  • the number of at least one shielded line 118 is two, and one of the shielded lines 118 is disposed on the first trace L1 in the second direction
  • another shielding wire 118 is disposed on the side of the second wiring L 2 away from the display area AA in the second direction Y.
  • the two sides of the plurality of first wirings L1 in the second direction Y and the two sides of the plurality of second wirings L2 in the second direction Y may also be arranged.
  • Shielded wires 118 are respectively provided on both sides.
  • DC signals such as the first power supply signal Vdd, the second power supply signal Vss, and the initialization signal Vinit may be loaded on the shielding wire 118 .
  • the shielding wire 118 and the touch signal wire 103 can be arranged in the same layer.
  • the sum of the shortest distance from each shielding line 118 to each touch signal line 103 and the line width of a single shielding line 118 may be greater than 30 ⁇ m, so as to better isolate the shielding Mutual interference of different signals (eg, Tx signal and Rx signal) on the touch signal line 103 on both sides of the line 118 .
  • the sum of the shortest distance from each shielding line 118 to each touch signal line 103 and the line width of a single shielding line 118 may not be equal.
  • the line width of a single shielded wire 118 may be approximately 9.2 ⁇ m.
  • the display substrate may further include: a crack detection line 119 (PCD) located on the side of the shielding line 118 away from the display area AA;
  • the border area BB where the first trace L1 is located spans the blocking dam 102, and is located between the blocking dam 102 and the display area AA in other border areas BB.
  • the crack detection line 119 has two loops, one on the left and right, and one end of the crack detection line 119 is connected to the panel testing (Cell Test) unit.
  • the data (Data) line corresponding to the green sub-pixel is connected to a high level (VGH) signal at the other end, and the VGH signal is provided by the flexible printed circuit board.
  • VGH high level
  • the data lines give a high voltage, which is input to the green sub-pixels of the corresponding column, so that the current flowing through the light-emitting device (such as OLED) of the green sub-pixel is relatively small, and the light-emitting device hardly emits light.
  • the detection voltage signal at this time is approximately 0V, and the 0V voltage is input to the green sub-pixels of the corresponding column, so that the current flowing through the light-emitting devices of the green sub-pixels in the column It is relatively large, causing the light-emitting device to emit light, and green bright lines appear under the black screen.
  • the crack detection line 119 can be set in the same layer as the touch signal line 103 .
  • the display substrate may further include: a ground wire 120 (GND) located between the shield wire 118 and the crack detection wire 119 , and the ground wire 120 is The orientation is substantially the same as that of the shielded wire 118 .
  • the ground wire 120 is set to ground and does not load any signal.
  • the grounding line 120 and the touch signal line 103 may be arranged in the same layer.
  • the above-mentioned display substrate provided by the present disclosure may be an organic electroluminescent display substrate (OLED), a quantum dot light-emitting display substrate (QLED), or a micro light emitting diode display substrate (Micro LED), and the like.
  • OLED organic electroluminescent display substrate
  • QLED quantum dot light-emitting display substrate
  • Micro LED micro light emitting diode display substrate
  • an embodiment of the present disclosure further provides a display device including the above-mentioned display substrate provided by an embodiment of the present disclosure.
  • the display device can be: mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, smart watch, fitness wristband, personal digital assistant, etc. any product or component with display function .
  • the display device can be: mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, smart watch, fitness wristband, personal digital assistant, etc. any product or component with display function .
  • other essential components of the display device eg, driver chips
  • the implementation of the display device may refer to the above-mentioned embodiment of the display panel, and the repetition will not be repeated.

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Abstract

本公开提供了显示基板及显示装置；包括衬底基板，该衬底基板包括：显示区，以及围绕显示区的边框区；至少一圈阻挡坝，在边框区内围绕显示区设置；触控金属层，位于阻挡坝所在层背离衬底基板的一侧；触控金属层包括多个触控电极、以及与多个触控电极电连接的多条触控信号线，其中，多个触控电极至少部分位于显示区，多条触控信号线位于边框区；多条触控信号线包括：沿第一方向平行设置的多条第一走线和多条第二走线；其中，多条第一走线在衬底基板上的正投影位于阻挡坝在衬底基板上的正投影与显示区之间，多条第二走线在衬底基板上的正投影位于阻挡坝在衬底基板上的正投影远离显示区的一侧。

Description

显示基板及显示装置
相关申请的交叉引用
本申请要求在2021年01月04日提交中国专利局、申请号为202110002159.7、申请名称为“显示基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
有机电致发光(OLED)显示装置是基于有机电致发光二极管的显示屏。其具备自发光、对比度高、厚度薄、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、构造及制程较简单等优异特性，受到了越来越多的关注，应用前景广阔。相关技术中，采用OLED显示模组内嵌触控结构的方式来整合触控功能，以实现OLED显示装置的显示功能和触控功能一体化。
发明内容
一方面，本公开实施例提供了一种显示基板，包括：
衬底基板，所述衬底基板包括：显示区，以及围绕所述显示区的边框区；
至少一圈阻挡坝，在所述边框区内围绕所述显示区设置；
触控金属层，位于所述阻挡坝所在层背离所述衬底基板的一侧；所述触控金属层包括多个触控电极、以及与所述多个触控电极电连接的多条触控信号线，其中，所述多个触控电极至少部分位于所述显示区，所述多条触控信号线位于所述边框区；所述多条触控信号线包括：沿第一方向平行设置的多条第一走线和多条第二走线；其中，所述多条第一走线在所述衬底基板上的正投影位于所述阻挡坝在所述衬底基板上的正投影与所述显示区之间，所述 多条第二走线在所述衬底基板上的正投影位于所述阻挡坝在所述衬底基板上的正投影远离所述显示区的一侧。
可选地，在本公开实施例提供的上述显示基板中，还包括：具有第一凹槽的有机绝缘层，所述第一凹槽位于所述阻挡坝在所述衬底基板上的正投影与所述多条第一走线在所述衬底基板上的正投影之间；
所述多条第一走线的数量N 1满足公式：N 1≤(D-d 1-d 2)/(d 3+d 4)，所述多条第二走线的数量N 2满足公式：N 2≥N-N 1；其中，
D为所述显示区的边界与所述阻挡坝之间的最短距离，d 1为所述第一凹槽与所述第一走线之间的最短距离，d 2为所述第一凹槽沿第二方向的宽度，d 3为所述第一走线L 1的线宽，d 4为相邻所述第一走线的间距，N为所述多条触控信号线的总数。
可选地，在本公开实施例提供的上述显示基板中，所述多条第一走线的数量小于或等于27，所述多条第二走线的数量小于或等于23。
可选地，在本公开实施例提供的上述显示基板中，所述多条触控信号线还包括：沿第二方向平行设置的多条第三走线和多条第四走线；其中，
所述第二方向与所述第一方向交叉设置；
所述第三走线与所述第一走线一一对应为一体结构，所述第四走线与所述第二走线一一对应为一体结构；
所述多条第三走线、以及所述多条第四走线在所述衬底基板上的正投影跨越所述阻挡坝在所述衬底基板上的正投影。
可选地，在本公开实施例提供的上述显示基板中，所述边框区包括位于所述阻挡坝远离所述显示区一侧的弯折区；
所述第二走线在所述衬底基板上的正投影位于所述阻挡坝在所述衬底基板上的正投影与所述弯折区之间；
所述第三走线在所述衬底基板上的正投影位于对应所述第一走线在所述衬底基板上的正投影与所述弯折区之间；
所述第四走线在所述衬底基板上的正投影位于对应所述第二走线在所述 衬底基板上的正投影与所述第一走线在所述衬底基板上的正投影之间。
可选地，在本公开实施例提供的上述显示基板中，所述边框区还包括位于所述弯折区远离所述阻挡坝一侧的焊盘区；
所述多条触控信号线还包括：沿所述第二方向平行设置的所述多条第五走线和多条第六走线；其中，
所述多条第五走线和多条第六走线并排设置于所述第二走线邻近所述衬底基板在所述第二方向上的中心轴的一侧；
所述第五走线、所述第三走线与所述第一走线一一对应为一体结构，所述第五走线通过所述第三走线与所述第一走线邻近所述衬底基板在所述第二方向上的中心轴的一端相连，且所述第五走线经过所述弯折区延伸至所述焊盘区；
所述第六走线、所述第四走线与所述第二走线一一对应为一体结构，所述第四走线与所述第二走线远离所述衬底基板在所述第二方向上的中心轴的另一端相连，所述第六走线与所述第二走线邻近所述衬底基板在所述第二方向上的中心轴的一端相连，且所述第六走线经过所述弯折区延伸至所述焊盘区。
可选地，在本公开实施例提供的上述显示基板中，所述第一走线远离所述衬底基板在所述第二方向上的中心轴的一端、以及所述第四走线远离所述第二走线的一端，位于所述多条第三走线所在所述边框区的相邻所述边框区内；
并且，所述第一走线远离所述衬底基板在所述第二方向上的中心轴的一端在所述衬底基板上的正投影、以及所述第四走线远离所述第二走线的一端在所述衬底基板上的正投影，位于所述阻挡坝在所述衬底基板上的正投影与所述显示区之间。
可选地，在本公开实施例提供的上述显示基板中，所述多条触控信号线还包括：沿所述第二方向平行设置的多条第七走线和多条第八走线；其中，
所述第七走线与所述第一走线一一对应为一体结构，所述第七走线与所述第一走线远离所述衬底基板在所述第二方向上的中心轴的一端相连；
所述第八走线与所述第四走线一一对应为一体结构，所述第八走线与所述第四走线远离所述第二走线的一端相连。
可选地，在本公开实施例提供的上述显示基板中，所述多条触控信号线划分为两组，两组所述触控信号线关于所述衬底基板在所述第二方向上的中心轴对称设置。
可选地，在本公开实施例提供的上述显示基板中，所述第一走线、所述第二走线的线宽小于所述第三走线、所述第四走线、所述第五走线、所述第六走线的线宽，且所述第一走线、所述第二走线的线宽大致等于所述第七走线、所述第八走线的线宽。
可选地，在本公开实施例提供的上述显示基板中，所述第一走线、所述第二走线的线宽为3μm-20μm，所述第三走线、所述第四走线、所述第五走线、所述第六走线的线宽为5-20μm，所述第七走线、所述第八走线的线宽为3μm-20μm。
可选地，在本公开实施例提供的上述显示基板中，各所述触控信号线的电阻值大致相同。
可选地，在本公开实施例提供的上述显示基板中，所述有机绝缘层还包括第二凹槽，其中，所述第二凹槽位于所述阻挡坝远离所述显示区的一侧；
所述第二走线在所述衬底基板上的正投影位于所述第二凹槽内。
可选地，在本公开实施例提供的上述显示基板中，所述第一走线在所述衬底基板上的正投影与所述阻挡坝在所述衬底基板上的正投影之间的最短距离，大于所述第二走线在所述衬底基板上的正投影与所述阻挡坝在所述衬底基板上的正投影之间的最短距离。
可选地，在本公开实施例提供的上述显示基板中，所述第一走线在所述衬底基板上的正投影与所述阻挡坝在所述衬底基板上的正投影之间的最短距离为30μm-200μm，所述第二走线在所述衬底基板上的正投影与所述阻挡坝在所述衬底基板上的正投影之间的最短距离为10μm-100μm。
可选地，在本公开实施例提供的上述显示基板中，在所述第二方向上， 所述第一凹槽的宽度小于所述第二凹槽的宽度。
可选地，在本公开实施例提供的上述显示基板中，还包括：至少一条屏蔽线；
所述至少一条屏蔽线位于所述多条第一走线在所述第二方向上的至少一侧，和/或，位于所述多条第二走线在所述第二方向上的至少一侧。
可选地，在本公开实施例提供的上述显示基板中，所述至少一条屏蔽线围绕包含所述第一走线的所述触控信号线设置，和/或，所述至少一条屏蔽线围绕包含所述第二走线的所述触控信号线设置。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述屏蔽线远离所述显示区一侧的裂纹检测线；
所述裂纹检测线在所述第一走线所在所述边框区跨越所述阻挡坝，且在其他所述边框区内位于所述阻挡坝与所述显示区之间。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述屏蔽线与所述裂纹检测线之间的接地线，且所述接地线的走向与所述屏蔽线的走向大致相同。
可选地，在本公开实施例提供的上述显示基板中，在远离所述衬底基板一侧的方向上，所述第一走线与所述衬底基板的距离，大于所述第二走线与所述衬底基板的距离。
另一方面，本公开实施例还提供了一种显示装置，包括上述显示基板。
附图说明
图1为本公开实施例提供的显示基板的一种平面结构示意图；
图2为图1中N区域的一种放大结构示意图；
图3为图1中N区域的又一种放大结构示意图；
图4为沿图3中I-II线的剖面结构示意图；
图5为沿图3中III-IV线的剖面结构示意图；
图6为图1中M区域的放大结构示意图；
图7为本公开实施例提供的显示基板的又一种平面结构示意图；
图8为本公开实施例提供的显示基板的又一种平面结构示意图；
图9为本公开实施例提供的显示基板的又一种平面结构示意图；
图10为本公开实施例提供的显示基板的又一种平面结构示意图；
图11为本公开实施例提供的显示基板的又一种平面结构示意图；
图12为本公开实施例提供的显示基板的又一种平面结构示意图；
图13为本公开实施例提供的显示基板的又一种平面结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
目前市场对显示屏(例如手机)的薄型化提出了越来越高的要求，柔性多层结构(Flexible Multi-Layer On Cell，FMLOC)技术应运而生。FMLOC工艺 是在显示模组的封装层上制作金属网格电极层来实现触控功能，因此无需外挂触控结构(TSP)，从而可以减小屏幕厚度。
FMLOC工艺多采用两层金属制作，一层为金属网格层(Metal Mesh，MM)，另一层为桥接金属层(Bridge Metal，BM)。金属网格位于显示区，并且按照横纵方向金属网格可以分为触控驱动(Tx)金属网格和触控感应(Rx)金属网格，其中，Rx金属网格和Tx金属网格中的一个相互连接，另一个通过桥接金属层连接。另外，FMLOC产品中还设置了位于边框区内的阻挡坝和多条触控信号线(trace)；其中，阻挡坝环绕显示区设置，以阻挡外部水汽或氧气进入显示区；多条触控信号线均设置在阻挡坝与显示区之间，并与Tx金属网格、Rx金属网格分别对应电连接。然而，随着市场发展，对产品的边框尤其是下边框提出了更严格的要求，上述将所有走线均放置在阻挡坝与显示区之间的设计，极大地限制了边框的缩窄。
针对相关技术中存在的上述问题，本公开实施例提供了一种显示基板，如图1和图2所示，包括：
衬底基板101，该衬底基板101包括：显示区AA，以及围绕显示区AA的边框区BB；
至少一圈阻挡坝102，在边框区BB内围绕显示区AA设置；
触控金属层MM，位于阻挡坝102所在层背离衬底基板101的一侧；触控金属层MM包括多个触控电极Tx/Rx、以及与多个触控电极Tx/Rx电连接的多条触控信号线103，其中，多个触控电极Tx/Rx至少部分位于显示区AA，多条触控信号线103位于边框区BB；多条触控信号线103可以包括：沿第一方向X平行设置的多条第一走线L 1和多条第二走线L 2；其中，多条第一走线L 1在衬底基板101上的正投影位于阻挡坝102在衬底基板101上的正投影与显示区AA之间，多条第二走线L 2在衬底基板101上的正投影位于阻挡坝102在衬底基板101上的正投影远离显示区AA的一侧。
在本公开实施例提供的上述显示基板中，通过将多条第一走线L 1放置在阻挡坝102内侧的边框区BB，并将与第一走线L 1平行设置的多条第二走线 L 2设置在阻挡坝102外侧的边框区BB，从而可以将阻挡坝102外侧的空间合理利用起来，进而有效减小了阻挡坝102以内边框区BB的宽度，利于实现更窄边框设计的产品需求。
需要说明的是，图1是以下侧的边框区BB所含平行设置的多条第一走线L 1、多条第二走线L 2分居阻挡坝102内外两侧为例进行说明。在具体实施时，在左侧的边框区BB、右侧的边框区BB和/或上侧的边框区BB内，为减小阻挡坝102与显示区AA之间的布线空间，也可以考虑将触控信号线103一分为二后，分别设置在阻挡坝102的内外两侧。
可选地，在本公开实施例提供的上述显示基板中，如图1和图2所示，还可以包括具有第一凹槽H 1的有机绝缘层104，第一凹槽H 1用于防止水氧入侵显示区AA，具体可以位于阻挡坝102在衬底基板101上的正投影与第一走线L 1在衬底基板101上的正投影之间，且与阻挡坝102接触、且与第一走线L 1之间的最短距离为d 1。在一些实施例中，显示区AA到凹槽H 1之间可以根据实际需要设置为斜面，这里，第一凹槽H 1的最短距离d 1为在平行于衬底基板的平面上的最短距离，也就是说，第一凹槽H 1的最短距离d 1不包括显示区AA到凹槽H 1之间的斜面。换言之，当显示区AA到凹槽H 1之间为斜面时，至少部分多条第一走线可以设置在斜面上。在一些实施例中，多条第一走线L 1的数量N 1满足公式：N 1≤(D-d 1-d 2)/(d 3+d 4)；其中，D代表显示区AA的边界(即显示区AA与第一凹槽H 1所在边框区BB的交界线)与阻挡坝102之间的最短距离，d 2代表第一凹槽H 1沿第二方向Y的宽度，d 3代表第一走线L 1的线宽，d 4代表第一走线L 1的间距。多条第二走线L 2的数量N 2满足公式：N 2≥N-N 1；其中，N为与Tx金属网格、以及Rx金属网格电连接的全部触控信号线103的总数。示例性地，多条第一走线L 1的数量小于或等于27，多条第二走线L 2的数量小于或等于23。可选地，N 1＝(D-d 1-d 2)/(d 3+d 4)且N 2＝N-N 1，在这种情况下，显示面板的边框区BB是最窄的，且不会干扰显示区AA正常显示。
可选地，在本公开实施例提供的上述显示基板中，如图2所示，多条触 控信号线103还可以包括：沿第二方向Y平行设置的多条第三走线L 3和多条第四走线L 4；其中，第二方向Y与第一方向X交叉设置；第三走线L 3与第一走线L 1一一对应为一体结构，第四走线L 4与第二走线L 2一一对应为一体结构；多条第三走线L 3、以及多条第四走线L 4在衬底基板101上的正投影跨越阻挡坝102在衬底基板101上的正投影。
通过设置跨越阻挡坝102的多条第三走线L 3和多条第四走线L 4，一方面可以将阻挡坝102内侧的第一走线L 1引出至阻挡坝102外侧，利于实现触控信号线103与外部驱动电路连接。在一些实施例中，外部驱动电路可以为柔性印刷电路板(Flexible Print Circuit Board，FPC)的电连接。另一方面，可以将阻挡坝102外侧的第二走线L 2引出至阻挡坝102内侧，利于实现触控信号线103与显示区AA内Tx或Rx金属网格的电连接；并且，第二走线L 2的设置方式，可以合理利用阻挡坝102外侧的空间，进而可缩小阻挡坝102内侧边框区BB的宽度，实现了边框区BB的进一步窄化设计。
可选地，在本公开实施例提供的上述显示基板中，为了实现窄边框的技术效果，如图2所示，还可以在阻挡坝102远离显示区AA的一侧设置弯折区BA。在这种情况下，第二走线L 2在衬底基板101上的正投影可以位于阻挡坝102在衬底基板101上的正投影与弯折区BA之间；第三走线L 3在衬底基板101上的正投影可以位于对应第一走线L 1在衬底基板101上的正投影与弯折区BA之间；第四走线L 4在衬底基板101上的正投影可以位于对应第二走线L 2在衬底基板101上的正投影与第一走线L 1在衬底基板101上的正投影之间；换言之，第三走线L 3自一体化设计的第一走线L 1处向弯折区BA延伸，第四走线L 4自一体化设计的第二走线L 2处向阻挡坝102内侧延伸。
可选地，在本公开实施例提供的上述显示基板中，如图2所示，边框区BB还可以包括位于弯折区BA远离阻挡坝102一侧的焊盘区PA；多条触控信号线103还可以包括：沿第二方向Y平行设置的多条第五走线L 5和多条第六走线L 6；其中，多条第五走线L 5和多条第六走线L 6并排设置于第二走线L 2邻近衬底基板101在第二方向Y上的中心轴的一侧；第五走线L 5、第三走 线L 3与第一走线L 1一一对应为一体结构，第五走线L 5通过第三走线L 3与第一走线L 1邻近衬底基板101在第二方向Y上的中心轴的一端相连，且第五走线L 5经过弯折区BA延伸至焊盘区PA；第六走线L 6、第四走线L 4与第二走线L 2一一对应为一体结构，第四走线L 4与第二走线L 2远离衬底基板101在第二方向Y上的中心轴的另一端相连，第六走线L 6与第二走线L 2邻近衬底基板在第二方向Y上的中心轴的一端相连，且第六走线L 6经过弯折区BA延伸至焊盘区PA。
在一些实施例中，焊盘区PA具有多个接触垫(或称焊盘、Pad)，每个接触垫被配置为电连接一条第五走线L 5或一条第六走线L 6。接触垫可以是暴露在焊盘区PA表面的，即不被任何层覆盖，这样便于电连接到柔性印刷电路板。柔性印刷电路板与外部控制器电连接，被配置为将来自外部控制器的信号或电力传输至第五走线L 5和第六走线L 6。
在一些实施例中，在边框区BB内布线的公共(Com)信号线、电源(VDD/VSS)线、接地(GND)线等的布线方式也可以采用上述触控信号线103的布线方式。在一些实施例中，如图3至图5所示，触控信号线103可以包括：与金属网格层MM同层设置的第一部分103a，以及与桥接金属层BM同层设置并与第一部分103a电连接的第二部分103b。
通过将触控信号线103设置为包括第一部分103a和第二部分103b的双层走线，可以使得在其中一层走线局部断裂后，仍可通过另一层走线对金属网格层MM加载触控信号，从而有效解决了单层走线断裂容易导致触控失效的问题；另外，相较于单层走线的设计，双层走线还可以减小触控信号线103的电阻值。在具体实施时，第一部分103a与第二部分103b之间通过贯穿无机绝缘层105的过孔电连接。
在一些实施例中，如图4所示，为使得弯折区BA的弯折应力均一，触控信号线103所含第五走线L 5和第六走线L 6可以在弯折区BA由金属网格层MM、桥接金属层BM换层至第二源漏金属层106(SD2)进行布线，并在焊盘区PA重新返回至金属网格层MM及桥接金属层BM进行布线。
需要说明的是，在本公开中，不仅可以采用上述金属网格技术的互容方式实现触控功能，还可以采用自容方式实现触控功能。并且在采用自容方式时，显示基板可以包括与多条触控走线异层设置的多个自电容电极，无机绝缘层105位于多条触控走线所在层与多个自电容电极所在层之间，且每条触控走线通过贯穿无机绝缘层105的过孔与一个自电容电极电连接。
另外，通常可将显示基板的显示侧默认为正面，与显示侧相反的一侧为背面。弯曲区BA的弯曲使得位于弯曲区BA的远离显示区DA一侧的焊盘区PA均处于显示基板的背面，这样可以提高空间利用率，降低边框区BB所占用的面积。
可选地，在本公开实施例提供的上述显示基板中，如图2所示，第一走线L 1远离衬底基板101在第二方向Y上的中心轴的一端、以及第四走线L 4远离第二走线L 2的一端，位于多条第三走线L 3所在边框区的相邻边框区内；并且，第一走线L 1远离衬底基板101在第二方向Y上的中心轴的一端在衬底基板101上的正投影、以及第四走线L 4远离第二走线L 2的一端在衬底基板101上的正投影，位于阻挡坝102在衬底基板101上的正投影与显示区AA之间。
由以上描述可知，在本公开中包括第一走线L 1、第三走线L 3和第五走线L 5的触控信号线103，先自右侧的边框区BB折向下侧的边框区BB，再跨越阻挡坝102，后经弯折区BA延伸至焊盘区PA与柔性印刷电路板电连接；并且包括第二走线L 2、第四走线L 4和第六走线L 6的触控信号线103，先自右侧的边框区BB跨越阻挡坝102，再折向下侧的边框区BB，后经弯折区BA延伸至焊盘区PA与柔性印刷电路板电连接。这样设置，一方面保证了各触控信号线103之间互不交叠，避免短路不良；另一方面保证了各触控信号线103的绕线较短，避免信号延迟(RC delay)。并且，第二走线L 2的设置方式，可以合理利用阻挡坝102外侧的空间，进而可缩小阻挡坝102内侧边框区BB的宽度，实现了边框区BB的进一步窄化设计。
可选地，在本公开实施例提供的上述显示基板中，如图2所示，多条触控信号线103还可以包括：沿第二方向Y平行设置的多条第七走线L 7和多条第 八走线L 8；其中，第七走线L 7与第一走线L 1一一对应为一体结构，第七走线L 7与第一走线L 1远离衬底基板101在第二方向Y上的中心轴的一端相连；第八走线L 8与第四走线L 4一一对应为一体结构，第八走线L 8与第四走线L 4远离第二走线L 2的一端相连。
由于第一走线L 1远离衬底基板101在第二方向Y上的中心轴的一端，位于多条第三走线L 3所在边框区的相邻边框区内，因此，第七走线L 7可以在该相邻边框区内沿第二方向Y上延伸。另外，由于第四走线L 4远离第二走线L 2的一端，位于多条第三走线L 3所在边框区的相邻边框区内，因此，第八走线L 8也可以在该相邻边框区内沿第二方向Y上延伸。这样设置最大限度地减小了触控信号线103的布线长度，从而使得触控信号线103的电阻值较小，避免了触控信号线103的上信号延迟。
可选地，在本公开实施例提供的上述显示基板中，如图1所示，多条触控信号线103可以划分为两组，两组触控信号线103关于衬底基板101在第二方向Y上的中心轴EF对称设置。具体而言，触控信号线103在阻挡坝内外两侧布线的方式在衬底基板101在第二方向Y上的中心轴EF两侧相同，但不限定两组触控信号线的具体数量，也就是说，两组触控信号线的数量可以相同，也可以不同。这样设置，便于均衡布线，提高工艺稳定性，且实现了边框区的进一步窄化设计。
可选地，在本公开实施例提供的上述显示基板中，为了保证各触控信号线103的电阻值大致相同，可以设置第一走线L 1、第二走线L 2的线宽小于第三走线L 3、第四走线L 4、第五走线L 5、第六走线L 6的线宽，且第一走线L 1、第二走线L 2的线宽大致等于第七走线L 7、第八走线L 8的线宽。
需要说明的是，在具体实施时，由于工艺条件的限制或测量等其他因素的影响，上述“大致”可能会完全等同，也可能会有一些偏差，因此上述特征之间“大致”的关系只要满足误差(例如上下10％的浮动)允许，均属于本公开的保护范围。
可选地，在本公开实施例提供的上述显示基板中，第一走线L 1、第二走 线L 2的线宽可以为3μm-20μm，例如7.3μm；第三走线L 3、第四走线L 4、第五走线L 5、第六走线L 6的线宽可以为5μm-20μm，例如9.2μm；第七走线L 7、第八走线L 8的线宽可以为3μm-20μm，例如7.2μm。
可选地，在本公开实施例提供的上述显示基板中，如图3和图5所示，还可以包括：有机绝缘层104，该有机绝缘层104中设置有第一凹槽H 1和第二凹槽H 2，其中，第一凹槽H 1位于阻挡坝102与显示区AA之间，第二凹槽H 2位于阻挡坝102远离显示区AA的一侧；第一走线L 1在衬底基板101上的正投影位于第一凹槽H 1与显示区AA之间，第二走线L 2在衬底基板101上的正投影位于第二凹槽H 2内。
在一些实施例中，第一凹槽H 1用于隔断绝缘层104，以防止水氧入侵至显示区AA；第二凹槽H 2用于释放弯折应力。通过将阻挡坝102内侧的第一走线L 1设置在第一凹槽H 1与显示区AA之间，避免了阻挡坝102内侧的第一走线L 1与第一凹槽H 1交叠，这样可以避免第一凹槽H 1对现有走线方式的影响。因为第二凹槽H 2处无有机封装层109(IJP)，且触控信号线103下方的有机绝缘层104的结构简单，基本为大面积挖除设计，使得膜层段差很小，即膜层平坦性较好，所以通过将阻挡坝102外侧的第二走线L 2设置在第二凹槽H 2内，对触控信号线103设计及工艺实现均有较大优势。
可选地，在本公开实施例提供的上述显示基板中，在远离所述衬底基板一侧的方向上，第一走线L 1与衬底基板101的距离，大于第二走线L 2与衬底基板101的距离。具体地，如图5所示，阻挡坝102内侧的第一走线L 1下的膜层较多，自下而上依次为衬底基板101、第一源漏金属层107(SD1)、第二平坦层1042(PLN2)、像素界定层1043(PDL)、第一无机封装层108、有机封装层109、第二无机封装层110和第二刻蚀阻挡层111(BFL2)；而阻挡坝102外侧的第二走线L 1下的膜层较少，自下而上依次为衬底基板101、第一源漏金属层107、第一无机封装层108、第二无机封装层110和第二刻蚀阻挡层111；在一些实施例中，保证阻挡坝102内外两侧的第一走线L 1和第二走线L 2的线宽大致相同。可选地，第一无机封装层108、有机封装层109、第二无 机封装层110构成薄膜封装层(EPL)。
如图4和图5所示，在一些实施例中，有机绝缘层104可以包括第一平坦层1041(PLN1)、第二平坦层1042、像素界定层1043；阻挡坝102可以包括环绕显示区AA的第一阻挡坝1021、以及环绕第一阻挡坝1021的第二阻挡坝1022；其中，第一阻挡坝1021的叠层图案位于第二平坦层1042和像素界定层1043，第二阻挡坝1022的叠层图案位于第一平坦层1041、第二平坦层1042和像素界定层1043。由于第一阻挡坝1021比第二阻挡坝1022少了位于第一平坦层1041的膜层图案，所以第一阻挡坝1021相对于衬底基板101的高度比第二阻挡坝1022相对于衬底基板101的高度低，这样使外部水汽和氧气进入显示区AA的路径变长，增加进入显示区AA的难度，进一步提高阻挡坝102的阻挡能力。在一些实施例中，第一阻挡坝1021的宽度、第二阻挡坝1022的宽度、以及第一阻挡坝1021与第二阻挡坝1022的间距可以大致相同，例如均为30μm。第一阻挡坝1021与第二阻挡坝1022的剖面形状可以为图4所示的矩形，也可以为图5所示的梯形，此时第一阻挡坝1021和第二阻挡坝1022至少具有靠近显示区AA一侧的侧边为斜面，在此不做限定。
在一些实施例中，为增大跨越阻挡坝102的第三走线L 3和第四走线L 4的粘附力，可以设置第三走线L 3和第四走线L 4在第一阻挡坝1021与第二阻挡坝1022间隙处的线宽变窄。
需要说明的是，在本公开中，“阻挡坝102内侧”具体指第一阻挡坝1021靠近显示区AA的一侧，“阻挡坝102外侧”具体指第二阻挡坝1022远离显示区AA的一侧。
另外，如图4所示，显示基板还可以包括：层间介电层112(ILD)、栅绝缘层113(GI)、第一刻蚀阻挡层114(BFL1)、缓冲层115(BRL)和隔垫物层116(PS)。应当理解的是，对于显示基板其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
可选地，在本公开实施例提供的上述显示基板中，如图3所示，第一走 线L 1在衬底基板101上的正投影与阻挡坝102在衬底基板101上的正投影之间的最短距离d 5，大于第二走线L 2在衬底基板101上的正投影与阻挡坝102在衬底基板101上的正投影之间的最短距离d 6。这样设置，可以使得阻挡坝102内侧的第一走线L 1避开第一凹槽H 1，使得阻挡坝102内侧的第一走线L 1与第一凹槽H 1互不交叠。
可选地，在本公开实施例提供的上述显示基板中，第一走线L 1在衬底基板101上的正投影与阻挡坝102在衬底基板101上的正投影之间的最短距离d 5可以为30μm-200μm，例如48.9μm；第二走线L 2在衬底基板101上的正投影与阻挡坝102在衬底基板101上的正投影之间的最短距离d 6可以为10μm-100μm，例如29.4μm。
可选地，在本公开实施例提供的上述显示基板中，为了实现窄边框的技术效果，如图3所示，在第二方向Y上，第一凹槽H 1在第二方向Y上的宽度d 2小于第二凹槽H 2在第二方向Y上的宽度d 7。示例性地，第一凹槽H 1的宽度d 2可以为30μ0-50μm，第二凹槽H 2的宽度d 7可以大于或等于70μm。在一些实施例中，如图6所示，可以在阻挡坝102与其内侧的第一走线L 1之间设置沿第一方向X上延伸的浮空线117(dummy)，且浮空线117与第一凹槽H 1的边界互不交叠，即浮空线117可以设置在第一凹槽H 1与第一走线L 1之间，也可以设置在第一凹槽H 1内部。
设置浮空线117之前，阻挡坝102与其内侧的第一走线L 1之间的区域为空白区域，通过在该空白区域设置浮空线117，可以使得该空白区域的布线与周围布线区结构更接近，从而可提升工艺稳定性、以及产品的稳定性。
可选地，在本公开实施例提供的上述显示基板中，如图7至图11所示，为了屏蔽干扰，还可以包括：至少一条屏蔽线118(Guard)；上述至少一条屏蔽线118可以位于多条第一走线L 1在第二方向Y上的至少一侧，和/或，位于多条第二走线L 2在第二方向Y上的至少一侧。
在一些实施例中，如图7所示，至少一条屏蔽线118可以围绕包含第一走线L 1的触控信号线103设置；在一些实施例中，如图8所示，至少一条屏 蔽线118可以围绕包含第二走线L 2的触控信号线103设置；在一些实施例中，至少一条屏蔽线118的数量为多条，则如图9所示，多条屏蔽线118可以围绕包含第一走线L 1的触控信号线103、以及包含第二走线L 2的触控信号线103设置。在另一些实施例中，如图10所示，至少一组触控信号线中，至少一条屏蔽线118的数量为两条，其中一条屏蔽线118设置在第一走线L 1在第二方向Y上邻近显示区AA的一侧，另一条屏蔽线118设置在第二走线L 2在第二方向Y上远离显示区AA的一侧。在另一些实施例中，如图11所示，还可以在多条第一走线L 1在第二方向Y上的两侧，以及多条第二走线L 2在第二方向Y上的两侧分别设置屏蔽线118。
在具体实施时，为了实现较好的屏蔽效果，屏蔽线118上可以加载第一电源信号Vdd、第二电源信号Vss、初始化信号Vinit等直流信号。并且为了减少膜层数量，可以设置屏蔽线118与触控信号线103同层。
可选地，在本公开实施例提供的上述显示基板中，各屏蔽线118到各触控信号线103的最短距离与单条屏蔽线118的线宽之和可以大于30μm，以更好地隔离屏蔽线118两侧触控信号线103上不同信号(例如Tx信号与Rx信号)的相互干扰。在一些实施例中，屏蔽线118两侧触控信号线103上信号相同的情况下，也可以不对各屏蔽线118到各触控信号线103的最短距离与单条屏蔽线118的线宽之和进行特殊限定。在一些实施例中，单条屏蔽线118的线宽可以约为9.2μm。
可选地，在本公开实施例提供的上述显示基板中，如图12所示，还可以包括：位于屏蔽线118远离显示区AA一侧的裂纹检测线119(PCD)；裂纹检测线119在第一走线L 1所在边框区BB跨越阻挡坝102，且在其他边框区BB内位于阻挡坝102与显示区AA之间。
整个PCD绕线设置在背板端和触控面板端上，在一些实施例中，裂纹检测线119有两个回路，左右各一个，裂纹检测线119的一端连接面板检测(Cell Test)单元中的绿色子像素对应的数据(Data)线，另一端接入高电平(VGH)信号，该VGH信号由柔性印刷电路板提供。在没有裂纹的情况下，数据线给 的是高电压，被输入到相应列的绿色子像素，使得流过该绿色子像素的发光器件(例如OLED)的电流比较小，该发光器件几乎不发光，呈现黑态；在有裂纹的情况下，可以认为此时的检测电压信号近似为0V，该0V电压被输入到相应列的绿色子像素，使得流过该列绿色子像素的发光器件的电流比较大，导致发光器件发光，在黑画面下出现绿色亮线。另外，为了减少膜层数量，可以设置裂纹检测线119与触控信号线103同层。
可选地，在本公开实施例提供的上述显示基板中，如图13所示，还可以包括：位于屏蔽线118与裂纹检测线119之间的接地线120(GND)，且接地线120的走向与屏蔽线118的走向大致相同。在具体实施时，接地线120接地设置，不加载任何信号。并且，为了减少膜层数量，可以设置接地线120与触控信号线103同层。
在一些实施例中，本公开提供的上述显示基板可以为有机电致发光显示基板(OLED)、量子点发光显示基板(QLED)、或微发光二极管显示基板(Micro LED)等。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示基板。
在一些实施例中，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。对于显示装置的其它必不可少的组成部分(例如驱动芯片)均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。另外，由于该显示装置解决问题的原理与上述显示面板解决问题的原理相似，因此，该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (23)

  1. 一种显示基板，其中，包括：
    衬底基板，所述衬底基板包括：显示区，以及围绕所述显示区的边框区；
    至少一圈阻挡坝，在所述边框区内围绕所述显示区设置；
    触控金属层，位于所述阻挡坝所在层背离所述衬底基板的一侧；所述触控金属层包括多个触控电极、以及与所述多个触控电极电连接的多条触控信号线，其中，所述多个触控电极至少部分位于所述显示区，所述多条触控信号线位于所述边框区；所述多条触控信号线包括：沿第一方向平行设置的多条第一走线和多条第二走线；其中，所述多条第一走线在所述衬底基板上的正投影位于所述阻挡坝在所述衬底基板上的正投影与所述显示区之间，所述多条第二走线在所述衬底基板上的正投影位于所述阻挡坝在所述衬底基板上的正投影远离所述显示区的一侧。
  2. 如权利要求1所述的显示基板，其中，还包括：具有第一凹槽的有机绝缘层，所述第一凹槽位于所述阻挡坝在所述衬底基板上的正投影与所述多条第一走线在所述衬底基板上的正投影之间；
    所述多条第一走线的数量N 1满足公式：N 1≤(D-d 1-d 2)/(d 3+d 4)，所述多条第二走线的数量N 2满足公式：N 2≥N-N 1；其中，
    D为所述显示区的边界与所述阻挡坝之间的最短距离，d 1为所述第一凹槽与所述第一走线之间的最短距离，d 2为所述第一凹槽沿第二方向的宽度，d 3为所述第一走线L 1的线宽，d 4为相邻所述第一走线的间距，N为所述多条触控信号线的总数。
  3. 如权利要求2所述的显示基板，其中，所述多条第一走线的数量小于或等于27，所述多条第二走线的数量小于或等于23。
  4. 如权利要求1所述的显示基板，其中，所述多条触控信号线还包括：沿第二方向平行设置的多条第三走线和多条第四走线；其中，
    所述第二方向与所述第一方向交叉设置；
    所述第三走线与所述第一走线一一对应为一体结构，所述第四走线与所述第二走线一一对应为一体结构；
    所述多条第三走线、以及所述多条第四走线在所述衬底基板上的正投影跨越所述阻挡坝在所述衬底基板上的正投影。
  5. 如权利要求4所述的显示基板，其中，所述边框区包括位于所述阻挡坝远离所述显示区一侧的弯折区；
    所述第二走线在所述衬底基板上的正投影位于所述阻挡坝在所述衬底基板上的正投影与所述弯折区之间；
    所述第三走线在所述衬底基板上的正投影位于对应所述第一走线在所述衬底基板上的正投影与所述弯折区之间；
    所述第四走线在所述衬底基板上的正投影位于对应所述第二走线在所述衬底基板上的正投影与所述第一走线在所述衬底基板上的正投影之间。
  6. 如权利要求5所述的显示基板，其中，所述边框区还包括位于所述弯折区远离所述阻挡坝一侧的焊盘区；
    所述多条触控信号线还包括：沿所述第二方向平行设置的所述多条第五走线和多条第六走线；其中，
    所述多条第五走线和多条第六走线并排设置于所述第二走线邻近所述衬底基板在所述第二方向上的中心轴的一侧；
    所述第五走线、所述第三走线与所述第一走线一一对应为一体结构，所述第五走线通过所述第三走线与所述第一走线邻近所述衬底基板在所述第二方向上的中心轴的一端相连，且所述第五走线经过所述弯折区延伸至所述焊盘区；
    所述第六走线、所述第四走线与所述第二走线一一对应为一体结构，所述第四走线与所述第二走线远离所述衬底基板在所述第二方向上的中心轴的另一端相连，所述第六走线与所述第二走线邻近所述衬底基板在所述第二方向上的中心轴的一端相连，且所述第六走线经过所述弯折区延伸至所述焊盘区。
  7. 如权利要求6所述的显示基板，其中，所述第一走线远离所述衬底基板在所述第二方向上的中心轴的一端、以及所述第四走线远离所述第二走线的一端，位于所述多条第三走线所在所述边框区的相邻所述边框区内；
    并且，所述第一走线远离所述衬底基板在所述第二方向上的中心轴的一端在所述衬底基板上的正投影、以及所述第四走线远离所述第二走线的一端在所述衬底基板上的正投影，位于所述阻挡坝在所述衬底基板上的正投影与所述显示区之间。
  8. 如权利要求7所述的显示基板，其中，所述多条触控信号线还包括：沿所述第二方向平行设置的多条第七走线和多条第八走线；其中，
    所述第七走线与所述第一走线一一对应为一体结构，所述第七走线与所述第一走线远离所述衬底基板在所述第二方向上的中心轴的一端相连；
    所述第八走线与所述第四走线一一对应为一体结构，所述第八走线与所述第四走线远离所述第二走线的一端相连。
  9. 如权利要求1所述的显示基板，其中，所述多条触控信号线划分为两组，两组所述触控信号线关于所述衬底基板在所述第二方向上的中心轴对称设置。
  10. 如权利要求8所述的显示基板，其中，所述第一走线、所述第二走线的线宽小于所述第三走线、所述第四走线、所述第五走线、所述第六走线的线宽，且所述第一走线、所述第二走线的线宽大致等于所述第七走线、所述第八走线的线宽。
  11. 如权利要求10所述的显示基板，其中，所述第一走线、所述第二走线的线宽为3μm-20μm，所述第三走线、所述第四走线、所述第五走线、所述第六走线的线宽为5μm-20μm，所述第七走线、所述第八走线的线宽为3μm-20μm。
  12. 如权利要求1所述的显示基板，其中，各所述触控信号线的电阻值大致相同。
  13. 如权利要求2所述的显示基板，其中，所述有机绝缘层还包括第二 凹槽，所述第二凹槽位于所述阻挡坝远离所述显示区的一侧；
    所述第二走线在所述衬底基板上的正投影位于所述第二凹槽内。
  14. 如权利要求1所述的显示基板，其中，所述第一走线在所述衬底基板上的正投影与所述阻挡坝在所述衬底基板上的正投影之间的最短距离，大于所述第二走线在所述衬底基板上的正投影与所述阻挡坝在所述衬底基板上的正投影之间的最短距离。
  15. 如权利要求14所述的显示基板，其中，所述第一走线在所述衬底基板上的正投影与所述阻挡坝在所述衬底基板上的正投影之间的最短距离为30μm-200μm，所述第二走线在所述衬底基板上的正投影与所述阻挡坝在所述衬底基板上的正投影之间的最短距离为10μm-100μm。
  16. 如权利要求13所述的显示基板，其中，在所述第二方向上，所述第一凹槽的宽度小于所述第二凹槽的宽度。
  17. 如权利要求1所述的显示基板，其中，还包括：至少一条屏蔽线；
    所述至少一条屏蔽线位于所述多条第一走线在所述第二方向上的至少一侧，和/或，位于所述多条第二走线在所述第二方向上的至少一侧。
  18. 如权利要求17所述的显示基板，其中，所述至少一条屏蔽线围绕包含所述第一走线的所述触控信号线设置，和/或，所述至少一条屏蔽线围绕包含所述第二走线的所述触控信号线设置。
  19. 如权利要求18所述的显示基板，其中，所述至少一条屏蔽线的数量为两条，其中一条所述屏蔽线设置在所述第一走线在所述第二方向上邻近所述显示区的一侧，另一条所述屏蔽线设置在所述第二走线在所述第二方向上远离所述显示区的一侧。
  20. 如权利要求19所述的显示基板，其中，还包括：位于所述屏蔽线远离所述显示区一侧的裂纹检测线；
    所述裂纹检测线在所述第一走线所在所述边框区跨越所述阻挡坝，且在其他所述边框区内位于所述阻挡坝与所述显示区之间。
  21. 如权利要求20所述的显示基板，其中，还包括：位于所述屏蔽线与 所述裂纹检测线之间的接地线，且所述接地线的走向与所述屏蔽线的走向大致相同。
  22. 如权利要求1-21任一项所述的显示基板，其中，在远离所述衬底基板一侧的方向上，所述第一走线与所述衬底基板的距离，大于所述第二走线与所述衬底基板的距离。
  23. 一种显示装置，其中，包括如权利要求1-22任一项所述的显示基板。
PCT/CN2021/126056 2021-01-04 2021-10-25 显示基板及显示装置 Ceased WO2022142633A1 (zh)

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