WO2022202912A1 - 金属板材、積層体、絶縁回路基板、および、金属板材の製造方法 - Google Patents
金属板材、積層体、絶縁回路基板、および、金属板材の製造方法 Download PDFInfo
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- WO2022202912A1 WO2022202912A1 PCT/JP2022/013602 JP2022013602W WO2022202912A1 WO 2022202912 A1 WO2022202912 A1 WO 2022202912A1 JP 2022013602 W JP2022013602 W JP 2022013602W WO 2022202912 A1 WO2022202912 A1 WO 2022202912A1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
- B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/20—Layered products comprising a layer of metal comprising aluminium or copper
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B3/00—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form
- B32B3/02—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by features of form at particular places, e.g. in edge regions
- B32B3/08—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by features of form at particular places, e.g. in edge regions characterised by added members at particular parts
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B3/00—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form
- B32B3/26—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer
- B32B3/30—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer characterised by a layer formed with recesses or projections, e.g. hollows, grooves, protuberances, ribs
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/10—Electroplating with more than one layer of the same or of different metals
- C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
- C25D5/14—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium two or more layers being of nickel or chromium, e.g. duplex or triplex layers
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/18—Electroplating using modulated, pulsed or reversing current
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/60—Electroplating characterised by the structure or texture of the layers
- C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/60—Electroplating characterised by the structure or texture of the layers
- C25D5/615—Microstructure of the layers, e.g. mixed structure
- C25D5/617—Crystalline layers
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/06—Wires; Strips; Foils
- C25D7/0614—Strips or foils
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2250/00—Layers arrangement
- B32B2250/02—2 layers
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2255/00—Coating on the layer surface
- B32B2255/06—Coating on the layer surface on metal layer
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2255/00—Coating on the layer surface
- B32B2255/20—Inorganic coating
- B32B2255/205—Metallic coating
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2307/00—Properties of the layers or laminate
- B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
- B32B2307/202—Conductive
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2307/00—Properties of the layers or laminate
- B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
- B32B2307/206—Insulating
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2307/00—Properties of the layers or laminate
- B32B2307/50—Properties of the layers or laminate having particular mechanical properties
- B32B2307/538—Roughness
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2307/00—Properties of the layers or laminate
- B32B2307/70—Other properties
- B32B2307/732—Dimensional properties
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2457/00—Electrical equipment
- B32B2457/08—PCBs, i.e. printed circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/69—Insulating materials thereof
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
Definitions
- the present invention relates to a metal plate material, a laminate having a structure in which a resin member and a metal plate material are laminated, an insulated circuit board, and a method for manufacturing the metal plate material.
- a power module, an LED module, and a thermoelectric module have a structure in which a power semiconductor element, an LED element, and a thermoelectric element are joined to an insulating circuit board in which a circuit layer made of a conductive material is formed on one side of an insulating layer.
- the insulating layer one using ceramics and one using insulating resin have been proposed.
- Patent Document 1 proposes a metal base circuit board.
- Patent Document 2 proposes a multilayer wiring board.
- an insulating resin layer is formed on the metal board, and a circuit layer having a circuit pattern is formed on the insulating resin layer.
- the insulating resin layer is made of epoxy resin, which is a thermosetting resin
- the circuit layer is made of copper foil.
- a semiconductor element is bonded onto the circuit layer, and a heat sink is provided on the opposite side of the metal substrate to the insulating resin layer, so that heat generated by the semiconductor element is transmitted to the heat sink side.
- the structure is designed to dissipate heat by
- the metal foil adhered to the resin film is subjected to an etching treatment so that the surface roughness (Ra) of the metal foil is 0.2 ⁇ m or more, and furthermore, the circuit pattern shape is obtained. Then, the wiring circuit layer formed on the surface of the resin film is embedded in the surface of the soft insulating sheet while applying pressure, and the wiring circuit layer is transferred to the surface of the insulating sheet. , is manufactured by laminating a plurality of insulating sheets obtained in this way and collectively heat-curing them.
- the surface roughness (Ra) of the wiring circuit layer is set to 0.2 ⁇ m or more and embedded in the insulating sheet, thereby improving the adhesion between the insulating sheet and the wiring circuit layer.
- the circuit layer is made of pure copper such as oxygen-free copper having excellent thermal conductivity and electrical conductivity, the crystal grains tend to become coarse. Moreover, even when the circuit layer is formed thick, the crystal grains tend to be coarsened.
- the present invention has been made in view of the circumstances described above, and includes a metal plate material having excellent adhesion to a laminated resin member, a laminate in which the metal plate material and the resin member are laminated, an insulated circuit board, and An object of the present invention is to provide a method for manufacturing a metal plate.
- the metal plate material of the present invention has a plate body and a roughened plating layer formed on the outermost layer of the plate body, and the roughened plating layer includes the plate
- An engagement convex portion is formed which protrudes toward the side opposite to the main body and has a widened portion whose width gradually increases toward the tip side in the direction of protrusion, along the thickness direction of the plate main body.
- a plurality of the engaging protrusions are formed on the surface layer crystal grains located on the outermost surface of the plate body, and the protrusion height of the engaging protrusions is H (unit: ⁇ m), N ⁇ H/W is 0.5 or more, where W is the maximum width of the surface layer crystal grains (unit: ⁇ m) and N is the number of the engaging protrusions in the maximum width of the surface layer crystal grains.
- the roughened plating layer formed on the outermost layer protrudes toward the side opposite to the plate body, and the width is gradually increased toward the tip side in the protrusion direction. Since the engaging convex portion having the portion is formed, when the resin member is laminated on the plate surface of this metal plate material, the engaging convex portion is engaged with the resin member, and the laminated resin It is possible to improve the adhesion to the member.
- H unit: ⁇ m
- W unit: ⁇ m
- W unit: ⁇ m
- the maximum width of the surface layer crystal grains may be 3 ⁇ m or more. In this case, even if the maximum width of the surface layer crystal grains of the plate body is coarsened to 3 ⁇ m or more, it can be sufficiently engaged with the laminated resin member, and the adhesion with the resin member can be improved. It becomes possible.
- the projection height of the engaging projection is 0.1 ⁇ m or more.
- the protrusion height of the engaging protrusion is set to 0.1 ⁇ m or more, it is possible to reliably improve the adhesion to the laminated resin member.
- the plate body is made of copper or a copper alloy.
- the plate body since the plate body is made of copper or a copper alloy, it has excellent electrical conductivity and thermal conductivity.
- the crystal grain size of the plate body is coarsened, it can be sufficiently engaged with the laminated resin member, and it is possible to improve the adhesion with the resin member.
- a laminate of the present invention is a laminate in which a resin member is laminated on the plate surface of the above-described metal plate material, and the engagement protrusion of the metal plate material is formed at the joint interface between the resin member and the metal plate material. The resin member is engaged with the portion.
- the resin member is laminated on the plate surface of the metal plate material in which the engaging convex portion having the widened portion whose width gradually widens toward the tip side in the projecting direction is formed, At the joint interface between the resin member and the metal plate material, the resin member is engaged with the engagement convex portion of the metal plate material, so that the adhesion between the resin member and the metal plate material can be improved. It becomes possible.
- An insulated circuit board includes an insulating resin layer and a circuit layer formed on one surface of the insulating resin layer, wherein the circuit layer is made of the metal plate material described above.
- the insulating resin layer is formed by bonding to one surface of the insulating resin layer, and the insulating resin layer is engaged with the engaging convex portion of the metal plate at the bonding interface between the insulating resin layer and the circuit layer. It is characterized by
- the metal plate member having the engaging convex portion with the widened portion whose width gradually widens toward the tip side in the projecting direction is joined to one surface of the insulating resin layer.
- a circuit layer is formed, and the insulating resin layer is engaged with the engaging convex portion of the circuit layer (copper member) at the bonding interface between the insulating resin layer and the circuit layer. Therefore, the adhesion between the circuit layer and the insulating resin layer can be improved.
- a method for manufacturing a metal plate material according to the present invention is a method for manufacturing the metal plate material described above, wherein the plate main body is subjected to DC electroplating, and then PR pulse electroplating is performed. to form the roughened plating layer on the outermost layer of the plate body.
- the plate body is first subjected to direct current electroplating and then to PR pulse electroplating.
- direct current electroplating and then to PR pulse electroplating.
- PR pulse electroplating it is possible to form a plurality of fine engaging projections dispersedly on the surface of the large surface layer crystal grains.
- the present invention it is possible to provide a metal plate having excellent adhesion to a laminated resin member, a laminate in which the metal plate and the resin member are laminated, an insulated circuit board, and a method for manufacturing the metal plate. becomes.
- FIG. 1 is a schematic explanatory diagram of a power module provided with an insulated circuit board according to an embodiment of the present invention
- FIG. BRIEF DESCRIPTION OF THE DRAWINGS It is explanatory drawing of the metal plate material which concerns on embodiment of this invention.
- (a) is an observation photograph near the surface, and
- (b) is a schematic diagram of an engaging projection.
- 4 is an observation photograph of a bonding interface between a circuit layer and an insulating resin layer of an insulated circuit board according to an embodiment of the present invention
- 1 is a flowchart showing a method for manufacturing an insulated circuit board according to an embodiment of the present invention
- FIG. 5 is a schematic explanatory diagram of a method for manufacturing the insulated circuit board shown in FIG. 4;
- the laminate according to the present embodiment is an insulated circuit board configured by bonding an insulating resin layer 12, which is a resin member, to a metal plate material 30 (circuit layer 13) and a metal substrate 11 according to the present embodiment.
- FIG. 1 shows an insulated circuit board 10 and a power module 1 using the insulated circuit board 10 according to an embodiment of the present invention.
- the power module 1 shown in FIG. 1 includes an insulating circuit board 10, a semiconductor element 3 bonded to one surface (upper surface in FIG. 1) of the insulating circuit board 10 via a first solder layer 2, and an insulating circuit board. 10 (lower side in FIG. 1) and a heat sink 41 bonded via a second solder layer 42 .
- the semiconductor element 3 is made of a semiconductor material such as Si.
- the first solder layer 2 that joins the insulating circuit board 10 and the semiconductor element 3 is made of, for example, a Sn--Ag-based, Sn--Cu-based, Sn--In-based, or Sn--Ag--Cu-based solder material (so-called lead-free solder). material).
- the heat sink 41 is for dissipating heat from the insulating circuit board 10 side.
- the heat sink 41 is made of copper, a copper alloy, aluminum, an aluminum alloy, or the like, which has good thermal conductivity.
- the radiator plate is made of oxygen-free copper.
- the thickness of the heat sink 41 is set within a range of 3 mm or more and 10 mm or less.
- the insulating circuit board 10 and the heat sink 41 are bonded via the second solder layer 42 .
- the second solder layer 42 can have the same configuration as the first solder layer 2 described above.
- the insulating circuit board 10 of the present embodiment includes a metal substrate 11, an insulating resin layer 12 formed on one surface (upper surface in FIG. 1) of the metal substrate 11, and an insulating resin and a circuit layer 13 formed on one surface of the layer 12 (upper surface in FIG. 1).
- the metal substrate 11 has the effect of improving the heat dissipation characteristics by spreading the heat generated in the semiconductor element 3 mounted on the insulated circuit substrate 10 in the plane direction. Therefore, the metal substrate 11 is made of a metal with excellent thermal conductivity, such as copper or a copper alloy, aluminum or an aluminum alloy. In this embodiment, it is made of a rolled sheet of oxygen-free copper. The thickness of the metal substrate 11 is set within a range of 0.05 mm or more and 3 mm or less, and is set to 2.0 mm in this embodiment.
- the insulating resin layer 12 prevents electrical connection between the circuit layer 13 and the metal substrate 11, and is made of an insulating thermosetting resin.
- a thermosetting resin containing a filler may be used in order to ensure the strength of the insulating resin layer 12 and to ensure thermal conductivity.
- alumina, boron nitride, aluminum nitride, or the like can be used as the filler.
- an epoxy resin, a polyimide resin, etc. can be used as a thermosetting resin.
- the insulating resin layer 12 is composed of an epoxy resin that does not use a filler.
- Other embodiments comprise an epoxy resin containing boron nitride as a filler.
- the thickness of the insulating resin layer 12 is set within a range of 20 ⁇ m or more and 250 ⁇ m or less, and is set to 150 ⁇ m in this embodiment.
- a metal plate material 30 (circuit layer 13) of the present embodiment is joined to one surface of the insulating resin layer 12 (the upper surface in FIG. 5A). It is formed by A circuit pattern is formed on the circuit layer 13, and one surface (upper surface in FIG. 1) of the circuit layer 13 serves as a mounting surface on which the semiconductor element 3 is mounted.
- the thickness of the circuit layer 13 is set within a range of 0.3 mm or more and 3 mm or less, and is set to 0.5 mm in this embodiment.
- the metal plate material 30 according to the present embodiment is made of a metal having excellent electrical conductivity and thermal conductivity. In the present embodiment, it is made of copper or a copper alloy, specifically oxygen-free copper. It is configured. As shown in FIG. 2A, the metal plate material 30 according to the present embodiment includes a plate body 31 and a roughened plating layer 35 formed on the outermost layer of the plate body 31. .
- the roughened plating layer 35 protrudes toward the opposite side of the plate body 31 (upper side in FIG. 2( a )) and toward the tip side in the protruding direction. Therefore, the engaging convex portion 36 is formed with a widened portion 36a whose width gradually increases.
- the roughening plated layer 35 may be made of a material different from that of the metal plate material 30 , and is preferably made of a material having higher thermal conductivity than the insulating resin layer 12 .
- the roughening plated layer 35 is made of copper or a copper alloy having the same composition as the metal plate material 30 .
- the cross section along the thickness direction of the plate body 31 as shown in FIG.
- the projection height of the engaging projection 36 is H (unit: ⁇ m)
- the maximum width of the surface layer crystal grain 32 is W (unit: ⁇ m)
- the engaging projection at the maximum width W of the surface layer crystal grain 32 is N ⁇ H/W, where N is the number of portions 36, is 0.5 or more.
- the maximum width W of the surface crystal grains 32 is measured at the interface between the plate body 31 and the roughened plating layer 35, as shown in FIG. 2(a).
- the maximum width W of the surface layer crystal grains 32 located on the outermost surface of the plate surface may be 3 ⁇ m or more. Although there is no particular upper limit for the maximum width W, it is generally 200 ⁇ m or less, and the maximum is 1000 ⁇ m. Note that the maximum width W of the surface layer crystal grains 32 located on the outermost surface of the plate surface, as shown in FIG. It can be obtained by observing the crystal grains in contact with the roughening plating layer 35 and measuring the width in the direction orthogonal to the thickness direction of the grains in contact with the roughening plating layer 35 .
- the interface between the plate body 31 and the roughened plating layer 35 observed in the cross section along the thickness direction of the plate body 31 and the roughened plating layer 35 is observed with a scanning electron microscope (SEM) (magnification 1000 times) and the maximum width of the surface layer crystal grains 32 in the field of view of 85 ⁇ m ⁇ 120 ⁇ m was measured three times, and the maximum value among the three measurements was taken as the maximum width W.
- SEM scanning electron microscope
- the protrusion height H of the engaging protrusions 36 is set to 0.1 ⁇ m or more.
- the protrusion height H of the engaging protrusions 36 is determined by observing a cross section along the thickness direction of the plate body 31 and measuring the valley bottoms on both sides of the engaging protrusions 36. It can be measured as the distance from the connected reference line (broken line in FIG. 2B) to the top of the engaging projection 36 .
- the insulated circuit board 10 of the present embodiment is insulated from the engaging projections 36 of the circuit layer 13 (metal plate material 30) at the bonding interface between the insulating resin layer 12 and the circuit layer 13.
- the resin layer 12 is engaged with each other, and the circuit layer 13 (the metal plate material 30) and the insulating resin layer 12 are intruded into each other.
- the metal substrate 11 also has a roughened surface having the above-described engagement projections on the joint surface with the insulating resin layer 12, as with the metal plate material 30.
- a plated layer 35 is formed.
- the insulating resin layer 12 is engaged with the engaging convex portion of the metal substrate 11, and the metal substrate 11 and the insulating resin layer 12 are intruded into each other. It is
- the number N of the engaging protrusions 36 in the maximum width of the surface layer crystal grains 32 of the plate body 31, the maximum number of surface layer crystal grains The reason why the width W, the protrusion height H of the engaging projection, and N ⁇ H/W are defined as described above will be described.
- a plurality of engaging protrusions 36 are formed on the surface layer crystal grains 32 of the plate body 31 .
- the number N of the engaging protrusions 36 in the maximum width W of the surface layer crystal grains 32 of the plate body 31 means the number N of the engaging protrusions formed on the surface layer crystal grains 32 having the maximum width W of the plate body 31.
- the number N of portions 36 is shown. If the number N of the engaging projections 36 is small, the adhesion to the insulating resin layer 12 may be insufficient.
- the metal plate material 30 of the present embodiment even if the maximum width W of the surface layer crystal grains of the plate body 31 is 3 ⁇ m or more, that is, even if the crystal grains of the plate body 31 are coarse, a sufficient number of engagement The protrusions 36 are secured, and the adhesion between the circuit layer 13 (metal plate material 30) and the insulating resin layer 12 can be improved.
- the metal plate material 30 since the metal plate material 30 is made of oxygen-free copper having excellent thermal conductivity and electrical conductivity, the crystal grains tend to become coarse, but a sufficient number of engaging convex portions 36 can be secured. Therefore, it is possible to configure the insulated circuit board 10 having excellent thermal conductivity and electrical conductivity.
- the lower limit of the maximum width W of the surface layer crystal grains of the plate body 31 is not particularly limited.
- the upper limit of the maximum width W of the surface layer crystal grains of the plate body 31 is not particularly limited, but it is preferably 50 ⁇ m or less, more preferably 25 ⁇ m or less.
- the projection height H of the engaging projections 36 is 0.1 ⁇ m or more, the engagement with the insulating resin layer 12 is more sufficient, and the circuit layer 13 is insulated. Adhesion to the resin layer 12 can be further improved.
- the protrusion height H of the engaging protrusions 36 is more preferably 0.5 ⁇ m or more, more preferably 1.0 ⁇ m or more. is more preferable, and may be 2.0 ⁇ m or more.
- the upper limit of the projection height H of the engaging projections 36 is not particularly limited, but in order to ensure sufficient insulation in the insulating resin layer 12, the projection height H of the engaging projections 36 is set at 15.5 mm. It is preferably 0 ⁇ m or less, more preferably 10.0 ⁇ m or less, and more preferably 6.0 ⁇ m or less.
- a plurality of engaging protrusions 36 are formed on the surface layer crystal grains 32 of the plate body 31 .
- the protrusion height H (unit: ⁇ m) of the engaging protrusions 36, the maximum width W (unit: ⁇ m) of the surface layer crystal grains 32, and the number N of the engaging protrusions 36 at the maximum width W of the surface layer crystal grains 32 when N ⁇ H/W is less than 0.5, the number of engaging protrusions 36 in the maximum width W of the surface layer crystal grains 32 is insufficient, or the protrusion height of the engaging protrusions 36 is insufficient. Therefore, the adhesion with the insulating resin layer 12 may be insufficient.
- the value of N ⁇ H/W at the maximum width W of the surface layer crystal grains 32 of the plate body 31 is set to 0.5 or more.
- the value of N ⁇ H/W of the plate body 31 is preferably 1.0 or more. It is more preferably 2.0 or more. Although there is no upper limit for the value of N ⁇ H/W of the plate body 31, the value of N ⁇ H/W is approximately 10 or less.
- a roughened plating layer 35 is formed on the surface of the plate body 31 of the metal plate material 30 that will become the circuit layer 13 .
- the roughening plated layer 35 is also formed on the metal substrate 11 (see FIG. 5A).
- This roughening plated layer 35 is formed as follows. Electroplating is applied to the joint surfaces of the plate body 31 (and the metal substrate 11).
- 3,3′-dithiobis(1-propanesulfonic acid) disodium is added to a copper sulfate bath containing copper sulfate (CuSO 4 ) and sulfuric acid (H 2 SO 4 ) as main components as an electrolytic plating solution.
- CuSO 4 copper sulfate
- H 2 SO 4 sulfuric acid
- the temperature of the plating bath is preferably within the range of 25° C. or higher and 35° C. or lower.
- the electroplating treatment is first performed by a DC electroplating method, and then performed by a PR (Periodic Reverse) pulse electroplating method.
- the current density is set within the range of 1 A/dm 2 or more and 20 A/dm 2 or less
- the application time is set within the range of 10 seconds or more and 120 seconds or less.
- the electroplating treatment first, the DC electroplating method is performed, and then the PR pulse electroplating method is performed, so that even if the surface layer crystal grains of the plate body 31 are large, the surface layer crystal grains are large. It is possible to form fine engagement projections 36 dispersedly on the surface of the .
- the PR pulse electroplating method is a method of performing electroplating by applying current while periodically reversing the direction of the current. For example, a positive electrolysis of 1 A/dm 2 or more and 30 A/dm 2 or less (anodic electrolysis using the plate body 31 (and the metal substrate 11) as an anode) is 1 ms or more and 1000 ms or less, and a negative electrolysis of 1 A/dm 2 or more and 30 A/dm 2 or less. Electrolysis (negative electrolysis using the plate body 31 (and the metal substrate 11) as the negative electrode) is repeated for 1 ms or more and 1000 ms or less. As a result, the dissolution of the surface of the plate body 31 (and the metal substrate 11) and the deposition of copper are repeated, and the roughened plating layer 35 is formed.
- the number of engaging protrusions 36 in the roughened plating layer 35 is adjusted depending on the surface properties of the plate body 31 (and the metal substrate 11) forming the roughened plating layer 35 and various plating conditions (pulse application time, pulse waveform (precipitation amount/dissolution amount ratio), pulse frequency). It is possible to adjust the number of engaging protrusions 36 in the roughened plating layer 35 . For example, by lengthening the pulse application time or by adjusting the precipitation/dissolution ratio of the pulse waveform, the size of the engaging protrusion 36 having the widened portion 36a gradually widens toward the tip side in the protrusion direction. can be increased. Also, by adjusting the pulse frequency, the number of engaging protrusions 36 can be increased.
- a resin composition 22 containing boron nitride as a filler, an epoxy resin as a thermosetting resin, and a curing agent is disposed on one surface of the metal substrate 11 (upper surface in FIG. 5B).
- the resin composition 22 is formed in a sheet shape.
- a metal plate material 30 to be the circuit layer 13 is arranged on one surface (upper surface in FIG. 5B) of the resin composition 22 .
- the resin composition 22 is laminated on the surfaces of the metal substrate 11 and the metal plate material 30 on which the roughened plating layer 35 is formed.
- thermocompression bonding step S03 Next, as shown in FIG. 5B, the laminated metal substrate 11, resin composition 22, and metal plate material 30 are pressed together in the stacking direction, and the resin composition 22 is cured to form an insulating resin layer. 12 is formed, the metal substrate 11 and the insulating resin layer 12, and the insulating resin layer 12 and the metal plate material 30 are joined (see FIG. 5(c)).
- the conditions of this thermocompression bonding step S03 are as follows: heating temperature in the range of 150° C. to 400° C., holding time at the heating temperature in the range of 15 minutes to 90 minutes, and pressure in the stacking direction of 1 MPa to 100 MPa. is preferably within the range of
- circuit pattern forming step S04 Next, the metal plate material 30 joined to the insulating resin layer 12 is etched to form a circuit pattern, thereby forming the circuit layer 13 .
- the insulated circuit board 10 of the present embodiment is manufactured as shown in FIG. 5(d).
- the heat sink 41 is joined to the other surface of the metal substrate 11 of the insulated circuit substrate 10 .
- the metal substrate 11 and the heat sink 41 are joined together via a solder material.
- semiconductor element bonding step S06 the semiconductor element 3 is bonded to the circuit layer 13 of the insulating circuit board 10 .
- the circuit layer 13 and the semiconductor element 3 are joined via a solder material.
- the plate body 31 and the roughened plating layer 35 formed on the outermost layer of the plate body 31 protrudes toward the opposite side, and the engagement convex portion 36 is provided with a widened portion 36a whose width gradually widens toward the tip side in the direction of protrusion. and the insulating resin layer 12, the engaging convex portion 36 of the circuit layer 13 (metal plate material 30) is engaged with the insulating resin layer 12, and the circuit layer 13 (metal plate material 30) and the insulating resin layer 12 can be improved.
- the engaging projections 36 Since the ratio of the number of engaging projections 36 to the maximum width W of the surface layer crystal grains 32 is 0.4 pieces/ ⁇ m or more, even if the crystal grains of the plate body 31 are coarse, the engaging projections The portion 36 can be sufficiently formed, and the adhesion between the circuit layer 13 (metal plate material 30) and the insulating resin layer 12 can be improved.
- the engaging convex portions 36 can be sufficiently formed, and the circuit layer 13 It is possible to improve the adhesion between (the metal plate material 30) and the insulating resin layer 12.
- the plate body 31 can be made of a metal (oxygen-free copper in this embodiment) having relatively coarse crystal grains, and the thermal conductivity and electrical conductivity of the plate body 31 can be improved.
- the adhesion between the circuit layer 13 (metal plate material 30) and the insulating resin layer 12 can be further improved. becomes possible.
- the joint surface of the plate body 31 (and the metal substrate 11) is electrolytically plated.
- the DC electroplating method is first performed, and then the PR pulse electroplating method is performed. Even so, fine engaging protrusions 36 can be formed dispersedly on the surfaces of large surface layer crystal grains.
- the present invention is not limited to this, and can be modified as appropriate without departing from the technical idea of the invention.
- the insulating circuit board is manufactured by the manufacturing method of the insulating circuit board shown in FIGS. 4 and 5(a) to 5(d), but it is not limited to this.
- the metal plate material for forming the circuit layer is described as being composed of oxygen-free copper, but is not limited to this, and is composed of other copper or copper alloy. or made of other metals such as aluminum or aluminum alloys. Furthermore, it may have a structure in which a plurality of metals are laminated.
- the metal substrate is described as being made of oxygen-free copper, but is not limited to this, and may be made of other copper or copper alloy. However, it may be made of other metals such as aluminum or aluminum alloys. Furthermore, it may have a structure in which a plurality of metals are laminated.
- a power module is configured by mounting a semiconductor element on an insulated circuit board, but it is not limited to this.
- an LED module may be configured by mounting an LED element on the circuit layer of the insulating circuit board, or a thermoelectric module may be configured by mounting a thermoelectric element on the circuit layer of the insulating circuit board.
- a metal substrate (40 mm ⁇ 40 mm ⁇ 2 mm thick) made of a rolled sheet of oxygen-free copper and a metal plate material (40 mm ⁇ 40 mm ⁇ 0.5 mm thickness) to be the circuit layer are prepared, and the insulating resin of these metal substrates and metal plate materials
- a roughened plating layer was formed on the joint surface with the layer by the DC electroplating method and the PR pulse electroplating method described in the above embodiment.
- Table 1 shows the plating conditions of Examples 1-7 and Comparative Examples 1-2.
- a sheet material (40 mm ⁇ 40 mm ⁇ 0.15 mm thick) of a resin composition containing an epoxy resin containing boron nitride as a filler was placed on the surface of the metal substrate on which the roughened plating layer was formed. Further, a metal plate material to be a circuit layer was laminated on one surface of the resin composition sheet material so that the surface on which the roughened plating layer was formed faced the resin composition sheet material side.
- the metal substrate, the sheet material of the resin composition, and the metal plate material laminated as described above are heated while being pressed in the stacking direction, and the resin composition is cured to form an insulating resin layer, and the metal substrate and the insulating resin are formed.
- the layer, and the insulating resin layer and the metal plate were joined to obtain an insulated circuit board.
- the pressure in the stacking direction was 10 MPa
- the heating temperature was 180° C.
- the holding time at the heating temperature was 60 minutes.
- the metal plates and insulating circuit boards of Examples 1 to 7 and Comparative Examples 1 and 2 thus obtained were evaluated for the following items.
- Maximum width W of surface layer crystal grains of metal plate material A cross-section along the thickness direction of the metal plate on which the roughened plating layer was formed was observed by SEM (magnification: 1000), and the maximum width W of surface layer crystal grains located on the outermost surface of the plate surface was measured. For the maximum width W, the value measured at the interface between the plate body and the roughened plating layer was used.
- the interface between the plate body and the roughened plating layer observed in the cross section along the thickness direction of the plate body and the roughened plating layer was observed with a scanning electron microscope (SEM) (1000 times magnification),
- SEM scanning electron microscope
- the maximum width of surface crystal grains in a field of view of 85 ⁇ m ⁇ 120 ⁇ m was measured three times, and the maximum value among the three measurements is shown in Table 1 as the maximum width W.
- Protrusion height H of engagement protrusion A cross-section along the thickness direction of the metal plate on which the roughened plating layer was formed was observed by SEM (magnification: 5000), and the protrusion height H of the engaging protrusion was measured. That is, a cross section along the thickness direction of the roughened plating layer is observed with an SEM (magnification of 5000 times), and for all the engaging convex portions observed in a field of view of 16 ⁇ m ⁇ 23 ⁇ m, both sides of the engaging convex portion The distance from the reference line connecting the valley bottoms to the apex of the engaging protrusion was measured, and the average value of the obtained values was taken as the protrusion height of the engaging protrusion in a field of view of 16 ⁇ m ⁇ 23 ⁇ m. This was carried out three times, and the average value is shown in Table 1 as the protrusion height H of the engaging protrusion.
- N ⁇ H/W The maximum width W of the surface layer crystal grains located on the outermost surface of the plate surface measured as described above, the number N of engaging protrusions present in the surface layer crystal grains having the maximum width, and the protrusion height H of the engaging protrusions Then, N ⁇ H/W was calculated.
- Comparative Example 1 only the PR pulse electroplating method was performed without performing the DC electroplating method, and the value of N ⁇ H/W was 0.31. As a result of evaluating adhesion, peeling occurred at the bonding interface between the insulating resin layer and the circuit layer, indicating that the adhesion between the insulating resin layer and the circuit layer was insufficient. In Comparative Example 2, only the PR pulse electroplating method was performed without performing the DC electroplating method, and the value of N ⁇ H/W was 0.35. As a result of evaluating adhesion, peeling occurred at the bonding interface between the insulating resin layer and the circuit layer, indicating that the adhesion between the insulating resin layer and the circuit layer was insufficient.
- Example 1 to 7 of the present invention the DC electroplating method was followed by the PR pulse electroplating method to form a roughened plating layer, and the value of N ⁇ H/W was 0.5 or more. rice field.
- peeling occurred inside the insulating resin layer, indicating excellent adhesion between the insulating resin layer and the circuit layer.
- Insulated circuit board (laminate) 12 Insulating resin layer (resin member) 13 circuit layer 30 metal plate material
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Abstract
Description
本願は、2021年3月26日に、日本に出願された特願2021-053445号に基づき優先権を主張し、その内容をここに援用する。
ここで、絶縁樹脂層を備えた絶縁回路基板として、例えば特許文献1には、金属ベース回路基板が提案されている。また、特許文献2には、多層配線基板が提案されている。
この金属ベース回路基板においては、回路層上に半導体素子が接合され、金属基板の絶縁樹脂層とは反対側の面にヒートシンクが配設されており、半導体素子で発生した熱をヒートシンク側に伝達して放熱する構造とされている。
ここで、特許文献1に記載された金属ベース回路基板においては、絶縁樹脂層と回路層との密着性を向上させることは考慮されておらず、使用時に絶縁樹脂層と回路層(金属板)の剥離が生じるおそれがあった。
ここで、回路層を、例えば、熱伝導性および電気伝導性に優れた無酸素銅等の純銅で構成した場合には、結晶粒が粗大化し易い。また、回路層を厚く形成した場合でも、結晶粒が粗大化する傾向がある。
回路層を構成する金属板の結晶粒が粗大な場合には、エッチング処理しても微細な凹凸が形成されず、表面粗さ(Ra)を0.2μm以上としても、絶縁シートとの密着性が確保できないおそれがあった。
そして、前記係合凸部の突出高さをH(単位:μm)とし、前記表層結晶粒の最大幅をW(単位:μm)とし、前記表層結晶粒の最大幅における前記係合凸部の個数をNとしたときのN×H/Wが0.5以上とされているので、板本体の結晶粒が粗大であった場合でも、係合凸部を十分に形成することができ、積層した樹脂部材との密着性を向上させることが可能となる。
この場合、前記板本体の前記表層結晶粒の最大幅が3μm以上と粗大化されていても、積層した樹脂部材と十分に係合することができ、樹脂部材との密着性を向上させることが可能となる。
この場合、前記係合凸部の突出高さが0.1μm以上とされているので、積層された樹脂部材との密着性を確実に向上させることができる。
この場合、板本体が銅又は銅合金で構成されているので、電気伝導性および熱伝導性に優れている。また、板本体の結晶粒径が粗大化しても、積層した樹脂部材と十分に係合することができ、樹脂部材との密着性を向上させることが可能となる。
本実施形態に係る積層体は、樹脂部材である絶縁樹脂層12と、本実施形態に係る金属板材30(回路層13)および金属基板11と、が接合されることにより構成された絶縁回路基板10とされている。
図1に、本発明の実施形態である絶縁回路基板10およびこの絶縁回路基板10を用いたパワーモジュール1を示す。
ここで、絶縁回路基板10とヒートシンク41とは、第2はんだ層42を介して接合されている。この第2はんだ層42は、上述の第1はんだ層2と同様の構成とすることができる。
本実施形態では、絶縁樹脂層12の強度を確保するとともに、熱伝導性を確保するために、フィラーを含有する熱硬化型樹脂を用いてもよい。ここで、フィラーとしては、例えばアルミナ、窒化ホウ素、窒化アルミニウム等を用いることができる。また、熱硬化型樹脂としては、エポキシ樹脂、ポリイミド樹脂等を用いることができる。図3に示す本実施形態では、絶縁樹脂層12は、フィラーを用いていないエポキシ樹脂で構成されている。その他の実施形態では、フィラーとして窒化ホウ素を含有するエポキシ樹脂で構成されている。また、絶縁樹脂層12の厚さは、20μm以上250μm以下の範囲内とされており、本実施形態では、150μmとされている。
この回路層13においては、回路パターンが形成されており、その一方の面(図1において上面)が、半導体素子3が搭載される搭載面とされている。ここで、回路層13の厚さは0.3mm以上3mm以下の範囲内に設定されており、本実施形態では0.5mmに設定されている。
本実施形態に係る金属板材30は、電気伝導性および熱伝導性に優れた金属で構成されており、本実施形態では、銅又は銅合金で構成されており、具体的には無酸素銅で構成されている。
そして、本実施形態に係る金属板材30においては、図2(a)に示すように、板本体31と、この板本体31の最表層に形成された粗化めっき層35と、を備えている。
粗化めっき層35は、金属板材30と異なる構成材料であってもよく、絶縁樹脂層12よりも熱伝導性に優れた材料で構成されていることが好ましい。本実施形態では、粗化めっき層35は、金属板材30と同じ組成の銅又は銅合金で構成されている。
ここで、板本体31の厚さ方向に沿った断面において、図2(a)に示すように、板面の最表面に位置する表層結晶粒32の上に複数の係合凸部36が形成されており、係合凸部36の突出高さをH(単位:μm)とし、表層結晶粒32の最大幅をW(単位:μm)とし、表層結晶粒32の最大幅Wにおける係合凸部36の個数をNとしたときのN×H/Wが0.5以上とされている。
なお、表層結晶粒32の最大幅Wは、図2(a)に示すように、板本体31と粗化めっき層35との界面において測定されるものである。
なお、板面の最表面に位置する表層結晶粒32の最大幅Wは、図2(a)に示すように、板本体31の厚さ方向に沿った断面を走査電子顕微鏡(SEM)を用いて観察し、粗化めっき層35と接触している結晶粒の厚さ方向と直交する方向に幅を測定することにより、求めることができる。
すなわち、板本体31と粗化めっき層35との厚さ方向に沿った断面で観察される、板本体31と粗化めっき層35との界面を走査電子顕微鏡(SEM)にて観察し(倍率1000倍)、85μm×120μmの視野における表層結晶粒32の最大幅を測定することを3回実施し、3回の測定中での最大の値を最大幅Wとした。
なお、係合凸部36の突出高さHは、図2(b)に示すように、板本体31の厚さ方向に沿った断面を観察し、係合凸部36の両側の谷底同士を結んだ基準線(図2(b)の破線部)から係合凸部36の頂部までの距離として測定することができる。
より具体的には、粗化めっき層35の厚さ方向に沿った断面をSEMにて観察し(倍率5000倍)、16μm×23μmの視野で観察される全ての係合凸部について、それぞれ係合凸部の両側の谷底同士を結んだ基準線から係合凸部の頂部までの距離を測定し、得られた値の平均値を16μm×23μmの視野における係合凸部の突出高さとした。これを3回実施して、その平均値を係合凸部の突出高さHとした。
本実施形態の金属板材30においては、板本体31の表層結晶粒32の上に複数の係合凸部36が形成されている。ここで、板本体31の表層結晶粒32の最大幅Wにおける係合凸部36の個数Nとは、板本体31の最大幅Wを有する表層結晶粒32の上に形成されている係合凸部36の個数Nを示す。この係合凸部36の個数Nが少ない場合には、絶縁樹脂層12との密着性が不十分となるおそれがある。
本実施形態の金属板材30において、板本体31の表層結晶粒の最大幅Wが3μm以上である場合、すなわち、板本体31の結晶粒が粗大な場合であっても、十分な個数の係合凸部36が確保され、回路層13(金属板材30)と絶縁樹脂層12との密着性を向上させることができる。
特に、本実施形態では、金属板材30を、熱伝導性および電気伝導性に優れた無酸素銅で構成されていることから、結晶粒が粗大化し易くなるが、十分な個数の係合凸部36を確保することができる。よって、熱伝導性および電気伝導性に優れた絶縁回路基板10を構成することが可能となる。
なお、板本体31の表層結晶粒の最大幅Wの下限に特に制限はない。また、板本体31の表層結晶粒の最大幅Wの上限にも特に制限はないが、50μm以下であることが好ましく、25μm以下であることがさらに好ましい。
本実施形態の金属板材30において、係合凸部36の突出高さHが0.1μm以上である場合には、絶縁樹脂層12とさらに十分に係合することになり、回路層13と絶縁樹脂層12との密着性をさらに向上させることができる。
なお、回路層13と絶縁樹脂層12との密着性をさらに向上させるためには、係合凸部36の突出高さHを0.5μm以上とすることがさらに好ましく、1.0μm以上とすることがより好ましく、2.0μm以上であってもよい。
また、係合凸部36の突出高さHの上限には特に制限はないが、絶縁樹脂層12における絶縁性を十分に確保するために、係合凸部36の突出高さHを15.0μm以下とすることが好ましく、10.0μm以下とすることがさらに好ましく、6.0μm以下とすることがより好ましい。
本実施形態の金属板材30においては、板本体31の表層結晶粒32の上に複数の係合凸部36が形成されている。ここで、係合凸部36の突出高さH(単位:μm)、表層結晶粒32の最大幅W(単位:μm)、表層結晶粒32の最大幅Wにおける係合凸部36の個数Nについて、N×H/Wが0.5未満の場合には、表層結晶粒32の最大幅Wにおける係合凸部36の個数が不足しているか、係合凸部36の突出高さが不足しているため、絶縁樹脂層12との密着性が不十分となるおそれがある。
このため、本実施形態では、板本体31の表層結晶粒32の最大幅WにおけるN×H/Wの値を0.5以上に設定している。
なお、さらなる回路層13(金属板材30)と絶縁樹脂層12との密着性をさらに向上させるためには、板本体31のN×H/Wの値を1.0以上とすることが好ましく、2.0以上であることがさらに好ましい。
なお、板本体31のN×H/Wの値の上限に制限はないが、N×H/Wの値は10以下程度である。
まず、回路層13となる金属板材30において、板本体31の表面に粗化めっき層35を形成する。なお、本実施形態では、金属基板11にも粗化めっき層35を形成する(図5(a)参照)。この粗化めっき層35は、以下のようにして形成される。
板本体31(および金属基板11)の接合面に電解めっき処理を施す。本実施形態では、電解めっき液として硫酸銅(CuSO4)および硫酸(H2SO4)を主成分とした硫酸銅浴に、3,3´-ジチオビス(1-プロパンスルホン酸)2ナトリウムを添加した水溶液からなる電解液を用いることが好ましい。また、めっき浴の温度は例えば25℃以上35℃以下の範囲内とすることが好ましい。
直流電解めっき法においては、電流密度を1A/dm2以上20A/dm2以下の範囲内、印加時間を10秒以上120秒以下の範囲内とする。
ここで、電解めっき処理として、まず、直流電解めっき法で実施し、その後、PRパルス電解めっき法で実施することで、板本体31の表層結晶粒が大きい場合であっても、大きな表層結晶粒の表面に、分散して細かな係合凸部36を形成することができる。
例えば、パルス印加時間を長くするか、パルス波形として析出量/溶解量比を調整すると、突出方向の先端側に向かうにしたがい漸次幅が広くなる拡幅部36aを備えた係合凸部36の大きさを大きくさせることができる。またパルス周波数を調整すると係合凸部36の個数を増加させることができる。
次に、金属基板11の一方の面(図5(b)において上面)に、フィラーとしての窒化ホウ素と熱硬化型樹脂としてのエポキシ樹脂と硬化剤とを含有する樹脂組成物22を配設する。なお、本実施形態では、樹脂組成物22は、シート状に形成されている。
また、この樹脂組成物22の一方の面(図5(b)において上面)に、回路層13となる金属板材30を配設する。
なお、樹脂組成物22は、金属基板11および金属板材30の粗化めっき層35が形成された面に積層される。
次に、図5(b)で示すように、積層した金属基板11、樹脂組成物22、金属板材30を、積層方向に加圧するとともに加圧して、樹脂組成物22を硬化させて絶縁樹脂層12を形成するとともに、金属基板11と絶縁樹脂層12、絶縁樹脂層12と金属板材30を接合する(図5(c)参照)。
この熱圧着工程S03の条件は、加熱温度を150℃以上400℃以下の範囲内、加熱温度での保持時間を15分以上90分以下の範囲内、積層方向の加圧圧力を1MPa以上100MPa以下の範囲内とすることが好ましい。
次に、絶縁樹脂層12に接合された金属板材30に対してエッチング処理を行い、回路パターンを形成し、回路層13を構成する。
次に、この絶縁回路基板10の金属基板11の他方の面に、ヒートシンク41を接合する。本実施形態では、金属基板11とヒートシンク41とを、はんだ材を介して接合している。
そして、絶縁回路基板10の回路層13に半導体素子3を接合する。本実施形態では、回路層13と半導体素子3とを、はんだ材を介して接合している。
以上の工程により、図1に示すパワーモジュール1が製造される。
また、板本体31を、比較的結晶粒が粗大となる金属(本実施形態では無酸素銅)で構成することができ、板本体31の熱伝導性および電気伝導性を向上させることができる。
本実施形態においては、図4および図5(a)~図5(d)に示す絶縁回路基板の製造方法によって絶縁回路基板を製造するものとして説明したが、これに限定されることはない。
また、この樹脂組成物のシート材の一方の面に、回路層となる金属板材を、粗化めっき層が形成された面が樹脂組成物のシート材側を向くように、積層した。
以上のようにして、得られた実施例1~7及び比較例1~2の金属板材および絶縁回路基板について、以下の項目についてそれぞれ評価した。
粗化めっき層を形成した金属板材の厚さ方向に沿った断面をSEM観察(倍率1000倍)し、板面の最表面に位置する表層結晶粒の最大幅Wを測定した。なお、最大幅Wは、板本体と粗化めっき層との界面で測定した値を用いた。
すなわち、板本体と粗化めっき層との厚さ方向に沿った断面で観察される、板本体と粗化めっき層との界面を走査電子顕微鏡(SEM)にて観察し(倍率1000倍)、85μm×120μmの視野における表層結晶粒の最大幅を測定することを3回実施し、3回の測定中での最大の値を最大幅Wとして表1に示した。
粗化めっき層を形成した金属板材の厚さ方向に沿った断面をSEM観察(倍率5000倍)し、係合凸部の突出高さHを測定した。
すなわち、粗化めっき層の厚さ方向に沿った断面をSEMにて観察し(倍率5000倍)、16μm×23μmの視野で観察される全ての係合凸部について、それぞれ係合凸部の両側の谷底同士を結んだ基準線から係合凸部の頂部までの距離を測定し、得られた値の平均値を16μm×23μmの視野における係合凸部の突出高さとした。これを3回実施して、その平均値を係合凸部の突出高さHとして表1に示した。
粗化めっき層を形成した金属板材の厚さ方向に沿った断面をSEM観察(倍率1000~5000倍)し、最大幅の表層結晶粒に存在する係合凸部の個数Nを測定した。
すなわち、板本体と粗化めっき層との厚さ方向に沿った断面で観察される、板本体と粗化めっき層との界面を走査電子顕微鏡(SEM)にて観察し(倍率1000~5000倍)、最大幅の表層結晶粒に存在する係合凸部の個数を測定し、これを最大幅Wにおける係合凸部の個数Nとして表1に示した。
上述のように測定した板面の最表面に位置する表層結晶粒の最大幅W、および、最大幅の表層結晶粒に存在する係合凸部の個数N、係合凸部の突出高さHから、N×H/Wを算出した。
JIS K 6854-1:1999に準拠した90度剥離試験を実施して、剥離した箇所を確認し、絶縁樹脂層と回路層との密着性を評価した。評価結果を表1に示す。
比較例2においては、直流電解めっき法を実施せずにPRパルス電解めっき法のみを実施しており、N×H/Wの値が0.35となった。密着性を評価した結果、絶縁樹脂層と回路層との接合界面で剥離が生じており、絶縁樹脂層と回路層との密着性が不十分であった。
12 絶縁樹脂層(樹脂部材)
13 回路層
30 金属板材
Claims (6)
- 銅又は銅合金からなる金属板材であって、
板本体と、この板本体の最表層に形成された粗化めっき層と、を有し、
前記粗化めっき層には、前記板本体とは反対側に向けて突出するとともに、突出方向の先端側に向かうにしたがい漸次幅が広くなる拡幅部を備えた係合凸部が形成されており、
前記板本体の厚さ方向に沿った断面において、前記板本体の最表面に位置する表層結晶粒の上に複数の前記係合凸部が形成されており、前記表層結晶粒の最大幅をW(単位:μm)とし、前記表層結晶粒の最大幅における前記係合凸部の個数をNとし、前記係合凸部の突出高さをH(単位:μm)としたときのN×H/Wが0.5以上であることを特徴とする金属板材。 - 前記表層結晶粒の最大幅が3μm以上であることを特徴とする請求項1に記載の金属板材。
- 前記係合凸部の突出高さが0.1μm以上とされていることを特徴とする請求項1又は請求項2に記載の金属板材。
- 請求項1から請求項3のいずれ一項に記載の金属板材の板面に、樹脂部材が積層された積層体であって、
前記樹脂部材と前記金属板材との接合界面においては、前記金属板材の前記係合凸部に前記樹脂部材が係合していることを特徴とする積層体。 - 絶縁樹脂層と、絶縁樹脂層の一方の面に形成された回路層と、を備えた絶縁回路基板であって、
前記回路層は、請求項1から請求項3のいずれか一項に記載の金属板材が、前記絶縁樹脂層の一方の面に接合することにより形成されており、
前記絶縁樹脂層と前記回路層との接合界面においては、前記金属板材の前記係合凸部に前記絶縁樹脂層が係合していることを特徴とする絶縁回路基板。 - 請求項1から請求項3のいずれか一項に記載の金属板材を製造する金属板材の製造方法であって、
前記板本体に対して、直流電解めっきを実施し、その後、PRパルス電解めっきを実施することにより、前記板本体の最表層に前記粗化めっき層を形成することを特徴とする金属板材の製造方法。
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| JP2023509254A JP7632594B2 (ja) | 2021-03-26 | 2022-03-23 | 金属板材、積層体、絶縁回路基板、および、金属板材の製造方法 |
| EP22775694.7A EP4317529A4 (en) | 2021-03-26 | 2022-03-23 | METAL FOIL MATERIAL, LAMINATED BODY, INSULATED CIRCUIT BOARD, AND METHOD FOR MANUFACTURING METAL FOIL MATERIAL |
| US18/283,519 US12563666B2 (en) | 2021-03-26 | 2022-03-23 | Metal sheet material, layered body, insulated circuit board, and metal sheet material manufacturing method |
| CN202280024338.3A CN117083419A (zh) | 2021-03-26 | 2022-03-23 | 金属板材、层叠体、绝缘电路基板以及金属板材的制造方法 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03202500A (ja) * | 1989-08-28 | 1991-09-04 | Matsushita Electric Works Ltd | 銅箔の粗面化方法 |
| JP2000077850A (ja) | 1998-08-31 | 2000-03-14 | Kyocera Corp | 多層配線基板およびその製造方法 |
| JP2006351677A (ja) * | 2005-06-14 | 2006-12-28 | Furukawa Circuit Foil Kk | 高周波回路用銅箔およびその製造方法 |
| JP2015207666A (ja) | 2014-04-21 | 2015-11-19 | 住友ベークライト株式会社 | 金属ベース基板、金属ベース基板の製造方法、金属ベース回路基板および電子装置 |
| JP2020158832A (ja) * | 2019-03-26 | 2020-10-01 | 古河電気工業株式会社 | 表面処理銅箔、並びにこれを用いた銅張積層板及びプリント配線板 |
| JP2020163650A (ja) * | 2019-03-29 | 2020-10-08 | 三菱マテリアル株式会社 | 接合体、及び、絶縁回路基板 |
| JP2021053445A (ja) | 2020-12-23 | 2021-04-08 | テルモ株式会社 | 医療用デバイス |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200535259A (en) * | 2004-02-06 | 2005-11-01 | Furukawa Circuit Foil | Treated copper foil and circuit board |
| JP5204908B1 (ja) * | 2012-03-26 | 2013-06-05 | Jx日鉱日石金属株式会社 | キャリア付銅箔、キャリア付銅箔の製造方法、プリント配線板用キャリア付銅箔及びプリント配線板 |
| WO2016038923A1 (ja) | 2014-09-09 | 2016-03-17 | 古河電気工業株式会社 | プリント配線板用銅箔及び銅張積層板 |
| JP5877282B1 (ja) * | 2014-09-09 | 2016-03-02 | 古河電気工業株式会社 | プリント配線板用銅箔及び銅張積層板 |
-
2022
- 2022-03-23 EP EP22775694.7A patent/EP4317529A4/en active Pending
- 2022-03-23 WO PCT/JP2022/013602 patent/WO2022202912A1/ja not_active Ceased
- 2022-03-23 CN CN202280024338.3A patent/CN117083419A/zh active Pending
- 2022-03-23 JP JP2023509254A patent/JP7632594B2/ja active Active
- 2022-03-23 US US18/283,519 patent/US12563666B2/en active Active
- 2022-03-24 TW TW111111112A patent/TW202307269A/zh unknown
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03202500A (ja) * | 1989-08-28 | 1991-09-04 | Matsushita Electric Works Ltd | 銅箔の粗面化方法 |
| JP2000077850A (ja) | 1998-08-31 | 2000-03-14 | Kyocera Corp | 多層配線基板およびその製造方法 |
| JP2006351677A (ja) * | 2005-06-14 | 2006-12-28 | Furukawa Circuit Foil Kk | 高周波回路用銅箔およびその製造方法 |
| JP2015207666A (ja) | 2014-04-21 | 2015-11-19 | 住友ベークライト株式会社 | 金属ベース基板、金属ベース基板の製造方法、金属ベース回路基板および電子装置 |
| JP2020158832A (ja) * | 2019-03-26 | 2020-10-01 | 古河電気工業株式会社 | 表面処理銅箔、並びにこれを用いた銅張積層板及びプリント配線板 |
| JP2020163650A (ja) * | 2019-03-29 | 2020-10-08 | 三菱マテリアル株式会社 | 接合体、及び、絶縁回路基板 |
| JP2021053445A (ja) | 2020-12-23 | 2021-04-08 | テルモ株式会社 | 医療用デバイス |
Non-Patent Citations (1)
| Title |
|---|
| See also references of EP4317529A4 |
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| CN117083419A (zh) | 2023-11-17 |
| EP4317529A4 (en) | 2025-10-08 |
| EP4317529A1 (en) | 2024-02-07 |
| JPWO2022202912A1 (ja) | 2022-09-29 |
| JP7632594B2 (ja) | 2025-02-19 |
| US20240178115A1 (en) | 2024-05-30 |
| US12563666B2 (en) | 2026-02-24 |
| TW202307269A (zh) | 2023-02-16 |
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