WO2023056701A1 - 量子比特组件、量子比特组件制备方法、芯片及设备 - Google Patents

量子比特组件、量子比特组件制备方法、芯片及设备 Download PDF

Info

Publication number
WO2023056701A1
WO2023056701A1 PCT/CN2021/135752 CN2021135752W WO2023056701A1 WO 2023056701 A1 WO2023056701 A1 WO 2023056701A1 CN 2021135752 W CN2021135752 W CN 2021135752W WO 2023056701 A1 WO2023056701 A1 WO 2023056701A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
photoresist
superconducting
etching
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/135752
Other languages
English (en)
French (fr)
Inventor
邹沉积
郑亚锐
王辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tencent Technology Shenzhen Co Ltd
Original Assignee
Tencent Technology Shenzhen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tencent Technology Shenzhen Co Ltd filed Critical Tencent Technology Shenzhen Co Ltd
Priority to EP21937220.8A priority Critical patent/EP4191693A4/en
Priority to US17/972,434 priority patent/US11917927B2/en
Publication of WO2023056701A1 publication Critical patent/WO2023056701A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/81—Containers; Mountings
    • H10N60/815—Containers; Mountings for Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Definitions

  • the present application relates to the technical field of micro-nano processing, and in particular to a qubit component, a method for preparing the qubit component, a chip and equipment.
  • the flip-chip superconducting quantum chip packaging process is a process of welding two planar quantum chips through superconducting materials to obtain a flip-chip superconducting quantum chip.
  • UBM Under Bump Metal
  • the embodiment of the present application provides a qubit component, a method for preparing the qubit component, a chip and a device, which can improve the performance of a flip-chip-bonded superconducting quantum chip.
  • the technical solution is as follows.
  • a qubit assembly is provided, and the qubit assembly is used for flip-chip welding superconducting quantum chips;
  • the qubit assembly includes: a substrate, a superconducting circuit layer, an under-bump metal layer, and solder joints;
  • the superconducting circuit layer is on the substrate
  • the UBM layer is located on the superconducting circuit layer, and the UBM layer forms a superconducting connection with the superconducting circuit layer; the material of the UBM layer is metal niobium;
  • the solder joint is located on the UBM layer, and the solder joint forms a superconducting connection with the UBM layer.
  • a method for preparing a qubit component is provided, which is performed by production line equipment, the method comprising:
  • An UBM layer is prepared on the upper surface of the superconducting circuit layer; the UBM layer forms a superconducting connection with the superconducting circuit layer; the material of the UBM layer is metal niobium;
  • Welding points are prepared on the upper surface of the UBM layer to obtain a qubit assembly for flip-chip welding superconducting quantum chips; the welding points form a superconducting connection with the UBM layer.
  • a flip-chip superconducting quantum chip in another aspect, includes two qubit components as described above;
  • the two qubit group components are welded through solder joints.
  • a computer device in another aspect, includes the flip-chip superconducting quantum chip as described above.
  • a production line equipment in another aspect, includes: a photolithography machine, an evaporation machine, and an etching machine; the photolithography machine, the evaporation machine, and the etching machine are used for cooperation Prepare qubit assemblies as described above.
  • under-bump metal layer made of metal niobium between the superconducting circuit layer and the solder joint in the qubit assembly for flip-chip welding superconducting quantum chips
  • the metal niobium is a superconducting material, and , the metal niobium is easier to peel off, and has less impact on the cleanliness of the superconducting circuit layer, and the oxide layer on the surface of niobium is easier to remove than the oxide layer on the surface of other superconducting materials, thus forming a cleaner bond between the solder joints Good superconducting contact, therefore, using metal niobium as the under-bump metal layer can greatly improve the superconducting performance between two planar superconducting quantum chips in flip-chip bonding superconducting quantum chips, thereby improving flip-chip bonding. Performance of superconducting quantum chips.
  • Fig. 1 is the structural representation of the qubit assembly involved in the present application
  • Fig. 2 is a method flow chart of a qubit component preparation method shown in an exemplary embodiment of the present application
  • Fig. 3 is the framework diagram of the preparation of the qubit assembly involved in the present application.
  • Fig. 4 is a method flowchart of a qubit component preparation method shown in an exemplary embodiment of the present application
  • Fig. 5 is the schematic diagram of the preparation of the metal niobium film layer involved in the embodiment shown in Fig. 4;
  • Fig. 6 is the comparison diagram of the niobium film involved in the embodiment shown in Fig. 4;
  • Fig. 7 is a schematic diagram of the etching curve involved in the embodiment shown in Fig. 4;
  • Fig. 8 is the surface electron microscope image of the niobium film under different air pressures involved in the embodiment shown in Fig. 4;
  • Fig. 9 is the surface electron microscope image of the niobium film under different distances involved in the embodiment shown in Fig. 4;
  • Fig. 10 is the surface electron microscope image of the niobium film under different coating powers involved in the embodiment shown in Fig. 4;
  • Fig. 11 is a schematic diagram of the superconducting transition temperature of niobium film samples under different coating powers involved in the embodiment shown in Fig. 4;
  • Fig. 12 is a characteristic curve diagram of the natural oxidation of the niobium film involved in the embodiment shown in Fig. 4;
  • Fig. 13 is a schematic diagram of a solution application scenario provided by an embodiment of the present application.
  • Fig. 14 is a schematic diagram of production line equipment shown in an exemplary embodiment of the present application.
  • Qubit In quantum information science, it is a unit of measurement for quantum information. Unlike classical bits, which can only be in one of the 0 or 1 states, qubits can be in the 0 and 1 states at the same time, that is, the quantum superposition state of 0 and 1.
  • Josephson Junction or superconducting tunnel junction.
  • it is a structure composed of two superconductors sandwiched by some kind of very thin barrier layer (thickness ⁇ coherence length of Cooper (Cooper) electron pair), such as S (Superconductor, superconductor)—I (semiconductor or insulator (Insulator) ))—S (superconductor) structure, referred to as SIS.
  • S Superconductor, superconductor
  • I semiconductor or insulator (Insulator)
  • S superconductor structure
  • Superconducting circuit When the ambient temperature drops to a certain threshold, the resistance of some materials will disappear, and a superconducting phenomenon will appear. The circuit structure made of these materials is called a superconducting circuit.
  • Quantum chip A chip based on the laws of quantum mechanics. In particular, when the selected carrier is a superconducting quantum circuit and a Josephson junction, the chip is called a superconducting quantum chip.
  • a superconducting quantum chip is one of the important carriers that can be used to study quantum computing. It generally consists of a substrate, a waveguide film layer (also known as a large circuit structure), a qubit structure, and other structures.
  • the main function of the waveguide film layer is to transmit the microwave and electromagnetic field that control the qubit.
  • the thickness of the waveguide film layer should be relatively thicker. The device performance obtained in this way, such as Q value will be better. Since the current qubit structure is dominated by Josephson junctions, the preparation method of its double-tilt evaporation limits the thickness of the junction region and the superconducting layer connecting the junction with the external circuit, so the thickness of the waveguide film layer of the large circuit is also limited accordingly.
  • Flip-chip superconducting quantum chip As the number of qubits increases, the simple planar quantum chip design is limited by size and difficult to expand. As a result, the flip-chip superconducting quantum chip packaging process has been developed.
  • the technological process mainly includes: respectively making contact solder joints on two chips (top chip and bottom chip) used for the flip-chip welding process; connecting the top chip and the bottom chip by pressure welding through the prepared solder joints.
  • Under-bump metal UBM layer in flip-chip superconducting quantum chips In the process of making the contact pads of the top and bottom sheets, since the superconducting circuit structure of the top and bottom sheets is formed based on the etching of the aluminum film, the contact The indium material and aluminum material used in solder joints are easy to form alloys and cannot be superconducted, which will destroy the superconducting circuit structure. In the process of making indium column solder joints, the UBM layer is often introduced as a medium between the indium column solder joints and the top (bottom) sheet. The UBM layer needs to meet the requirements of forming a good superconducting contact with the top (bottom) sheet, and also needs to form a good superconducting contact with the indium pillar solder joint.
  • Magnetron sputtering coating is a common coating method. The basic principle is that electrons collide with gas molecules (usually nitrogen molecules or argon molecules) under the combined action of electric field and magnetic field to generate nitrogen Cations or argon cations, the cations bombard the surface of the target, causing the target atoms to evaporate onto the surface of the substrate.
  • gas molecules usually nitrogen molecules or argon molecules
  • Niobium A superconducting metal material with a superconducting transition temperature of about 9K.
  • Ion beam etching a physical etching method, the basic principle of which is that electrons collide with inert gas molecules (usually argon molecules) to generate cations, which are accelerated to bombard the surface of the sample under the action of an electric field to achieve physical etching effects.
  • inert gas molecules usually argon molecules
  • the solution shown in the embodiment of the present application provides a qubit assembly for flip-chip bonding superconducting quantum chips.
  • the qubit assembly can be a single-chip planar superconducting quantum chip in flip-chip bonding Conductive quantum chip, or, the qubit component can also be a part of the above-mentioned planar superconducting quantum chip.
  • FIG. 1 shows a schematic structural diagram of a qubit component shown in an exemplary embodiment of the present application.
  • the qubit component may include a substrate 101, a superconducting circuit layer 102, an under-bump metal layer 103, and a solder joint 104;
  • the superconducting circuit layer 102 is located on the substrate 101;
  • the UBM layer 103 is located on the superconducting circuit layer 102, and the UBM layer 103 forms a superconducting connection with the superconducting circuit layer 102; the material of the UBM layer 103 is metal niobium;
  • the solder joint 104 is located on the UBM layer 103 , and the solder joint 104 forms a superconducting connection with the UBM layer 103 .
  • the solder joint 104 is made of metal indium.
  • metal indium is used as the material of the solder joint, so that a good superconducting contact can be formed between the solder joint and the UBM layer, and the superconducting effect at the solder joint can be improved.
  • the material of the superconducting circuit layer 102 is aluminum.
  • a good superconducting contact can be formed between the metal indium and the metal niobium, and a good superconducting contact can also be formed between the metal niobium and the superconducting circuit layer. layer, it can also avoid direct contact between the metal indium and the aluminum superconducting circuit layer to form an alloy and destroy the superconducting circuit structure.
  • a layer of bumps made of metal niobium is provided between the superconducting circuit layer and the solder joint.
  • metal niobium is a superconducting material, and metal niobium is easier to peel off, which has less impact on the cleanliness of the superconducting circuit layer, and the oxide layer on the surface of niobium is compared with that on the surface of other superconducting materials. The oxide layer is easier to remove, thereby forming a better superconducting contact with the solder joints.
  • metal niobium as the metal layer under the bump can greatly improve the superconductivity of the two planes in the flip-chip superconducting quantum chip. Superconducting properties between quantum chips, and then improve the performance of flip-chip superconducting quantum chips.
  • the superconducting metal niobium is used as the UBM layer, which can be applied to flip-chip superconducting quantum chips (such as 2-bit flip-chip superconducting quantum chips, or 49-bit flip-chip superconducting quantum chips, etc.) Among them, the superconducting line connection between the multilayer aluminum superconducting circuit layers is realized.
  • the niobium film can hinder the formation of alloys between the aluminum circuit and the indium of the solder joints, thereby affecting the superconducting connection.
  • its excellent etching rate and The convenient preparation method also greatly improves the efficiency and performance of multilayer aluminum superconducting circuit connections.
  • FIG. 2 shows a flow chart of a method for preparing a qubit component shown in an exemplary embodiment of the present application. As shown in Figure 2, the method may include the following steps:
  • Step 201 preparing a superconducting circuit layer on a substrate.
  • the above-mentioned substrate can be made of sapphire or high-resistance silicon, and the superconducting circuit layer can be made of metal aluminum.
  • the superconducting circuit layer may include physical qubits (such as Josephson junctions), and outer circuits connected to the physical qubits.
  • Step 202 preparing an UBM layer on the upper surface of the superconducting circuit layer; the UBM layer forms a superconducting connection with the superconducting circuit layer; the material of the UBM layer is metal niobium.
  • Step 203 preparing solder joints on the upper surface of the UBM layer to obtain qubit components for flip-chip bonding superconducting quantum chips; the solder joints form superconducting connections with the UBM layer.
  • the solder joint may be a columnar structure made of metal indium.
  • the qubit component includes a substrate, a superconducting circuit layer, an under-bump metal layer, and a solder joint from bottom to top.
  • the superconducting circuit layer , the UBM layer and the solder joints are prepared layer by layer in sequence.
  • the superconducting circuit layer, the metal niobium metal layer and the solder joint are prepared layer by layer on the substrate; since the metal niobium is a superconducting material, and the metal Niobium is easier to peel off than gold, and has less impact on the cleanliness of the superconducting circuit layer, and the oxide layer on the surface of niobium is easier to remove than the oxide layer on the surface of other superconducting materials, so it is compatible with soldering A better superconducting contact is formed between the dots.
  • the superconducting performance between two planar superconducting quantum chips in the flip-chip superconducting quantum chip can be greatly improved by using metal niobium as the metal layer under the bump.
  • the performance of flip-chip superconducting quantum chips can be improved.
  • FIG. 3 shows a framework diagram of the preparation of the qubit component involved in the present application.
  • the main preparation steps of superconducting metal niobium as the under-bump metal layer of the flip-chip superconducting quantum chip and then preparing indium solder joints can be divided into:
  • FIG. 4 shows a flow chart of a method for preparing a qubit component according to an exemplary embodiment of the present application. As shown in Figure 4, the method may include the following steps:
  • Step 401 preparing a superconducting circuit layer on a substrate.
  • the superconducting circuit layer can be prepared on the substrate through the steps of evaporating superconducting metal, defining the circuit layer by photolithography and developing, and solution etching.
  • the material of the above-mentioned superconducting circuit layer is metal aluminum.
  • the substrate for example, the material of the substrate can be sapphire or high-resistance silicon
  • a layer of superconducting material such as metal aluminum
  • the first photoresist is spin-coated on the superconducting material.
  • the pattern of the superconducting circuit layer is defined on the surface of the superconducting material by means of lithography and development.
  • the substrate contains a layer of superconducting material and the first photoresist on the upper layer of the superconducting material that has not been removed by lithography and development; and then The defined circuit pattern is etched with an acidic solution, and finally the residual first photoresist spin coating is removed by the glue remover and deionized water, and the above-mentioned superconducting circuit layer is retained on the substrate.
  • the above-mentioned first photoresist is a positive photoresist.
  • the above-mentioned photolithography method can be ultraviolet exposure or laser direct writing.
  • the developer mentioned above can be tetramethylammonium hydroxide (Tetramethylammonium Hydroxide, TMAH), or TMAH diluent, etc.
  • TMAH tetramethylammonium Hydroxide
  • TMAH diluent tetramethylammonium Hydroxide
  • AZ6112 photoresist can be spin-coated on the sample (that is, the substrate sample evaporated with superconducting material), and baked at a certain temperature (such as 100°C) for a period of time;
  • the sample is placed in a laser direct writing device (ie, the above-mentioned lithography machine), and a pattern (ie, the pattern corresponding to the above-mentioned superconducting circuit layer) is written with specific parameters; then the sample is placed in a 2.38% TMAH solution for development for a period of time, Then put into deionized water for fixing.
  • development refers to the key step of generating patterns in the photoresist on the surface of the substrate. After the photoresist is exposed, the soluble region can be dissolved by a chemical developer, leaving visible island or window patterns on the substrate surface.
  • the positive photoresist positive photoresist
  • the negative photoresist negative photoresist
  • the negative photoresist in the non-exposed area first forms a gel in the developer, and then decomposes.
  • the photoresist pattern left after development will be used as a mask in subsequent processes such as etching and ion implantation.
  • Step 402 preparing a photoresist covering the superconducting circuit layer on the substrate.
  • a layer of second photoresist can be spin-coated on the substrate, and the second photoresist covers the above-mentioned superconducting circuit layer.
  • the above-mentioned second photoresist and the first photoresist may be photoresists of the same material, or photoresists of different materials.
  • Step 403 removing the photoresist in the first target area on the upper surface of the superconducting circuit layer by photolithography and development; the first target area is the area where the UBM layer is located.
  • the area where the UBM layer needs to be prepared on the upper surface of the superconducting circuit layer i.e. The second photoresist in the above-mentioned first target region
  • the second photoresist in the remaining regions remains.
  • Step 404 after removing the photoresist in the first target region, bake the remaining photoresist on the substrate for a first duration.
  • the duration interval of the first duration is 1 minute to 2 minutes.
  • Step 405 performing etching for a second duration on the first target region and the remaining photoresist on the substrate, where the etching is ion beam etching or chemical etching.
  • FIG. 5 shows a schematic diagram of the preparation of the metal niobium film layer involved in the embodiment of the present application.
  • the niobium film is obtained as a UBM layer by a stripping process; its basic principle is to use a photolithography process to expose the UBM layer growth region, and then use the glue removal solution ( For example, RemoverPG) cleans the photoresist, so that only the grown UBM layer niobium film remains.
  • glue removal solution For example, RemoverPG
  • FIG. 6 shows a comparison diagram of a cracked niobium film under stress and a high-quality niobium film after process optimization involved in the embodiment of the present application.
  • the niobium film on the left side in Figure 6 is cracked, and the photoresist and the niobium film layer on the surface cannot be completely peeled off in the subsequent stripping process, while the niobium film on the right side is not cracked, and the subsequent stripping process In this process, the photoresist and the niobium film layer on its surface can be stripped more cleanly to obtain a high-quality UBM layer.
  • the second photoresist after photolithography and development can be treated to increase the stress of the second photoresist on the niobium film support role.
  • the above-mentioned processing method includes a hardening process (ie, baking on a hot plate after the development is completed), and an etching process.
  • the photoresist can be baked before the photolithography, and the photoresist is no longer baked after the photolithography development is completed; and in the scheme shown in the embodiment of this application, the photoresist can be added After the etching and development are completed, one or more baking operations are performed on the photoresist to improve the supporting effect of the photoresist on the stress of the niobium film.
  • the photoresist can be etched once (such as ion beam etching), so as to form etching marks on the surface of the photoresist and increase the photoresist.
  • the contact area between the resist and the niobium film layer is increased, thereby improving the supporting effect of the photoresist on the stress of the niobium film.
  • the ion beam etching process can increase the support of the photoresist (AZ6112) for the stress of the niobium film; by comparing experimental group 4 and experimental group 5, it can be obtained that the film hardening process can be On the basis of the ion beam etching process, further improve the supporting effect of the photoresist AZ6112 on the stress of the niobium film; by comparing the experimental group 5 and the experimental group 6, it can be obtained that the film hardening time of about 1 minute can improve the photoresist AZ6112 for the stress of the niobium film. Niobium film stress support, so as to meet the growth requirements of the UBM layer.
  • the scheme shown in the embodiment of the present application can set the first duration of baking the remaining photoresist on the substrate to about 1 minute.
  • the first duration can be set as 1 minute or 2 minutes, or, the first duration can also be set to any duration between 1 minute and 2 minutes, so as to ensure the effect of photoresist supporting the stress of the niobium film.
  • the etching method is ion beam etching, and optionally, the above etching method may also be chemical etching.
  • the above step of etching the first target region on the upper surface of the superconducting circuit layer can not only improve the supporting effect of the remaining photoresist on the stress of the niobium film, but also remove the Oxide layer on the first target area of the surface.
  • aluminum As a superconducting metal material, aluminum has a critical transition temperature of 1.196K, and it is easy to form a Josephson junction of aluminum-alumina-aluminum structure, so aluminum is widely used in the preparation of superconducting circuits.
  • a dense oxide layer forms on the surface, which has an insulating effect and affects superconductivity. Therefore, in the embodiment of the present application, before the UBM layer is prepared on the upper layer of the superconducting circuit layer, ion beam etching or chemical etching can be performed on the first target area on the upper surface of the superconducting circuit layer to remove the superconducting circuit layer. An oxide layer on the first target area on the upper surface of the conductive circuit layer.
  • the second etching time ranges from 120 seconds to 180 seconds.
  • the thickness of the oxide layer and the etching time required to etch the oxide layer are calculated by measuring the experimental results of the resistance of the film strips after different etching times for a group of film strip resistances prepared by the aluminum film. time.
  • FIG. 7 shows a schematic diagram of the etching curve involved in the embodiment of the present application.
  • the etching rates for aluminum oxide and aluminum are different, please refer to the etching curves with different slopes in Figure 7, wherein the etching curve 71 is a certain etching condition
  • the second duration of ion beam etching or chemical etching on the first target area and the remaining photoresist on the substrate can be set between 2 minutes and 3 minutes, so that Ensure the removal effect of the oxide layer on the aluminum superconducting circuit layer, while avoiding excessive loss to the aluminum superconducting circuit under the oxide layer, for example, the second duration can be 120s, 150s or 180s, etc. , or, the second duration may also be set to any other duration between 2 minutes and 3 minutes.
  • an UBM layer can be prepared on the first target region on the upper surface of the superconducting circuit layer. Please refer to the subsequent steps for this process.
  • Step 406 preparing a metal niobium film layer on the photoresist and the first target area.
  • a metal niobium film layer is prepared on the photoresist and the first target region, including:
  • a metal niobium film layer is prepared on the photoresist and the first target area by means of magnetron sputtering.
  • the gas pressure of the magnetron sputtering ranges from 8 ⁇ 10 ⁇ 4 torr to 2 ⁇ 10 ⁇ 3 torr.
  • the distance between the niobium target material of magnetron sputtering and the substrate ranges from 8 cm to 12 cm.
  • the power of the magnetron sputtering ranges from 150 watts to 220 watts.
  • the gas flow rate of the magnetron sputtering ranges from 4 standard milliliters/minute to 6 standard milliliters/minute.
  • the growth method of the niobium film may be magnetron sputtering, so as to provide a feasible preparation scheme of the niobium film.
  • the basic principle is that electrons collide with argon molecules under the combined action of electric field and magnetic field to generate argon cations, which bombard the surface of the niobium target, so that the target atoms are evaporated to the substrate surface.
  • gas flow rate, working pressure, distance between target and substrate, and coating power are all parameters that can be adjusted.
  • the gas flow rate, working pressure, distance between the target and the substrate, and coating power may be selected based on the following experimental results.
  • Fig. 8 from left to right are the electron microscope images of the niobium film surface under the working pressure of 10 -3 torr, 5 ⁇ 10 -3 torr, and 10 -2 torr respectively. It can be seen from the above figure that when the working pressure is 10 -3 torr, the surface of the niobium film is in the shape of long strip grains; when the working pressure is 5 ⁇ 10 -3 torr, the surface of the niobium film is elongated. Strip grains and irregular grains coexist; when the working pressure is 10 -2 torr, the surface of the niobium film completely changes to the state of irregular grains.
  • the air pressure of about 10-3 torr can be selected as the working air pressure of the optimized niobium film coating to ensure the coating quality on the surface of the niobium film.
  • the air pressure of 10-3 torr can be selected as the working air pressure.
  • 8 ⁇ 10 -4 torr or 2 ⁇ 10 -3 torr may also be selected as the working air pressure, or any other air pressure between 8 ⁇ 10 -4 torr and 2 ⁇ 10 -3 torr may be selected as the above working air pressure.
  • the experimental design is: keep the gas flow rate 5sccm constant, keep the coating power 150w constant, keep the working pressure 10 -3 torr constant, the distance between the target and the substrate The working distance can be adjusted to 8cm and 10cm. After the coating is completed, its morphology is observed under a scanning electron microscope. Please refer to FIG. 9 , which shows electron microscope images of the surface of the niobium film at different distances involved in the embodiment of the present application.
  • Fig. 9 from left to right are electron microscope images of the surface of the niobium film at working distances of 10 cm and 8 cm, respectively. It can be seen from Figure 9 that when the working distance is 10 cm, the grain size on the surface of the niobium film is smaller and more uniform, while when the working distance is 8 cm, the grain size on the surface of the niobium film becomes larger. Therefore, in the embodiment of the present application, a distance between the target and the substrate of about 10 cm can be selected as the optimized working distance.
  • the distance of 10cm can be selected as the working distance
  • the distance of 8cm or 12cm can be selected as the working distance
  • any other distance between 8cm and 12cm can be selected as the above-mentioned working distance, thereby ensuring the crystal surface of the niobium film. uniformity of grains.
  • the experimental design is: keep the gas flow rate 5sccm constant, keep the working pressure 10 -3 torr constant, keep the working distance between the target and the substrate constant at 10cm, and the coating power is respectively 100w, 150w, 200w, after the coating is completed, observe its morphology under the scanning electron microscope, please refer to Figure 10, which shows the surface electron microscope images of the niobium film under different coating powers involved in the embodiment of the present application.
  • Fig. 10 from left to right are the electron microscope images of the surface of the niobium film under the coating power of 100w, 150w and 200w respectively.
  • FIG. 11 shows a schematic diagram of the superconducting transition temperature of niobium film samples under different coating powers.
  • the coating power can be Combining 150w and 200w to determine, for example, considering the coating efficiency, you can choose a power of about 200w as the coating power. For example, you can directly set the coating power to 200W, or you can choose 150W or 220W as the coating power, or you can choose any other power between 150W and 220W as the above coating power, so as to ensure the coating efficiency .
  • Step 407 removing the photoresist and the metal niobium film layer on the photoresist to obtain the UBM layer on the upper surface of the superconducting circuit layer.
  • an UBM layer of metal niobium material may be left on the upper layer of the superconducting circuit layer.
  • the process of removing the second photoresist and the metal niobium film on the upper layer of the second photoresist may be to clean the sample on which the metal niobium film is vapor-deposited with a glue remover solution and deionized water.
  • the UBM layer After the UBM layer is prepared on the upper layer of the superconducting circuit layer, the UBM layer can be etched to remove the oxide layer on the upper surface of the UBM layer.
  • the above-mentioned etching is ion beam etching or Chemical etching, please refer to the subsequent step 408 to step 410 for the process.
  • the under-bump metal layer is prepared by means of photolithography development, metal niobium film layer preparation, and photoresist cleaning and removal.
  • Step 408 preparing a photoresist covering the superconducting circuit layer and the UBM layer on the substrate.
  • a layer of third photoresist can be spin-coated on the substrate, and the third photoresist covers the above-mentioned bumps. Click on the metal layer.
  • the above-mentioned third photoresist and the first photoresist/second photoresist may be photoresists of the same material, or may be photoresists of different materials.
  • Step 409 removing the photoresist in the second target area on the upper surface of the UBM layer by photolithography and development; the second target area is the area where the solder joints are located.
  • the area where solder joints need to be prepared on the upper surface of the UBM layer that is, the above-mentioned The third photoresist in the second target area
  • the third photoresist in the remaining areas remains.
  • Step 410 etching the second target area on the upper surface of the UBM layer to remove the oxide layer on the second target area on the upper surface of the UBM layer; the above-mentioned etching is ion beam etching or chemical etching .
  • a solution is provided to remove the oxide layer of the second target area on the upper surface of the UBM layer by etching, so as to ensure that the subsequently prepared solder joints can have a gap between the UBM layer and the UBM layer. Good superconducting contacts.
  • the depth of the ion beam etching or chemical etching ranges from 15 nm to 18 nm.
  • the niobium film is used as the UBM layer. After many process steps, the process of removing the oxide layer can be performed, and then the superconducting contact with the indium solder joint can be completed. In order to completely remove the oxide layer at the position of the solder joint on the surface of the niobium film, so that it can form a good superconducting contact with the indium solder joint, the study of the oxidation characteristics of the niobium film is also a key point in the scheme of using the niobium film as the UBM layer of the flip-chip superconducting quantum chip. important part.
  • the resistance of the niobium film under the conditions of coating power of 100w, 150w and 200w were respectively studied, and its characteristic curve of natural oxidation in air was tested.
  • FIG. 12 shows a natural oxidation characteristic curve of the niobium film involved in the embodiment of the present application.
  • the metal layer under the bump can be etched by ion beam or
  • the etching depth in the chemical etching process is set above 15nm, that is to say, in the ion beam etching or chemical etching process, the film layer above 15nm can be removed, so as to ensure the oxidation layer on the surface of the metal layer under the bump.
  • the removal effect ensures the effect of the superconducting contact between the solder joint and the UBM layer.
  • the ion beam etching or chemical etching depth of the UBM layer can be set to 15 nm, 18 nm, or any depth between 15 nm and 18 nm.
  • Step 411 preparing solder joints on the upper surface of the UBM layer to obtain qubit components for flip-chip bonding superconducting quantum chips; the solder joints form a superconducting connection with the UBM layer.
  • a solder joint made of indium material can be prepared on the second target area on the upper surface of the UBM layer.
  • the above-mentioned solder joints may be prepared by evaporation after photolithography and development. At this time, the preparation process of the above-mentioned solder joints may be similar to the preparation process of the UBM layer, which will not be repeated here.
  • the superconducting circuit layer, the metal niobium metal layer and the solder joint are prepared layer by layer on the substrate; since the metal niobium is a superconducting material, and the metal Niobium is easier to peel off and has less impact on the cleanliness of the superconducting circuit layer, and the oxide layer on the surface of niobium is easier to remove than the oxide layer on the surface of other superconducting materials, thus forming a better bond with the solder joints.
  • a flip-chip superconducting quantum chip is also provided, and the flip-chip superconducting quantum chip includes the qubit assembly as shown in FIG. 1 above.
  • the qubit component can be prepared through the method flow shown in FIG. 2 or FIG. 4 .
  • a computer device which includes a flip-chip superconducting quantum chip, and the flip-chip superconducting quantum chip includes the qubit assembly shown in FIG. 1 .
  • the qubit component can be prepared through the method flow shown in FIG. 2 or FIG. 4 .
  • FIG. 13 shows a schematic diagram of an application scenario of a solution provided by an embodiment of the present application.
  • the application scenario may be a superconducting quantum computing platform, and the application scenario includes: a qubit chip 131 , a dilution refrigerator 132 , a control device 133 and a computer 134 .
  • the qubit chip 131 is a circuit acting on a physical qubit, and the qubit chip 131 can be implemented as a quantum computing device.
  • the dilution refrigerator 132 is used to provide an absolute zero environment for the superconducting quantum chip.
  • the above-mentioned qubit chip 131 may be the above-mentioned flip-chip superconducting quantum chip.
  • the control device 133 is used to control the qubit chip 131
  • the computer 134 is used to control the control device 133 .
  • the written quantum program is compiled into an instruction through the software in the computer 134 and sent to the control device 133 (such as an electronic/microwave control system), and the control device 133 converts the above-mentioned instruction into an electronic/microwave control signal and inputs it to the dilution refrigerator 132, Controlling superconducting qubits at temperatures less than 10mK.
  • the reading process is the opposite, and the reading waveform is sent to the qubit chip 131 .
  • FIG. 14 shows a schematic diagram of production line equipment shown in an exemplary embodiment of the present application.
  • the production line equipment includes: an etching machine 1401 , a photolithography machine 1402 and an evaporation machine 1403 .
  • the etching machine 1401 , the photolithography machine 1402 and the evaporation machine 1403 are used for cooperatively preparing the qubit assembly shown in FIG. 1 above.
  • the etching machine 1401, photolithography machine 1402, and evaporation machine 1403 can be used to cooperate to perform the following steps:
  • An UBM layer is prepared on the upper surface of the superconducting circuit layer; the UBM layer forms a superconducting connection with the superconducting circuit layer; the material of the UBM layer is metal niobium;
  • Welding points are prepared on the upper surface of the UBM layer to obtain a qubit assembly for flip-chip welding superconducting quantum chips; the welding points form a superconducting connection with the UBM layer.
  • the evaporation machine 1403 is used to prepare a superconducting circuit layer on the substrate;
  • the photolithography machine 1402, the evaporation machine 1403 and the etching machine 1401 are used to prepare an under bump metal layer on the upper surface of the superconducting circuit layer;
  • the superconducting circuit layer forms a superconducting connection;
  • the metal layer under the bump is made of metal niobium;
  • the photolithography machine 1402, the vapor deposition machine 1403 and the etching machine 1401 are used to prepare solder joints on the upper surface of the UBM layer to obtain quantum chips for flip-chip bonding superconducting quantum chips.
  • a bit component; the solder joint forms a superconducting connection with the UBM layer.
  • an under bump metal layer is prepared on the upper surface of the superconducting circuit layer to prepare an indium solder joint, including:
  • the first target region is the region where the UBM layer is located;
  • the photolithography machine 1402 is used to prepare a photoresist covering the superconducting circuit layer on the substrate; remove the superconducting circuit layer by photolithography development The photoresist of the first target area on the upper surface; the first target area is the area where the UBM layer is located;
  • the evaporation machine 1403 and the etching machine 1401 are used to prepare a metal niobium film layer on the photoresist and the first target area; remove the photoresist and the upper layer of the photoresist A metal niobium film layer is used to obtain the UBM layer located on the upper surface of the superconducting circuit layer.
  • the metal niobium film layer on the photoresist and the first target region before preparing the metal niobium film layer on the photoresist and the first target region, it further includes:
  • the remaining photoresist on the substrate is baked for a first duration.
  • the vapor deposition machine 1403 can be used for removing the photoresist in the first target region and before preparing the metal niobium film layer on the photoresist and the first target region, The remaining photoresist on the substrate is baked for a first period of time.
  • the duration interval of the first duration is 1 minute to 2 minutes.
  • the metal niobium film layer on the photoresist and the first target region before preparing the metal niobium film layer on the photoresist and the first target region, it further includes:
  • etch the remaining photoresist on the first target region and the substrate for a second duration, so as to remove the oxide layer in the first target region and improve the remaining Part of the photoresist supports the stress of the niobium film; the above etching is ion beam etching or chemical etching.
  • the etching machine 1401 can be used for removing the photoresist in the first target area and before preparing the metal niobium film layer on the photoresist and the first target area, for the second A target area and the remaining photoresist on the substrate are subjected to ion beam etching or chemical etching for a second duration.
  • the second duration ranges from 2 minutes to 3 minutes.
  • preparing a metal niobium film layer on the photoresist and the first target region includes:
  • a metal niobium film layer is prepared on the photoresist and the first target region by means of magnetron sputtering.
  • the evaporation machine 1403 and the etching machine 1401 can be used to prepare a metal niobium film layer on the photoresist and the first target region by means of magnetron sputtering.
  • the gas pressure of the magnetron sputtering ranges from 8 ⁇ 10 -4 Torr to 2 ⁇ 10 -3 Torr.
  • the distance between the niobium target material for magnetron sputtering and the substrate ranges from 8 cm to 12 cm.
  • the power of the magnetron sputtering ranges from 150 watts to 220 watts.
  • the gas flow rate of the magnetron sputtering ranges from 4 standard milliliters/minute to 6 standard milliliters/minute.
  • the etching machine 1401 can also be used to etch the UBM layer before preparing solder joints on the upper surface of the UBM layer, so as to remove the UBM layer An oxide layer on the upper surface; the above etching is ion beam etching or chemical etching.
  • the above-mentioned process of etching the UBM layer may include: preparing a photoresist covering the superconducting circuit layer and the UBM layer on the substrate; removing the UBM layer by photolithography and development.
  • the photoresist of the second target area on the upper surface; the second target area is the area where the solder joint is located; ion beam etching or chemical etching is carried out on the second target area on the upper surface of the UBM layer to remove the bump An oxide layer on the second target area on the upper surface of the lower metal layer.
  • the etching depth ranges from 15 nanometers to 18 nanometers.
  • etching machine 1401, photolithography machine 1402 and vapor deposition machine 1403 can refer to the introduction in the embodiment shown in FIG. 2 or FIG.
  • the production line equipment also includes a processor, which can be electrically connected to the etching machine 1401, the photolithography machine 1402, and the vapor deposition machine 1403 respectively, so as to control the etching machine 1401, the photolithography machine Plating machine 1403 and so on.
  • a processor which can be electrically connected to the etching machine 1401, the photolithography machine 1402, and the vapor deposition machine 1403 respectively, so as to control the etching machine 1401, the photolithography machine Plating machine 1403 and so on.
  • the production line equipment also includes a power supply, which is used to supply electrical equipment such as the processor, the etching machine 1401 , the photolithography machine 1402 , and the vapor deposition machine 1403 .
  • the various machines are spatially connected through a conveyor belt, or the movement of the preparation between the various machines is completed based on a robotic arm.
  • the production line equipment further includes a memory, which can be used to store at least one computer instruction, and the processor executes the at least one computer instruction, so that the production line equipment executes the above method for preparing a qubit component.
  • a computer-readable storage medium at least one computer instruction is stored in the computer-readable storage medium, and the at least one computer instruction is executed by a processor in the production line equipment, so that The production line equipment executes the above qubit component preparation method.
  • a computer program product or computer program comprising computer instructions stored in a computer readable storage medium.
  • the processor of the production line equipment reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the production line equipment executes the above-mentioned qubit component preparation method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

一种量子比特组件、量子比特组件制备方法、芯片及设备，涉及微纳加工技术领域。量子比特组件包括：衬底(101)、超导电路层(102)、凸点下金属层(103)以及焊点(104)；所述超导电路层(102)位于所述衬底(101)上；所述凸点下金属层(103)位于所述超导电路层(102)上，且所述凸点下金属层(103)与所述超导电路层(102)形成超导连接；所述凸点下金属层(103)的材质为金属铌；所述焊点(104)位于所述凸点下金属层(103)上，且所述焊点(104)与所述凸点下金属层(103)形成超导连接。上述方案可以提高倒装焊超导量子芯片的性能。

Description

量子比特组件、量子比特组件制备方法、芯片及设备
本申请要求于2021年10月08日提交的、申请号为202111172563.5、发明名称为“量子比特组件、量子比特组件制备方法、芯片及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及微纳加工技术领域，特别涉及一种量子比特组件、量子比特组件制备方法、芯片及设备。
背景技术
倒装焊超导量子芯片封装工艺是一种将两片平面量子芯片通过超导材料焊接，得到倒装焊超导量子芯片的工艺。
在倒装焊超导量子芯片工艺中，在超导电路层和焊点之间通常设置有一层凸点下金属(Under Bump Metal，UBM)层，避免焊点和超导电路层之间形成合金而破坏两者之间的超导电路结构。
发明内容
本申请实施例提供了一种量子比特组件、量子比特组件制备方法、芯片及设备，可以提高倒装焊超导量子芯片的性能，该技术方案如下。
一方面，提供了一种量子比特组件，所述量子比特组件用于倒装焊超导量子芯片；所述量子比特组件包括：衬底、超导电路层、凸点下金属层以及焊点；
所述超导电路层位于所述衬底上；
所述凸点下金属层位于所述超导电路层上，且所述凸点下金属层与所述超导电路层形成超导连接；所述凸点下金属层的材质为金属铌；
所述焊点位于所述凸点下金属层上，且所述焊点与所述凸点下金属层形成超导连接。
另一方面，提供了一种量子比特组件制备方法，由生产线设备执行，所述方法包括：
在衬底上制备超导电路层；
在所述超导电路层的上表面制备凸点下金属层；所述凸点下金属层与所述超导电路层形成超导连接；所述凸点下金属层的材质为金属铌；
在所述凸点下金属层的上表面制备焊点，获得用于倒装焊超导量子芯片的量子比特组件；所述焊点与所述凸点下金属层形成超导连接。
又一方面，提供了一种倒装焊超导量子芯片，所述倒装焊超导量子芯片包含两个如上所述的量子比特组件；
两个所述量子比特组组件之间通过焊点相焊接。
另一方面，提供了一种计算机设备，所述计算机设备包含如上所述的倒装焊超导量子芯片。
另一方面，提供了一种生产线设备，所述生产线设备包括：光刻机、蒸镀机、以及刻蚀机；所述光刻机、所述蒸镀机以及所述刻蚀机用于合作制备如上所述的量子比特组件。
本申请实施例提供的技术方案带来的有益效果至少包括：
通过在用于倒装焊超导量子芯片的量子比特组件中，在超导电路层和焊点之间设置一层材质为金属铌的凸点下金属层，由于金属铌为超导材料，并且，金属铌更容易进行剥离，对超导电路层的洁净度影响更小，并且，铌表面的氧化层相比于其他超导材料表面的氧化层更 容易去除，从而和焊点之间形成更良好的超导接触，因此，通过金属铌作为凸点下金属层，可以极大的提高倒装焊超导量子芯片中两个平面超导量子芯片之间的超导性能，进而提高倒装焊超导量子芯片的性能。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本申请。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。
图1是本申请涉及的量子比特组件的结构示意图；
图2是本申请一示例性实施例示出的量子比特组件制备方法的方法流程图；
图3是本申请涉及的量子比特组件的制备框架图；
图4是本申请一示例性实施例示出的量子比特组件制备方法的方法流程图；
图5是图4所示实施例涉及的金属铌膜层制备示意图；
图6是图4所示实施例涉及的铌膜对比图；
图7是图4所示实施例涉及的刻蚀曲线示意图；
图8是图4所示实施例涉及的不同气压下的铌膜表面电镜图像；
图9是图4所示实施例涉及的不同距离下的铌膜表面电镜图像；
图10是图4所示实施例涉及的不同镀膜功率下的铌膜表面电镜图像；
图11是图4所示实施例涉及的不同镀膜功率下的铌膜样品的超导转变温度示意图；
图12是图4所示实施例涉及的铌膜自然氧化特征曲线图；
图13是本申请一个实施例提供的方案应用场景的示意图；
图14是本申请一示例性实施例示出的生产线设备的示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
量子比特(Qubit)：在量子信息学中是量子信息的计量单位。不同于经典比特只能处于0或1其中一个态，量子比特可以同时处于0和1态，即0和1的量子叠加态。
约瑟夫森结(Josephson Junction)：或称为超导隧道结。一般是由两块超导体夹以某种很薄的势垒层(厚度≤库珀(Cooper)电子对的相干长度)而构成的结构，例如S(Superconductor，超导体)—I(半导体或绝缘体(Insulator))—S(超导体)结构，简称SIS。在约瑟夫森结中，超导电子可以通过隧道效应而从一边穿过半导体或绝缘体薄膜到达另一边。
超导电路：当环境温度降低到一定阈值时，一些材料的电阻会消失，出现超导现象，用这些材料制作的电路结构称为超导电路。
量子芯片：一种基于量子力学规律的芯片，特别地，当所选载体为超导量子电路和约瑟夫森结时，该芯片称为超导量子芯片。
超导量子芯片是可用于研究量子计算的重要载体之一，其一般由衬底、波导膜层(又俗称大电路结构)、量子比特结构、以及其他结构等组成。波导膜层的主要作用为传递控制量子比特的微波和电磁场，从理论上来说，考虑到微波和电磁场的损耗，波导膜层的厚度要相对厚一些比较好，这样做出来的器件性能，如Q值会更佳。由于现阶段量子比特结构以约瑟夫森结为主，其双倾角蒸镀的制备方法限制了结区以及结与外电路连接的超导层厚度，所以大电路的波导膜层厚度也有了相应的限制。
倒装焊超导量子芯片：随着量子比特数目的增加，简单的平面量子芯片设计受制于尺寸大小而难以扩展。由此发展出了倒装焊超导量子芯片封装工艺。其工艺流程主要包括：在用于进行倒装焊工艺的两片芯片(顶片和底片)上分别制作接触焊点；将顶片和底片通过制作好的焊点进行压焊连接。
倒装焊超导量子芯片中的凸点下金属UBM层：在制作顶片和底片的接触焊点过程中，由于顶片和底片的超导电路结构是基于铝膜刻蚀形成的，而接触焊点所用的铟材料与铝材料易形成合金而无法超导，破坏超导电路结构。在制作铟柱焊点过程中，往往会引入UBM层作为铟柱焊点与顶(底)片的媒介。UBM层既需要满足与顶(底)片形成良好超导接触，也需要与铟柱焊点形成良好超导接触。
磁控溅射镀膜：磁控溅射镀膜是一种常见的镀膜方法，其基本原理是电子在电场和磁场的共同作用下与气体分子发生碰撞(通常为氮气分子或者氩气分子)，产生氮阳离子或者氩阳离子，阳离子轰击靶材表面，使得靶材原子蒸镀到衬底表面。
铌：一种超导金属材料，其超导转变温度约为9K。
离子束刻蚀：一种物理刻蚀方法，其基本原理是电子碰撞惰性气体分子(通常为氩气分子)，产生阳离子，阳离子在电场的作用下加速轰击样品表面达到物理刻蚀效果。
本申请实施例所示的方案，提供了一种用于倒装焊超导量子芯片的量子比特组件，比如，该量子比特组件可以是倒装焊超导量子芯片中的一个单片的平面超导量子芯片，或者，该量子比特组件也可以是上述平面超导量子芯片中的一部分。请参考图1，其示出了本申请一示例性实施例示出的量子比特组件的结构示意图。如图1所示，该量子比特组件可以包括衬底101、超导电路层102、凸点下金属层103以及焊点104；
超导电路层102位于衬底101上；
凸点下金属层103位于超导电路层102上，且凸点下金属层103与超导电路层102形成超导连接；凸点下金属层103的材质为金属铌；
焊点104位于凸点下金属层103上，且焊点104与凸点下金属层103形成超导连接。
在一种可能的实现方式中，上述焊点104的材质为金属铟。
在本申请实施例中，使用金属铟作为焊点的材质，能够使得焊点和凸点下金属层之间形成良好的超导接触，提高焊点处的超导效果。
在一种可能的实现方式中，超导电路层102的材质为铝。
在本申请实施例中，金属铟与金属铌之间可以形成良好的超导接触，并且金属铌与超导电路层之间也可以形成良好的超导接触，同时，金属铌作为凸点下金属层，还可以避免金属铟和铝制的超导电路层直接接触形成合金而破坏超导电路结构。
综上所述，本申请实施例所示的方案，通过在用于倒装焊超导量子芯片的量子比特组件中，在超导电路层和焊点之间设置一层材质为金属铌的凸点下金属层，由于金属铌为超导材料，并且，金属铌更容易进行剥离，对超导电路层的洁净度影响更小，并且，铌表面的氧化层相比于其他超导材料表面的氧化层更容易去除，从而和焊点之间形成更良好的超导接触，因此，通过金属铌作为凸点下金属层，可以极大的提高倒装焊超导量子芯片中两个平面超导量子芯片之间的超导性能，进而提高倒装焊超导量子芯片的性能。
本申请上述实施例中，使用超导金属铌作为UBM层，可以应用于倒装焊超导量子芯片(比如2比特倒装焊超导量子芯片，或者49比特倒装焊超导量子芯片等)中，实现多层铝制超导电路层之间的超导线路连接，铌膜作为UBM层能阻碍铝制电路与焊点铟间形成合金从而影响超导连接，同时其优良的刻蚀速率和方便的制备方法也大大提高了多层铝制超导线路连接的效率和性能。
本申请后续实施例提供一种量子比特组件的制备方案。请参考图2，其示出了本申请一 示例性实施例示出的量子比特组件制备方法的方法流程图。如图2所示，该方法可以包括如下步骤：
步骤201，在衬底上制备超导电路层。
其中，上述衬底可以由蓝宝石或者高阻硅构成，超导电路层可以由金属铝构成。
其中，超导电路层中可以包含物理量子比特(比如约瑟夫森结)，以及与物理量子比特相连接的外层电路。
步骤202，在超导电路层的上表面制备凸点下金属层；凸点下金属层与超导电路层形成超导连接；凸点下金属层的材质为金属铌。
步骤203，在凸点下金属层的上表面制备焊点，获得用于倒装焊超导量子芯片的量子比特组件；焊点与凸点下金属层形成超导连接。
在本申请实施例中，焊点可以是金属铟构成的柱形结构。
在本申请实施例中，量子比特组件从下到上分别包含衬底、超导电路层、凸点下金属层以及焊点，相应的，在制备该量子比特组件时，也按照超导电路层、凸点下金属层以及焊点的顺序逐层进行制备。
综上所述，本申请实施例所示的方案，在衬底上逐层制备超导电路层、金属铌材质的凸点下金属层以及焊点；由于金属铌为超导材料，并且，金属铌相比于金材质来说更容易进行剥离，对超导电路层的洁净度影响更小，并且，铌表面的氧化层相比于其他超导材料表面的氧化层更容易去除，从而和焊点之间形成更良好的超导接触，因此，通过金属铌作为凸点下金属层，可以极大的提高倒装焊超导量子芯片中两个平面超导量子芯片之间的超导性能，进而提高倒装焊超导量子芯片的性能。
请参考图3，其示出了本申请涉及的量子比特组件的制备框架图。如图3所示，在本申请上述实施例中，超导金属铌作为倒装焊超导量子芯片的凸点下金属层进而制备铟焊点的主要制备步骤可以分为：
光刻显影定义UBM层图形(S31)、坚膜工艺提高光刻胶对铌膜应力的支持(S32)、刻蚀去除铝膜表面的氧化层(S33)、高质量铌膜的生长(S34)、铌膜剥离(S35)、光刻显影定义焊点层图形(S36)、刻蚀去除铌膜表面的氧化层(S37)、以及焊点制备(S38)。
结合上述图3，请参考图4，其示出了本申请一示例性实施例示出的量子比特组件制备方法的方法流程图。如图4所示，该方法可以包括如下步骤：
步骤401，在衬底上制备超导电路层。
在本申请实施例中，可以通过蒸镀超导金属，光刻显影定义电路层及溶液刻蚀的步骤在衬底上制备超导电路层。
其中，上述超导电路层的材质为金属铝。
比如，首先在衬底(比如，衬底的材质可以是蓝宝石或者高阻硅)上蒸镀一层超导材料(比如金属铝)，然后在超导材料上层旋涂第一光刻胶，通过光刻显影的方式在超导材料表面定义出超导电路层的图形，此时衬底上包含一层超导材料，以及超导材料上层未被光刻显影去除的第一光刻胶；然后使用酸性溶液蚀刻定义出来的电路图形，最后通过去胶液和去离子水去除残留的第一光刻胶旋涂，并在衬底上保留上述超导电路层。
其中，上述的第一光刻胶是正性光刻胶。
上述的光刻方式可以为紫外曝光或者激光直写。
上述的显影液可以为四甲基氢氧化铵(Tetramethylammonium Hydroxide，TMAH)，或TMAH稀释液等等。
比如，在本申请实施例中，可以在样品(即蒸镀有超导材料的衬底样品)上旋涂AZ6112光刻胶，并以一定的温度(比如100℃)烘烤一段时间；然后将样品放入激光直写设备(即上述光刻机)中，以特定参数刻写出图形(即上述超导电路层对应的图形)；然后将样品置于 2.38％的TMAH溶液中显影一段时间，接着放入去离子水中进行定影。
其中，显影是指在衬底表面光刻胶中产生图形的关键步骤。光刻胶经过曝光后可溶解区域可以被化学显影剂溶解，并将可见的岛或者窗口图形留在衬底表面。对于正胶(正性光刻胶)来说，在显影过程中，非曝光区的光刻胶由于在曝光时并未发生化学反应，在显影时也就不会存在酸碱中和，因此非曝光区的光刻胶将被保留下来，而经过曝光的正性光刻胶会被逐渐溶解。对于负胶(负性光刻胶)来说，非曝光区的负胶在显影液中首先形成凝胶体，然后再分解。显影后留下的光刻胶图形将在后续的刻蚀和离子注入等工艺中作为掩模。
步骤402，在衬底上制备覆盖超导电路层的光刻胶。
在本申请实施例中，在衬底上制备好超导电路层之后，即可以在衬底上旋涂一层第二光刻胶，该第二光刻胶覆盖上述超导电路层。
其中，上述第二光刻胶和第一光刻胶可以是相同材质的光刻胶，也可以是不同材质的光刻胶。
步骤403，通过光刻显影的方式去除超导电路层上表面的第一目标区域的光刻胶；第一目标区域是凸点下金属层所在的区域。
在本步骤中，在旋涂了覆盖超导电路层的第二光刻胶之后，可以通过光刻显影的方式，将超导电路层上表面上，需要制备凸点下金属层的区域(即上述第一目标区域)的第二光刻胶去除，并保留其余区域的第二光刻胶。
步骤404，在去除第一目标区域的光刻胶之后，对衬底上剩余的光刻胶进行第一时长的烘烤。
在一种可能的实现方式中，第一时长所在的时长区间为1分钟至2分钟。
步骤405，对第一目标区域及衬底上剩余的光刻胶进行第二时长的刻蚀，上述刻蚀为离子束刻蚀或化学刻蚀。
请参考图5，其示出了本申请实施例涉及的金属铌膜层制备示意图。如图5所示，在本申请实施例中，铌膜作为UBM层，是通过剥离的工艺获得的；其基本原理为利用光刻工艺露出UBM层生长区域，镀膜完成后再使用去胶液(比如RemoverPG)清洗掉光刻胶，从而只保留生长的UBM层铌膜。
在实际镀膜过程中，由于铌膜表面存在很大的应力，如果没有做很好的样品表面处理，铌膜层应力会导致膜层龟裂，这会导致后续对光刻胶进行剥离的过程中，无法将光刻胶及其表面的铌膜层完全剥离，从而影响超导电路的洁净度，降低超导量子芯片的性能。请参考图6，其示出了本申请实施例涉及的应力作用下龟裂的铌膜和工艺优化后高质量的铌膜对比图。其中，图6中左侧的铌膜发生龟裂，后续剥离过程中将无法完全的对光刻胶及其表面的铌膜层进行剥离，而右侧的铌膜未发生龟裂，后续剥离过程中，可以更干净地剥离光刻胶及其表面的铌膜层，获得高质量的UBM层。
对于上述问题，在本申请实施例所示的方案中，可以在制备金属铌膜层之前，对光刻显影之后的第二光刻胶进行处理，以提高第二光刻胶对铌膜的应力的支持作用。其中，上述处理方式包括坚膜工艺(即显影完成后在热板上进行烘烤)，以及刻蚀工艺。
在通常情况下，在光刻之前可以对光刻胶进行烘烤，而光刻显影完成后不再对光刻胶进行烘烤；而在本申请实施例所示的方案中，可以增加在光刻显影完成后，再对光刻胶进行一次或多次烘烤的操作，以提高光刻胶对铌膜的应力的支持作用。
此外，本申请实施例所示的方案，还可以在光刻显影完成后，对光刻胶进行一次刻蚀(比如离子束刻蚀)，从而在光刻胶表面形成刻蚀痕迹，增大光刻胶与铌膜层的接触面积，从而提高光刻胶对铌膜的应力的支持作用。
请参考下述表1，以光刻胶为AZ6112光刻胶为例，其示出了本申请实施例涉及的铌膜应力作用下薄膜龟裂的时间表。
表1
Figure PCTCN2021135752-appb-000001
通过比较实验组3和实验组4可以得到，离子束刻蚀工艺能够增加光刻胶(AZ6112)对于铌膜应力的支持作用；通过比较实验组4和实验组5可以得到，坚膜工艺可以在离子束刻蚀工艺的基础上，进一步提高光刻胶AZ6112对于铌膜应力的支持作用；通过比较实验组5和实验组6可以得到，坚膜时间在1分钟左右即可以提升光刻胶AZ6112对于铌膜应力的支持，从而满足UBM层的生长需求。
基于上述表1所示的实验数据，本申请实施例所示的方案可以将对衬底上剩余的光刻胶进行烘烤的第一时长设置为1分钟左右，比如，可以设置第一时长为1分钟或者2分钟，或者，也可以设置第一时长为1分钟至2分钟之间的任意时长，从而可以保证光刻胶对铌膜的应力的支持的效果。
其中，上述表1中的实验数据中，刻蚀方式为离子束刻蚀，可选的，上述刻蚀方式也可以为化学刻蚀。
本申请实施例中，上述对超导电路层上表面的第一目标区域进行刻蚀的步骤除了可以改善剩余的光刻胶对铌膜应力的支持作用之外，还可以去除超导电路层上表面的第一目标区域的氧化层。
铝作为一种超导金属材料，其临界转变温度为1.196K，其易于形成铝-氧化铝-铝结构的约瑟夫森结，因此铝被广泛应用于超导电路制备。
铝制材料暴露在空气中时，会在表面形成一层致密的氧化层，该氧化层具有绝缘作用，会影响超导性能。因此，在本申请实施例中，在超导电路层的上层制备凸点下金属层之前，可以对超导电路层上表面的第一目标区域进行离子束刻蚀或者化学刻蚀，以去除超导电路层上表面的第一目标区域的氧化层。
在一种可能的实现方式中，刻蚀的第二时长的范围为120秒至180秒。
本申请实施例中，通过铝膜制备的一组膜条电阻，通过测量其不同刻蚀时间后的膜条电阻的实验结果，进而推算出氧化层厚度和刻蚀掉氧化层所需要的刻蚀时间。该方法原理为刻蚀后电阻值/刻蚀前电阻值＝刻蚀前铝膜厚度/刻蚀后铝膜厚度≈刻蚀前铝和氧化铝的总厚度/刻蚀后铝和氧化铝的总厚度。
请参考图7，其示出了本申请实施例涉及的刻蚀曲线示意图。如图7所示，对于相同刻蚀条件的离子源，对氧化铝和铝的刻蚀速率不同，请参考图7中不同斜率的刻蚀曲线，其中，刻蚀曲线71是某个刻蚀条件下的离子源对氧化铝进行刻蚀时的刻蚀厚度和刻蚀时间的曲线，其对应关系为y＝0.0617x；其中，y为刻蚀厚度，x为刻蚀时间；刻蚀曲线72是相同刻蚀条件下该离子源对铝进行刻蚀时的刻蚀厚度和刻蚀时间的曲线，其对应关系为y＝0.1583x-9.765；刻蚀曲线71和刻蚀曲线72相交的时间点(101.087s)可以视为氧化层刚好被刻蚀掉的时间，基于上述实验结果，取150s左右的时长作为刻蚀时间(即上述第二时长)，保证铝与铌的超导接触。比如，本申请实施例所示的方案可以将对第一目标区域及衬底上剩余的光刻胶进行离子束刻蚀或者化学刻蚀的第二时长设置在2分钟至3分钟之间，从而保证对铝制的超导电路层上的氧化层的去除效果，同时避免对氧化层下的铝制超导电路造成过多的损耗，比如，该第二时长可以是120s、150s或者180s等等，或者，也可以设置第二时长为2分钟至3分 钟之间的其它任意时长。
在去除超导电路层上表面的第一目标区域的氧化层之后，即可以在超导电路层的上表面的第一目标区域制备凸点下金属层，该过程请参考后续步骤。
步骤406，在光刻胶以及第一目标区域上制备金属铌膜层。
在一种可能的实现方式中，在光刻胶以及第一目标区域上制备金属铌膜层，包括：
通过磁控溅射的方式，在光刻胶以及第一目标区域上制备金属铌膜层。
在一种可能的实现方式中，磁控溅射的气压的范围为8×10 -4托至2×10 -3托(torr)。
在一种可能的实现方式中，磁控溅射的铌靶材与衬底之间的距离的范围为8厘米至12厘米。
在一种可能的实现方式中，磁控溅射的功率的范围为150瓦至220瓦。
在一种可能的实现方式中，磁控溅射的气体流量的范围为4标准毫升/分钟至6标准毫升/分钟。
本申请实施例中，铌膜的生长方式可以是磁控溅射，从而提供一种可实现的铌膜制备方案。其基本原理是电子在电场和磁场的共同作用下与氩气分子发生碰撞，产生氩阳离子，阳离子轰击铌靶材表面，使得靶材原子蒸镀到衬底表面。在磁控溅射镀膜过程中，气体流量、工作气压、靶与衬底距离、镀膜功率都是可以调节的参数。
在本申请实施例中，可以基于以下实验结果来选择上述气体流量、工作气压、靶与衬底距离、镀膜功率。
1)通过第一组实验确定工作气压，其实验设计为：保持气体流量5标准毫升/分钟(standard cubic centimeter per minute，sccm)不变，保持靶与衬底距离10cm不变，镀膜功率150w不变，工作气压分为10 -3torr，5×10 -3torr，10 -2torr。镀膜完成后在扫描电镜下观察其形貌，请参考图8，其示出了本申请实施例涉及的不同气压下的铌膜表面电镜图像。
在图8中，从左到右分别是在10 -3torr，5×10 -3torr，10 -2torr的工作气压下，铌膜表面的电镜图像。从上图中可以看出，当工作气压为10 -3torr时，铌膜的表面为有序的长条晶粒状；当工作气压为5×10 -3torr时，铌膜的表面为长条晶粒与不规则的晶粒共存的状态；当工作气压为10 -2torr时，铌膜的表面完全变为不规则的晶粒状态。由此，本申请实施例可以选择10 -3torr左右的气压作为优化后的铌膜镀膜的工作气压，以保证铌膜表面的镀膜质量，比如，可以选择10 -3torr的气压作为工作气压，也可以选择8×10 -4torr或者2×10 -3torr作为工作气压，或者，也可以选择8×10 -4torr至2×10 -3torr之间的任意其它气压作为上述工作气压。
2)通过第二组实验确定靶与衬底的工作距离，其实验设计为：保持气体流量5sccm不变，保持镀膜功率150w不变，保持工作气压10 -3torr不变，靶与衬底的工作距离调节至8cm和10cm。镀膜完成后在扫描电镜下观察其形貌，请参考图9，其示出了本申请实施例涉及的不同距离下的铌膜表面电镜图像。
在图9中，从左到右分别是在10cm和8cm的工作距离下，铌膜表面的电镜图像。从图9中可以看出，当工作距离为10cm时，铌膜表面的晶粒尺寸更小，更均匀一些，而工作距离为8cm时，铌膜表面的晶粒尺寸变大。由此，本申请实施例可以选定10cm左右的靶与衬底之间的距离作为优化后的工作距离。比如，可以选择10cm的距离作为工作距离，也可以选择8cm或者12cm的距离作为工作距离，或者，也可以选择8cm至12cm之间的任意其它距离作为上述工作距离，从而保证了铌膜表面的晶粒的均匀程度。
3)通过第三组实验确定镀膜功率，其实验设计为：保持气体流量5sccm不变，保持工作气压10 -3torr不变，保持靶与衬底的工作距离为10cm不变，镀膜功率分别为100w，150w，200w，镀膜完成后在扫描电镜下观察其形貌，请参考图10，其示出了本申请实施例涉及的不同镀膜功率下的铌膜表面电镜图像。
在图10中，从左到右分别是在100w、150w和200w的镀膜功率下，铌膜表面的电镜图像。
从图10中来看，扫描电镜下，几个不同镀膜功率下的铌膜表面并没有较大区别，为了进一步确认优化后的镀膜功率，分别测试上述三种不同镀膜功率下的铌膜样品的超导转变温度，请参考图11，其示出了不同镀膜功率下的铌膜样品的超导转变温度示意图。
由图11可以看出，在100w的镀膜功率下，铌膜的超导转变温度为6.9K，而在150w和200w镀膜功率下，铌膜的超导转变温度为8K左右，因此，镀膜功率可以结合150w和200w来确定，比如，考虑到镀膜效率，可选选择200w左右的功率作为镀膜功率。比如，可以直接将镀膜功率设置为200W，或者，也可以选择150W或者220W的功率作为镀膜功率，或者，也可以选择150W至220W之间的任意其它功率作为上述镀膜功率，从而保证了镀膜的效率。
步骤407，去除光刻胶以及光刻胶上层的金属铌膜层，获得位于超导电路层上表面的凸点下金属层。
在本申请实施例中，在去除第二光刻胶以及第二光刻胶上层的金属铌膜之后，可以在超导电路层的上层留下金属铌材料的凸点下金属层。
其中，去除第二光刻胶以及第二光刻胶上层的金属铌膜的过程，可以是通过去胶液和去离子水对蒸镀了金属铌膜的样品进行清洗。
在超导电路层的上层制备了凸点下金属层之后，即可以对凸点下金属层进行刻蚀，以去除凸点下金属层上表面的氧化层，上述刻蚀为离子束刻蚀或化学刻蚀，该过程请见后续步骤408至步骤410。
本申请实施例中，通过光刻显影、金属铌膜层制备以及光刻胶清洗去除的方式，实现了凸点下金属层的制备。
步骤408，在衬底上制备覆盖超导电路层以及凸点下金属层的光刻胶。
在本申请实施例中，在衬底上制备好超导电路层和凸点下金属层之后，即可以在衬底上旋涂一层第三光刻胶，该第三光刻胶覆盖上述凸点下金属层。
其中，上述第三光刻胶和第一光刻胶/第二光刻胶可以是相同材质的光刻胶，也可以是不同材质的光刻胶。
步骤409，通过光刻显影的方式去除凸点下金属层上表面的第二目标区域的光刻胶；第二目标区域是焊点所在的区域。
在本步骤中，在旋涂了覆盖凸点下金属层的第三光刻胶之后，可以通过光刻显影的方式，将凸点下金属层上表面上，需要制备焊点的区域(即上述第二目标区域)的第三光刻胶去除，并保留其余区域的第三光刻胶。
步骤410，对凸点下金属层上表面的第二目标区域进行刻蚀，以去除凸点下金属层上表面的第二目标区域的氧化层；上述刻蚀为离子束刻蚀或化学刻蚀。
本申请实施例中，提供了一种通过刻蚀的方式去除凸点下金属层上表面的第二目标区域的氧化层的方案，保证后续制备的焊点能够与凸点下金属层之间具有良好的超导接触。
在一种可能的实现方式中，离子束刻蚀或化学刻蚀的深度的范围为15纳米至18纳米。
在倒装焊超导量子芯片中，铌膜作为UBM层，会经历很多工艺步骤后再做去除氧化层的工艺，之后才能完成与铟质焊点的超导接触。为完全去除铌膜上表面焊点位置的氧化层，使其与铟质焊点形成良好的超导接触，研究铌膜的氧化特性也是铌膜作为倒装焊超导量子芯片UBM层方案中的重要一环。本申请实施例中，分别研究了镀膜功率为100w，150w和200w情况下的铌膜电阻，测试了其在空气中自然氧化的特征曲线。请参考图12，其示出了本申请实施例涉及的铌膜自然氧化特征曲线图。
如图12所示，其中包含了氧化层厚度-天数的关系曲线，由上述图12可以看出，随着时间的推移，铌膜的氧化曲线越来越平缓，在三种不同的功率情况下，30天后铌膜表面氧化层的厚度均在10nm左右，为保证铌膜氧化层厚度完全去除，在本申请实施例所示的方案中，可以将对凸点下金属层进行离子束刻蚀或者化学刻蚀工艺中的刻蚀深度设置在15nm以上，也就是说，在离子束刻蚀或者化学刻蚀工艺中，可以去除15nm以上的膜层，从而保证凸点 下金属层表面的氧化层的去除效果，保证了焊点与凸点下金属层之间的超导接触的效果。
比如，在本申请实施例中，可以将对凸点下金属层进行离子束刻蚀或者化学刻蚀的深度设置为15nm、18nm或者15nm至18nm之间的任意深度。
步骤411，在凸点下金属层的上表面制备焊点，获得用于倒装焊超导量子芯片的量子比特组件；焊点与凸点下金属层形成超导连接。
在本申请实施例中，在去除凸点下金属层的上表面的第二目标区域的氧化层之后，即可以在凸点下金属层的上表面的第二目标区域制备铟材质的焊点。
在一种可能的实现方式中，可以通过光刻显影后蒸镀的方式制备上述焊点。此时，上述焊点的制备过程，可以与凸点下金属层的制备过程类似，此处不再赘述。
综上所述，本申请实施例所示的方案，在衬底上逐层制备超导电路层、金属铌材质的凸点下金属层以及焊点；由于金属铌为超导材料，并且，金属铌更容易进行剥离，对超导电路层的洁净度影响更小，并且，铌表面的氧化层相比于其他超导材料表面的氧化层更容易去除，从而和焊点之间形成更良好的超导接触，因此，通过金属铌作为凸点下金属层，可以极大的提高倒装焊超导量子芯片中两个平面超导量子芯片之间的超导性能，进而提高倒装焊超导量子芯片的性能。
在本申请的一个示例性实施例中，还提供一种倒装焊超导量子芯片，该倒装焊超导量子芯片包含如上述图1所示的量子比特组件。该量子比特组件可以通过图2或图4所示的方法流程进行制备。
在本申请的一个示例性实施例中，还提供一种计算机设备，该计算机设备包含倒装焊超导量子芯片，该倒装焊超导量子芯片包含图1所示的量子比特组件。该量子比特组件可以通过图2或图4所示的方法流程进行制备。
请参考图13，其示出了本申请一个实施例提供的方案应用场景的示意图。如图13所示，该应用场景可以是超导量子计算平台，该应用场景包括：量子比特芯片131、稀释制冷机132、控制设备133和计算机134。
量子比特芯片131是一种作用在物理量子比特上的电路，量子比特芯片131可以实现成为量子计算器件。稀释制冷机132用于为超导量子芯片提供绝对零度的环境。其中，上述量子比特芯片131可以是上述的倒装焊超导量子芯片。
控制设备133用于对量子比特芯片131进行控制，计算机134用于对控制设备133进行控制。例如，编写好的量子程序经过计算机134中的软件编译成指令发送给控制设备133(如电子/微波控制系统)，控制设备133将上述指令转换为电子/微波控制信号输入到稀释制冷机132，控制处于小于10mK温度的超导量子比特。读取的过程则与之相反，读取波形被输送到量子比特芯片131。
图14示出了本申请一示例性实施例示出的生产线设备的示意图，如图14所示，该生产线设备包括：刻蚀机1401、光刻机1402以及蒸镀机1403。该刻蚀机1401、光刻机1402以及蒸镀机1403用于合作制备上述图1所示的量子比特组件。
可选的，该刻蚀机1401、光刻机1402以及蒸镀机1403可以用于协作执行以下步骤：
在衬底上制备超导电路层；
在所述超导电路层的上表面制备凸点下金属层；所述凸点下金属层与所述超导电路层形成超导连接；所述凸点下金属层的材质为金属铌；
在所述凸点下金属层的上表面制备焊点，获得用于倒装焊超导量子芯片的量子比特组件；所述焊点与所述凸点下金属层形成超导连接。
例如，在本申请实施例中，所述蒸镀机1403，用于在衬底上制备超导电路层；
所述光刻机1402、所述蒸镀机1403以及所述刻蚀机1401，用于在所述超导电路层的上表面制备凸点下金属层；所述凸点下金属层与所述超导电路层形成超导连接；所述凸点下金 属层的材质为金属铌；
所述光刻机1402、所述蒸镀机1403以及所述刻蚀机1401，用于在所述凸点下金属层的上表面制备焊点，获得用于倒装焊超导量子芯片的量子比特组件；所述焊点与所述凸点下金属层形成超导连接。
在一种可能的实现方式中，在超导电路层的上表面制备凸点下金属层进而制备铟焊点，包括：
在所述衬底上制备覆盖所述超导电路层的光刻胶；
通过光刻显影的方式去除所述超导电路层上表面的第一目标区域的光刻胶；所述第一目标区域是所述凸点下金属层所在的区域；
在所述光刻胶以及所述第一目标区域上制备金属铌膜层；
去除所述光刻胶以及所述光刻胶上层的金属铌膜层，获得位于所述超导电路层上表面的所述凸点下金属层。
例如，在本申请实施例中，所述光刻机1402，用于在所述衬底上制备覆盖所述超导电路层的光刻胶；通过光刻显影的方式去除所述超导电路层上表面的第一目标区域的光刻胶；所述第一目标区域是所述凸点下金属层所在的区域；
所述蒸镀机1403以及所述刻蚀机1401，用于在所述光刻胶以及所述第一目标区域上制备金属铌膜层；去除所述光刻胶以及所述光刻胶上层的金属铌膜层，获得位于所述超导电路层上表面的所述凸点下金属层。
在一种可能的实现方式中，在所述光刻胶以及所述第一目标区域上制备金属铌膜层之前，还包括：
在去除所述第一目标区域的光刻胶之后，对所述衬底上剩余的光刻胶进行第一时长的烘烤。
其中，所述蒸镀机1403，可以用于在去除所述第一目标区域的光刻胶之后，且在所述光刻胶以及所述第一目标区域上制备金属铌膜层之前，对所述衬底上剩余的光刻胶进行第一时长的烘烤。
在一种可能的实现方式中，所述第一时长所在的时长区间为1分钟至2分钟。
在一种可能的实现方式中，在所述光刻胶以及所述第一目标区域上制备金属铌膜层之前，还包括：
在去除所述第一目标区域的光刻胶之后，对第一目标区域及所述衬底上剩余的光刻胶进行第二时长的刻蚀，以去除第一目标区域的氧化层及提高剩余部分光刻胶对铌膜应力的支持作用；上述刻蚀为离子束刻蚀或者化学刻蚀。
其中，所述刻蚀机1401，可以用于在去除所述第一目标区域的光刻胶之后，且在所述光刻胶以及所述第一目标区域上制备金属铌膜层之前，对第一目标区域及所述衬底上剩余的光刻胶进行第二时长的离子束刻蚀或者化学刻蚀。
在一种可能的实现方式中，所述第二时长的范围为2分钟至3分钟。
在一种可能的实现方式中，在所述光刻胶以及所述第一目标区域上制备金属铌膜层，包括：
通过磁控溅射的方式，在所述光刻胶以及所述第一目标区域上制备金属铌膜层。
其中，所述蒸镀机1403以及所述刻蚀机1401，可以用于通过磁控溅射的方式，在所述光刻胶以及所述第一目标区域上制备金属铌膜层。
在一种可能的实现方式中，磁控溅射的气压的范围为8×10 -4托至2×10 -3托。
在一种可能的实现方式中，磁控溅射的铌靶材与所述衬底之间的距离的范围为8厘米至12厘米。
在一种可能的实现方式中，磁控溅射的功率的范围为150瓦至220瓦。
在一种可能的实现方式中，磁控溅射的气体流量的范围为4标准毫升/分钟至6标准毫升 /分钟。
在一种可能的实现方式中，在所述凸点下金属层的上表面制备焊点之前，还包括：
对所述凸点下金属层进行刻蚀，以去除所述凸点下金属层上表面的氧化层。
其中，所述刻蚀机1401，还可以用于在所述凸点下金属层的上表面制备焊点之前，对所述凸点下金属层进行刻蚀，以去除所述凸点下金属层上表面的氧化层；上述刻蚀为离子束刻蚀或者化学刻蚀。
其中，上述对凸点下金属层进行刻蚀的过程可以包括：在衬底上制备覆盖超导电路层以及凸点下金属层的光刻胶；通过光刻显影的方式去除凸点下金属层上表面的第二目标区域的光刻胶；第二目标区域是焊点所在的区域；对凸点下金属层上表面的第二目标区域进行离子束刻蚀或者化学刻蚀，以去除凸点下金属层上表面的第二目标区域的氧化层。
在一种可能的实现方式中，所述刻蚀的深度的范围为15纳米至18纳米。
其中，上述刻蚀机1401、光刻机1402以及蒸镀机1403制备量子比特组件的过程可以参考图2或图4所示的实施例中的介绍，此处不再赘述。
可选的，该生产线设备还包括处理器，该处理器可以与刻蚀机1401、光刻机1402以及蒸镀机1403分别电性相连，用以控制刻蚀机1401、光刻机1402以及蒸镀机1403等等。
可选的，该生产线设备还包括电源，用以为处理器、刻蚀机1401、光刻机1402以及蒸镀机1403等电学设备进行电量供应。
可选的，各个机器之间通过传送带进行空间连接，或者基于机械臂完成制备物在各个机器间的移动。
可选的，该生产线设备还包括存储器，该存储器可用于存储至少一条计算机指令，处理器执行上述至少一条计算机指令，以使得生产线设备执行上述量子比特组件制备方法。
在一个示例性实施例中，还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有至少一条计算机指令，该至少一条计算机指令在被生产线设备中的处理器执行，以使得生产线设备执行上述量子比特组件制备方法。
在示例性实施例中，还提供了一种计算机程序产品或计算机程序，该计算机程序产品或计算机程序包括计算机指令，该计算机指令存储在计算机可读存储介质中。生产线设备的处理器从计算机可读存储介质读取该计算机指令，处理器执行该计算机指令，使得生产线设备执行上述量子比特组件制备方法。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由权利要求指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。

Claims (31)

  1. 一种量子比特组件，所述量子比特组件用于倒装焊超导量子芯片；所述量子比特组件包括：衬底、超导电路层、凸点下金属层以及焊点；
    所述超导电路层位于所述衬底上；
    所述凸点下金属层位于所述超导电路层上，且所述凸点下金属层与所述超导电路层形成超导连接；所述凸点下金属层的材质为金属铌；
    所述焊点位于所述凸点下金属层上，且所述焊点与所述凸点下金属层形成超导连接。
  2. 根据权利要求1所述的量子比特组件，所述焊点的材质为金属铟。
  3. 一种量子比特组件制备方法，由生产线设备执行，所述方法包括：
    在衬底上制备超导电路层；
    在所述超导电路层的上表面制备凸点下金属层；所述凸点下金属层与所述超导电路层形成超导连接；所述凸点下金属层的材质为金属铌；
    在所述凸点下金属层的上表面制备焊点，获得用于倒装焊超导量子芯片的量子比特组件；所述焊点与所述凸点下金属层形成超导连接。
  4. 根据权利要求3所述的方法，在所述超导电路层的上表面制备凸点下金属层，包括：
    在所述衬底上制备覆盖所述超导电路层的光刻胶；
    通过光刻显影的方式去除所述超导电路层上表面的第一目标区域的光刻胶；所述第一目标区域是所述凸点下金属层所在的区域；
    在所述光刻胶以及所述第一目标区域上制备金属铌膜层；
    去除所述光刻胶以及所述光刻胶上层的金属铌膜层，获得位于所述超导电路层上表面的所述凸点下金属层。
  5. 根据权利要求4所述的方法，在所述光刻胶以及所述第一目标区域上制备金属铌膜层之前，还包括：
    在去除所述第一目标区域的光刻胶之后，对所述衬底上剩余的光刻胶进行第一时长的烘烤。
  6. 根据权利要求5所述的方法，所述第一时长所在的时长区间为1分钟至2分钟。
  7. 根据权利要求4所述的方法，在所述光刻胶以及所述第一目标区域上制备金属铌膜层之前，还包括：
    在去除所述第一目标区域的光刻胶之后，对第一目标区域及所述衬底上剩余的光刻胶进行第二时长的刻蚀，所述刻蚀为离子束刻蚀或化学刻蚀。
  8. 根据权利要求7所述的方法，所述第二时长的范围为2分钟至3分钟。
  9. 根据权利要求4所述的方法，在所述光刻胶以及所述第一目标区域上制备金属铌膜层，包括：
    通过磁控溅射的方式，在所述光刻胶以及所述第一目标区域上制备金属铌膜层。
  10. 根据权利要求9所述的方法，磁控溅射的气压的范围为8×10 -4托至2×10 -3托。
  11. 根据权利要求9所述的方法，磁控溅射的铌靶材与所述衬底之间的距离的范围为8厘米至12厘米。
  12. 根据权利要求9所述的方法，磁控溅射的功率的范围为150瓦至220瓦。
  13. 根据权利要求9所述的方法，磁控溅射的气体流量的范围为4标准毫升/分钟至6标准毫升/分钟。
  14. 根据权利要求3所述的方法，在所述凸点下金属层的上表面制备焊点之前，还包括：
    对所述凸点下金属层进行刻蚀，以去除所述凸点下金属层上表面的氧化层，所述刻蚀为离子束刻蚀或化学刻蚀。
  15. 根据权利要求14所述的方法，所述刻蚀的深度的范围为15纳米至18纳米。
  16. 一种倒装焊超导量子芯片，所述倒装焊超导量子芯片包含两个如权利要求1或2所述的量子比特组件；
    两个所述量子比特组组件之间通过焊点相焊接。
  17. 一种计算机设备，所述计算机设备包含如权利要求16所述的倒装焊超导量子芯片。
  18. 一种生产线设备，所述生产线设备包括：光刻机、蒸镀机、以及刻蚀机；所述光刻机、所述蒸镀机以及所述刻蚀机用于合作制备如权利要求1或2所述的量子比特组件。
  19. 根据权利要求18所述的生产线设备，
    所述蒸镀机，用于在衬底上制备超导电路层；
    所述光刻机、所述蒸镀机以及所述刻蚀机，用于在所述超导电路层的上表面制备凸点下金属层；所述凸点下金属层与所述超导电路层形成超导连接；所述凸点下金属层的材质为金属铌；
    所述光刻机、所述蒸镀机以及所述刻蚀机，用于在所述凸点下金属层的上表面制备焊点，获得用于倒装焊超导量子芯片的量子比特组件；所述焊点与所述凸点下金属层形成超导连接。
  20. 根据权利要求19所述的生产线设备，
    所述光刻机，用于在所述衬底上制备覆盖所述超导电路层的光刻胶；通过光刻显影的方式去除所述超导电路层上表面的第一目标区域的光刻胶；所述第一目标区域是所述凸点下金属层所在的区域；
    所述蒸镀机以及所述刻蚀机，用于在所述光刻胶以及所述第一目标区域上制备金属铌膜层；去除所述光刻胶以及所述光刻胶上层的金属铌膜层，获得位于所述超导电路层上表面的所述凸点下金属层。
  21. 根据权利要求20所述的生产线设备，所述蒸镀机，用于在去除所述第一目标区域的光刻胶之后，且在所述光刻胶以及所述第一目标区域上制备金属铌膜层之前，对所述衬底上剩余的光刻胶进行第一时长的烘烤。
  22. 根据权利要求21所述的生产线设备，所述第一时长所在的时长区间为1分钟至2分钟。
  23. 根据权利要求20所述的生产线设备，所述刻蚀机，用于在去除所述第一目标区域的 光刻胶之后，且在所述光刻胶以及所述第一目标区域上制备金属铌膜层之前，对第一目标区域及所述衬底上剩余的光刻胶进行第二时长的刻蚀；所述刻蚀为离子束刻蚀或者化学刻蚀。
  24. 根据权利要求23所述的生产线设备，所述第二时长的范围为2分钟至3分钟。
  25. 根据权利要求20所述的生产线设备，所述蒸镀机以及所述刻蚀机，用于通过磁控溅射的方式，在所述光刻胶以及所述第一目标区域上制备金属铌膜层。
  26. 根据权利要求25所述的生产线设备，磁控溅射的气压的范围为8×10 -4托至2×10 -3托。
  27. 根据权利要求25所述的生产线设备，磁控溅射的铌靶材与所述衬底之间的距离的范围为8厘米至12厘米。
  28. 根据权利要求25所述的生产线设备，磁控溅射的功率的范围为150瓦至220瓦。
  29. 根据权利要求25所述的生产线设备，磁控溅射的气体流量的范围为4标准毫升/分钟至6标准毫升/分钟。
  30. 根据权利要求19所述的生产线设备，所述刻蚀机，还用于在所述凸点下金属层的上表面制备焊点之前，对所述凸点下金属层进行刻蚀，以去除所述凸点下金属层上表面的氧化层；所述刻蚀为离子束刻蚀或者化学刻蚀。
  31. 根据权利要求30所述的生产线设备，所述刻蚀的深度的范围为15纳米至18纳米。
PCT/CN2021/135752 2021-10-08 2021-12-06 量子比特组件、量子比特组件制备方法、芯片及设备 Ceased WO2023056701A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP21937220.8A EP4191693A4 (en) 2021-10-08 2021-12-06 SET OF QUANTUM BITS, ASSOCIATED PREPARATION METHOD, CHIP AND DEVICE
US17/972,434 US11917927B2 (en) 2021-10-08 2022-10-24 Qubit assembly, qubit assembly preparation method, chip, and device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111172563.5 2021-10-08
CN202111172563.5A CN115968251B (zh) 2021-10-08 2021-10-08 量子比特组件、量子比特组件制备方法、芯片及设备

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/972,434 Continuation US11917927B2 (en) 2021-10-08 2022-10-24 Qubit assembly, qubit assembly preparation method, chip, and device

Publications (1)

Publication Number Publication Date
WO2023056701A1 true WO2023056701A1 (zh) 2023-04-13

Family

ID=84363002

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/135752 Ceased WO2023056701A1 (zh) 2021-10-08 2021-12-06 量子比特组件、量子比特组件制备方法、芯片及设备

Country Status (4)

Country Link
US (1) US11917927B2 (zh)
EP (1) EP4191693A4 (zh)
CN (1) CN115968251B (zh)
WO (1) WO2023056701A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119365062B (zh) * 2024-10-21 2025-09-19 中国科学院上海微系统与信息技术研究所 超导量子芯片封装结构及超导量子芯片的倒装封装方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140246763A1 (en) * 2012-12-17 2014-09-04 D-Wave Systems Inc. Systems and methods for testing and packaging a superconducting chip
US9761542B1 (en) * 2016-09-07 2017-09-12 International Business Machines Corporation Liquid metal flip chip devices
US20170373044A1 (en) * 2015-11-05 2017-12-28 Massachusetts Institute Of Technology Interconnect structures and semiconductor structures for assembly of cryogenic electronic packages
CN111183434A (zh) * 2017-10-05 2020-05-19 谷歌有限责任公司 成倒装几何结构的低占位面积谐振器
US20200335685A1 (en) * 2019-04-19 2020-10-22 International Business Machines Corporation Qubit frequency tuning structures and fabrication methods for flip chip quantum computing devices
US20200401921A1 (en) * 2019-06-19 2020-12-24 International Business Machines Corporation Transmon qubit flip-chip structures for quantum computing devices
CN112585772A (zh) * 2018-09-20 2021-03-30 国际商业机器公司 混合凸块下金属化部件
CN112652540A (zh) * 2020-07-01 2021-04-13 腾讯科技（深圳）有限公司 铟柱焊点的制备方法、芯片衬底及芯片
US20210175408A1 (en) * 2019-12-05 2021-06-10 Microsoft Technology Licensing, Llc Semiconductor-superconductor hybrid device and its fabrication

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH531910A (fr) * 1970-07-08 1972-12-31 Battelle Memorial Institute Procédé de décapage de tôle oxydée et installation pour la mise en oeuvre de ce procédé
FR2696544B1 (fr) * 1992-10-05 1995-06-23 Europ Agence Spatiale Cellule de detection, detecteur, capteur et spectroscope.
US5567551A (en) * 1994-04-04 1996-10-22 The United States Of America As Represented By The Secretary Of The Navy Method for preparation of mask for ion beam lithography
JPH08204244A (ja) * 1995-01-26 1996-08-09 Tanaka Denshi Kogyo Kk 超伝導装置
US5714037A (en) * 1996-05-17 1998-02-03 Microunity Systems Engineering, Inc. Method of improving adhesion between thin films
US20020028390A1 (en) * 1997-09-22 2002-03-07 Mohammad A. Mazed Techniques for fabricating and packaging multi-wavelength semiconductor laser array devices (chips) and their applications in system architectures
US6015652A (en) * 1998-02-27 2000-01-18 Lucent Technologies Inc. Manufacture of flip-chip device
JP2001094163A (ja) * 1999-09-21 2001-04-06 Sanyo Electric Co Ltd 酸化物薄膜パターンを有する電子素子及びその製造方法
US6926921B2 (en) * 2003-05-05 2005-08-09 Hewlett-Packard Development Company, L.P. Imprint lithography for superconductor devices
JP4106438B2 (ja) * 2003-06-20 2008-06-25 独立行政法人産業技術総合研究所 多層微細配線インターポーザおよびその製造方法
DE102004054856B4 (de) * 2004-11-12 2006-08-10 Hydro Aluminium Deutschland Gmbh Verfahren und Vorrichtung zum Bestimmen des elektrischen Widerstands eines Metallflachprodukts
JP2006270031A (ja) * 2005-02-25 2006-10-05 Casio Comput Co Ltd 半導体装置およびその製造方法
CN101964364B (zh) * 2009-07-24 2012-05-23 中国科学院物理研究所 一种晶体管器件及其制造方法
US20130080105A1 (en) 2011-09-23 2013-03-28 Tektronix, Inc Enhanced awg wavef0rm calibration using s-parameters
US10396269B2 (en) * 2015-11-05 2019-08-27 Massachusetts Institute Of Technology Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits
CN106252204B (zh) * 2016-08-29 2019-05-31 复旦大学 一种将庞磁阻锰氧化物薄膜在纳米尺度图形化的方法
US10608158B2 (en) * 2017-09-29 2020-03-31 International Business Machines Corporation Two-component bump metallization
CN107758607A (zh) * 2017-09-29 2018-03-06 湖南大学 一种高深宽比高保形纳米级正型结构的制备方法
US10263170B1 (en) * 2017-11-30 2019-04-16 International Business Machines Corporation Bumped resonator structure
US11121302B2 (en) * 2018-10-11 2021-09-14 SeeQC, Inc. System and method for superconducting multi-chip module
US11165010B2 (en) * 2019-02-11 2021-11-02 International Business Machines Corporation Cold-welded flip chip interconnect structure
US10833241B1 (en) * 2019-06-20 2020-11-10 International Business Machines Corporation Thermalization structure for cryogenic temperature devices
CN113011591B (zh) 2020-11-09 2023-07-28 深圳市腾讯计算机系统有限公司 一种用于多比特量子反馈控制的量子测控系统

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140246763A1 (en) * 2012-12-17 2014-09-04 D-Wave Systems Inc. Systems and methods for testing and packaging a superconducting chip
US20170373044A1 (en) * 2015-11-05 2017-12-28 Massachusetts Institute Of Technology Interconnect structures and semiconductor structures for assembly of cryogenic electronic packages
US9761542B1 (en) * 2016-09-07 2017-09-12 International Business Machines Corporation Liquid metal flip chip devices
CN111183434A (zh) * 2017-10-05 2020-05-19 谷歌有限责任公司 成倒装几何结构的低占位面积谐振器
CN112585772A (zh) * 2018-09-20 2021-03-30 国际商业机器公司 混合凸块下金属化部件
US20200335685A1 (en) * 2019-04-19 2020-10-22 International Business Machines Corporation Qubit frequency tuning structures and fabrication methods for flip chip quantum computing devices
US20200401921A1 (en) * 2019-06-19 2020-12-24 International Business Machines Corporation Transmon qubit flip-chip structures for quantum computing devices
US20210175408A1 (en) * 2019-12-05 2021-06-10 Microsoft Technology Licensing, Llc Semiconductor-superconductor hybrid device and its fabrication
CN112652540A (zh) * 2020-07-01 2021-04-13 腾讯科技（深圳）有限公司 铟柱焊点的制备方法、芯片衬底及芯片

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4191693A4

Also Published As

Publication number Publication date
CN115968251B (zh) 2025-11-14
US11917927B2 (en) 2024-02-27
US20230115860A1 (en) 2023-04-13
EP4191693A1 (en) 2023-06-07
EP4191693A4 (en) 2023-11-15
CN115968251A (zh) 2023-04-14

Similar Documents

Publication Publication Date Title
CN114914355B (zh) 一种三维封装超导量子比特器件、其制备方法和设备
WO2019041858A1 (zh) 刻蚀方法、薄膜晶体管的制造方法、工艺设备、显示装置
CN107104044A (zh) 一种电极制作方法及阵列基板的制作方法
CN106384714A (zh) 薄膜晶体管及其制备方法、阵列基板
WO2023056701A1 (zh) 量子比特组件、量子比特组件制备方法、芯片及设备
CN104299891B (zh) 低温多晶硅薄膜的制备方法、tft、阵列基板及显示装置
CN211789023U (zh) 一种量子芯片立体结构
CN107706199A (zh) 一种薄膜晶体管阵列基板的制作方法
CN118284246A (zh) 基于顺排单壁碳纳米管阵列膜的自旋场效应晶体管及制备
HK40084254B (zh) 量子比特组件、量子比特组件制备方法、芯片及设备
CN108461391B (zh) 一种igzo有源层、氧化物薄膜晶体管的制备方法
CN114937590B (zh) 一种光刻方法
HK40084254A (zh) 量子比特组件、量子比特组件制备方法、芯片及设备
WO2024174406A9 (zh) 量子芯片的制备方法、量子芯片及量子计算机
CN110133961A (zh) 一种改善光阻显影和变形的方法
CN103258739A (zh) 基于自停止刻蚀的凹槽栅氮化镓基增强型器件的制备方法
CN118284312A (zh) 基于顺排多壁碳纳米管阵列膜的自旋场效应晶体管及制备
CN107799407A (zh) 一种晶体管的凹槽栅制备方法及大功率射频器件
CN107516672B (zh) 一种适用于铝镓氮化合物/氮化镓高电子迁移率晶体管的肖特基接触系统
CN114743870B (zh) 一种百纳米级栅极凹槽的刻蚀方法
CN101017781A (zh) 异质结双极晶体管t型发射极金属图形制作方法的改进
US20230422634A1 (en) Method and system for preparing josephson junction
CN110323128A (zh) 一种空气桥的制作方法以及空气桥
CN115472506A (zh) 双栅极器件的制备方法及双栅极器件
CN121888866A (zh) 一种约瑟夫森结电路制备方法、约瑟夫森结电路及超导量子芯片

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2021937220

Country of ref document: EP

Effective date: 20221028

NENP Non-entry into the national phase

Ref country code: DE