WO2024016394A1 - 显示面板、拼接显示模组以及拼接显示模组的制作方法 - Google Patents

显示面板、拼接显示模组以及拼接显示模组的制作方法 Download PDF

Info

Publication number
WO2024016394A1
WO2024016394A1 PCT/CN2022/110757 CN2022110757W WO2024016394A1 WO 2024016394 A1 WO2024016394 A1 WO 2024016394A1 CN 2022110757 W CN2022110757 W CN 2022110757W WO 2024016394 A1 WO2024016394 A1 WO 2024016394A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
light
driving component
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/110757
Other languages
English (en)
French (fr)
Inventor
李柱辉
李燕芬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to JP2022572459A priority Critical patent/JP7620032B2/ja
Priority to US17/799,662 priority patent/US20250386635A1/en
Priority to EP22757820.0A priority patent/EP4560611A4/en
Publication of WO2024016394A1 publication Critical patent/WO2024016394A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/34—Active-matrix LED displays characterised by the geometry or arrangement of subpixels within a pixel, e.g. relative disposition of the RGB subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/01—Manufacture or treatment
    • H10H29/012—Manufacture or treatment of active-matrix LED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/20—Assemblies of multiple devices comprising at least one light-emitting semiconductor device covered by group H10H20/00
    • H10H29/24—Assemblies of multiple devices comprising at least one light-emitting semiconductor device covered by group H10H20/00 comprising multiple light-emitting semiconductor devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/49—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G09G2300/026—Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present application relates to the field of display, and specifically to a display panel, a spliced display module and a method of making a spliced display module.
  • QLED quantum dot light-emitting diodes
  • E-ink electronic ink screens
  • Perovskite light-emitting diodes Perovskite light-emitting diodes
  • PeLEDs Perovskite light-emitting diodes
  • Mini Light-emitting Diode Mini LED
  • Micro Light-emitting diode Micro Light-emitting Diode
  • Micro-LED refers to a technology that uses micron-level LEDs as light-emitting pixel units and assembles them with drive modules to form a high-density display array.
  • Micro LED has cross-generation advantages in terms of brightness, resolution, energy consumption, service life, response speed and thermal stability, and is an internationally recognized future display technology.
  • the large-size display market is very huge, such as shopping mall advertisements, center consoles, conference rooms, stadiums, etc.
  • the glass-based Micro-LED splicing screen not only has all the advantages of the glass-based Mini LED splicing screen, but also has the advantages of higher resolution, more delicate image quality, etc., has better display characteristics, and is suitable for Large size display.
  • the pixel unit in the prior art usually includes a driving component 1 and a light-emitting component 2.
  • the light-emitting component 2 is located on one side of the driving component 1.
  • the width of the driving component 1 is equal to the width of the pixel unit.
  • the negative tolerance area 3 on the edge of the screen can be cut off to increase
  • the amount of splicing redundancy can meet the seamless splicing effect, but this solution is only suitable for low-resolution splicing screens and is not suitable for high-resolution splicing screens.
  • the inventor of the present application found that, as shown in Figure 2, the seams can be reduced by setting a negative tolerance on the pixel unit. Specifically, the space of the driving assembly 1 can be compressed. , a negative tolerance area 3 is formed around the driving component 1 and the light-emitting component 2.
  • the negative tolerance area 3 at the edge of the screen can be cut off to increase the splicing redundancy and meet the requirement of seamless splicing. The effect is good, but the solution in Figure 2 still cannot eliminate the seams well.
  • Embodiments of the present application provide a display panel, a splicing display module, and a manufacturing method of a splicing display module, which can solve the technical problem of difficulty in eliminating seams in splicing screens.
  • An embodiment of the present application provides a display panel.
  • the display panel includes a first display area and a second display area.
  • the second display area is provided on the periphery of one side of the first display area at least along a first direction.
  • the display panel includes:
  • the first pixel group includes a first driving component, a second driving component, a first light-emitting component and a second light-emitting component.
  • the first driving component electrically is electrically connected to the first light-emitting component
  • the second driving component is electrically connected to the second light-emitting component; in the first pixel group, the first driving component is provided along the first direction.
  • the second driving component is disposed on a side of the first driving component away from the first light-emitting component along the first direction.
  • the second light-emitting component is along the first direction.
  • One direction is provided on a side of the second driving component away from the first driving component.
  • the first driving component and the second driving component are arranged axially symmetrically, and the first driving component and the The structure of the second drive component is the same.
  • the display panel further includes a plurality of second pixel groups, the plurality of second pixel groups are provided in the first display area, and the plurality of first pixels The group and the plurality of second pixel groups are distributed in an array.
  • the structure of the first pixel group is the same as the structure of the second pixel group.
  • the pixel pitch of the first pixel group is equal to the pixel pitch of the second pixel group.
  • the first driving component includes at least one first thin film transistor
  • the first light emitting component includes at least one light emitting component
  • the first thin film transistor is electrically connected to the corresponding of the light-emitting component.
  • the display panel further includes a plurality of gate lines, a plurality of data lines, a plurality of first power lines and a plurality of second power lines;
  • the first driving component further includes at least one second thin film transistor, the control terminal of the second thin film transistor is electrically connected to the gate line, and the input terminal of the second thin film transistor is electrically connected to the data line. , the output terminal of the second thin film transistor is electrically connected to the control terminal of the first thin film transistor, and the input terminal of the first thin film transistor is electrically connected to the first power line;
  • the light-emitting component has a first pin and a second pin.
  • the output end of the first thin film transistor is electrically connected to the first pin of the light-emitting component.
  • the second pin of the light-emitting component is electrically connected. on the second power cord.
  • the first driving component further includes at least one storage capacitor, and the output terminal of the second thin film transistor is connected to the output terminal of the first thin film transistor through the storage capacitor. connect.
  • the display panel further includes a first signal line and a second signal line;
  • the first driving component further includes at least one third thin film transistor, the control terminal of the third thin film transistor is electrically connected to the first signal line, and the input terminal of the third thin film transistor is connected to the second signal line.
  • the output terminal of the third thin film transistor is electrically connected to the output terminal of the first thin film transistor.
  • An embodiment of the present application also provides a spliced display module, including at least two display panels, at least two of the display panels are spliced, and the display panel adopts the display panel as described above.
  • the first driving component and the second driving component are arranged axially symmetrically, and the first driving component and the The structure of the second drive component is the same.
  • the display panel further includes a plurality of second pixel groups, the plurality of second pixel groups are provided in the first display area, and the plurality of first pixels The group and the plurality of second pixel groups are distributed in an array.
  • the structure of the first pixel group is the same as the structure of the second pixel group.
  • the pixel pitch of the first pixel group is equal to the pixel pitch of the second pixel group.
  • the first driving component includes at least one first thin film transistor
  • the first light emitting component includes at least one light emitting device
  • the first thin film transistor is electrically connected to the corresponding of the light-emitting device.
  • the display panel further includes a plurality of gate lines, a plurality of data lines, a plurality of first power lines and a plurality of second power lines;
  • the first driving component further includes at least one second thin film transistor, the control terminal of the second thin film transistor is electrically connected to the gate line, and the input terminal of the second thin film transistor is electrically connected to the data line. , the output terminal of the second thin film transistor is electrically connected to the control terminal of the first thin film transistor, and the input terminal of the first thin film transistor is electrically connected to the first power line;
  • the light-emitting device has a first pin and a second pin.
  • the output end of the first thin film transistor is electrically connected to the first pin of the light-emitting device.
  • the second pin of the light-emitting device is electrically connected. on the second power cord.
  • the first driving component further includes at least one storage capacitor, and the output terminal of the second thin film transistor is connected to the output terminal of the first thin film transistor through the storage capacitor. connect.
  • the display panel further includes a first signal line and a second signal line;
  • the first driving component further includes at least one third thin film transistor, the control terminal of the third thin film transistor is electrically connected to the first signal line, and the input terminal of the third thin film transistor is connected to the second signal line.
  • the output terminal of the third thin film transistor is electrically connected to the output terminal of the first thin film transistor.
  • An embodiment of the present application also provides a method for manufacturing a splicing display module, including:
  • Step B1 Provide at least two display panels.
  • the display panels include a first display area, a second display area and a negative tolerance area.
  • the second display area is provided at least along the first direction on the periphery of the first display area.
  • the negative tolerance area is provided on a side of the second display area away from the first display area
  • the second display area is provided with a plurality of first pixel groups, the first pixel group includes a first Driving component, second driving component, first lighting component and second lighting component, the first driving component is electrically connected to the first lighting component, the second driving component is electrically connected to the second lighting component component; in the first pixel group, the first driving component is disposed on one side of the first light-emitting component along the first direction, and the second driving component is disposed on the first light-emitting component along the first direction.
  • a side of a driving component away from the first light-emitting component, the second light-emitting component being disposed along the first direction on a side of the second driving component away from
  • Step B2 Remove the negative tolerance area of the display panel
  • Step B3 Splice at least two of the display panels together to obtain a spliced display module.
  • the width of the negative tolerance zone is greater than or equal to 0.2 mm, and the width of the negative tolerance zone is less than or equal to 0.6 mm.
  • the embodiment of the present application adopts a display panel, a splicing display module and a manufacturing method of a splicing display module.
  • Figure 1 is a schematic structural diagram of a pixel unit in the prior art
  • Figure 2 is a schematic structural diagram of an improved pixel unit
  • Figure 3 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a first pixel group provided by an embodiment of the present application.
  • Figure 5 is a schematic diagram comparing the pixel unit of Figure 2 and the first pixel group of the present application;
  • Figure 6 is a schematic diagram of the principle of a display panel provided by an embodiment of the present application.
  • Figure 7 is a schematic top structural view of a pixel unit provided by an embodiment of the present application.
  • Figure 8 is an equivalent circuit diagram of a pixel unit provided by an embodiment of the present application.
  • Figure 9 is a schematic cross-sectional structural diagram of a first thin film transistor provided by an embodiment of the present application.
  • Figure 10 is a schematic cross-sectional structural diagram of a second thin film transistor provided by an embodiment of the present application.
  • Figure 11 is a schematic cross-sectional structural diagram of a storage capacitor provided by an embodiment of the present application.
  • Figure 12 is a schematic cross-sectional structural diagram of a third thin film transistor provided by an embodiment of the present application.
  • Figure 13 is a schematic structural diagram of a splicing display module provided by an embodiment of the present application.
  • Embodiments of the present application provide a display panel, a spliced display module, and a manufacturing method of the spliced display module. Each is explained in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.
  • An embodiment of the present application provides a display panel 10.
  • the display panel 10 includes a first display area AA1 and a second display area AA2.
  • the second display area AA2 is provided at least along the first direction Y at the first display area AA1. , that is, compared to the first display area AA1 , the second display area AA2 is closer to the edge of the display panel 10 along the first direction Y.
  • the second display area AA2 surrounds the first display area AA1.
  • the second display area AA2 can only be disposed on the first display area along the first direction Y.
  • One side of the periphery of the area AA1, or the second display area AA2 is provided on opposite sides of the periphery of the first display area AA1 along the first direction Y, which is not uniquely limited here.
  • the display panel 10 includes a plurality of first pixel groups PG1, and the first pixel groups PG1 are provided in the second display area AA2.
  • the first pixel group PG1 includes a first pixel unit P1 and a second pixel unit P2.
  • the first pixel unit P1 is provided on one side of the second pixel unit P2 along the first direction Y.
  • the first pixel unit P1 includes a first driving component 17 and a first light-emitting component 16.
  • the first driving component 17 is electrically connected to the first light-emitting component 16.
  • the first driving component 17 is used to control the turning on of the first light-emitting component 16. with closure.
  • the second pixel unit P2 includes a second driving component 18 and a second light-emitting component 19.
  • the second driving component 18 is electrically connected to the second light-emitting component 19.
  • the second driving component 18 is used to control the turning on and off of the second lighting component 19. .
  • the first driving component 17 is disposed on one side of the first light-emitting component 16 along the first direction Y
  • the second driving component 18 is disposed on a side away from the first driving component 17 along the first direction Y.
  • a second light-emitting component 19 is disposed on a side of the second driving component 18 away from the first driving component 17 along the first direction Y, that is, the first light-emitting component 16, the first driving component 17, and the first driving component 17.
  • the two driving components 18 and the second light-emitting component 19 are arranged in sequence along the first direction Y.
  • Figure 5 is a schematic comparison diagram of the pixel unit in Figure 2 and the first pixel group PG1 of the present application.
  • this application transfers the driving component 1 of the upper pixel unit among the two adjacent pixel units to the bottom of the light-emitting component 2, so that the two adjacent pixel units In a pixel unit, two driving components 1 are located between two light-emitting components 2, thereby obtaining the first pixel group PG1 of the present application.
  • the length of the display panel 10 along the first direction Y is L1; the first pixel group PG1 of the present application After cutting off the outermost negative tolerance area NTA of the corresponding display panel 10 , the length of the display panel 10 along the first direction Y is L2. Obviously, L2 is smaller than L1. It can be seen that by arranging the first driving component 17 and the second driving component 18 between the first lighting component 16 and the second lighting component 19 in this application, the space between the first lighting component 16 and the second lighting component 19 can be fully utilized. The spacing area increases the negative tolerance of the display panel 10 along the first direction Y, and the outermost sides of the display panel 10 along the first direction Y are all light-emitting components, which can effectively eliminate seams.
  • the negative tolerance above is larger, that is, the negative tolerance of the display panel 10 above the first direction Y is The margin is large.
  • the positions of all pixel units in the display panel 10 can be adjusted so that all pixel units in the display panel 10 are centered, so that the lower negative tolerance is consistent with the upper negative tolerance.
  • the first driving component 17 , the second driving component 18 , and the first driving component 18 can be adjusted.
  • first direction Y and the second direction X is greater than 0° and less than or equal to 90°.
  • first direction Y and the second direction X are perpendicular.
  • the angle between the first direction Y and the second direction X can be adjusted appropriately, and is not limited here.
  • both the first light-emitting component 16 and the second light-emitting component 19 include a light-emitting device 161.
  • the light-emitting device 161 may be an LED, a Mini LED, a Micro LED, an OLED, etc., and is not uniquely limited here.
  • the first driving component 17 and the second driving component 18 refer to components used to drive the light emitting device 161 to operate, and may specifically include, but are not limited to, thin film transistors, capacitors, and other components.
  • the display panel 10 according to the embodiment of the present application can reduce the non-luminous area at the edge.
  • the display panel 10 according to the embodiment of the present application for splicing it is possible to obtain seamless
  • the patchwork splicing display module is conducive to realizing high-resolution splicing display module.
  • the first driving component 17 includes at least one sub-driving group 171
  • the first light-emitting component 16 includes at least one light-emitting device 161 .
  • the sub-driving group 171 corresponds to the light-emitting device 161 one-to-one, and each The sub-driving group 171 is electrically connected to the corresponding light-emitting device 161 .
  • the driving component includes three sub-driving groups 171.
  • the first light-emitting component 16 includes three light-emitting devices 161.
  • the three light-emitting devices 161 are respectively a red light-emitting device 1611, a green light-emitting device 1612 and a blue light-emitting device 1613. , each sub-driving group 171 is electrically connected to the corresponding light-emitting device 161 .
  • the red light-emitting device 1611 refers to the light-emitting device 161 for emitting red light
  • the green light-emitting device 1612 refers to the light-emitting device 161 for emitting green light
  • the blue light-emitting device 1613 refers to the light-emitting device 161 for emitting blue light.
  • the number of sub-driving groups 171 in the first driving assembly 17 and the number of light-emitting devices 161 in the first light-emitting assembly 16 can be appropriately adjusted according to actual situation selection and specific demand settings, which will not be done here. Only limited.
  • the sub-driving group 171 includes a first thin film transistor T1 , and the first thin film transistor T1 is electrically connected to the corresponding light emitting device 161 , so that the first thin film transistor T1 can drive the corresponding light emitting device 161 .
  • the light emitting device 161 operates.
  • a thin film transistor can be used to control the turning on and off of the light-emitting device 161.
  • the structure is simple and easy to implement.
  • the display panel 10 includes a substrate 11, a first light-shielding electrode LS1, a buffer layer 12, a first active layer AL1, a gate insulating layer 13, a first gate GE1, and an interlayer insulating layer 14. , the first source electrode SE1, the first drain electrode DE1 and the passivation layer 15.
  • the first light-shielding electrode LS1 is provided on the substrate 11
  • the buffer layer 12 covers the substrate 11 and the first light-shielding electrode LS1 .
  • the first active layer AL1 is provided on the buffer layer 12, and the first active layer AL1 is provided corresponding to the first light-shielding electrode LS1.
  • the gate insulating layer 13 is provided on the first active layer AL1, the first gate GE1 is provided on the gate insulating layer 13, and the first gate GE1 is provided corresponding to the first active layer AL1.
  • the interlayer insulating layer 14 covers the first active layer AL1, the gate insulating layer 13 and the first gate electrode GE1.
  • the first source electrode SE1 and the first drain electrode DE1 are spaced apart on the interlayer insulating layer 14, and the first source electrode SE1 is electrically connected to the first light-shielding electrode LS1.
  • the first source electrode SE1 and the first active layer AL1 are electrically connected. One end is electrically connected, and the first drain DE1 is electrically connected to the other end of the first active layer AL1.
  • the passivation layer 15 covers the interlayer insulating layer 14, the first source electrode SE1 and the first drain electrode DE1.
  • the first active layer AL1, the first gate electrode GE1, the first source electrode SE1 and the first drain electrode DE1 form the first thin film transistor T1, wherein the control end of the first thin film transistor T1 is the first The gate GE1, the input terminal is the first source SE1, and the output terminal is the first drain DE1.
  • the display panel 10 further includes a first soldering pad Pad1, which is electrically connected to the first drain electrode DE1.
  • the light-emitting device 161 has a first pin 1614, and the first pin 1614 is bound to the first soldering electrode. pad Pad1, so that the first thin film transistor T1 is electrically connected to the light emitting device 161.
  • the display panel 10 also includes a plurality of gate lines G, a plurality of data lines D, a first power line VDD and a second power line VSS.
  • the sub-driving group 171 also includes a second thin film transistor T2.
  • the control terminal of the second thin film transistor T2 is electrically connected to the gate line G.
  • the input terminal of the second thin film transistor T2 is electrically connected to the data line D.
  • the second thin film transistor T2 The output end of the first thin film transistor T1 is electrically connected to the control end of the first thin film transistor T1, and the input end of the first thin film transistor T1 is electrically connected to the first power line VDD.
  • the light emitting device 161 also has a second pin 1615, which emits light.
  • the second pin 1615 of the device 161 is electrically connected to the second power line VSS.
  • the display panel 10 further includes a second light-shielding electrode LS2, a second active layer AL2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.
  • the second light-shielding electrode LS2 is disposed on the substrate 11 and is spaced apart from the first light-shielding electrode LS1.
  • the buffer layer 12 also covers the second light-shielding electrode LS2.
  • the second active layer AL2 is disposed on the buffer layer 12, and the second active layer AL2 is disposed corresponding to the second light-shielding electrode LS2.
  • the gate insulating layer 13 is also disposed on the second active layer AL2, the second gate GE2 is disposed on the gate insulating layer 13, and the second gate GE2 is disposed corresponding to the second active layer AL2.
  • the interlayer insulating layer 14 covers the second active layer AL2 and the second gate electrode GE2.
  • the second source electrode SE2 and the second drain electrode DE2 are spaced apart on the interlayer insulating layer 14, and the second source electrode SE2 is electrically connected to the second light-shielding electrode LS2.
  • the second source electrode SE2 and the second active layer AL2 are electrically connected. One end is electrically connected, and the second drain DE2 is electrically connected to the other end of the second active layer AL2.
  • the passivation layer 15 also covers the second source electrode SE2 and the second drain electrode DE2.
  • the second active layer AL2, the second gate electrode GE2, the second source electrode SE2 and the second drain electrode DE2 form a second thin film transistor T2, wherein the control end of the second thin film transistor T2 is the second thin film transistor T2.
  • the first source SE1 is electrically connected to the first power line VDD
  • the second pin 1615 is electrically connected to the second power line VSS
  • the second gate GE2 is electrically connected to the gate line G
  • the second drain DE2 is electrically connected to the first gate GE1.
  • the display panel 10 further includes a second bonding pad Pad2.
  • the second bonding pad Pad2 is electrically connected to the second power line VSS.
  • the second pin 1615 is bound to the second bonding pad. Pad2.
  • the display panel 10 further includes a first signal line RD and a second signal line Vref.
  • the first driving component 17 also includes at least one third thin film transistor T3.
  • the control terminal of the third thin film transistor T3 is electrically connected to the first signal line RD.
  • the input terminal of the third thin film transistor T3 is electrically connected to the second signal line Vref.
  • the output terminal of the third thin film transistor T3 is electrically connected to the output terminal of the first thin film transistor T1.
  • the display panel 10 further includes a third light-shielding electrode LS3, a third active layer AL3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.
  • the third light-shielding electrode LS3 is provided on the substrate 11 , and the third light-shielding electrode LS3 , the second light-shielding electrode LS2 and the first light-shielding electrode LS1 are spaced apart from each other.
  • the buffer layer 12 also covers the third light-shielding electrode LS3 .
  • the third active layer AL3 is provided on the buffer layer 12, and the third active layer AL3 is provided corresponding to the third light-shielding electrode LS3.
  • the gate insulating layer 13 is also disposed on the third active layer AL3, the third gate GE3 is disposed on the gate insulating layer 13, and the third gate GE3 is disposed corresponding to the third active layer AL3.
  • the interlayer insulating layer 14 covers the third active layer AL3 and the third gate electrode GE3.
  • the third source electrode SE3 and the third drain electrode DE3 are spaced apart on the interlayer insulating layer 14, and the third source electrode SE3 is electrically connected to the third light-shielding electrode LS3.
  • the third source electrode SE3 and the third active layer AL3 are electrically connected. One end is electrically connected, and the third drain DE3 is electrically connected to the other end of the third active layer AL3.
  • the passivation layer 15 also covers the third source electrode SE3 and the third drain electrode DE3.
  • the third active layer AL3, the third gate electrode GE3, the third source electrode SE3 and the third drain electrode DE3 form a third thin film transistor T3, wherein the control end of the third thin film transistor T3 is the third thin film transistor T3.
  • the input terminal of the gate GE3 is the third source electrode SE3, and the output terminal is the third drain electrode DE3.
  • the third drain electrode DE3 is electrically connected to the first drain electrode DE1.
  • the sub-driving group 171 also includes a storage capacitor Cst.
  • the output terminal of the second thin film transistor T2 is connected to the output terminal of the first thin film transistor T1 through the storage capacitor Cst.
  • the storage capacitor Cst includes a first capacitor C1 and a second capacitor C2.
  • the first capacitor C1 and the second capacitor C2 are connected in parallel.
  • the first capacitor C1 is formed between the first drain DE1 and the first gate GE1.
  • a second capacitor C2 is formed between the first light-shielding electrode LS1 and the first gate electrode GE1.
  • the first pixel unit P1 and the second pixel unit P2 are arranged axially symmetrically, that is, the first driving component 17 and the second driving component 18 are arranged axially symmetrically, and the first light-emitting component 16 and The second light-emitting component 19 is arranged axially symmetrically.
  • the first driving component 17 and the second driving component 18 have the same structure, and the first light-emitting component 16 and the second light-emitting component 19 have the same structure.
  • the first driving component 17 and the second driving component 18 have the same structure, and the first light-emitting component 16 and the second light-emitting component 19 have the same structure, which means that the second driving component 18 also includes at least one sub-driving group 171.
  • the two light-emitting components 19 include at least one light-emitting device 161.
  • the sub-driving groups 171 of the second driving component 18 correspond to the light-emitting devices 161 of the second light-emitting component 19.
  • the sub-driving groups 171 of each second driving component 18 are electrically connected.
  • the light-emitting device 161 corresponding to the second light-emitting component 19.
  • the first driving component 17 and the second driving component 18 are arranged axially symmetrically, and the first light-emitting component 16 and the second lighting component 19 are arranged axially symmetrically, which refers to the layout of the components in the first driving component 17 and the second driving component
  • the layout of the elements in 18 is arranged axially symmetrically, and the layout of the light-emitting devices 161 in the first light-emitting assembly 16 and the layout of the light-emitting devices 161 in the second light-emitting assembly 19 are arranged axially symmetrically.
  • the gate line G, the data line D, the first power line VDD, the second power line VSS, the first signal line RD and the second signal line Vref are arranged in parallel.
  • the gate line G, the data line D, the first power line VDD and the second signal line Vref are arranged in parallel.
  • a power supply line VDD, a second power supply line VSS, a first signal line RD and a second signal line Vref are parallel to the first direction Y.
  • the gate line G and the first power line VDD are respectively disposed on opposite sides of the first pixel unit P1 and the second pixel unit P2.
  • the gate line G and the first power line VDD are disposed on the first pixel unit P1 and the second pixel unit P2 along the second direction X.
  • the first signal line RD is provided on the side of the gate line G close to the first power supply line VDD
  • the second power line VSS is provided on the side of the first signal line RD close to the first power line VDD.
  • the data line D and the second signal line Vref are provided between the first power line VDD and the second power line VSS.
  • the first driving component 17, the second driving component 18, the first light-emitting component 16 and The second light-emitting component 19 is located between the first power line VDD and the second power line VSS.
  • the sub-driving groups 171 in the first driving component 17 and the second driving component 18 are arranged along the second direction One side of the driving group 171 and its corresponding light-emitting device 161 .
  • the wiring, sub-driving group 171 and light-emitting device 161 will generate heat when working.
  • the wiring, sub-driving group 171 and light-emitting device 161 can be evenly distributed.
  • the display panel 10 can generate heat evenly to avoid abnormality of the display panel 10 caused by heat concentration, thereby improving the reliability of the display panel 10 .
  • the display panel 10 includes a plurality of first pixel units P1 and a plurality of second pixel units P2.
  • the plurality of first pixel units P1 and the plurality of second pixel units P2 are distributed in an array.
  • the first direction Y that is, in the column direction
  • the first pixel units P1 and the second pixel units P2 are staggered.
  • the second direction that is, in the second direction
  • the display panel 10 also includes a plurality of first transfer lines S1.
  • the first transfer lines S1 are parallel to the second direction X.
  • the grid lines G overlap with the first transfer lines S1.
  • the grid lines G pass through
  • the first switching line S1 is electrically connected to the control terminal of the second thin film transistor T2.
  • the display panel 10 also includes a plurality of second transfer lines S2.
  • the second transfer lines S2 are parallel to the second direction X.
  • the first power line VDD overlaps the second transfer lines S2.
  • the power line VDD is electrically connected to the input terminal of the first thin film transistor T1 through the second transfer line S2.
  • the display panel 10 also includes a plurality of third adapter lines S3.
  • the third adapter lines S3 are parallel to the second direction X.
  • the second power line VSS overlaps the third adapter lines S3.
  • the power line VSS is electrically connected to the second pad Pad2 through the third transfer line S3.
  • the display panel 10 further includes a plurality of fourth transfer lines S4.
  • the fourth transfer lines S4 are parallel to the second direction X.
  • the first signal line RD overlaps the fourth transfer lines S4.
  • the signal line RD is electrically connected to the control terminal of the third thin film transistor T3 through the fourth transfer line S4.
  • the display panel 10 further includes a plurality of fifth transfer lines S5.
  • the fifth transfer lines S5 are parallel to the second direction X.
  • the second signal line Vref overlaps the fifth transfer lines S5.
  • the signal line Vref is electrically connected to the input terminal of the third thin film transistor T3 through the fifth transfer line S5.
  • the input terminal of the first thin film transistor T1 of the red light-emitting device 1611, the input terminal of the first thin film transistor T1 of the green light-emitting device 1612 and The input end of the first thin film transistor T1 of the blue light emitting device 1613 is electrically connected to different data lines D; the control end of the second thin film transistor T2 of the red light emitting device 1611 and the control end of the second thin film transistor T2 of the green light emitting device 1612
  • the control terminal of the third thin film transistor T3 of the red light emitting device 1611 and the third thin film transistor T3 of the green light emitting device 1612 are electrically connected to the same gate line G.
  • the control terminal and the control terminal of the third thin film transistor T3 of the blue light-emitting device 1613 are electrically connected to the same first signal line RD.
  • the input end of the third thin film transistor T3 and the input end of the third thin film transistor T3 of the blue light-emitting device 1613 are electrically connected to the same second signal line Vref.
  • the display panel 10 further includes a plurality of second pixel groups PG2.
  • the plurality of second pixel groups PG2 are provided in the first display area AA1.
  • the plurality of first pixel groups PG1 and the plurality of second pixel groups PG2 are distributed in an array.
  • the structure of the first pixel group PG1 is the same as the structure of the second pixel group PG2, that is, the second pixel group PG2 also includes a first pixel unit P1 and a second pixel unit P2, and the first pixel unit in the second pixel group PG2
  • the pixel unit P1 and the second pixel unit P2 are arranged axially symmetrically.
  • the pixel pitch of the first pixel group PG1 is equal to the pixel pitch of the second pixel group PG2, so that the display panel 10 can emit light evenly. It should be noted that the pixel pitch refers to the distance between the centers of two adjacent pixel units.
  • an embodiment of the present application also provides a spliced display module, which includes at least two display panels 10 as described above, and the at least two display panels 10 are spliced together.
  • Splicing display modules can be fixed terminals, such as desktop computers, TVs, large-size display screens, etc.
  • the splicing display module also includes a terminal body 20 , the terminal body 20 is the shell, and the display panel 10 is fixed on the terminal body 20 .
  • An embodiment of the present application also provides a method for manufacturing a splicing display module, including:
  • Step B1 as shown in FIG. 6, at least two display panels 10 are provided.
  • the display panel 10 adopts the display panel 10 of the above embodiment, and the display panel 10 also includes a negative tolerance area NTA.
  • the negative tolerance area NTA is provided in the second display. The side of area AA2 away from the first display area AA1;
  • Step B2 remove the negative tolerance area NTA of the display panel 10.
  • the negative tolerance area NTA of the display panel 10 can be removed by, but is not limited to, laser cutting and grinding;
  • Step B3 as shown in Figure 13, at least two display panels 10 are spliced together to obtain a spliced display module.
  • the width of the negative tolerance area NTA is greater than or equal to 0.2 mm, and the seam between two adjacent display panels 10 can be eliminated by cutting off the negative tolerance area NTA.
  • the width of the negative tolerance area NTA is less than or equal to 0.6 mm, which can avoid wasting materials due to the negative tolerance area NTA being too large.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Multimedia (AREA)
  • Electroluminescent Light Sources (AREA)
  • Transforming Electric Information Into Light Information (AREA)

Abstract

一种显示面板（10）、拼接显示模组以及拼接显示模组的制作方法，显示面板（10）包括第一显示区（AA1）和第二显示区（AA2），第二显示区（AA2）至少沿第一方向（Y）设于第一显示区（AA1）的外围；第二显示区（AA2）设有第一像素组（PG1），第一像素组（PG1）包括沿第一方向（Y）依次设置的第一发光组件（16）、第一驱动组件（17）、第二驱动组件（18）和第二发光组件（19）。

Description

显示面板、拼接显示模组以及拼接显示模组的制作方法 技术领域
本申请涉及显示领域，具体涉及一种显示面板、拼接显示模组以及拼接显示模组的制作方法。
 背景技术
近年来也兴起了很多新型的显示技术，例如量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示、电子墨水屏(E-ink)、柔性LCD、钙钛矿发光二极管(Perovskite light-emitting didoes，PeLEDs)显示、迷你发光二极管(Mini Light-emitting Diode，Mini LED)、微发光二极管(Micro Light-emitting Diode，Micro LED)等等。这些新技术因还存在成本、寿命、可靠性等一些问题，还具备不了像液晶显示器(Liquid Crystal Display，LCD)和有机电激光显示(Organic Light-Emitting Diode，OLED)同样高的量产性。其中，Micro-LED是指以微米量级LED为发光像素单元，将其与驱动模块组装形成高密度显示阵列的技术。与当前主流的LCD、OLED等显示技术相比，Micro LED在亮度、分辨率、能耗、使用寿命、响应速度和热稳定性等方面具有跨代优势，是国际公认的未来显示技术。
大尺寸显示市场非常庞大，例如商场广告、中控台、会议室、体育馆等等。目前的大尺寸显示屏主要有四种：
(1)LCD拼接屏，该方案成本较低，但只能应用在室内，且有明显的拼接缝；
(2)PCB板小间距LED拼接屏，该技术可以实现无缝拼接及高亮显示，但分辨率较低，且模组庞大复杂；
(3)投影显示，该技术亮度很低，且画面不清晰，图像易变形，仅能满足一般的室内办公；
(4)玻璃基Mini LED拼接屏，该技术可以实现无缝拼接及高亮、高分辨率显示，而且轻薄美观，缺点在于Mini LED芯片大，颗粒感明显，不适合近距离观看。
相比于上述方案，玻璃基Micro-LED拼接屏不仅具备了玻璃基Mini LED拼接屏的所有优点，而且还具备更高分辨率、更细腻画质等优点，具有更佳的显示特性，适用于大尺寸显示。
如图1所示，现有技术的像素单元通常包括驱动组件1和发光组件2，发光组件2设于驱动组件1的一侧，驱动组件1的宽度等于像素单元的宽度，采用上述像素单元的屏幕在拼接时，拼缝较大，影响观感。为了解决拼缝问题，如图2所示，发光组件2可以采用小尺寸的LED灯珠，并在像素单元四周设置负公差区3，拼接时，可以将屏幕边缘的负公差区3切除，增加拼接冗余量，可以满足无缝拼接的效果，但该方案只适用于低分辨率的拼接屏，并不适用于高分辨率的拼接屏。
在对现有技术的研究和实践过程中，本申请的发明人发现，如图2所示，可以通过在像素单元上设置负公差来减小拼缝，具体来说，压缩驱动组件1的空间，在驱动组件1和发光组件2的周围形成负公差区3，采用上述像素单元的屏幕在拼接时，可以将屏幕边缘的负公差区3切除，增加拼接冗余量，可以满足无缝拼接的效果，但是图2的方案仍然无法很好地消除拼缝。
因此，亟需一种能够解决上述问题的技术方案。
 技术问题
本申请实施例提供一种显示面板、拼接显示模组以及拼接显示模组的制作方法，可以解决难以消除拼接屏幕的拼缝的技术问题。
 技术解决方案
本申请实施例提供一种显示面板，所述显示面板包括第一显示区和第二显示区，所述第二显示区至少沿第一方向设于所述第一显示区的一侧的外围，所述显示面板包括：
多个第一像素组，设于所述第二显示区，所述第一像素组包括第一驱动组件、第二驱动组件、第一发光组件和第二发光组件，所述第一驱动组件电性连接于所述第一发光组件，所述第二驱动组件电性连接于所述第二发光组件；在所述第一像素组中，所述第一驱动组件沿所述第一方向设于第一发光组件的一侧，所述第二驱动组件沿所述第一方向设于所述第一驱动组件的远离所述第一发光组件的一侧，所述第二发光组件沿所述第一方向设于所述第二驱动组件的远离所述第一驱动组件的一侧。
可选的，在本申请的一些实施例中，在所述第一像素组中，所述第一驱动组件和所述第二驱动组件呈轴对称设置，且所述第一驱动组件和所述第二驱动组件的结构相同。
可选的，在本申请的一些实施例中，所述显示面板还包括多个第二像素组，所述多个第二像素组设于所述第一显示区，多个所述第一像素组和多个所述第二像素组呈阵列分布。
可选的，在本申请的一些实施例中，所述第一像素组的结构与所述第二像素组的结构相同。
可选的，在本申请的一些实施例中，所述第一像素组的像素间距等于所述第二像素组的像素间距。
可选的，在本申请的一些实施例中，所述第一驱动组件包括至少一个第一薄膜晶体管，所述第一发光组件包括至少一个发光组件，所述第一薄膜晶体管电性连接于对应的所述发光组件。
可选的，在本申请的一些实施例中，所述显示面板还包括多条栅线、多条数据线、多条第一电源线和多条第二电源线；
所述第一驱动组件还包括至少一个第二薄膜晶体管，所述第二薄膜晶体管的控制端电性连接于所述栅线，所述第二薄膜晶体管的输入端电性连接于所述数据线，所述第二薄膜晶体管的输出端电性连接于所述第一薄膜晶体管的控制端，所述第一薄膜晶体管的输入端电性连接于所述第一电源线；
所述发光组件具有第一引脚和第二引脚，所述第一薄膜晶体管的输出端电性连接于所述发光组件的第一引脚，所述发光组件的第二引脚电性连接于所述第二电源线。
可选的，在本申请的一些实施例中，所述第一驱动组件还包括至少一个存储电容，所述第二薄膜晶体管的输出端通过所述存储电容与所述第一薄膜晶体管的输出端连接。
可选的，在本申请的一些实施例中，所述显示面板还包括第一信号线和第二信号线；
所述第一驱动组件还包括至少一个第三薄膜晶体管，所述第三薄膜晶体管的控制端与所述第一信号线电性连接，所述第三薄膜晶体管的输入端与所述第二信号线电性连接，所述第三薄膜晶体管的输出端与所述第一薄膜晶体管的输出端电性连接。
本申请实施例还提供一种拼接显示模组，包括至少两个显示面板，至少两个所述显示面板拼接，所述显示面板采用如上所述的显示面板。
可选的，在本申请的一些实施例中，在所述第一像素组中，所述第一驱动组件和所述第二驱动组件呈轴对称设置，且所述第一驱动组件和所述第二驱动组件的结构相同。
可选的，在本申请的一些实施例中，所述显示面板还包括多个第二像素组，所述多个第二像素组设于所述第一显示区，多个所述第一像素组和多个所述第二像素组呈阵列分布。
可选的，在本申请的一些实施例中，所述第一像素组的结构与所述第二像素组的结构相同。
可选的，在本申请的一些实施例中，所述第一像素组的像素间距等于所述第二像素组的像素间距。
可选的，在本申请的一些实施例中，所述第一驱动组件包括至少一个第一薄膜晶体管，所述第一发光组件包括至少一个发光器件，所述第一薄膜晶体管电性连接于对应的所述发光器件。
可选的，在本申请的一些实施例中，所述显示面板还包括多条栅线、多条数据线、多条第一电源线和多条第二电源线；
所述第一驱动组件还包括至少一个第二薄膜晶体管，所述第二薄膜晶体管的控制端电性连接于所述栅线，所述第二薄膜晶体管的输入端电性连接于所述数据线，所述第二薄膜晶体管的输出端电性连接于所述第一薄膜晶体管的控制端，所述第一薄膜晶体管的输入端电性连接于所述第一电源线；
所述发光器件具有第一引脚和第二引脚，所述第一薄膜晶体管的输出端电性连接于所述发光器件的第一引脚，所述发光器件的第二引脚电性连接于所述第二电源线。
可选的，在本申请的一些实施例中，所述第一驱动组件还包括至少一个存储电容，所述第二薄膜晶体管的输出端通过所述存储电容与所述第一薄膜晶体管的输出端连接。
可选的，在本申请的一些实施例中，所述显示面板还包括第一信号线和第二信号线；
所述第一驱动组件还包括至少一个第三薄膜晶体管，所述第三薄膜晶体管的控制端与所述第一信号线电性连接，所述第三薄膜晶体管的输入端与所述第二信号线电性连接，所述第三薄膜晶体管的输出端与所述第一薄膜晶体管的输出端电性连接。
本申请实施例还提供一种拼接显示模组的制作方法，包括：
步骤B1、提供至少两个显示面板，所述显示面板包括第一显示区、第二显示区和负公差区，所述第二显示区至少沿第一方向设于所述第一显示区的外围，所述负公差区设于所述第二显示区的远离所述第一显示区的一侧，所述第二显示区设有多个第一像素组，所述第一像素组包括第一驱动组件、第二驱动组件、第一发光组件和第二发光组件，所述第一驱动组件电性连接于所述第一发光组件，所述第二驱动组件电性连接于所述第二发光组件；在所述第一像素组中，所述第一驱动组件沿所述第一方向设于第一发光组件的一侧，所述第二驱动组件沿所述第一方向设于所述第一驱动组件的远离所述第一发光组件的一侧，所述第二发光组件沿所述第一方向设于所述第二驱动组件的远离所述第一驱动组件的一侧；
步骤B2、去除所述显示面板的负公差区；
步骤B3、将至少两个所述显示面板拼接在一起，从而得到拼接显示模组。
可选的，在本申请的一些实施例中，在所述步骤B1中，所述负公差区的宽度大于或等于0.2毫米，且所述负公差区的宽度小于或等于0.6毫米。
 有益效果
本申请实施例采用一种显示面板、拼接显示模组以及拼接显示模组的制作方法，通过在第一发光组件和第二发光组件之间设置第一驱动组件和第二驱动组件，可以充分利用第一发光组件和第二发光组件之间的间隔区域，使得显示面板在沿第一方向上的负公差增大，且显示面板在沿第一方向上的最外侧均是发光组件，可以有效消除拼缝。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术的像素单元的结构示意图；
图2是一种改进的像素单元的结构示意图；
图3是本申请实施例提供的显示面板的结构示意图；
图4是本申请实施例提供的第一像素组的结构示意图；
图5是图2的像素单元和本申请的第一像素组的对比示意图；
图6是本申请实施例提供的显示面板的原理示意图；
图7是本申请实施例提供的像素单元的俯视结构示意图；
图8是本申请实施例提供的像素单元的等效电路图；
图9是本申请实施例提供的第一薄膜晶体管的剖视结构示意图；
图10是本申请实施例提供的第二薄膜晶体管的剖视结构示意图；
图11是本申请实施例提供的存储电容的剖视结构示意图；
图12是本申请实施例提供的第三薄膜晶体管的剖视结构示意图；
图13是本申请实施例提供的拼接显示模组的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
本申请实施例提供一种显示面板、拼接显示模组以及拼接显示模组的制作方法。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参阅图3，本申请实施例提供一种显示面板10，显示面板10包括第一显示区AA1和第二显示区AA2，第二显示区AA2至少沿第一方向Y设于第一显示区AA1的外围，即相比于第一显示区AA1而言，第二显示区AA2沿第一方向Y更靠近显示面板10的边缘。在本申请实施例中，第二显示区AA2环绕第一显示区AA1的四周，当然，根据实际情况的选择和具体需求设置，第二显示区AA2可以只沿第一方向Y设于第一显示区AA1外围的一侧，或者，第二显示区AA2沿第一方向Y设于第一显示区AA1外围的相对两侧，在此不做唯一限定。
具体的，结合图3与图4，显示面板10包括多个第一像素组PG1，第一像素组PG1设于第二显示区AA2。第一像素组PG1包括第一像素单元P1和第二像素单元P2，第一像素单元P1沿第一方向Y设于第二像素单元P2的一侧。其中，第一像素单元P1包括第一驱动组件17和第一发光组件16，第一驱动组件17电性连接于第一发光组件16，第一驱动组件17用于控制第一发光组件16的开启与关闭。第二像素单元P2包括第二驱动组件18和第二发光组件19，第二驱动组件18电性连接于第二发光组件19，第二驱动组件18用于控制第二发光组件19的开启与关闭。
在一个第一像素组PG1中，第一驱动组件17沿第一方向Y设于第一发光组件16的一侧，第二驱动组件18沿第一方向Y设于第一驱动组件17的远离第一发光组件16的一侧，第二发光组件19沿第一方向Y设于第二驱动组件18的远离第一驱动组件17的一侧，即第一发光组件16、第一驱动组件17、第二驱动组件18和第二发光组件19沿第一方向Y依次排列。
如图5所示，图5为图2的像素单元和本申请的第一像素组PG1的对比示意图。在相同像素间距的情况下，本申请在图2的像素单元的基础上，将相邻两个像素单元中，位于上方的像素单元的驱动组件1转移至发光组件2的下方，使得相邻两个像素单元中，两个驱动组件1位于两个发光组件2之间，从而得到本申请的第一像素组PG1。相比之下，图2的像素单元所对应的显示面板10的在切除最外围的负公差区3后，显示面板10的沿第一方向Y的长度为L1；本申请的第一像素组PG1所对应的显示面板10的在切除最外围的负公差区NTA后，显示面板10的沿第一方向Y的长度为L2，显然，L2小于L1。由此可见，本申请通过在第一发光组件16和第二发光组件19之间设置第一驱动组件17和第二驱动组件18，可以充分利用第一发光组件16和第二发光组件19之间的间隔区域，使得显示面板10在沿第一方向Y上的负公差增大，且显示面板10在沿第一方向Y上的最外侧均是发光组件，可以有效消除拼缝。
值得一提的是，如图5所示，本申请的第一像素组PG1所对应的显示面板10中，上方的负公差较大，即显示面板10在第一方向Y的上方的负公差的余量较大。为了使得下方的负公差与上方的负公差一致，可以调整显示面板10中的所有像素单元的位置，使得显示面板10中的所有像素单元居中设置，使得下方的负公差与上方的负公差一致。同样的，由于显示面板10在第一方向Y上的负公差的余量较大，为了增大显示面板10左右两边的负公差，可以调整第一驱动组件17、第二驱动组件18、第一发光组件16和第二发光组件19的形状，例如，增大第一驱动组件17、第二驱动组件18、第一发光组件16和第二发光组件19沿第一方向Y的长度，缩小第一驱动组件17、第二驱动组件18、第一发光组件16和第二发光组件19沿第二方向X的宽度，从而使得显示面板10上方、下方、左侧和右侧的负公差增加。
需要说明的是，第一方向Y和第二方向X之间的夹角大于0°且小于或等于90°，在本申请实施例中，第一方向Y和第二方向X垂直，当然，根据实际情况的选择和具体需求设置，第一方向Y和第二方向X之间的夹角可以做适当调整，在此不做唯一限定。
在本申请实施例中，第一发光组件16和第二发光组件19均包括发光器件161，发光器件161可以为LED、Mini LED、Micro LED和OLED等，在此不做唯一限定。第一驱动组件17和第二驱动组件18指的是用于驱动发光器件161工作的元件，具体可以但不限于包括薄膜晶体管和电容等元件。
如图3和图6所示，本申请实施例的显示面板10在切除完负公差区NTA后，可以减少边缘的不发光的区域，采用本申请实施例的显示面板10进行拼接，可以得到无拼缝的拼接显示模组，有利于实现高分辨率的拼接显示模组。
具体的，如图7至图9所示，第一驱动组件17包括至少一个子驱动组171，第一发光组件16包括至少一个发光器件161，子驱动组171和发光器件161一一对应，每个子驱动组171电性连接于对应的发光器件161。在本申请实施例中，驱动组件包括三个子驱动组171，第一发光组件16包括三个发光器件161，三个发光器件161分别为红色发光器件1611、绿色发光器件1612和蓝色发光器件1613，每个子驱动组171电性连接于对应的发光器件161。需要说明的是，红色发光器件1611指用于发红光的发光器件161，绿色发光器件1612指用于发绿光的发光器件161，蓝色发光器件1613指用于发蓝光的发光器件161。
可以理解的是，根据实际情况的选择和具体需求设置，第一驱动组件17中的子驱动组171的数量和第一发光组件16中的发光器件161的数量可以做适当调整，在此不做唯一限定。
具体的，如图7至图9所示，子驱动组171包括一个第一薄膜晶体管T1，第一薄膜晶体管T1电性连接于对应的发光器件161，从而使得第一薄膜晶体管T1可以驱动对应的发光器件161工作。此结构下，通过一个薄膜晶体管可以控制发光器件161的开启和关闭，结构简单，易于实现。
具体的，如图9所示，显示面板10包括基板11、第一遮光电极LS1、缓冲层12、第一有源层AL1、栅极绝缘层13、第一栅极GE1、层间绝缘层14、第一源极SE1、第一漏极DE1以及钝化层15。第一遮光电极LS1设于基板11上，缓冲层12覆盖在基板11和第一遮光电极LS1上。第一有源层AL1设于缓冲层12上，且第一有源层AL1对应第一遮光电极LS1设置。栅极绝缘层13设于第一有源层AL1上，第一栅极GE1设于栅极绝缘层13上，且第一栅极GE1对应第一有源层AL1设置。层间绝缘层14覆盖在第一有源层AL1、栅极绝缘层13和第一栅极GE1上。第一源极SE1和第一漏极DE1间隔设于层间绝缘层14上，且第一源极SE1与第一遮光电极LS1电性连接，第一源极SE1与第一有源层AL1的一端电性连接，第一漏极DE1与第一有源层AL1的另一端电性连接。钝化层15覆盖在层间绝缘层14、第一源极SE1和第一漏极DE1上。
本申请实施例中，第一有源层AL1、第一栅极GE1、第一源极SE1和第一漏极DE1组成第一薄膜晶体管T1，其中，第一薄膜晶体管T1的控制端为第一栅极GE1，输入端为第一源极SE1，输出端为第一漏极DE1。
具体的，显示面板10还包括第一焊垫Pad1，第一焊垫Pad1与第一漏极DE1电性连接，发光器件161具有第一引脚1614，第一引脚1614绑定于第一焊垫Pad1，从而使得第一薄膜晶体管T1与发光器件161电性连接。
具体的，如图7、图8和图10所示，显示面板10还包括多条栅线G、多条数据线D、第一电源线VDD和第二电源线VSS。子驱动组171还包括一个第二薄膜晶体管T2，第二薄膜晶体管T2的控制端电性连接于栅线G，第二薄膜晶体管T2的输入端电性连接于数据线D，第二薄膜晶体管T2的输出端电性连接于第一薄膜晶体管T1的控制端，第一薄膜晶体管T1的输入端电性连接于第一电源线VDD；结合图9，发光器件161还具有第二引脚1615，发光器件161的第二引脚1615电性连接于第二电源线VSS。
具体的，如图10所示，显示面板10还包括第二遮光电极LS2、第二有源层AL2、第二栅极GE2、第二源极SE2以及第二漏极DE2。第二遮光电极LS2设于基板11上，且第二遮光电极LS2与第一遮光电极LS1间隔设置，缓冲层12还覆盖在第二遮光电极LS2上。第二有源层AL2设于缓冲层12上，且第二有源层AL2对应第二遮光电极LS2设置。栅极绝缘层13还设于第二有源层AL2上，第二栅极GE2设于栅极绝缘层13上，且第二栅极GE2对应第二有源层AL2设置。层间绝缘层14覆盖在第二有源层AL2和第二栅极GE2上。第二源极SE2和第二漏极DE2间隔设于层间绝缘层14上，且第二源极SE2与第二遮光电极LS2电性连接，第二源极SE2与第二有源层AL2的一端电性连接，第二漏极DE2与第二有源层AL2的另一端电性连接。钝化层15还覆盖在第二源极SE2和第二漏极DE2上。
本申请实施例中，第二有源层AL2、第二栅极GE2、第二源极SE2和第二漏极DE2组成第二薄膜晶体管T2，其中，第二薄膜晶体管T2的控制端为第二栅极GE2，输入端为第二源极SE2，输出端为第二漏极DE2。第一源极SE1电性连接于第一电源线VDD，第二引脚1615电性连接于第二电源线VSS，第二栅极GE2电性连接于栅线G，第二源极SE2电性连接于数据线D，第二漏极DE2电性连接于第一栅极GE1。
具体的，如图7至图9所示，显示面板10还包括第二焊垫Pad2，第二焊垫Pad2与第二电源线VSS电性连接，第二引脚1615绑定于第二焊垫Pad2。
具体的，如图7、图8和图11所示，显示面板10还包括第一信号线RD和第二信号线Vref。第一驱动组件17还包括至少一个第三薄膜晶体管T3，第三薄膜晶体管T3的控制端与第一信号线RD电性连接，第三薄膜晶体管T3的输入端与第二信号线Vref电性连接，第三薄膜晶体管T3的输出端与第一薄膜晶体管T1的输出端电性连接。此结构下，当检测到第一薄膜晶体管T1的阈值电压异常时，可以为第一薄膜晶体管T1的输出端提供补偿电压。
具体的，如图11所示，显示面板10还包括第三遮光电极LS3、第三有源层AL3、第三栅极GE3、第三源极SE3以及第三漏极DE3。第三遮光电极LS3设于基板11上，且第三遮光电极LS3、第二遮光电极LS2与第一遮光电极LS1相互间隔设置，缓冲层12还覆盖在第三遮光电极LS3上。第三有源层AL3设于缓冲层12上，且第三有源层AL3对应第三遮光电极LS3设置。栅极绝缘层13还设于第三有源层AL3上，第三栅极GE3设于栅极绝缘层13上，且第三栅极GE3对应第三有源层AL3设置。层间绝缘层14覆盖在第三有源层AL3和第三栅极GE3上。第三源极SE3和第三漏极DE3间隔设于层间绝缘层14上，且第三源极SE3与第三遮光电极LS3电性连接，第三源极SE3与第三有源层AL3的一端电性连接，第三漏极DE3与第三有源层AL3的另一端电性连接。钝化层15还覆盖在第三源极SE3和第三漏极DE3上。
本申请实施例中，第三有源层AL3、第三栅极GE3、第三源极SE3和第三漏极DE3组成第三薄膜晶体管T3，其中，第三薄膜晶体管T3的控制端为第三栅极GE3，输入端为第三源极SE3，输出端为第三漏极DE3，第三漏极DE3电性连接于第一漏极DE1。
具体的，如图7、图8和图12所示，子驱动组171还包括存储电容Cst，第二薄膜晶体管T2的输出端通过存储电容Cst与第一薄膜晶体管T1的输出端连接。具体来说，存储电容Cst包括第一电容C1和第二电容C2，第一电容C1和第二电容C2并联，其中，第一漏极DE1和第一栅极GE1之间形成第一电容C1，第一遮光电极LS1和第一栅极GE1之间形成第二电容C2。
具体的，同一第一像素组PG1中，第一像素单元P1和第二像素单元P2呈轴对称设置，即第一驱动组件17和第二驱动组件18呈轴对称设置，第一发光组件16和第二发光组件19呈轴对称设置。并且，第一驱动组件17和第二驱动组件18的结构相同，第一发光组件16和第二发光组件19的结构相同。其中，第一驱动组件17和第二驱动组件18的结构相同，第一发光组件16和第二发光组件19的结构相同，指的是第二驱动组件18也包括至少一个子驱动组171，第二发光组件19包括至少一个发光器件161，第二驱动组件18的子驱动组171与第二发光组件19的发光器件161一一对应，每个第二驱动组件18的子驱动组171电性连接于第二发光组件19对应的发光器件161。第一驱动组件17和第二驱动组件18呈轴对称设置，第一发光组件16和第二发光组件19呈轴对称设置，指的是第一驱动组件17中的元件的布局和第二驱动组件18中的元件的布局呈轴对称设置，第一发光组件16中的发光器件161的布局和第二发光组件19中的发光器件161的布局呈轴对称设置。
具体的，栅线G、数据线D、第一电源线VDD、第二电源线VSS、第一信号线RD和第二信号线Vref平行设置，具体来说，栅线G、数据线D、第一电源线VDD、第二电源线VSS、第一信号线RD和第二信号线Vref平行于第一方向Y。栅线G和第一电源线VDD分别设置于第一像素单元P1和第二像素单元P2的相对两侧，具体来说，栅线G和第一电源线VDD沿第二方向X设置于第一像素单元P1和第二像素单元P2的相对两侧，第一信号线RD设于栅线G的靠近第一电源线VDD的一侧，第二电源线VSS设第一信号线RD的靠近第一电源线VDD的一侧，数据线D和第二信号线Vref设于第一电源线VDD和第二电源线VSS之间，第一驱动组件17、第二驱动组件18、第一发光组件16和第二发光组件19位于第一电源线VDD和第二电源线VSS之间，第一驱动组件17和第二驱动组件18中的子驱动组171沿第二方向X排列，数据线D设于子驱动组171及其对应的发光器件161的其中一侧。此结构下，走线、子驱动组171和发光器件161工作时会发热，通过合理分配走线、子驱动组171和发光器件161，使得走线、子驱动组171和发光器件161均匀分布，显示面板10可以均匀发热，避免热量集中导致显示面板10异常，从而提高显示面板10的可靠性。
具体的，如图6所示，显示面板10包括多个第一像素单元P1和多个第二像素单元P2，多个第一像素单元P1和多个第二像素单元P2呈阵列分布。在第一方向Y上，即在列方向上，第一像素单元P1和第二像素单元P2交错设置。在第二方向X上，即在行方向上，第2n行的像素单元为第二像素单元P2，第2n+1行的像素单元为第一像素单元P1，其中，n为自然数。
具体的，如图8所示，显示面板10还包括多条第一转接线S1，第一转接线S1平行于第二方向X，栅线G与第一转接线S1搭接，栅线G通过第一转接线S1与第二薄膜晶体管T2的控制端电性连接。
具体的，如图8所示，显示面板10还包括多条第二转接线S2，第二转接线S2平行于第二方向X，第一电源线VDD与第二转接线S2搭接，第一电源线VDD通过第二转接线S2与第一薄膜晶体管T1的输入端电性连接。
具体的，如图8所示，显示面板10还包括多条第三转接线S3，第三转接线S3平行于第二方向X，第二电源线VSS与第三转接线S3搭接，第二电源线VSS通过第三转接线S3与第二焊垫Pad2电性连接。
具体的，如图8所示，显示面板10还包括多条第四转接线S4，第四转接线S4平行于第二方向X，第一信号线RD与第四转接线S4搭接，第一信号线RD通过第四转接线S4与第三薄膜晶体管T3的控制端电性连接。
具体的，如图8所示，显示面板10还包括多条第五转接线S5，第五转接线S5平行于第二方向X，第二信号线Vref与第五转接线S5搭接，第二信号线Vref通过第五转接线S5与第三薄膜晶体管T3的输入端电性连接。
具体的，在同一像素单元(第一像素单元P1或第二像素单元P2)中，红色发光器件1611的第一薄膜晶体管T1的输入端、绿色发光器件1612的第一薄膜晶体管T1的输入端和蓝色发光器件1613的第一薄膜晶体管T1的输入端电性连接于不同的数据线D；红色发光器件1611的第二薄膜晶体管T2的控制端、绿色发光器件1612的第二薄膜晶体管T2的控制端和蓝色发光器件1613的第二薄膜晶体管T2的控制端电性连接于同一条栅线G；红色发光器件1611的第三薄膜晶体管T3的控制端、绿色发光器件1612的第三薄膜晶体管T3的控制端和蓝色发光器件1613的第三薄膜晶体管T3的控制端电性连接于同一条第一信号线RD，红色发光器件1611的第三薄膜晶体管T3的输入端、绿色发光器件1612的第三薄膜晶体管T3的输入端和蓝色发光器件1613的第三薄膜晶体管T3的输入端电性连接于同一条第二信号线Vref。
具体的，显示面板10还包括多个第二像素组PG2，多个第二像素组PG2设于第一显示区AA1，多个第一像素组PG1和多个第二像素组PG2呈阵列分布。
具体的，第一像素组PG1的结构与第二像素组PG2的结构相同，即第二像素组PG2也包括第一像素单元P1和第二像素单元P2，且第二像素组PG2中的第一像素单元P1和第二像素单元P2呈轴对称设置。
具体的，第一像素组PG1的像素间距等于第二像素组PG2的像素间距，使得显示面板10可以均匀出光。需要说明的是，像素间距指的是相邻两个像素单元之间的中心的间距。
请参阅图13，本申请实施例还提供一种拼接显示模组，包括至少两个如上所述的显示面板10，至少两个显示面板10拼接在一起。拼接显示模组可以是固定终端，例如台式电脑、电视、大尺寸显示屏幕等。在此实施例中，拼接显示模组还包括终端本体20，终端本体20即为外壳，显示面板10固定于终端本体20上。
本申请实施例还提供一种拼接显示模组的制作方法，包括：
步骤B1、如图6所示，提供至少两个显示面板10，显示面板10采用上述实施例的显示面板10，并且，显示面板10还包括负公差区NTA，负公差区NTA设于第二显示区AA2的远离第一显示区AA1的一侧；
步骤B2、如图6所示，去除显示面板10的负公差区NTA，具体可以但不限于通过激光切割和研磨等方式去除显示面板10的负公差区NTA；
步骤B3、如图13所示，将至少两个显示面板10拼接在一起，从而得到拼接显示模组。
具体的，负公差区NTA的宽度大于或等于0.2毫米，通过切除负公差区NTA可以消除相邻两个显示面板10之间的拼缝。
进一步的，负公差区NTA的宽度小于或等于0.6毫米，可以避免由于负公差区NTA太大而导致浪费物料的情况发生。
以上对本申请实施例所提供的一种显示面板、拼接显示模组以及拼接显示模组的制作方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括第一显示区和第二显示区，所述第二显示区至少沿第一方向设于所述第一显示区的外围，所述显示面板包括：
    多个第一像素组，设于所述第二显示区，所述第一像素组包括第一驱动组件、第二驱动组件、第一发光组件和第二发光组件，所述第一驱动组件电性连接于所述第一发光组件，所述第二驱动组件电性连接于所述第二发光组件；在所述第一像素组中，所述第一驱动组件沿所述第一方向设于第一发光组件的一侧，所述第二驱动组件沿所述第一方向设于所述第一驱动组件的远离所述第一发光组件的一侧，所述第二发光组件沿所述第一方向设于所述第二驱动组件的远离所述第一驱动组件的一侧。
  2. 如权利要求1所述的显示面板，其中，在所述第一像素组中，所述第一驱动组件和所述第二驱动组件呈轴对称设置，且所述第一驱动组件和所述第二驱动组件的结构相同。
  3. 如权利要求1所述的显示面板，其中，所述显示面板还包括多个第二像素组，所述多个第二像素组设于所述第一显示区，多个所述第一像素组和多个所述第二像素组呈阵列分布。
  4. 如权利要求3所述的显示面板，其中，所述第一像素组的结构与所述第二像素组的结构相同。
  5. 如权利要求3所述的显示面板，其中，所述第一像素组的像素间距等于所述第二像素组的像素间距。
  6. 如权利要求1所述的显示面板，其中，所述第一驱动组件包括至少一个第一薄膜晶体管，所述第一发光组件包括至少一个发光器件，所述第一薄膜晶体管电性连接于对应的所述发光器件。
  7. 如权利要求6所述的显示面板，其中，所述显示面板还包括多条栅线、多条数据线、多条第一电源线和多条第二电源线；
    所述第一驱动组件还包括至少一个第二薄膜晶体管，所述第二薄膜晶体管的控制端电性连接于所述栅线，所述第二薄膜晶体管的输入端电性连接于所述数据线，所述第二薄膜晶体管的输出端电性连接于所述第一薄膜晶体管的控制端，所述第一薄膜晶体管的输入端电性连接于所述第一电源线；
    所述发光器件具有第一引脚和第二引脚，所述第一薄膜晶体管的输出端电性连接于所述发光器件的第一引脚，所述发光器件的第二引脚电性连接于所述第二电源线。
  8. 如权利要求7所述的显示面板，其中，所述第一驱动组件还包括至少一个存储电容，所述第二薄膜晶体管的输出端通过所述存储电容与所述第一薄膜晶体管的输出端连接。
  9. 如权利要求6所述的显示面板，其中，所述显示面板还包括第一信号线和第二信号线；
    所述第一驱动组件还包括至少一个第三薄膜晶体管，所述第三薄膜晶体管的控制端与所述第一信号线电性连接，所述第三薄膜晶体管的输入端与所述第二信号线电性连接，所述第三薄膜晶体管的输出端与所述第一薄膜晶体管的输出端电性连接。
  10. 一种拼接显示模组，其包括至少两个显示面板，至少两个所述显示面板拼接，所述显示面板采用如权利要求1所述的显示面板。
  11. 如权利要求10所述的拼接显示模组，其中，在所述第一像素组中，所述第一驱动组件和所述第二驱动组件呈轴对称设置，且所述第一驱动组件和所述第二驱动组件的结构相同。
  12. 如权利要求10所述的拼接显示模组，其中，所述显示面板还包括多个第二像素组，所述多个第二像素组设于所述第一显示区，多个所述第一像素组和多个所述第二像素组呈阵列分布。
  13. 如权利要求12所述的拼接显示模组，其中，所述第一像素组的结构与所述第二像素组的结构相同。
  14. 如权利要求12所述的拼接显示模组，其中，所述第一像素组的像素间距等于所述第二像素组的像素间距。
  15. 如权利要求10所述的拼接显示模组，其中，所述第一驱动组件包括至少一个第一薄膜晶体管，所述第一发光组件包括至少一个发光器件，所述第一薄膜晶体管电性连接于对应的所述发光器件。
  16. 如权利要求15所述的拼接显示模组，其中，所述显示面板还包括多条栅线、多条数据线、多条第一电源线和多条第二电源线；
    所述第一驱动组件还包括至少一个第二薄膜晶体管，所述第二薄膜晶体管的控制端电性连接于所述栅线，所述第二薄膜晶体管的输入端电性连接于所述数据线，所述第二薄膜晶体管的输出端电性连接于所述第一薄膜晶体管的控制端，所述第一薄膜晶体管的输入端电性连接于所述第一电源线；
    所述发光器件具有第一引脚和第二引脚，所述第一薄膜晶体管的输出端电性连接于所述发光器件的第一引脚，所述发光器件的第二引脚电性连接于所述第二电源线。
  17. 如权利要求16所述的拼接显示模组，其中，所述第一驱动组件还包括至少一个存储电容，所述第二薄膜晶体管的输出端通过所述存储电容与所述第一薄膜晶体管的输出端连接。
  18. 如权利要求15所述的拼接显示模组，其中，所述显示面板还包括第一信号线和第二信号线；
    所述第一驱动组件还包括至少一个第三薄膜晶体管，所述第三薄膜晶体管的控制端与所述第一信号线电性连接，所述第三薄膜晶体管的输入端与所述第二信号线电性连接，所述第三薄膜晶体管的输出端与所述第一薄膜晶体管的输出端电性连接。
  19. 一种拼接显示模组的制作方法，其包括：
    步骤B1、提供至少两个显示面板，所述显示面板包括第一显示区、第二显示区和负公差区，所述第二显示区至少沿第一方向设于所述第一显示区的外围，所述负公差区设于所述第二显示区的远离所述第一显示区的一侧，所述第二显示区设有多个第一像素组，所述第一像素组包括第一驱动组件、第二驱动组件、第一发光组件和第二发光组件，所述第一驱动组件电性连接于所述第一发光组件，所述第二驱动组件电性连接于所述第二发光组件；在所述第一像素组中，所述第一驱动组件沿所述第一方向设于第一发光组件的一侧，所述第二驱动组件沿所述第一方向设于所述第一驱动组件的远离所述第一发光组件的一侧，所述第二发光组件沿所述第一方向设于所述第二驱动组件的远离所述第一驱动组件的一侧；
    步骤B2、去除所述显示面板的负公差区；
    步骤B3、将至少两个所述显示面板拼接在一起，从而得到拼接显示模组。
  20. 如权利要求19所述的拼接显示模组的制作方法，其中，在所述步骤B1中，所述负公差区的宽度大于或等于0.2毫米，且所述负公差区的宽度小于或等于0.6毫米。
PCT/CN2022/110757 2022-07-18 2022-08-08 显示面板、拼接显示模组以及拼接显示模组的制作方法 Ceased WO2024016394A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2022572459A JP7620032B2 (ja) 2022-07-18 2022-08-08 表示パネル、タイリング表示モジュール及びタイリング表示モジュールの製造方法
US17/799,662 US20250386635A1 (en) 2022-07-18 2022-08-08 Display panel, spliced display module, and method of manufacturing spliced display module
EP22757820.0A EP4560611A4 (en) 2022-07-18 2022-08-08 DISPLAY PANEL, MOSAIC DISPLAY MODULE AND METHOD FOR MANUFACTURING MOSAIC DISPLAY MODULES

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210843822.0A CN115273677B (zh) 2022-07-18 2022-07-18 显示面板、拼接显示模组以及拼接显示模组的制作方法
CN202210843822.0 2022-07-18

Publications (1)

Publication Number Publication Date
WO2024016394A1 true WO2024016394A1 (zh) 2024-01-25

Family

ID=83767646

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/110757 Ceased WO2024016394A1 (zh) 2022-07-18 2022-08-08 显示面板、拼接显示模组以及拼接显示模组的制作方法

Country Status (5)

Country Link
US (1) US20250386635A1 (zh)
EP (1) EP4560611A4 (zh)
JP (1) JP7620032B2 (zh)
CN (1) CN115273677B (zh)
WO (1) WO2024016394A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115938236B (zh) * 2022-12-12 2024-08-09 湖北长江新型显示产业创新中心有限公司 显示面板、拼接显示装置及其制备方法
TWI889277B (zh) 2024-04-08 2025-07-01 友達光電股份有限公司 顯示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013089475A (ja) * 2011-10-19 2013-05-13 Canon Inc 発光表示装置及びその製造方法
CN211858095U (zh) * 2020-04-27 2020-11-03 重庆康佳光电技术研究院有限公司 一种显示面板及拼接显示装置
CN112991964A (zh) * 2021-03-29 2021-06-18 上海天马微电子有限公司 显示面板、显示装置及显示面板的制作方法
CN214752699U (zh) * 2021-02-25 2021-11-16 广州视源电子科技股份有限公司 Led显示模组及显示屏
CN114141156A (zh) * 2021-12-09 2022-03-04 惠州华星光电显示有限公司 一种拼接屏及显示装置
CN114497103A (zh) * 2020-10-26 2022-05-13 佛山市国星光电股份有限公司 一种可拼接的显示模块、制备方法及显示装置
CN114648923A (zh) * 2022-03-16 2022-06-21 Tcl华星光电技术有限公司 一种拼接屏及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107658326A (zh) * 2017-03-20 2018-02-02 广东聚华印刷显示技术有限公司 电致发光显示器件及其像素结构和制作方法
KR102427082B1 (ko) * 2017-12-15 2022-07-29 엘지디스플레이 주식회사 마이크로led 표시장치 및 그 구동방법
KR102589620B1 (ko) * 2018-10-29 2023-10-17 삼성전자주식회사 표시 장치 및 이의 제조 방법
WO2021103014A1 (zh) * 2019-11-29 2021-06-03 京东方科技集团股份有限公司 阵列基板、显示面板、拼接显示面板及显示驱动方法
US11862617B2 (en) * 2020-03-18 2024-01-02 BOE MLED Technology Co., Ltd Display panel and display apparatus
KR102783809B1 (ko) * 2020-04-21 2025-03-24 삼성디스플레이 주식회사 표시 장치 및 이를 포함하는 타일드 표시 장치
CN113223420B (zh) * 2021-05-06 2023-04-21 湖北长江新型显示产业创新中心有限公司 一种显示面板及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013089475A (ja) * 2011-10-19 2013-05-13 Canon Inc 発光表示装置及びその製造方法
CN211858095U (zh) * 2020-04-27 2020-11-03 重庆康佳光电技术研究院有限公司 一种显示面板及拼接显示装置
CN114497103A (zh) * 2020-10-26 2022-05-13 佛山市国星光电股份有限公司 一种可拼接的显示模块、制备方法及显示装置
CN214752699U (zh) * 2021-02-25 2021-11-16 广州视源电子科技股份有限公司 Led显示模组及显示屏
CN112991964A (zh) * 2021-03-29 2021-06-18 上海天马微电子有限公司 显示面板、显示装置及显示面板的制作方法
CN114141156A (zh) * 2021-12-09 2022-03-04 惠州华星光电显示有限公司 一种拼接屏及显示装置
CN114648923A (zh) * 2022-03-16 2022-06-21 Tcl华星光电技术有限公司 一种拼接屏及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4560611A4 *

Also Published As

Publication number Publication date
JP7620032B2 (ja) 2025-01-22
US20250386635A1 (en) 2025-12-18
CN115273677A (zh) 2022-11-01
EP4560611A1 (en) 2025-05-28
CN115273677B (zh) 2024-03-15
EP4560611A4 (en) 2026-01-07
JP2024531001A (ja) 2024-08-29

Similar Documents

Publication Publication Date Title
CN113383382B (zh) 阵列基板、显示面板、拼接显示面板及显示驱动方法
CN113990209B (zh) 一种显示模组及无缝拼接显示装置
TWI741569B (zh) 顯示裝置
TWM609728U (zh) 一種拼接顯示裝置
CN114300505B (zh) 发光模组和显示装置
WO2021258489A1 (zh) 显示面板及显示装置
JP2022501629A (ja) フレキシブルマイクロ発光ダイオード表示パネル及びマイクロ発光ダイオード表示装置
CN111552131A (zh) 显示装置
CN113764455B (zh) 拼接显示面板及拼接显示装置
TW202010120A (zh) 微型發光二極體顯示裝置
CN108957852A (zh) 显示模组和显示装置
WO2024016394A1 (zh) 显示面板、拼接显示模组以及拼接显示模组的制作方法
KR102812650B1 (ko) 타일형 표시 장치
CN114999334B (zh) 一种拼接显示装置
CN114299828B (zh) 显示单元、拼接屏以及显示装置
CN116249400A (zh) 显示基板及显示装置
TW202133134A (zh) 顯示裝置
CN116709848A (zh) 显示装置和包括该显示装置的拼接显示装置
CN116364710A (zh) 发光显示设备以及包括发光显示设备的多屏显示设备
WO2023133718A1 (zh) 显示面板以及拼接显示屏
CN222721937U (zh) 显示基板、显示装置
KR102825567B1 (ko) 반도체 발광소자를 포함하는 디스플레이 장치
CN118411895A (zh) 显示设备
WO2024145918A1 (zh) 显示面板和显示装置
CN116666387A (zh) 显示装置和包括该显示装置的拼接显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202217066674

Country of ref document: IN

WWE Wipo information: entry into national phase

Ref document number: 2022572459

Country of ref document: JP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22757820

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2022757820

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2022757820

Country of ref document: EP

Effective date: 20250218

WWP Wipo information: published in national office

Ref document number: 2022757820

Country of ref document: EP