WO2024060744A1 - 最大似然序列的检测电路、检测方法、检测装置和电子设备 - Google Patents

最大似然序列的检测电路、检测方法、检测装置和电子设备 Download PDF

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Publication number
WO2024060744A1
WO2024060744A1 PCT/CN2023/102686 CN2023102686W WO2024060744A1 WO 2024060744 A1 WO2024060744 A1 WO 2024060744A1 CN 2023102686 W CN2023102686 W CN 2023102686W WO 2024060744 A1 WO2024060744 A1 WO 2024060744A1
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Prior art keywords
state
soft value
signal
signal state
detection
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English (en)
French (fr)
Inventor
李晋鑫
陆小凡
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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Priority to EP23867039.2A priority Critical patent/EP4593333A4/en
Priority to US19/113,953 priority patent/US20260100868A1/en
Publication of WO2024060744A1 publication Critical patent/WO2024060744A1/zh
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03203—Trellis search techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03312—Arrangements specific to the provision of output signals
    • H04L25/03318—Provision of soft decisions

Definitions

  • the present disclosure relates to the field of electronic circuit technology, and in particular, to a maximum likelihood sequence detection circuit, detection method, detection device and electronic equipment.
  • the Maximum Likelihood Sequence Detector (MLSD) is also introduced. Improve balancing capabilities to meet performance needs.
  • FFE Feed Forward Equalizer
  • DFE Decision Feedback Equalizer
  • MLSD Maximum Likelihood Sequence Detector
  • the purpose of the embodiments of the present disclosure is to provide a detection circuit, detection method, detection device and electronic equipment for a maximum likelihood sequence, which can reduce the computational complexity of detecting a maximum likelihood sequence. and power consumption.
  • the present disclosure provides a maximum likelihood sequence detection circuit, including: an equalization processing module 10, which is used to equalize an analog to digital converter (ADC) output signal and output a soft value according to the ADC output signal; a state selection module 20, which is connected to the equalization processing module 10 and is used to determine a target signal state according to the soft value; a detection module 30, which is connected to the state selection module 20 and is used to perform maximum likelihood sequence detection according to the target signal state and output a detection result after decoding.
  • ADC analog to digital converter
  • the present disclosure provides a method for detecting a maximum likelihood sequence, including: equalizing an ADC output signal and outputting a soft value according to the ADC output signal; determining a target signal state that matches the soft value. ; Detect the maximum likelihood sequence according to the target signal state, and output the detection result after decoding.
  • the present disclosure provides a maximum likelihood sequence detection device, including: an output module for equalizing an ADC output signal and outputting a soft value according to the ADC output signal; a determination module for To determine the target signal state that matches the soft value; the detection module 30 is configured to detect the maximum likelihood sequence according to the target signal state, and output the detection result after decoding.
  • the present disclosure provides an electronic device, including: a memory, a processor, and computer-executable instructions stored on the memory and executable on the processor, the computer-executable instructions being When the processor is executed, the maximum likelihood sequence detection method described in the second aspect is implemented.
  • the present disclosure provides a computer-readable storage medium that stores one or more programs, and when the one or more programs are executed by an electronic device including a plurality of application programs, such that The electronic device implements the maximum likelihood sequence detection method described in the second aspect.
  • Figure 1 shows a schematic structural diagram of a maximum likelihood sequence detection circuit according to an embodiment of the present disclosure
  • Figure 2 shows a schematic structural diagram of a maximum likelihood sequence detection circuit according to an embodiment of the present disclosure
  • Figure 3 shows a schematic structural diagram of a state selection module according to an embodiment of the present disclosure
  • Figure 4 shows a schematic structural diagram of a maximum likelihood sequence detection circuit according to an embodiment of the present disclosure
  • Figure 5 is a schematic flowchart of a maximum likelihood sequence detection method according to an embodiment of the present disclosure
  • Figure 6 shows a schematic structural diagram of a maximum likelihood sequence detection device according to an embodiment of the present disclosure
  • FIG. 7 shows a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present disclosure.
  • FIG. 1 shows a schematic structural diagram of a maximum likelihood sequence detection circuit according to an embodiment of the present disclosure.
  • the maximum likelihood sequence detection circuit includes: an equalization processing module 10 , a state selection module 20 and a detection module 30 .
  • the equalization processing module 10 is used to perform equalization processing on an analog to digital converter (Analog to Digital Converter, ADC) output signal and output a soft value according to the ADC output signal.
  • the state selection module 20 is connected to the equalization processing module 10 and is used to determine the target signal state according to the soft value.
  • the detection module 30 is connected to the state selection module 20, Used to perform maximum likelihood sequence detection according to the target signal state and output the detection result after decoding.
  • FIG. 2 shows a schematic structural diagram of a maximum likelihood sequence detection circuit according to an embodiment of the present disclosure.
  • the signal processed by the analog front end is sampled by ADC 1 and then the digital signal is sent to the detection circuit 2 of the maximum likelihood sequence.
  • the detection circuit 2 of the maximum likelihood sequence includes: Equalization processing module 10, state selection module 20 and detection module 30 and coefficient adaptation module.
  • the equalization processing module 10 may include: FFE and/or DFE.
  • the equalization processing module 10 may include a DFE and output soft values through the DFE.
  • Detection module 30 may include MLSD.
  • the signals processed by FFE are sent to DFE and MLSD for processing respectively.
  • DFE can work alone or together with MLSD.
  • the DFE can be turned on alone to complete the equalization work.
  • the DFE output is the output of the digital equalization of the receiver.
  • DFE and MLSD may share a set of adaptive tap coefficients.
  • the tap coefficients of the MLSD may also be inconsistent with the DFE. That is, the compensation result of DFE itself is used as a soft value, and a compensation result is calculated as the input of MLSD after excluding the taps covered by MLSD.
  • FIG3 shows a schematic diagram of the structure of a state selection module according to an embodiment of the present disclosure.
  • the state selection module 20 includes: a threshold calculation unit 21 and a threshold comparison unit 22 .
  • the threshold calculation unit 21 is used to calculate the level value corresponding to each state of the signal based on the input first coefficient value, that is, the first tap coefficient value, and calculate the decision threshold based on the level value corresponding to each state.
  • the threshold comparison unit 22 is connected to the threshold calculation unit 21 and is used to select a target signal state that matches the soft value.
  • FIG. 4 shows a schematic structural diagram of a maximum likelihood sequence detection circuit according to an embodiment of the present disclosure.
  • the equalization processing module 10 includes: a delay processor 11 , a multiplication processor 12 , an input port 13 and a decider 14 .
  • the delay processor 11 is used to perform delay processing on the first decision result.
  • the multiplication processor 12 is connected to the delay processor 11 and is used to multiply the delayed first judgment result and the second coefficient value to obtain a compensation parameter.
  • the input port 13 is connected to the multiplication processor 12 for receiving input data and compensation parameters, and compensating the input data according to the compensation parameters to obtain soft values.
  • the determiner 14 is connected to the input port 13 and is used to determine the soft value to obtain a second determination result.
  • the DFE may be one-stage or multi-stage, and the delayed decision result may be one or multiple.
  • the second input data will become the first input data in the next shot processing, and there is a delay relationship between them.
  • the first coefficient value and the second coefficient value are independent of each other, and the coefficients of different taps can be calculated separately.
  • the equalization processing module 10, the state selection module 20 and the detection module 30 can work simultaneously.
  • the detection module 30 includes: MLSD, and the state selection module 20 is set in the MLSD.
  • the first coefficient value and the second coefficient value are different, and the second coefficient value may have multiple values, and the number of the second coefficient value depends on the order of the DFE.
  • MLSD also includes: branch measurement module, addition selection module and survivor path module.
  • FFE equalization is a digital signal that undergoes a finite impulse response. (Finite Impulse Response, FIR) filter.
  • FIR Finite Impulse Response
  • the FFE of the tap coefficient N receives the data d ADC output by the ADC and the FFE coefficient f 0 ⁇ N-1 output by the adaptive module, and obtains the output result d FFE after FIR filtering.
  • This output is sent to the DFE and MLSD as input signals.
  • DFE compensates the input signal through the judgment result and judges the compensated result.
  • the DFE calculates based on the judgment result s DFE of the previous moment and the tap coefficient h 1 after receiving the output d FFE of the FFE. Get the soft value result d DFE .
  • d DFE (t) d FFE (t)-h 1 ⁇ a(s DFE (t-1))
  • a represents the level value corresponding to the judgment result state.
  • the soft value result is sent to the decision maker and compared with the threshold to obtain the decision result.
  • the decision thresholds include:
  • the decision result s DFE is output as the decision result of digital equalization when DFE works alone.
  • MLSD works, the soft value result d DFE obtained before needs to be sent to MLSD.
  • the level value corresponding to each state of the signal is calculated according to the input first coefficient value; the decision threshold is determined according to the level value corresponding to each state; according to the decision Threshold, select at least two target signal states matching the soft value from at least three signal states.
  • the decision threshold from at least three signal states Select at least two target signal states that match the soft value, including at least one of the following situations.
  • the target signal state is the first signal state or the second signal state; the first threshold is determined based on the first signal state parameter and the third signal state parameter.
  • the target signal state is the second signal state or the third signal state; the second threshold is determined based on the second signal state parameter and the fourth signal state.
  • the signal status parameters are determined.
  • the target signal state is a third signal state or a fourth signal state.
  • a group of states whose level value is closest to the DFE soft value is selected as the state branch of MLSD processing.
  • the state selection module calculates the decision threshold based on the coefficients.
  • the PAM4 states are recorded as 0, 1, 2, and 3 from low to high level values.
  • the DFE soft value is not greater than the average of state 0 and state 2
  • the two states closest to the soft value are 0 and 1.
  • the DFE soft value is greater than the mean value of state 0 and state 2
  • the specific calculation and comparison process is as follows:
  • the branch metric module no longer calculates all states of the signal but only selected states.
  • the received selected state level value is multiplied and summed by the tap coefficient, and then the difference is calculated with the FFE output and squared to obtain the branch metric value of the state.
  • BM[0] (d FFE -h 0 ⁇ a(k sel [0](t))-h 1 ⁇ a(k sel [0](t-1))) 2
  • BM[1] (d FFE -h 0 ⁇ a(k sel [0](t))-h 1 ⁇ a(k sel [1](t-1))) 2
  • BM[2] (d FFE -h 0 ⁇ a(k sel [1](t))-h 1 ⁇ a(k sel [0](t-1)) 2
  • BM[3] (d FFE -h 0 ⁇ a(k sel [1](t))-h 1 ⁇ a(k sel [1](t-1)) 2
  • the calculation results are sent to the addition selection module for processing.
  • the plus selection module for each branch state branch, select the branch with a smaller sum of its branch metric and cumulative metric value, and update the cumulative metric value and surviving path.
  • the branch metric values are added and compared in groups of 2, the selection result of the 2 states is output, and the cumulative metric value m is updated. Processed in parallel in 2 plus selection modules.
  • the state selected by m[0] is marked as k[0](t)
  • the state selected by m[1] is marked as k[1](t)
  • the selection result is sent to the survivor path.
  • the survivor path module will point to the stored path according to the comparison selection result of each state branch, and keep the path length unchanged.
  • the state branch obtained by the backtracking is decoded into the corresponding selection state and then output as the decision result.
  • the state branch obtained by the backtracking is decoded into the corresponding selection state and then output as the decision result.
  • This state k[x](t) It represents the direction of the state x at time t to the state at the previous time.
  • the previous state selection result k sel [y](t) also needs to be stored in the survivor path.
  • This state y represents the path state at time t.
  • the survivor path maintains length L, so after adding the state at time t, the state at time tL is deleted.
  • the power consumption and area of MLSD implementation can be effectively reduced.
  • the signal state can be The number is reduced from n to m, and the branch metric operation implemented by the algorithm can be reduced to that of the related scheme in the background technology.
  • the additive selection operation can be reduced to the related scheme in the background art.
  • the number of branches of the surviving path can be reduced to the related scheme in the background technology Taking the selection of 2-state 2-tap MLSD for PAM4 signals as an example, the related scheme in the background technology needs to calculate 16 branch metric values, which can be reduced to 4 in the embodiment of the present invention; the related scheme introduced in the background technology needs to calculate 4 groups of each branch metric value. Groups of 4 branch metric values are subjected to an addition and selection operation. In the embodiment of the present invention, the number is reduced to 2 groups of 2.
  • the related scheme introduced in the background art requires maintaining the surviving paths of 4 state branches. In the embodiment of the present invention, the number is reduced to 2. indivual.
  • MLSD and DFE can also choose to share adaptive coefficients, which can reduce the overhead of the corresponding coefficient adaptation modules.
  • FIG5 is a flow chart of a method for detecting a maximum likelihood sequence according to an embodiment of the present disclosure, which method may be performed by an electronic device, such as a digital equalizer in a high-speed interconnect device. In other words, the method may be performed by software or hardware installed in the electronic device. As shown in FIG5 , the method may include the following steps.
  • Step S502 performing equalization processing on the ADC output signal, and outputting a soft value according to the ADC output signal.
  • outputting a soft value according to the ADC output signal includes: delaying the decision result of the first input data; multiplying the delayed decision result by a second coefficient value to obtain a compensation parameter; Receive the second input data, and compensate the second input data according to the compensation parameter to obtain the soft value.
  • Step S504 Determine the target signal state matching the soft value.
  • the level value corresponding to each state of the signal is calculated according to the input first coefficient value; the decision threshold is determined according to the level value corresponding to each state; according to the decision threshold, from at least three Select at least two target signal states matching the soft value from the signal states.
  • At least two target signal states matching the soft value are selected from at least three signal states according to the decision threshold, including one of the following.
  • the target signal state is the first signal state or the second signal state; the first threshold is determined based on the first signal state parameter and the third signal state parameter.
  • the target signal state is the second signal state or the third signal state; the second threshold is determined based on the second signal state parameter and the fourth signal state.
  • the signal status parameters are determined.
  • the target signal state is a third signal state or a fourth signal state.
  • Step S506 Detect the maximum likelihood sequence according to the target signal state, and output the detection result after decoding.
  • the present disclosure can use the soft value output of DFE to select the signal state in MLSD processing in advance, reduce the number of state branches in MLSD processing, and thereby detect the operation amount and power consumption of the maximum likelihood sequence.
  • FIG. 6 shows a schematic structural diagram of a maximum likelihood sequence detection device according to an embodiment of the present disclosure.
  • the detection device 600 includes: an output module 610, a determination module 620 and a processing module 630.
  • the output module 610 is used to equalize the ADC output signal and output a soft value according to the ADC output signal; the determination module 620 is used to determine a target signal state that matches the soft value; the processing module 630 is used to detect the maximum likelihood sequence according to the target signal state, and output the detection result after decoding.
  • the output module 610 is used to delay the decision result of the first input data; multiply the delayed decision result by the second coefficient value to obtain the compensation parameter; receive the second input data, and The second input data is compensated according to the compensation parameter to obtain the soft value.
  • the determination module 620 is used to calculate the level value corresponding to each state of the signal according to the input first coefficient value; and determine the level value corresponding to each state according to the level value. Determine a decision threshold; select at least two target signal states matching the soft value from at least three signal states according to the decision threshold.
  • the determination module 620 is configured to perform one of the following operations.
  • the target signal state is the first signal state or the second signal state; the first threshold is determined based on the first signal state parameter and the third signal state parameter.
  • the target signal state is the second signal state or the third signal state; the second threshold is determined based on the second signal state parameter and the fourth signal state.
  • the signal status parameters are determined.
  • the target signal state is a third signal state or a fourth signal state.
  • the detection device 600 provided by the present disclosure can execute each method described in the previous method embodiments, and realize the functions and beneficial effects of each method described in the previous method embodiments, which will not be described again here.
  • FIG. 7 shows a schematic diagram of the hardware structure of an electronic device according to the present disclosure.
  • the electronic device includes a processor, optionally including an internal bus, a network interface, and a memory.
  • the memory may include memory, such as high-speed random access memory (Random-Access Memory, RAM), or may also include non-volatile memory (non-volatile memory), such as at least one disk memory.
  • RAM random access memory
  • non-volatile memory such as at least one disk memory.
  • the electronic device may also include other hardware required by the business.
  • the processor, network interface, and memory can be connected to each other through an internal bus, which can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an extended industry standard Structure (Extended Industry Standard Architecture, EISA) bus, etc.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, only a two-way arrow is used in the figure, but it does not mean that there is only one bus or one type of bus.
  • the memory is used to store programs.
  • the program may include program code, and the program code includes computer operation instructions.
  • the memory may include internal memory and non-volatile memory, and provide instructions and data to the processor.
  • the processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, forming a device for locating the target user at the logical level.
  • the processor executes the program stored in the memory, and is specifically configured to execute the maximum likelihood sequence detection method described with reference to Figure 5, and achieve the same technical effect.
  • the method shown in FIG. 5 of the present disclosure can be applied to a processor or implemented by a processor.
  • the processor may be an integrated circuit chip with signal processing capabilities.
  • each step of the method can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software.
  • the processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.
  • the steps of the method disclosed in the present disclosure can be directly embodied as a hardware decoding processor to be executed, or a combination of hardware and software modules in the decoding processor to be executed.
  • the software module can be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc.
  • the storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.
  • the electronic device can also execute each method described in the previous method embodiments, and realize the functions and beneficial effects of each method described in the previous method embodiments, which will not be described again here.
  • the electronic device of the present disclosure does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logical unit. It can also be hardware or logic devices.
  • the present disclosure also proposes a computer-readable storage medium that stores one or more programs that, when executed by an electronic device including a plurality of application programs, causes the electronic device to The device performs maximum likelihood as described with reference to Figure 5 Sequence detection method and achieve the same technical effect.
  • Computer-readable storage media include read-only memory (ROM), random access memory (RAM), magnetic disks or optical disks, etc.
  • the present disclosure also provides a computer program product.
  • the computer program product includes a computer program stored on a non-transitory computer-readable storage medium.
  • the computer program includes program instructions. When the program instructions are executed by a computer, When executed, the detection method of the maximum likelihood sequence described with reference to Figure 5 is implemented, and the same technical effect is achieved.
  • a typical implementation device is a computer.
  • the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or A combination of any of these devices.
  • Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information.
  • Information can be computer readable instructions, data structures, program modules or other data.
  • Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.
  • computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

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Abstract

本公开提供了一种最大似然序列的检测电路、检测方法、检测装置和电子设备，该最大似然序列的检测电路包括：均衡处理模块，其用于对模拟数字转换器(ADC)输出信号进行均衡处理并根据所述ADC输出信号输出软值；状态选择模块，其与所述均衡处理模块连接，并且用于根据所述软值确定目标信号状态；检测模块，其与所述状态选择模块连接，并且用于根据所述目标信号状态进行最大似然序列检测并在译码后输出检测结果。

Description

最大似然序列的检测电路、检测方法、检测装置和电子设备
相关申请的交叉引用
该专利申请要求于2022年9月21日在中国国家知识产权局提交的中国专利申请202211152294.0的优先权，该中国专利申请的公开以引用方式全文并入本文中。
技术领域
本公开涉及电子电路技术领域，尤其涉及一种最大似然序列的检测电路、检测方法、检测装置和电子设备。
背景技术
在高速互联通信接收器中，随着数据速率提升，信道环境恶劣，对数字均衡的能力要求也更高。因此在数字均衡中，在前馈均衡器(Feed Forward Equalizer,FFE)、判决反馈均衡器(Decision Feedback Equalizer,DFE)之外，还引入最大似然序列检测器(Maximum Likelihood Sequence Detector,MLSD)，以提升均衡能力来满足性能需求。在MLSD处理过程中需要对信号的各种状态分支的度量值进行计算，并在此基础上进行加比选、幸存路径更新、路径回溯等操作。各步处理的运算量与状态分支数正相关，而对于信号状态数为M的N抽头MLSD，状态分支数为MN-1。
相关方案中，全部状态分支均需要经过相同的计算过程，通过计算度量值再经过加比选排除，导致检测最大似然序列的运算量和功耗大。
发明内容
本公开实施例的目的是提供一种最大似然序列的检测电路、检测方法、检测装置和电子设备，能够降低检测最大似然序列的运算量 和功耗。
为解决上述技术问题，本公开实施例是通过以下各方面实现的。
第一方面，本公开提供了一种最大似然序列的检测电路，包括：均衡处理模块10，其用于对模拟数字转换器(Analog to Digital Converter，ADC)输出信号进行均衡处理并根据所述ADC输出信号输出软值；状态选择模块20，其与所述均衡处理模块10连接，并且用于根据所述软值确定目标信号状态；检测模块30，其与所述状态选择模块20连接，并且用于根据所述目标信号状态进行最大似然序列检测并在译码后输出检测结果。
第二方面，本公开提供了一种最大似然序列的检测方法，包括：对ADC输出信号进行均衡处理，并根据所述ADC输出信号输出软值；确定与所述软值匹配的目标信号状态；根据所述目标信号状态检测最大似然序列，并在译码后输出检测结果。
第三方面，本公开提供了一种最大似然序列的检测装置，包括：输出模块，其用于对ADC输出信号进行均衡处理，并根据所述ADC输出信号输出软值；确定模块，其用于确定与所述软值匹配的目标信号状态；检测模块30，其用于根据所述目标信号状态检测最大似然序列，并在译码后输出检测结果。
第四方面，本公开提供了一种电子设备，包括：存储器、处理器和存储在所述存储器上并可在所述处理器上运行的计算机可执行指令，所述计算机可执行指令被所述处理器执行时实现上述第二方面所述的最大似然序列的检测方法。
第五方面，本公开提供了一种计算机可读存储介质，所述计算机可读存储介质存储一个或多个程序，所述一个或多个程序被包括多个应用程序的电子设备执行时，使得所述电子设备实现上述第二方面所述的最大似然序列的检测方法。
附图说明
为了更清楚地说明本公开的实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地，下面描述中的附图仅仅是本公开中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1示出根据本公开的实施例的最大似然序列的检测电路的结构示意图；
图2示出根据本公开的实施例的最大似然序列的检测电路的结构示意图；
图3示出根据本公开的实施例的状态选择模块的结构示意图；
图4示出根据本公开的实施例的最大似然序列的检测电路的结构示意图；
图5是根据本公开的实施例的最大似然序列的检测方法的流程示意图；
图6示出根据本公开的实施例的最大似然序列的检测装置的结构示意图；
图7示出根据本公开的实施例的的电子设备的硬件结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本公开中的技术方案，下面将结合本公开的附图，对本公开的实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都应当属于本公开保护的范围。
图1示出根据本公开的实施例的最大似然序列的检测电路的一种结构示意图，最大似然序列的检测电路包括：均衡处理模块10、状态选择模块20和检测模块30。
均衡处理模块10用于对模拟数字转换器(Analog to Digital Converter,ADC)输出信号进行均衡处理并根据所述ADC输出信号输出软值。状态选择模块20与所述均衡处理模块10连接，用于根据所述软值确定目标信号状态。检测模块30与所述状态选择模块20连接， 用于根据所述目标信号状态进行最大似然序列检测并在译码后输出检测结果。
在一种实现方式中，图2示出根据本公开的实施例的最大似然序列的检测电路的结构示意图。在多状态数信号的高速通信链路接收机中，经过模拟前端处理后的信号经过ADC 1采样后将数字信号送至最大似然序列的检测电路2，最大似然序列的检测电路2包括：均衡处理模块10、状态选择模块20和检测模块30和系数自适应模块。均衡处理模块10可以包括：FFE和/或DFE。均衡处理模块10可以包括DFE，并通过DFE输出软值。如果一个系统数字均衡中不包含DFE，则FFE本身的输出已经可以达到较好的均衡效果，那么FFE的输出也可以作为发明方案所需的软值被使用，即均衡处理模块10可以仅包括FFE。检测模块30可以包括MLSD。经FFE处理后的信号分别送至DFE和MLSD进行处理。根据模式选择，DFE可以单独工作也可以和MLSD一起工作，在DFE性能满足预定要求时可以单独开启DFE完成均衡工作，DFE输出即为接收机数字均衡的输出。当需要MLSD工作时可以同时开启DFE和MLSD，将MLSD的输出作为接收机数字均衡的输出。DFE和MLSD的抽头覆盖范围相同，范围之外的码间串扰(InterSymbol Interference,ISI)交由模拟前端以及FFE进行消除。
在实施例中，DFE和MLSD可以共用一套自适应抽头系数。在实施例中，MLSD的抽头系数也可以与DFE不一致。即DFE本身的补偿结果作为软值，而排除掉MLSD覆盖的抽头后再计算一个补偿结果作为MLSD的输入。
对于MLSD，全部状态分支均需要经过相同的计算过程，通过计算度量值再经过加比选排除，即电平值距离DFE软值较远的信号状态，也进行同样的运算再进行排除，造成了运算量的浪费。本公开利用已有的DFE模块输出的软值，可以直接排除掉电平值距离DFE软值较远的信号状态，选择出需要MLSD进行处理的状态分支。这样MLSD在处理过程中就不必对已经排除掉的状态分支进行计算，从而减少了运算量。由于用来筛选的DFE软值本身足够可靠，在软值附近选取状态来进行MLSD处理基本可以保证覆盖到正确信号的状态，因此经过分支 状态数优化后的MLSD性能不会出现下降。这样，利用已有的DFE输出结果，在不会带来明显性能损失的情况下，本公开可以显著降低处理多状态数信号的MLSD实现所需的功耗、面积开销。
在一种实现方式中，图3示出根据本公开的实施例的状态选择模块的结构示意图。如图3所示，所述状态选择模块20，包括：门限计算单元21和门限比较单元22。
门限计算单元21用于根据输入的第一系数值，即第一抽头系数值，计算得到信号各状态对应的电平值，根据所述各状态对应的电平值计算判决门限。门限比较单元22与所述门限计算单元21连接，用于选择与所述软值匹配的目标信号状态。
在一种实现方式中，图4示出根据本公开的实施例的最大似然序列的检测电路的结构示意图。如图4所示，均衡处理模块10包括：延迟处理器11、乘法处理器12、输入端口13和判决器14。
延迟处理器11用于对第一判决结果进行延迟处理。乘法处理器12与所述延迟处理器11连接，用于对延迟后的所述第一判决结果与第二系数值相乘得到补偿参数。输入端口13与所述乘法处理器12连接，用于接收输入数据和补偿参数，并根据所述补偿参数对所述输入数据进行补偿，得到软值。判决器14与所述输入端口13连接，用于对所述软值进行判决得到第二判决结果。
在实施例中，DFE可以是一阶的也可以是多阶的，延迟后的判决结果可以是一个也可以是多个。第二输入数据在下一拍处理中会变成第一输入数据，它们之间有延迟的关系。第一系数值和第二系数值是相互独立的，针对不同抽头的系数，可以分别进行计算。
所述均衡处理模块10、所述状态选择模块20和所述检测模块30可以同时工作。在一种实现方式中，检测模块30包括：MLSD,状态选择模块20设置在MLSD中。在实施例中，第一系数值和第二系数值不相同，并且第二系数值可以为多个值，第二系数值的个数取决于DFE的阶数。MLSD还包括：支路度量模块、加比选模块和幸存路径模块。
具体来讲，FFE均衡就是数字信号经过一个有限冲击响应 (Finite Impulse Response，FIR)滤波器。抽头系数N的FFE收到ADC输出的数据dADC以及自适应模块输出的FFE系数f0～N-1，经过FIR滤波处理得到输出结果dFFE。
该输出结果被发送至DFE和MLSD作为输入信号。
DFE通过判决结果对输入信号进行补偿并对补偿后的结果进行判决。以四电平脉冲幅度调制(4-Level Pulse Amplitude Modulation，PAM4)信号的1抽头DFE为例，DFE在接收到FFE的输出dFFE后根据前一时刻的判决结果sDFE与抽头系数h1计算得到软值结果dDFE。
dDFE(t)＝dFFE(t)-h1×a(sDFE(t-1))
式中a表示判决结果状态对应的电平值。将软值结果送入判决器与门限进行比较得到判决结果。对于PAM4信号，判决门限包括：


当软值结果dDFE≤thrDFE[0]时，判决结果sDFE＝0，当软值结果thrDFE[0]＜dDFE≤thrDFE[1]时，sDFE＝1，当软值结果thrDFE[1]＜dDFE≤thrDFE[2]时，sDFE＝2，当dDFE＞thrDFE[2]时，sDFE＝3。得到的判决结果sDFE在DFE单独工作时作为数字均衡的判决结果输出，当MLSD工作时需要将之前得到的软值结果dDFE送至MLSD。除此之外，在得到判决结果后还需要计算得到误差信息并送至自适应模块以进行系数自适应。
err＝dDFE-h0×a(sDFE)
在状态选择模块20，在一种实现方式中，根据输入的第一系数值，计算得到信号各状态对应的电平值；根据所述各状态对应的电平值确定判决门限；根据所述判决门限，从至少三个信号状态中选择至少两个与所述软值匹配的目标信号状态。
在一种实现方式中，根据所述判决门限，从至少三个信号状态 中选择至少两个与所述软值匹配的目标信号状态，包括以下情况中的至少一种。
在所述软值小于或等于第一门限时，所述目标信号状态为第一信号状态或第二信号状态；所述第一门限是根据第一信号状态参数和第三信号状态参数确定的。
在所述软值大于所述第一门限且小于等于第二门限时，所述目标信号状态为第二信号状态或第三信号状态；所述第二门限是根据第二信号状态参数和第四信号状态参数确定的。
在所述软值大于所述第二门限时，所述目标信号状态为第三信号状态或第四信号状态。
例如，选择出电平值与DFE软值最近的一组状态作为MLSD处理的状态分支。以PAM4信号选择出2状态为例，状态选择模块根据系数计算出判决门限。将PAM4状态按照电平值从低到高记为0、1、2、3，当DFE软值不大于状态0和状态2的均值时，距离软值最近的2个状态即为0和1。当DFE软值大于状态0和状态2的均值时，需要再与状态1和状态3的均值进行比较，若不大于该值，则距离软值较近的2个状态为1和2，否则为2和3。具体计算和比较过程如下所示：

当DFE送来的软值结果dDFE≤thrMLSD[0]时，选择状态ksel＝[0，1]，当thrMLSD[0]＜dDFE≤thrMLSD[1]时，ksel＝[1，2]，当dDFE＞thrMLSD[1]时，ksel＝[2，3]。这样就将MLSD需要处理的状态数从4降低至2，将状态选择结果送至后续的支路度量以及幸存路径部分以便进行后续处理。
支路度量模块不再对信号的所有状态而是对选择出的状态进行计算。将收到的选择状态电平值与抽头系数相乘求和，之后与FFE输出求差并进行平方运算得到该状态的支路度量值。以PAM4信号选择出2状态，2抽头MLSD为例，背景技术中相关方案MLSD对于PAM4信号共有42＝16种支路度量组合，经过选择后将分支状态组合数降 低至22＝4，在4支路度量模块中并行计算。
BM[0]＝(dFFE-h0×a(ksel[0](t))-h1×a(ksel[0](t-1)))2
BM[1]＝(dFFE-h0×a(ksel[0](t))-h1×a(ksel[1](t-1)))2
BM[2]＝(dFFE-h0×a(ksel[1](t))-h1×a(ksel[0](t-1)))2
BM[3]＝(dFFE-h0×a(ksel[1](t))-h1×a(ksel[1](t-1)))2
计算结果送至加比选模块进行处理。在加比选模块，对于每个分支状态的分支，选择其支路度量与累计度量值之和较小的分支，更新累计度量值和幸存路径。以PAM4信号选择出2状态，MLSD2抽头为例，支路度量值2个一组进行加比选运算，输出2状态的选择结果，并更新累计度量值m。在2个加比选模块中并行处理。
m[0](t)＝min{BM[0]+m[0](t-1)，BM[1]+m[1](t-1)}
m[1](t)＝min{BM[2]+m[0](t-1)，BM[3]+m[1](t-1)}
m[0]选择出的状态记为k[0](t)，m[1]选择出的状态记为k[1](t)，将选择结果送至幸存路径。
幸存路径模块，按照每个状态分支的加比选结果将指向存入路径，并保持路径长度不变。在回溯输出时，将回溯得到的状态分支译码为对应的选择状态再作为判决结果输出。以PAM4信号选择出2状态，MLSD2抽头为例，将此前加比选得到的k[0](t)、k[1](t)存入幸存路径中，这个状态k[x](t)就表示了t时刻状态x对上一时刻状态的指向，除此之外，还需要将之前的状态选择结果ksel[y](t)存入幸存路径，这个状态y表示了t时刻路径状态对应的信号状态。幸存路径保持长度L，因此加入t时刻状态后就删去t-L时刻的状态。
路径更新完成之后进行回溯，选择累计度量值较小的状态作为起点，根据该状态对上一时刻状态的指向向前回溯，直至回溯长度达到幸存路径的长度L，最终回溯到的状态0/1对应的选择状态ksel[0/1]就是MLSD对t-L+1时刻信号的判决结果，作为判决结果进行输出，也就是数字均衡的输出。
通过选择减少MLSD的分支状态数可以有效减少MLSD实现的功耗和面积。对于a抽头的MLSD，通过本发明实施例可以将信号状态 数从n减少至m，算法实现的支路度量运算可减少为背景技术中相关方案的加比选运算可减少为背景技术中相关方案的幸存路径的分支数可减少为背景技术中相关方案以对PAM4信号选择2状态的2抽头MLSD为例，背景技术中相关方案需要计算16个支路度量值，本发明实施例可减少为4个；背景技术中介绍的相关方案需要对4组每组4个支路度量值进行加比选运算，本发明实施例减少为2组每组2个；背景技术中介绍的相关方案需要保持4个状态分支的幸存路径，本发明实施例减少为2个。可见本发明实施例优化后MLSD实现所需的功耗、面积都有明显的降低。并且，使用DFE软值信息进行选择能够在减少分支状态数的同时保证数字均衡的性能，在降低功耗、面积代价的同时避免出现性能损失。此外，MLSD与DFE也可以选择共用自适应系数，这样就可以减少对应的系数自适应模块的开销。
图5是根据本公开的实施例的最大似然序列的检测方法的流程示意图，该方法可以由电子设备执行，例如高速互联设备中的数字均衡器。换言之，所述方法可以由安装在电子设备的软件或硬件来执行。如图5所示，该方法可以包括以下步骤。
步骤S502：对ADC输出信号进行均衡处理，并根据所述ADC输出信号输出软值。
在一种实现方式中，根据所述ADC输出信号输出软值，包括：对第一输入数据的判决结果进行延迟处理；对延迟后的所述判决结果与第二系数值相乘得到补偿参数；接收第二输入数据，并根据所述补偿参数对所述第二输入数据进行补偿，得到所述软值。具体与参照图1至图4描述的均衡处理模块10部分的说明类似，在此不再赘述。
步骤S504：确定与所述软值匹配的目标信号状态。
在一种实现方式中，根据输入的第一系数值，计算得到信号各状态对应的电平值；根据所述各状态对应的电平值确定判决门限；根据所述判决门限，从至少三个信号状态中选择至少两个与所述软值匹配的目标信号状态。
在一种实现方式中，根据所述判决门限，从至少三个信号状态中选择至少两个与所述软值匹配的目标信号状态，包括以下之一。
在所述软值小于或等于第一门限时，所述目标信号状态为第一信号状态或第二信号状态；所述第一门限是根据第一信号状态参数和第三信号状态参数确定的。
在所述软值大于所述第一门限且小于等于第二门限时，所述目标信号状态为第二信号状态或第三信号状态；所述第二门限是根据第二信号状态参数和第四信号状态参数确定的。
在所述软值大于所述第二门限时，所述目标信号状态为第三信号状态或第四信号状态。
具体与参照图1至图4描述的均衡处理模块10部分的说明类似，在此不再赘述。
步骤S506：根据所述目标信号状态检测最大似然序列，并在译码后输出检测结果。
具体与参照图1至图4描述的检测模块30部分的说明类似，在此不再赘述。
本公开能够利用DFE的软值输出对MLSD处理时的信号状态提前进行选择，降低MLSD处理中的状态分支数，从而检测最大似然序列的运算量和功耗。
图6示出根据本公开的实施例的最大似然序列的检测装置的结构示意图。该检测装置600包括：输出模块610、确定模块620和处理模块630。
在一种实现方式中，输出模块610用于对ADC输出信号进行均衡处理，并根据所述ADC输出信号输出软值；确定模块620用于确定与所述软值匹配的目标信号状态；处理模块630用于根据所述目标信号状态检测最大似然序列，并在译码后输出检测结果。
在一种实现方式中，输出模块610用于对第一输入数据的判决结果进行延迟处理；对延迟后的所述判决结果与第二系数值相乘得到补偿参数；接收第二输入数据，并根据所述补偿参数对所述第二输入数据进行补偿，得到所述软值。
在一种实现方式中，确定模块620用于根据输入的第一系数值，计算得到信号各状态对应的电平值；根据所述各状态对应的电平值确 定判决门限；根据所述判决门限，从至少三个信号状态中选择至少两个与所述软值匹配的目标信号状态。
在一种实现方式中，确定模块620用于执行以下操作之一。
在所述软值小于或等于第一门限时，所述目标信号状态为第一信号状态或第二信号状态；所述第一门限是根据第一信号状态参数和第三信号状态参数确定的。
在所述软值大于所述第一门限且小于等于第二门限时，所述目标信号状态为第二信号状态或第三信号状态；所述第二门限是根据第二信号状态参数和第四信号状态参数确定的。
在所述软值大于所述第二门限时，所述目标信号状态为第三信号状态或第四信号状态。
本公开提供的该检测装置600可执行前文方法实施例中所述的各方法，并实现前文方法实施例中所述的各方法的功能和有益效果，在此不再赘述。
图7示出根据本公开的电子设备的硬件结构示意图。参考图7，在硬件层面，电子设备包括处理器，可选地，包括内部总线、网络接口、存储器。存储器可包含内存，例如高速随机存取存储器(Random-Access Memory，RAM)，也可还包括非易失性存储器(non-volatile memory)，例如至少1个磁盘存储器等。当然，该电子设备还可包括其他业务所需要的硬件。
处理器、网络接口和存储器可以通过内部总线相互连接，该内部总线可以是工业标准体系结构(Industry Standard Architecture，ISA)总线、外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，该图中仅用一个双向箭头表示，但并不表示仅有一根总线或一种类型的总线。
存储器用于存放程序。具体地，程序可以包括程序代码，所述程序代码包括计算机操作指令。存储器可以包括内存和非易失性存储器，并向处理器提供指令和数据。
处理器从非易失性存储器中读取对应的计算机程序到内存中然后运行，在逻辑层面上形成定位目标用户的装置。处理器，执行存储器所存放的程序，并具体用于执行参照图5描述的最大似然序列的检测方法，并实现相同的技术效果。
上述如本公开的图5所示的方法可以应用于处理器中，或者由处理器实现。处理器可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器可以是通用处理器，包括中央处理器(Central Processing Unit，CPU)、网络处理器(Network Processor，NP)等；还可以是数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field－Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本公开中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本公开所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
该电子设备还可执行前文方法实施例中所述的各方法，并实现前文方法实施例中所述的各方法的功能和有益效果，在此不再赘述。
当然，除了软件实现方式之外，本公开的电子设备并不排除其他实现方式，比如逻辑器件抑或软硬件结合的方式等等，也就是说以下处理流程的执行主体并不限定于各个逻辑单元，也可以是硬件或逻辑器件。
本公开还提出了一种计算机可读存储介质，所述计算机可读介质存储一个或多个程序，所述一个或多个程序当被包括多个应用程序的电子设备执行时，使得所述电子设备执行参照图5描述的最大似然 序列的检测方法，并实现相同的技术效果。
计算机可读存储介质包括只读存储器(Read-Only Memory，简称ROM)、随机存取存储器(Random Access Memory，简称RAM)、磁碟或者光盘等。
进一步地，本公开还提供了一种计算机程序产品，所述计算机程序产品包括存储在非暂态计算机可读存储介质上的计算机程序，所述计算机程序包括程序指令，当所述程序指令被计算机执行时，实现参照图5描述的最大似然序列的检测方法，并实现相同的技术效果。
总之，以上所述仅为本公开的优选实施例，并非用于限定本公开的保护范围。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。
上述实施例阐明的系统、装置、模块或单元，具体可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算机。具体的，计算机例如可以为个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任何设备的组合。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带，磁带磁磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、 商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。

Claims (12)

  1. 一种最大似然序列的检测电路，包括：
    均衡处理模块，其用于对模拟数字转换器(ADC)输出信号进行均衡处理并根据所述ADC输出信号输出软值；
    状态选择模块，其与所述均衡处理模块连接，并且用于根据所述软值确定目标信号状态；
    检测模块，其与所述状态选择模块连接，并且用于根据所述目标信号状态进行最大似然序列检测并在译码后输出检测结果。
  2. 根据权利要求1所述的检测电路，其中，所述状态选择模块包括：
    门限计算单元，其用于根据输入的第一系数值，计算得到信号各状态对应的电平值，根据所述各状态对应的电平值计算判决门限；
    门限比较单元，其与所述门限计算单元连接，用于选择与所述软值匹配的目标信号状态。
  3. 根据权利要求1所述的检测电路，其中，所述均衡处理模块包括：
    延迟处理器，其用于对第一判决结果进行延迟处理；
    乘法处理器，其与所述延迟处理器连接，用于对延迟后的所述第一判决结果与第二系数值相乘得到补偿参数；
    输入端口，其与所述乘法处理器连接，用于接收输入数据，并根据所述补偿参数对所述输入数据进行补偿，得到所述软值；
    判决器，其与所述输入端口连接，用于对所述软值进行判决得到第二判决结果。
  4. 根据权利要求1所述的检测电路，其中，所述均衡处理模块、所述状态选择模块和所述检测模块同时工作。
  5. 根据权利要求1所述的检测电路，其中，所述均衡处理模块包括：前馈均衡器(FFE)和/或判决反馈均衡器(DFE)。
  6. 一种最大似然序列的检测方法，包括：
    对模拟数字转换器(ADC)输出信号进行均衡处理，并根据所述ADC输出信号输出软值；
    确定与所述软值匹配的目标信号状态；
    根据所述目标信号状态检测最大似然序列，并在译码后输出检测结果。
  7. 根据权利要求6所述的检测方法，其中，根据所述ADC输出信号输出软值包括：
    对第一输入数据的判决结果进行延迟处理；
    对延迟后的所述判决结果与第二系数值相乘得到补偿参数；
    接收第二输入数据，并根据所述补偿参数对所述第二输入数据进行补偿，得到所述软值。
  8. 根据权利要求6所述的检测方法，其中，确定与所述软值匹配的目标信号状态包括：
    根据输入的第一系数值，计算得到信号各状态对应的电平值；
    根据所述各状态对应的电平值确定判决门限；
    根据所述判决门限，从至少三个信号状态中选择至少两个与所述软值匹配的目标信号状态。
  9. 根据权利要求8所述的检测方法，其中，根据所述判决门限，从至少三个信号状态中选择至少两个与所述软值匹配的目标信号状态包括以下步骤之一：
    在所述软值小于或等于第一门限时，所述目标信号状态为第一信号状态或第二信号状态，所述第一门限是根据第一信号状态参数和第三信号状态参数确定的；
    在所述软值大于所述第一门限且小于等于第二门限时，所述目标信号状态为第二信号状态或第三信号状态，所述第二门限是根据第二信号状态参数和第四信号状态参数确定的；
    在所述软值大于所述第二门限时，所述目标信号状态为第三信号状态或第四信号状态。
  10. 一种最大似然序列的检测装置，包括：
    输出模块，其用于对模拟数字转换器(ADC)输出信号进行均衡处理，并根据所述ADC输出信号输出软值；
    确定模块，其用于确定与所述软值匹配的目标信号状态；
    处理模块，其用于根据所述目标信号状态检测最大似然序列，并在译码后输出检测结果。
  11. 一种电子设备，包括：
    处理器；以及
    存储计算机可执行指令的存储器，所述可执行指令在被所述处理器执行时，使得所述处理器执行根据权利要求6-9中任一项所述的最大似然序列的检测方法。
  12. 一种计算机可读介质，所述计算机可读介质存储一个或多个程序，所述一个或多个程序被包括多个应用程序的电子设备执行时，使得所述电子设备执行根据权利要求6-9中任一项所述的最大似然序列的检测方法。
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