WO2024242544A1 - Multilayer filter and front end module comprising same - Google Patents

Abstract

A multilayer filter of an embodiment comprises: first and second ground layers; a plurality of conductive pattern layers disposed between the first ground layer and the second ground layer; and a dielectric layer disposed between the first and second ground layers and the plurality of conductive pattern layers, wherein adjacent conductive pattern layers among the plurality of conductive pattern layers include capacitance pattern layers forming a first capacitance, and at least some of the plurality of conductive pattern layers include an inductance pattern layer forming an inductor, wherein the capacitance pattern layers face each of the first and second ground layers to form parasitic capacitance, and filter a signal having a desired frequency band by using the first capacitor, the inductor, and the parasitic capacitance.

Description

Multilayer filter and front-end module including same

The embodiment relates to a multilayer filter and a front-end module including the same.

Wi-Fi 6E is an extension of Wi-Fi 6 (also known as 802.11ax) that enables functionality on the 6 GHz band in addition to the currently supported 2.4 GHz and 5 GHz bands. Wi-Fi 6E operates under the same Wi-Fi standard as Wi-Fi 6, but with a wider spectrum. 6 GHz is a new frequency band ranging from 5.945 GHz to 7.125 GHz, allowing for up to 1,200 MHz of additional spectrum. Unlike existing frequencies where many channels are densely packed into a limited spectrum, the 6 GHz band allows networks to utilize more bandwidth, faster speeds, and lower latency without the problems of overlap and interference.

However, as the frequency increases, the directivity of the radio wave increases, which increases the level attenuation of the propagated signal, which causes a decrease in the data processing rate (throughput). To compensate for this, a front end module is required to distinguish the frequency band.

A front-end module (FEM) is a transceiver that controls radio signals used in mobile communication terminals. It refers to a composite component in which several electronic components are implemented serially on a single substrate and the integrated space is minimized. Most of these existing front-end modules use elastic wave filters such as SAW (Surface acoustic wave) or BAW (Bulk acoustic wave) filters. As a result, the price and size of existing front-end modules have increased, and research is being conducted on this.

The embodiment provides an inexpensive and compact multilayer filter and a front-end module including the same.

According to one embodiment, a multilayer filter comprises first and second ground layers; a plurality of conductive pattern layers disposed between the first ground layer and the second ground layer; and a dielectric layer disposed between the first and second ground layers and the plurality of conductive pattern layers, wherein adjacent conductive pattern layers among the plurality of conductive pattern layers include capacitance pattern layers forming a first capacitance, and at least some of the plurality of conductive pattern layers include inductance pattern layers forming an inductor, wherein the capacitance pattern layers form parasitic capacitances facing each of the first and second ground layers, and a signal having a desired frequency band can be filtered using the first capacitor, the inductor, and the parasitic capacitance.

For example, the capacitance pattern layer and the inductance pattern layer may have a shape that is symmetrical with respect to an imaginary horizontal line passing through the center of the long axis of the multilayer filter and parallel to the short axis direction of the multilayer filter.

For example, the plurality of conductive pattern layers may include first to third conductive pattern layers sequentially laminated between the first ground layer and the second ground layer.

For example, the inductance pattern layer may include a first inductor layer disposed on the second conductive pattern layer; a second inductor layer disposed across the second conductive pattern layer and the third conductive pattern layer; a third inductor layer disposed on the first conductive pattern layer; and a fourth inductor layer disposed on the third conductive pattern layer.

For example, each of the first, second, third and fourth inductor layers may have a planar shape that is folded at least once in the horizontal direction.

For example, the capacitance pattern layer may include a first capacitor layer disposed on the second conductive pattern layer; and a second capacitor layer disposed on the third conductive pattern layer and facing the first capacitor layer to form the first capacitance.

For example, the plurality of conductive pattern layers may further include fourth and fifth conductive pattern layers sequentially laminated between the third conductive pattern layer and the second ground layer.

For example, the capacitance pattern layer may further include a third capacitor layer connected to the first capacitor layer; and a fourth capacitor layer connected to the second capacitor layer.

For example, the multilayer filter may include a first via connecting the first capacitor layer and the third capacitor layer; and a second via connecting the second capacitor layer and the fourth capacitor layer.

For example, the first capacitance may include an eleventh capacitance formed by opposing the first capacitor layer and the second capacitor layer; a twelfth capacitance formed by opposing the second capacitor layer and the third capacitor layer; and a thirteenth capacitance formed by opposing the third capacitor layer and the fourth capacitor layer.

For example, the parasitic capacitance may include a first parasitic capacitance formed by each of the first capacitor layer and the third capacitor layer facing the first and second ground layers, respectively; and a second parasitic capacitance formed by each of the second capacitor layer and the fourth capacitor layer facing the first and second ground layers, respectively.

For example, the first capacitor layer may include eleventh and twelfth capacitor layers facing each other and spaced apart in the horizontal direction by a first distance, and the third capacitor layer may include thirty-first and 32nd capacitor layers facing each other and spaced apart in the horizontal direction by a second distance.

For example, the first or second distance may be 50 μm to 300 μm.

For example, the first via may include an eleventh via connecting the eleventh capacitor layer and the 31st capacitor layer; and a twelfth via connecting the twelfth capacitor layer and the 32nd capacitor layer.

For example, the second capacitor layer may include a first through hole through which the eleventh via passes and is spaced apart from the eleventh via; and a second through hole through which the twelfth via passes and is spaced apart from the twelfth via.

For example, the 31st and 32nd capacitor pattern layers may have a planar shape spaced apart from each other with the second via interposed therebetween.

For example, the second inductor layer may include a second upper inductor layer having one end connected to the first capacitor layer and disposed on the second conductive pattern layer; and a second lower inductor layer having one end connected to the other end of the second upper inductor layer and the other end connected to the second capacitor layer and disposed on the third conductive pattern layer.

For example, the multilayer filter may include a 31st via connected to one end of the 21st upper inductor layer, which is one of the 11th capacitor layer and the second upper inductor layer, and one end of the 11th inductor layer, which is one of the first inductor layers; a 32nd via connected to one end of the 22nd upper inductor layer, which is the other of the 12th capacitor layer and the second upper inductor layer, and one end of the 12th inductor layer, which is the other of the first inductor layers; a 41st via connected to the other end of the 11th inductor layer and the first port; a 42nd via connected to the other end of the 12th inductor layer and the second port; a 5th via connected to one end of the 31st inductor layer, which is one of the third inductor layers, and the first ground layer; a 61st via connected to the other end of the 21st upper inductor layer; a 62nd via connected to the other end of the 22nd upper inductor layer; It may include a 71st via connected to one end of a 41st inductor layer, which is one of the fourth inductor layers; a 72nd via connected to one end of a 42nd inductor layer, which is another of the fourth inductor layers; and at least one 8th via connecting the first ground layer and the second ground layer.

For example, the other end of the 31st inductor layer may be connected to the 11th via, one end and the other end of the 32nd inductor layer, which is another of the 3rd inductor layers, may be connected to the 5th via and the 12th via, respectively, the 21st lower inductor layer, which is one of the 2nd lower inductor layers, may have one end and the other end respectively connected to the 61st via and the second capacitor layer, the 22nd lower inductor layer, which is another of the 2nd lower inductor layers, may have one end and the other end respectively connected to the 62nd via and the second capacitor layer, and the other ends of each of the 41st inductor layer and the 42nd inductor layer may be connected to the second capacitor layer.

In another embodiment, a multilayer filter comprises: an eleventh inductor having one end connected to a first port; a twelfth inductor having one end connected to a second port; a 21st inductor having one end connected to the other end of the eleventh inductor; a 22nd inductor having one end connected to the other end of the 12th inductor; a 31st inductor connected between the other end of the eleventh inductor and ground; a 32nd inductor connected between the other end of the 12th inductor and the ground; a 41st inductor connected between the other end of the 21st inductor and the ground; a 42nd inductor connected between the other end of the 22nd inductor and the ground; a eleventh capacitor connected in parallel to the 21st inductor; a 12th capacitor connected in parallel to the 22nd inductor; a 21st capacitor connected in parallel to the 31st inductor; a 22nd capacitor connected in parallel to the 32nd inductor; And it may include a third capacitor connected in parallel with the 41st and 42nd inductors between the contact points of the 21st and 22nd inductors and the ground.

For example, the twenty-first, twenty-second and third capacitors may be parasitic capacitances.

A front-end module according to another embodiment may include: an antenna; a first amplifier for amplifying a signal received through the antenna; a multilayer filter for filtering and outputting the signal amplified by the first amplifier; a second amplifier for amplifying a signal to be transmitted through the antenna; and a switch disposed between each of an input terminal of the first amplifier and an output terminal of the second amplifier and the antenna.

A multilayer filter according to an embodiment and a front-end module including the same have a small size, enable easy frequency tuning, and have a configuration that allows easy increase in capacitance and inductance.

Figure 1 shows a cross-sectional view of a multilayer filter according to an embodiment.

FIG. 2 schematically illustrates a perspective view according to one embodiment of the multilayer filter illustrated in FIG. 1.

Figure 3 shows a circuit diagram of a multilayer filter according to one embodiment.

Figure 4 shows a perspective view of the exterior of a multilayer filter according to one embodiment.

FIG. 5a shows a perspective view of the multilayer filter illustrated in FIG. 4 with the first ground layer removed.

Figure 5b shows a plan view of the perspective view shown in Figure 5a.

Figure 6 shows a plan view of the first challenge pattern layer illustrated in Figure 5b.

Figure 7a shows a perspective view of Figure 5a with the first challenge pattern layer removed.

Figure 7b shows a plan view of the second challenge pattern layer.

Figure 8a shows a perspective view of Figure 7a with the second challenge pattern layer removed.

Figure 8b shows a plan view of the third challenge pattern layer.

Figure 9a shows a perspective view of Figure 8a with the third challenge pattern layer removed.

Figure 9b shows a plan view of the fourth challenge pattern layer.

Figure 10a shows a perspective view of Figure 9a with the fourth challenge pattern layer removed.

Figure 10b shows a plan view of the fifth challenge pattern layer.

Figure 11 is a cross-sectional view taken along line I-I’ of the multilayer filter illustrated in Figure 4.

Figure 12 is a graph examining the performance of a multilayer filter according to an embodiment.

Figure 13 shows a block diagram of a front-end module according to an embodiment.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

However, the technical idea of the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention can be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, can be interpreted in consideration of the contextual meaning of the related technology.

In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “A and (or) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, C.

In addition, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and are not intended to limit the nature, order, or sequence of the components.

In addition, when a component is described as being “connected,” “coupled,” or “connected” to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is “connected,” “coupled,” or “connected” by another component between the component and the other component.

In addition, when described as being formed or arranged “above or below” each component, above or below includes not only the case where the two components are in direct contact with each other, but also the case where one or more other components are formed or arranged between the two components. In addition, when expressed as “above or below,” it can include the meaning of the downward direction as well as the upward direction based on one component.

Hereinafter, a multilayer filter (100, 100A) and a front-end module (200) including the same according to an embodiment will be described with reference to the attached drawings as follows. For convenience, the multilayer filter (100, 100A) will be described using a Cartesian coordinate system (x-axis, y-axis, z-axis), but it is obvious that the multilayer filter (100, 100A) can also be described using other coordinate systems. In addition, according to the Cartesian coordinate system, the x-axis, the y-axis, and the z-axis are orthogonal to each other, but the embodiment is not limited thereto. That is, the x-axis, the y-axis, and the z-axis may intersect each other. Hereinafter, for convenience of explanation, the x-axis direction is referred to as a ‘first direction’, the y-axis direction is referred to as a ‘second direction’, and the z-axis direction is referred to as a ‘third direction’.

Figure 1 shows a cross-sectional view of a multilayer filter (100) according to an embodiment.

According to an embodiment, the multilayer filter (100) includes a plurality of layers. That is, as illustrated in FIG. 1, the multilayer filter (100) may include a first ground (or ground) layer (GL1), a second ground layer (GL2), first to Nth conductive pattern layers (TL1 to TLN), and dielectric layers (or printed circuit boards (PCBs)) (DL1 to DL(N+1)). Here, N is a positive integer greater than or equal to 3.

The first to Nth challenge pattern layers (TL1 to TLN) can be sequentially stacked and arranged in a third direction between the first ground layer (GL1) and the second ground layer (GL2).

According to an embodiment, the ground connected to each of the first and second ground layers (GL1, GL2) may be an RF ground or a DC ground. Here, when the multilayer filter (100) is a single product, each of the first and second ground layers (GL1, GL2) is connected to an RF ground, and when the multilayer filter (100) is included in a front-end module (200) described later, each of the first and second ground layers (GL1, GL2) may be connected to an RF or DC ground, but the embodiment is not limited thereto.

In addition, the dielectric layers (DL1 to DL(N+1)) may be disposed between the first and second ground layers (GL1, GL2) and the first to Nth conductive pattern layers (TL1 to TLN). That is, the first dielectric layer (DL1) may be disposed between the first ground layer (GL1) and the first conductive pattern layer (TL1), and the N+1th dielectric layer (DL(N+1)) may be disposed between the Nth conductive pattern layer (TLN) and the second ground layer (GL2). In this way, the kth dielectric layer (DLk) may be disposed between the kth conductive pattern layer (TLk) and the k+1th conductive pattern layer (TL(k+1)). Here, 1≤k≤N-1. In this way, the number of dielectric layers may be one more than the number of conductive pattern layers.

If N=3, the first to third conductive pattern layers (TL1 to TL3) may be sequentially laminated between the first ground layer (GL1) and the second ground layer (GL2), and the first to fourth dielectric layers (DL1 to DL4) may be arranged between the first ground layer (GL1), the first to third conductive pattern layers (TL1 to TL3), and the second ground layer (GL2).

FIG. 2 schematically illustrates a perspective view of one embodiment (100A) of the multilayer filter (100) illustrated in FIG. 1.

When N=5, as illustrated in FIG. 2, first to fifth conductive pattern layers (TL1 to TL5) may be sequentially stacked and arranged between the first ground layer (GL1) and the second ground layer (GL2), and first to sixth dielectric layers (DL1 to DL6) may be arranged between the first ground layer (GL1), the first to fifth conductive pattern layers (TL1 to TL5), and the second ground layer (GL2), respectively.

Adjacent conductive pattern layers among the first to Nth conductive pattern layers (TL1 to TLN) may include capacitance pattern layers forming a first capacitance. For example, vertically adjacent second conductive pattern layers (TL2) and third conductive pattern layers (TL3) may each have their respective capacitor pattern layers implemented as conductors having electrical conductivity, and a third dielectric layer (DL3) made of a dielectric material may be disposed therebetween, thereby forming a first capacitance.

Additionally, at least some of the first to Nth conductive pattern layers (TL1 to TLN) may include an inductance pattern layer forming an inductor. For this purpose, the inductance pattern layer may be implemented as a conductor. For example, each of the first to third conductive pattern layers (TL1 to TL3) may include an inductance pattern layer.

Additionally, according to the embodiment, the capacitance pattern layer forming the first capacitor can form parasitic capacitances forming the second and third capacitors facing the first and second ground layers (GL1, GL2), respectively.

As described above, the multilayer filter (100, 100A) according to the implemented embodiment may be a bandpass filter that filters a signal having a desired frequency band by using a first capacitor, an inductor, and second and third capacitors.

Hereinafter, a multilayer filter according to an embodiment of the present invention will be described as follows, in which N=5, the second to fifth conductive pattern layers (TL2 to TL5), excluding the first conductive pattern layer (TL1), include capacitance pattern layers, and the first, second, and third conductive pattern layers (TL1 to TL3) include inductance pattern layers.

Figure 3 shows a circuit diagram of a multilayer filter according to one embodiment.

The multilayer filter according to the embodiment illustrated in FIG. 3 is a kind of bandpass filter and includes the eleventh, twelfth, twentieth, twenty-first, twenty-second, thirty-first, thirty-second, forty-first, and forty-second inductors (L11, L12, L21, L22, L31, L32, L41, L42), and the eleventh, twelfth, twentieth, twenty-first, twenty-second, and third capacitors (C11, C12, C21, C22, C3).

The eleventh inductor (L11) has one end connected to the first port (P1). The twelfth inductor (L12) has one end connected to the second port (P2).

The first port (P1) may be an input port from which a signal enters and the second port (P2) may be an output port from which a signal is output. Alternatively, the first port (P1) may be an output port from which a signal is output and the second port (P2) may be an input port from which a signal enters.

The 21st inductor (L21) has one end connected to the other end of the 11th inductor (L11), and the 22nd inductor (L22) has one end connected to the other end of the 12th inductor (L12). The 31st inductor (L21) can be connected between the other end of the 11th inductor (L11), that is, a point of contact between the 11th inductor (L11) and the 21st inductor (L21), and ground, and the 32nd inductor (L32) can be connected between the other end of the 12th inductor (L12), that is, a point of contact between the 12th inductor (L12) and the 22nd inductor (L22), and ground.

The 41st inductor (L41) may be connected between the other terminal of the 21st inductor (L21), that is, the contact point between the 21st inductor (L21) and the 22nd inductor (L22), and the ground, and the 42nd inductor (L42) may be connected between the other terminal of the 22nd inductor (L22), that is, the contact point between the 21st inductor (L21) and the 22nd inductor (L22), and the ground.

Meanwhile, the 11th capacitor (C11) can be connected in parallel to the 21st inductor (L21), and the 12th capacitor (C12) can be connected in parallel to the 22nd inductor (L22).

The 21st capacitor (C21) is connected in parallel to the 31st inductor (L31), and the 22nd capacitor (C22) is connected in parallel to the 32nd inductor (L32).

The third capacitor (C3) is connected in parallel with the 41st and 42nd inductors (L41, L42) between the contacts of the 21st and 22nd inductors (L21, L22) and ground.

According to an embodiment, the 21st, 22nd and 3rd capacitors (C21, C22, C3) can be implemented as parasitic capacitances.

The multilayer filter according to the embodiment may have various configurations to perform the function of the bandpass filter illustrated in FIG. 3, and an example is described below with reference to FIGS. 4 to 10b, but the embodiment is not limited thereto. That is, the multilayer filter according to the embodiment may implement a filter having a circuit configuration different from the circuit configuration illustrated in FIG. 3.

FIG. 4 is a perspective view of an exterior of a multilayer filter according to an embodiment, FIG. 5a is a perspective view of the multilayer filter illustrated in FIG. 4 with the first ground layer (GL1) removed, FIG. 5b is a plan view of the perspective view illustrated in FIG. 5a, FIG. 6 is a plan view of the first conductive pattern layer (TL1) illustrated in FIG. 5b, FIG. 7a is a perspective view of FIG. 5a with the first conductive pattern layer (TL1) removed, FIG. 7b is a plan view of the second conductive pattern layer (TL2), FIG. 8a is a perspective view of FIG. 7a with the second conductive pattern layer (TL2) removed, FIG. 8b is a plan view of the third conductive pattern layer (TL3), FIG. 9a is a perspective view of FIG. 8a with the third conductive pattern layer (TL3) removed, FIG. 9b is a plan view of the fourth conductive pattern layer (TL4), and FIG. 10a is a perspective view of FIG. 9a with the third conductive pattern layer (TL3) removed. A perspective view is shown with the fourth challenge pattern layer (TL4) removed, and FIG. 10b shows a plan view of the fifth challenge pattern layer (TL5).

Just as the circuit illustrated in FIG. 3 is symmetrical left/right, the capacitance pattern layer and the inductance pattern layer illustrated in FIGS. 4 to 10b may have a symmetrical shape based on an imaginary horizontal line (IH) that passes through the center of the long axis (i.e., x-axis) of the multilayer filter and is parallel to the second direction, which is the short axis direction of the multilayer filter.

The inductance pattern layer may include a first inductor layer (LP11, LP12), a second inductor layer (LP2U1, LP2U2, LP2L1, LP2L2), a third inductor layer (LP31, LP32), and a fourth inductor layer (LP41, LP42).

The first inductor layer (LP11, LP12) is a layer that implements the 11th and 12th inductors (L11, L12) respectively illustrated in FIG. 3, and can be placed on the second conductive pattern layer (TL2) as illustrated in FIGS. 7a and 7b.

The second inductor layer can be arranged across the second conductive pattern layer (TL2) and the third conductive pattern layer (TL3). That is, the second inductor layer includes a second upper inductor layer arranged on the second conductive pattern layer (TL2) and having one end connected to the first capacitor layers (CP11, CP12) as illustrated in FIG. 7b, and a second lower inductor layer arranged on the third conductive pattern layer (TL3) and having one end each connected to the other end of the second upper inductor layer and the other end connected to the second capacitor layer (CP2) as illustrated in FIG. 8b. At this time, the second upper inductor layer includes the twenty-first upper inductor layer (LP2U1) and the twenty-second upper inductor layer (LP2U2), and the second lower inductor layer includes the twenty-first lower inductor layer (LP2L1) and the twenty-second lower inductor layer (LP2L2).

The 21st upper inductor layer (LP2U1) and the 21st lower inductor layer (LP2L1) implement the 21st inductor (L21) illustrated in FIG. 3, and the 22nd upper inductor layer (LP2U2) and the 22nd lower inductor layer (LP2L2) implement the 22nd inductor (L22) illustrated in FIG. 3.

In addition, the third inductor layer (LP31, LP32) is a layer that implements the 31st and 32nd inductors (L31, L32) illustrated in FIG. 3, respectively, and can be placed on the first conductive pattern layer (TL1) as illustrated in FIG. 5a and FIG. 6.

In addition, the fourth inductor layer (LP41, LP42) is a layer that implements the 41st and 42nd inductors (L41, L42) illustrated in FIG. 3, respectively, and can be placed on the third conductive pattern layer (TL3) as illustrated in FIGS. 8a and 8b.

According to an embodiment, each of the first, second, third and fourth inductor layers may have a planar shape folded at least once in the horizontal direction. For example, as illustrated in FIGS. 7b and 8b, each of the second upper inductor layers (LP2U1, LP2U2), the second lower inductor layers (LP2L1, LP2L2) and the fourth inductor layer (LP41, LP42) may have a planar shape folded once in the horizontal direction, and as illustrated in FIG. 6, the third inductor layer (LP31, LP32) may have a planar shape folded twice in the horizontal direction.

Meanwhile, the capacitance pattern layer may include a first capacitor layer (CP11, CP12), a second capacitor layer (CP2), a third capacitor layer (CP31, CP32), and a fourth capacitor layer (CP4).

The first capacitor layer having the first capacitance may be arranged on the second conductive pattern layer (TL2) as illustrated in FIGS. 7a and 7b, and may include eleventh and twelfth capacitor layers (CP11, CP12) facing each other and spaced apart from each other by a first distance (X1) in the first direction, which is the horizontal direction.

A second capacitor layer (CP2) having a second capacitance can be arranged on the third conductive pattern layer (TL3), as illustrated in FIGS. 8a and 8b.

The third capacitor layer having the third capacitance may be arranged on the fourth conductive pattern layer (TL4) as illustrated in FIGS. 9a and 9b, and may include 31st and 32nd capacitor layers (CP31, CP32) facing each other and spaced apart from each other by a second distance (X2) in the first direction, which is the horizontal direction.

According to an embodiment, if each of the first and second distances (X1, X2) is less than 50 μm, an unwanted parasitic capacitance may be generated, narrowing the bandwidth of the pass band or generating spurious waves, which may affect harmonics, and if it is greater than 300 μm, there is little change in performance and only the size of the multilayer filter may increase. Therefore, each of the first and second distances (X1, X2) may be 50 μm to 300 μm, but the embodiment is not limited thereto.

A fourth capacitor layer (CP4) having a fourth capacitance can be arranged on the fifth conductive pattern layer (TL5) as illustrated in FIGS. 10a and 10b.

Referring to FIGS. 5A, 6A, 7A, 8A, 9A, and 10A, the first capacitor layer (CP11, CP12) and the third capacitor layer (CP31, CP32) may be connected to each other, and the second capacitor layer (CP2) and the fourth capacitor layer (CP4) may be electrically connected to each other. That is, the eleventh capacitor layer (CP11) may be electrically connected to the 31st capacitor layer (CP31), and the twelfth capacitor layer (CP12) may be electrically connected to the 32nd capacitor layer (CP32).

To this end, the multilayer filter may include first and second vias. The first via connects the first capacitor layer (CP11, CP12) and the third capacitor layer (CP31, CP32), and the second via (VA2) connects the second capacitor layer (CP2) and the fourth capacitor layer (CP4).

The first via may include an eleventh via (VA11) and a twelfth via (VA12).

The 11th via (VA11) electrically connects the 11th capacitor layer (CP11) and the 31st capacitor layer (CP31), and the 12th via (VA12) electrically connects the 12th capacitor layer (CP12) and the 32nd capacitor layer (CP32).

The eleventh and twelfth vias (VA11, VA12) penetrate the second capacitor layer (CP2), and the second capacitor layer (CP2) may include first and second through-holes (TH1, TH2) as illustrated in FIG. 8B. The eleventh via (VA11) may penetrate the first through-hole (TH1), and the twelfth via (VA12) may penetrate the second through-hole (TH2). In order for the eleventh and twelfth vias (VA11, VA12) to be electrically separated from the second capacitor layer (CP2), the diameter of the first through-hole (TH1) may be formed larger than the diameter of the eleventh via (VA11), and the diameter of the second through-hole (TH2) may be formed larger than the diameter of the twelfth via (VA12).

Referring to FIG. 9b, the 31st and 32nd capacitor pattern layers (CP31, CP32) may have a planar shape in which they are spaced apart from each other with the second via (VA2) interposed therebetween. Accordingly, the 31st and 32nd capacitor pattern layers (CP31, CP32) may be electrically spaced apart from the second via (VA2).

The above-described inductance pattern layer and capacitance pattern layer can be connected to each other in the vertical and horizontal directions by vias to implement the circuit illustrated in FIG. 3.

The multilayer filter according to the embodiment may include the 31st, 32nd, 41st, 42nd, 5th, 61st, 62nd, 71st, and 72nd vias (VA31, VA32, VA41, VA42, VA5, VA61, VA62, VA71, VA72).

The 31st via (VA31) is connected to one end of the 11th capacitor layer (CP11) and the 21st upper inductor layer (LP2U1) and one end of the 11th inductor layer (LP11), and is not connected to the first and second ground layers (GL1, GL2).

The 32nd via (VA32) is connected to one end of the 12th capacitor layer (CP12) and the 22nd upper inductor layer (LP2U2) and one end of the 12th inductor layer (LP12), and is not connected to the first and second ground layers (GL1, GL2).

The 41st via (VA41) is connected to the other end of the 11th inductor layer (LP11) and the first port (P1), and the 42nd via (VA42) is connected to the other end of the 12th inductor layer (LP12) and the second port (P2).

The 41st and 42nd vias (VA41, VA42) are not connected to the first and second ground layers (GL1, GL2).

The fifth via (VA5) connects one end of each of the 31st inductor layer (LP31) and the 32nd inductor layer (LP32) to the first ground layer (GL1). The other end of the 31st inductor layer (LP31) can be connected to the 11th via (VA11), and the other end of the 32nd inductor layer (LP32) can be connected to the 12th via (VA12).

The 61st via (VA61) is connected to the other end of the 21st upper inductor layer (LP2U1) and one end of the 21st lower inductor layer (LP2L1), respectively, and the 62nd via (VA62) is connected to the other end of the 22nd upper inductor layer (LP2U2) and one end of the 22nd lower inductor layer (LP2L2), respectively. At this time, the 61st and 62nd vias (VA61, VA62) are not connected to the first and second ground layers (GL1, GL2).

At this time, the other end of the 21st lower inductor layer (LP2L1) is connected to the second capacitor layer (CP2), and the other end of the 22nd lower inductor layer (LP2L2) is also connected to the second capacitor layer (CP2).

The 71st via (VA71) is connected to one end of the 41st inductor layer (LP41) and the second ground layer (GL2), respectively, and the 72nd via (VA71) is connected to one end of the 42nd inductor layer (LP42) and the second ground layer (GL2), respectively.

The other end of each of the 41st inductor layer (LP41) and the 42nd inductor layer (LP42) is connected to the second capacitor layer (CP2).

Additionally, the multilayer filter according to the embodiment may further include an eighth via. The eighth via serves to connect the first ground layer (GL1) and the second ground layer (GL2). As illustrated, the eighth via may include ten eighth vias (VA81 to VA810), but the embodiment is not limited to a specific number of the eighth vias.

In addition, the multilayer filter according to the embodiment may further include a ninth via (VA91, VA92) as illustrated in FIGS. 5b, 7b, 8b, and 9b, respectively. The ninth via (VA91, VA92) serves to connect the second to fourth conductive pattern layers (TL2, TL3, TL4) to each other, and as illustrated in FIGS. 5a, 7a, 8a, and 9a, the ninth via (VA91, VA92) may be omitted.

FIG. 11 is a cross-sectional view taken along line I-I’ of the multilayer filter illustrated in FIG. 4, showing only the first and second ground layers (GL1, GL2) and the first to third capacitor layers (CP11, CP12, CP2, CP3).

The first capacitance of each of the eleventh and twelfth capacitors (C11, C12) may include the eleventh, twelfth, and thirteenth capacitances.

The 11th capacitance is formed by opposing the first capacitor layer (CP11, CP12) and the second capacitor layer (CP2), the 12th capacitance is formed by opposing the second capacitor layer (CP2) and the third capacitor layer (CP31, CP32), and the 13th capacitance is formed by opposing the third capacitor layer (CP31, CP32) and the fourth capacitor layer (CP4).

Specifically, the aforementioned capacitance pattern layer can implement the capacitors (C11, C12, C21, C22, C3) illustrated in FIG. 3 as follows.

First, the capacitance of the 11th capacitor (C11) illustrated in FIG. 3 is a result of synthesizing the 11th capacitance formed by opposing the 11th capacitor layer (CP11) and the 2nd capacitor layer (CP2) spaced apart by a distance (Z111), the 12th capacitance formed by opposing the 2nd capacitor layer (CP2) and the 31st capacitor layer (CP31) spaced apart by a distance (Z112), and the 13th capacitance formed by opposing the 31st capacitor layer (CP31) and the 4th capacitor layer (CP4) spaced apart by a distance (Z113).

Similarly, the capacitance of the 12th capacitor (C12) is a result of synthesizing the 11th capacitance formed by opposing the 12th capacitor layer (CP12) and the 2nd capacitor layer (CP2) spaced apart by a distance (Z121), the 12th capacitance formed by opposing the 2nd capacitor layer (CP2) and the 32nd capacitor layer (CP32) spaced apart by a distance (Z122), and the 13th capacitance formed by opposing the 32nd capacitor layer (CP32) and the 4th capacitor layer (CP4) spaced apart by a distance (Z123).

Unlike the first capacitance (C1) mentioned above, the second and third capacitances may correspond to parasitic capacitances.

First, the capacitance of the 21st capacitor (C21) is a result of synthesizing the parasitic capacitance caused between the 11th capacitor layer (CP11) and the first ground layer (GL1) spaced apart by a distance (Z211), the parasitic capacitance caused between the 11th capacitor layer (CP11) and the second ground layer (GL2) spaced apart by a distance (Z212), the parasitic capacitance caused between the 31st capacitor layer (CP31) and the first ground layer (GL1) spaced apart by a distance (Z213), and the parasitic capacitance caused between the 31st capacitor layer (CP31) and the second ground layer (GL2) spaced apart by a distance (Z214).

The capacitance of the 22nd capacitor (C22) is a result of synthesizing the parasitic capacitance caused between the 12th capacitor layer (CP12) and the first ground layer (GL1) spaced apart by a distance (Z221), the parasitic capacitance caused between the 12th capacitor layer (CP12) and the second ground layer (GL2) spaced apart by a distance (Z222), the parasitic capacitance caused between the 32nd capacitor layer (CP32) and the first ground layer (GL1) spaced apart by a distance (Z223), and the parasitic capacitance caused between the 32nd capacitor layer (CP32) and the second ground layer (GL2) spaced apart by a distance (Z224).

The capacitance of the third capacitor (C3) is a result of the synthesis of the parasitic capacitance between the second capacitor layer (CP2) and the first ground layer (GL1) spaced apart by a distance (Z31), the parasitic capacitance between the second capacitor layer (CP2) and the second ground layer (GL2) spaced apart by a distance (Z32), the parasitic capacitance between the second capacitor layer (CP2) and the first ground layer (GL1) spaced apart by a distance (Z33), and the parasitic capacitance between the fourth capacitor layer (CP2) and the second ground layer (GL2) spaced apart by a distance (Z34).

To obtain a desired capacitance, the ground layers (GL1, GL2) and capacitor layers (CP11, CP12, CP2, CP31, CP32, CP4) that are vertically adjacent to each other can be vertically overlapped as much as desired, and the permittivity of the dielectric layer arranged between the ground layers (GL1, GL2) and the capacitor layers (CP11, CP12, CP2, CP31, CP32, CP4) can be adjusted, and the area of the capacitor layers that form the capacitance facing each other can be adjusted.

A multilayer filter according to another embodiment may include only the first to third conductive pattern layers (TL1 to TL4) and the first to fourth dielectric layers (DL1 to DL4) described above (i.e., N=3). That is, according to another embodiment, the fourth and fifth conductive pattern layers (TL4, TL5) and the first and second vias (VA11, VA12, VA2) in FIGS. 4 to 11 may be omitted. Except for this, the multilayer filter according to another embodiment is the same as the multilayer filter according to one embodiment, and thus, a redundant description will be omitted.

In addition, by arranging the second upper inductor layer on the second conductive pattern layer (TL2), arranging the second lower inductor layer on the third conductive pattern layer (TL3), and then connecting them using the 51st and 52nd vias (VA51, VA52), the length of the second inductors (L21, L22) can be increased so that they have a desired inductance.

In the case of a multilayer filter according to one embodiment, since the 11th and 12th capacitor layers (CP11, CP12) are connected to the 31st and 32nd capacitor layers (CP31, CP32) by the 11th and 12th vias (VA11, VA12), the capacitors can have a structure in which they are connected in parallel, thereby increasing the first capacitance as much as desired.

However, if there is no need to increase the first capacitance, the fourth and fifth conductive pattern layers (TL3, TL4) and the eleventh and twelfth and second vias (VA11, VA12, VA2) may be omitted as in other embodiments.

Hereinafter, the operation of the multilayer filter illustrated in FIG. 3 according to an embodiment is described as follows with reference to the attached drawings.

Figure 12 is a graph that examines the performance of a multilayer filter according to an embodiment, in which the horizontal axis represents frequency and the vertical axis represents S parameters, respectively.

Fig. 12 shows the simulation result of applying a multilayer filter according to an embodiment to WiFi 6E having a passband of 5.925㎓ to 7.125㎓, and the insertion loss is -5㏈ or less.

The 21st and 22nd inductors (L21, L22) and the 11th and 12th capacitors (C11, C12) illustrated in Fig. 3 serve to create a transmission zero. Referring to Fig. 12, two transmission zeros can be created in the ‘A’ portion of the transmission zero (310). In the case of Fig. 12, the transmission zeros are overlapped and illustrated as one.

In addition, the 31st and 32nd inductors (L31, L32), the 41st and 42nd inductors (L41, L42), the 21st capacitor (C21), the 22nd capacitor (C22), and the third capacitor (C3) illustrated in Fig. 3 serve to create a resonator. Referring to Fig. 12, it can be seen that the multilayer filter has the characteristics of a third-order resonator (320) having three resonances, as in part ‘B’.

Hereinafter, a front-end module according to an embodiment is described with reference to the attached drawings.

Figure 13 shows a block diagram of a front-end module (200) according to an embodiment.

The front-end module (200) according to the embodiment illustrated in FIG. 13 may include an antenna (210), first and second amplifiers (220, 240), a multilayer filter (220), and a switch (250).

The first amplifier (220) can amplify a signal received through the antenna (210) and provide the amplified result to the multilayer filter (220). For example, the first amplifier (220) can be a low noise amplifier (LNA).

The multilayer filter (220) filters the signal amplified by the first amplifier (220) and outputs it through the output terminal OUT. Since it may be the multilayer filter (100, 100A) according to the above-described embodiment, a duplicate description is omitted.

The second amplifier (240) amplifies a signal coming in through the input terminal IN and transmits the amplified result through the antenna (210). For example, the second amplifier (240) may be a power amplifier (PA).

A switch (250) is placed between the input terminal of the first amplifier (220) and the output terminal of the second amplifier (240) and the antenna, and serves to select their signal paths.

According to an embodiment, when a multilayer filter (100, 100A) is embedded inside a front-end module using LCiP (Inductance & Capacitance in Package) technology, and the second capacitor (C21, C22) and the third capacitance (C3), which are shunt capacitors, are implemented as parasitic capacitances between the 11th, 12th, 2nd, 31st, 32nd, and 4th capacitor layers (CP11, CP12, CP2, CP31, CP32, CP4) and the first and second ground layers (GL1, GL2) as described above, separate capacitor layers for the second capacitors (C21, C22) and the third capacitance (C3) do not need to be formed.

That is, in the case of the multilayer filter according to the embodiment, in order to obtain the capacitances of the 11th and 12th capacitors (C11, C12), the 11th, 12th, 2nd, 31st, 32nd, and 4th capacitor layers (CP11, CP12, CP2, CP31, CP32, CP4) are arranged, and the capacitances of the 21st, 22nd, and 3rd capacitors (C21, C22, C3) can be formed by utilizing the parasitic capacitances between the 11th, 12th, 2nd, 31st, 32nd, and 4th capacitor layers (CP11, CP12, CP2, CP31, CP32, CP4) and the first and second ground layers (GL1, GL2). Therefore, the parasitic capacitors can be utilized without requiring separate capacitor layers for forming the capacitances of the 21st, 22nd, and 3rd capacitors (C21, C22, C3). Thanks to this, the size of the multilayer filter (100, 100A) or front-end module (200) can be reduced, and the frequency can be easily tuned.

Additionally, by vertically stacking capacitor layers and connecting them, the capacitance (e.g., first capacitance) can be easily increased in a limited size.

Additionally, by stacking the inductor layers vertically to increase the length, the inductance (e.g., the inductance of the second inductor) can be easily increased.

The multilayer filter and front-end module according to the above-described embodiment can be applied to a field having a frequency band of 6 GHz or higher, and for example, can be applied to modules for antennas including televisions, mobile devices, Bluetooth, and WiFi.

Although the above has been described with reference to embodiments, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will recognize that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiment. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, the differences related to such modifications and applications should be interpreted as being included in the scope of the present invention defined in the appended claims.

The best mode for carrying out the invention has been sufficiently described in the above-mentioned “Best Mode for Carrying Out the Invention.”

The multilayer filter of the embodiment and the front-end module including the same can be used in a mobile communication terminal, etc.

Claims (10)

First and second ground layers; A plurality of conductive pattern layers arranged between the first ground layer and the second ground layer; and A dielectric layer disposed between the first and second ground layers and the plurality of conductive pattern layers, Among the plurality of above-mentioned challenge pattern layers, adjacent challenge pattern layers include capacitance pattern layers forming a first capacitance, At least some of the above plurality of challenge pattern layers include an inductance pattern layer forming an inductor, The above capacitance pattern layer forms a parasitic capacitance facing each of the first and second ground layers, A multilayer filter that filters a signal having a desired frequency band by using the first capacitor, the inductor, and the parasitic capacitance. In the first paragraph, the capacitance pattern layer and the inductance pattern layer are a multilayer filter having a symmetrical shape based on an imaginary horizontal line passing through the center of the long axis of the multilayer filter and parallel to the short axis direction of the multilayer filter. In the first paragraph, a multilayer filter including first to third conductive pattern layers sequentially laminated between the first ground layer and the second ground layer, wherein the plurality of conductive pattern layers are In the third paragraph, The above inductance pattern layer A first inductor layer disposed on the second challenge pattern layer; A second inductor layer arranged across the second conductive pattern layer and the third conductive pattern layer; A third inductor layer disposed on the first challenge pattern layer; and A multilayer filter comprising a fourth inductor layer disposed on the third challenge pattern layer. In the fourth paragraph, a multilayer filter in which each of the first, second, third and fourth inductor layers has a planar shape folded at least once in the horizontal direction. In the fourth paragraph, The above capacitance pattern layer A first capacitor layer disposed on the second challenge pattern layer; and A multilayer filter comprising a second capacitor layer disposed on the third challenge pattern layer and facing the first capacitor layer to form the first capacitance. In Article 6, A multilayer filter wherein the plurality of conductive pattern layers further include fourth and fifth conductive pattern layers sequentially laminated between the third conductive pattern layer and the second ground layer. In Article 7, The above capacitance pattern layer a third capacitor layer connected to the first capacitor layer; and A multilayer filter further comprising a fourth capacitor layer connected to the second capacitor layer. In Article 8, A first via connecting the first capacitor layer and the third capacitor layer; and A multilayer filter including a second via connecting the second capacitor layer and the fourth capacitor layer. antenna; A first amplifier for amplifying a signal received through the antenna; A multilayer filter that filters and outputs a signal amplified by the first amplifier, the multilayer filter according to any one of claims 1 to 21; a second amplifier for amplifying a signal to be transmitted through the antenna; and A front-end module including a switch positioned between each of the input terminal of the first amplifier and the output terminal of the second amplifier and the antenna.

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