WO2024253618A1 - Commutateur pcie basé sur un fpga - Google Patents

Commutateur pcie basé sur un fpga Download PDF

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Publication number
WO2024253618A1
WO2024253618A1 PCT/TR2024/050557 TR2024050557W WO2024253618A1 WO 2024253618 A1 WO2024253618 A1 WO 2024253618A1 TR 2024050557 W TR2024050557 W TR 2024050557W WO 2024253618 A1 WO2024253618 A1 WO 2024253618A1
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Prior art keywords
fpga
logical blocks
devices
interface connection
adjuster
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English (en)
Inventor
Salih ESER
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Aselsan Elektronik Sanayi ve Ticaret AS
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Aselsan Elektronik Sanayi ve Ticaret AS
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the invention relates to an FPGA (Field Programmable Gate Arrays) based reconfigurable (soft) PCIe switch that enables RC (Root Complex) and EP (Endpoint) devices to communicate with each other.
  • FPGA Field Programmable Gate Arrays
  • RC Root Complex
  • EP Endpoint
  • PCIe Peripheral Component Interface Express
  • RC and EP devices there are RC and EP devices, and said RC can access more than one EP through a switch.
  • the devices communicate with each other through a switch.
  • communication architecture is generally designed using PCIe switch.
  • more than one device is configured from the RC and the device at each end communicates with each other with appropriate addresses.
  • PCI Peripheral Component Interface
  • the interface basically comprises of two different bridges, the North Bridge and the South Bridge, and there is a PCI bus between the two bridges.
  • the north bridge provides link control between the processor and the memories, which may include a display controller or discrete graphics cards.
  • the southern bridge controls connections such as, input/output (I/O), parallel and serial drives, USB, audio ports. While the north bridge is directly connected to the processor, the south bridge is connected to the processor through the north bridge.
  • the PCI architecture supports access from address spaces and access to these units is provided from the unique address of each unit.
  • PCIe simultaneously sends and receives data with a two- way connection. Communication between receivers and transmitters is provided after a link is established between them. Said link is related to the physical connection between the devices.
  • the communication link may contain more than one lane. Having more than one lane from the transmitter to the receiver or from the receiver to the transmitter is represented as x1 , x2, x4, ..., x32, and there are transmitter-receiver, receiver-transmitter forwardings within a single lane.
  • the first generation PCIe bandwidth is 0.5 GB/s in a single lane, it reaches a speed of 16 GB/s when expanded to 32 lanes.
  • the second generation PCIe bandwidth is 1 GB/s on a single lane
  • the third generation PCIe bandwidth is 2 GB/s on a single lane
  • the fourth generation PCIe bandwidth is 4 GB/s on a single lane
  • the fifth generation PCIe bandwidth is 8 GB/s on a single lane.
  • RC Root Complex/Upstream
  • EP Endpoint/Downstream
  • RC is widely perceived as the interface between the processor and the PCIe topology. In addition, this interface may include other components such as processor interface, DRAM, etc.
  • EP is a device connected to a single RC in the PCIe topology, and more than one EP can be connected to a RC through a switch.
  • PCIe starts from the physical layer first.
  • the physical layer contains the encoder and the decoder.
  • the packet structure of the data in the physical layer includes the packet to be transferred from the link between the start and end conditions.
  • TLP Transaction Layer Packet
  • TLP Transaction Layer Packet
  • the Software Layer is responsible for tasks such as memory, I/O, configuration, message requests, and sends addresses, transaction type, and data.
  • Devices on PCIe lanes can use common clock pulse or discrete clock pulse.
  • LTSSM Link Training and Status State Machine
  • PCIe lanes controls situations such as link, reset, power, signalization, recovery steps, etc. on PCIe lanes.
  • the lanes are electrically active on the physical layer, in other words, all transmitters should be detected by the receivers at the opposite end. In every case, there is a certain timeout period and the necessary transactions are expected to be taken during this period. Timeout periods are set in the PCIe standard. If more than one lane is used in the link, the status of all the lanes used is checked. After the receivers and transmitters in the lanes detect the presence of each other, there is a need for bitstream transmission or bit and symbol detection to provide the solution of any reverse polarization problems.
  • the transmitters send consecutive packets to the receivers and the necessary analysis is made between the receiver and the transmitter. How ports will be connected and assigning the lane numbers is done in the next step. Usually all states have their own internal recovery steps. Test and debug modes can also be used in a negative state.
  • PCIe High-speed communication requirements in real-time systems are often provided by PCIe topology based designs.
  • the use of PCIe is not limited to its use in user computers as it was in the 1990s when it first appeared, but it has started to be widely used in most of the embedded systems. It is increasing its importance day by day as it supports high bandwidth data transfers with its new generations.
  • PCIe switches are used, which allow the RC to control more than one EP and make communication configurations.
  • the addition of an extra chip on the printed circuit board (PCB) limits the designer's mobility. Considering designs with too many components and size limitations, it is very important to be able to get rid of an extra chip.
  • an FPGA-based PCIe switch design that can be integrated into PCIe designs used by FPGA manufacturers or any designer, has low resource consumption, has low power consumption, has low latency, has compatibility with PCIe generations, has software control interface, has end-to-end addressing controls, has compliance with interface standards and compliance with timing criteria, which eliminates the chip-based use of PCIe switches, limited port support, compatibility problem with all generations, space occupancy on the printed circuit board, high power consumption, configuration adaptation in split lines, real-time debugging problems, the necessity of all lanes to operate and end- to-end different PCIe generation usage problems seen in embodiments in the state of the art.
  • the purpose of the invention is to realize an FPGA-based PCIe switch that provides requirements such as low resource consumption, low power consumption, low latency, compatibility with PCIe generations, integrable into PCIe designs used by FPGA manufacturers or any designer, software control interface, end-to-end addressing controls, compliance with interface standards and compliance with timing criteria.
  • the FPGA-based PCIe switch of the invention it can be ensured that different end-to-end PCIe generations are used. Apart from this, low power and resource consumption is realized and communication between devices is ensured. In addition, real-time debugging can be performed, configurable port support is provided, the need for any chip on the PCB is eliminated, operation can be performed on lanes operating with automatic LTSSM control, and end-to-end interrupt can be sent.
  • Figure 1 is the schematic view of an embodiment of the FPGA-based PCIe switch of the invention.
  • FIG. 2 is the detailed block diagram of an embodiment of the FPGA-based PCIe switch of the invention.
  • FIG. 3 is the detailed block diagram of an embodiment of EP units comprising FPGA/CPU/GPU communicating with units comprising the FPGA-based PCIe switch of the invention and FPGA cards configured as RC.
  • FIG. 4 is the detailed block diagram of an implementation of RC units comprising FPGA/CPU/GPU communicating with units comprising the FPGA-based PCIe switch of the invention and FPGA cards configured as EP.
  • FIG. 5 is the block diagram of a cloud system in which the FPGA-based PCIe switch of the invention is used.
  • FIG. 6 is the detailed block diagram of an embodiment of a management system and subsystems using the FPGA-based PCIe switch of the invention.
  • FIG. 7 is the detailed block diagram of an embodiment of a management system and sub/management systems using the FPGA-based PCIe switch of the invention.
  • Figure 8 is the block diagram of an embodiment of an FPGA/GPU/CPU supported motherboard.
  • FIG. 9 is the detailed block diagram of an embodiment of an FPGA/GPU/CPU supported motherboard.
  • Switch controller logical block 9. Software control interface logical block
  • RAM/ROM RAM/ROM memory module
  • SSD SSD memory module
  • the FPGA-based PCIe switch (1 ) of the invention which enables data communication between a large number of devices connected to a large number of ports and using the same or different PCIe generations; comprising the following: multiple input interface connection logical blocks (2) and multiple output interface connection logical blocks (3) each of which being configured to enable data communication through a predetermined data communication interface, PCIe adapter logical blocks (4) configured to adapt between devices connected electrically to input interface connection logical blocks (2) and output interface connection logical blocks (3) and also between communication interfaces which are connected to ports with data communication interfaces that are located on connection interface logic blocks, logical blocks of input clock domain crossing adjuster (5) configured to arrange the timing domains of signals containing at least one data and target address information which come to input interface connection logical blocks (2) to one primary timing domain, logical blocks of output clock domain crossing adjuster (6) configured to arrange the timing domain of signals to be transmitted through the output interface connection logical blocks (3) to one secondary timing domain, at least one address and data transfer adjuster logical block (7) configured to transmit the signals in question to ports that
  • FIG. 1 The general block diagram of an embodiment of the FPGA-based PCIe switch is shown in figure 1.
  • An FPGA-based PCIe switch (1 ) shown in this embodiment can have a large number of ports, each of which represents a lane that allows a large number of devices to exchange data with each other, for example a central processing unit (CPU) and a graphics processing unit (GPU).
  • CPU central processing unit
  • GPU graphics processing unit
  • end-to-end communication of multiple devices can be provided through a single FPGA-based PCIe switch (1 ).
  • the maximum number of PCIe lanes supported by an FPGA (F) card with the FPGA-based PCIe switch (1 ) of the invention can be configured over the FPGA- based PCIe switch (1 ) design.
  • information such as the interfaces to be used, the basic addresses of the devices to be communicated with each other and how many ports to open are given as input to the design of the FPGA-based PCIe switch (1 ).
  • an addressing map is created. The addressing map can be changed from the configuration settings of the FPGA-based PCIe switch (1 ) design under user control.
  • the addressing map contains information such as the addresses that allow the devices to communicate with each other, which device and which unit of this device (e.g. DDR, EEPROM%) to access using these addresses.
  • FIG. 1 A detailed block diagram of an embodiment of the FPGA-based PCIe switch (1 ) is shown in Figure 2, which is organized to enable two devices to communicate with each other.
  • the invention is not limited to this, but can also be configured to enable more than one device to communicate with each other.
  • the FPGA-based PCIe switch (1 ) comprises two input interface connection logical blocks (2), two output interface connection logical blocks (3), two PCIe adapter logical blocks (4), two logical blocks of input clock domain crossing adjuster (5), two logical blocks of output clock domain crossing adjuster (6), an address and data transfer adjuster logical block (7), a switch controller logical block (8), and a software control interface logical block (9), each of said logic blocks are reprogrammable logic blocks such as logic modules, digital signal processing blocks, and/or random access memory blocks.
  • an amount of reprogrammable logical blocks such as the input interface connection logical block (2), the output interface connection logical block (3), the logical block of input clock domain crossing adjuster (5), the logical block of output clock domain crossing adjuster (6) equal to that of the amount of devices can be added to the FPGA-based PCIe switch (1 ).
  • each of the PCIe adapter logical blocks (4) is configured to be connected to an input interface connection logical block (2), the input interface connection logical blocks (2) to a logical block of input clock domain crossing adjuster (5), and the logical block of input clock domain crossing adjuster (5) to an address and data transfer adjuster logical block (7) to establish data communication between them.
  • the address and data transfer adjuster logical block (7) is further configured to be connected to a logical block of output clock domain crossing adjuster (6), the logical block of output clock domain crossing adjuster (6) to an output interface connection logical block (3), and the output interface connection logical block (3) to a PCIe adapter logical block (4), which is also connected to an input interface connection logical block (2), to establish data communication.
  • the FPGA-based PCIe switch (1 ) of the invention There is no interface restriction in the FPGA-based PCIe switch (1 ) of the invention, and communication interfaces frequently used by manufacturers such as AXI, Avalon can be used. However, the invention is not limited to these communication interfaces, different communication interfaces can also be used.
  • the input interface connection logical block (2) and the output interface connection logical block (3) included in the FPGA-based PCIe switch (1 ) may be used differently from end-to-end, for example, the FPGA- based PCIe switch (1 ) may be configured to use Avalon on one side and AXI on the other side.
  • the FPGA-based PCIe switch (1 ) can be configured so that the same communication interface can be used on both sides.
  • the PCIe adapter logical blocks (4) enable the adaptation of the communication interfaces of the devices with the internal communication interfaces in the said interface connection logic blocks used in the FPGA-based PCIe switch (1 ). Thus, it is possible to perform data communication between devices using different communication interfaces and the FPGA-based PCIe switch (1 ).
  • the logical blocks of input clock domain crossing adjuster (5) enable the communication between the devices operating in different clock domains. For this, the logical blocks of input clock domain crossing adjuster (5) enable the clock pulse of the signal from a device to be converted to the internal clock pulse of the FPGA (F), and the logical block of output clock domain crossing adjuster (6) enable the clock pulses of the signals to be transmitted to the devices to be converted to the clock pulse used by the said devices.
  • the logical blocks of input clock domain crossing adjuster (5) in the FPGA-based PCIe switch (1 ) are supplied with different clock pulse and reset signals by the switch controller logical block (8) according to the PCIe generations used by the devices, and thus the synchronization required for data communication between these devices is provided in the internal structure of the FPGA-based PCIe switch (1 ).
  • the switch controller logical block (8) according to the PCIe generations used by the devices, and thus the synchronization required for data communication between these devices is provided in the internal structure of the FPGA-based PCIe switch (1 ).
  • a large number of devices operating in different PCIe generations can be connected to the ends of the FPGA-based PCIe switch (1 ), and data losses and incorrect data sampling that may arise from asynchronization in end-to-end data transfers are prevented and data and address synchronization between the ends is ensured.
  • the address and data transfer adjuster logical block (7) are positioned between the logical blocks of input clock domain crossing adjuster (5) and the logical blocks of output clock domain crossing adjuster (6) and is configured to control that the devices connected to the FPGA-based PCIe switch (1 ) access each other's correct address spaces.
  • the address and data transfer adjuster logical block (7) directs the signals received through the logical blocks of input clock domain crossing adjuster (5) and containing a target address information and data to be transmitted to the relevant port to transmit to the device/s previously associated with the said target address information using an addressing map.
  • the switch controller logical block (8) is electrically connected to the input interface connection logical blocks (2), the output interface connection logical blocks (3), the logical blocks of input clock domain crossing adjuster (5), the logical blocks of output clock domain crossing adjuster (6) and the address and data transfer adjuster logical block (7) and is configured to control all interface connections, address settings, input and output pulse domain crossings.
  • the block diagram of an embodiment of the FPGA-based PCIe switch is shown in figure 8.
  • slots on a motherboard (MB) have FPGA (F), central processing unit (CPU) and graphics processing unit (GPU) chips, and an FPGA- based PCIe Switch (1 ) is operated in the FPGA (F).
  • the FPGA (F) is configured to be an end point (EP), and the central processing unit (CPU) and graphics processing unit (GPU) chips are configured to be the root unit (RC), but the invention is not limited to this, but the root unit (RC) and end unit (EP) configurations can be made as desired in user control.
  • the central processing unit (CPU) can access the DDR memory module (DDR) on the card containing the graphics processing unit (GPU) through the FPGA-based PCIe switch (1 ) with appropriate addresses
  • the graphics processing unit (GPU) can access the DDR memory module (DDR) on the card containing the central processing unit (CPU) through the FPGA-based PCIe switch (1 ) with appropriate addresses, which does not require the use of memory such as any DDR memory unit (DDR) etc. on the FPGA (F) and these access transactions are performed end-to-end in real time.
  • both the central processing unit (CPU) and the graphics processing unit (GPU) can provide access to the external world interfaces (UART/I2C/SPI) defined in the FPGA (F).
  • all chips can read and write to each other's DDR memory modules (DDR) from appropriate addresses and provide access to other required areas.
  • the detailed block diagram of the embodiment given in Figure 8 is shown in Figure 9. Slots on a motherboard (MB) have FPGA (F), central processing unit (CPU), graphics processing unit (GPU) chips, and FPGA-based PCIe Switch (1 ) in the FPGA (F). All cards have their own components such as DDR memory module (DDR), external interfaces (Uart/l2C/SPI), flash memories (FM), etc.
  • DDR DDR memory module
  • FM flash memories
  • the graphics processing unit (GPU) and/or central processing unit (CPU) can access and communicate with all components such as the DDR memory module (DDR), RAM/ROM memory module (RAM/ROM), external interfaces (Uart/l2C/SPI), etc. given in the addressing in the FPGA (F) over PCIe lanes.
  • DDR DDR memory module
  • RAM/ROM RAM/ROM memory module
  • Uart/l2C/SPI external interfaces
  • the graphics processing unit (GPU) and the central processing unit (CPU) have the ability to read and write from DDR memory modules (DDR).
  • the FPGA (F) can write the images it receives from one or more detectors to the DDR memory modules (DDR) on both the central processing unit (CPU) and the graphics processing unit (GPU), send interrupts (I) for the management of the write and read synchronizations of the images, and read the image processing result outputs of the central processing unit (CPU) and the graphics processing unit (GPU) from the DDR memory modules (DDR) of the central processor unit (CPU) and the graphics processor unit (GPU).
  • DDR DDR memory modules
  • FPGA- based PCIe Switch (1 FPGA- based PCIe Switch (1 ) in the joint transactions of the central processing unit (CPU) and the graphics processing unit (GPU), and synchronize the transactions by sending interruptions (I) to each other through the FPGA-based PCIe switch (1 ). All these transactions can be carried out with low power consumption and real-time operation of the FPGA-based PCIe Switch (1 ).
  • the switch controller logical block (8) is configured to maintain communication with other devices in the event of interruption of data communication with one device.
  • the switch controller logical block (8) is configured to maintain communication with other devices in the event of interruption of data communication with one device.
  • the FPGA-based PCIe switch (1 ) comprises a software control interface logical block (9) configured to send addressing to other devices as a notification message regarding devices whose access is blocked or not possible.
  • the addresses to be blocked in an embodiment are stored in at least one memory module that creates a reprogrammable logic block.
  • the software control interface logical block (9) is configured to detect the non-operation of said logic blocks, the link state between the devices and to perform real-time debugging.
  • the software control interface logical block (9) is connected to a state machine called LTSSM, allowing the detection of situations such as failure of one of the devices, falling off the lane or failure to access this failed device for different reasons.
  • An FPGA (F) containing the FPGA-based PCIe switch (1 ) of the invention can be used in more than one area and can be configured as a root unit (RC) or end point (EP).
  • FIG. 3 A block diagram regarding an embodiment of an FPGA (F) containing the FPGA-based PCIe switch (1 ) of the invention in which the responsibility in the PCIe is the root unit (RC) is given in Figure 3.
  • the FPGA (F) containing the FPGA-based PCIe switch is configured as the root unit (RC), allowing the other devices on the left and right of the FPGA (F) to communicate with itself and with each other.
  • the devices on the left and right provide direct access to each other through the FPGA (F) containing the FPGA-based PCIe switch (1 ).
  • the block diagram where the responsibility of the FPGA (F) in PCIe is the end point (EP) is given in Figure 4.
  • the FPGA (F) containing the FPGA-based PCIe switch (1 ) is configured as an end point (EP), and the FPGA (F) also enables other devices on the left and right to communicate with itself and with each other.
  • the devices on the left and right provide direct access to each other through the FPGA (F) containing the FPGA- based PCIe switch (1 ).
  • the FPGA (F) allows multiple configurations in discrete lanes.
  • the FPGA (F) containing the FPGA-based PCIe switch (1 ) can be configured as the root unit (RC), while in the other line, the FPGA (F) containing the FPGA-based PCIe switch (1 ) can also act as the end point (EP).
  • RC root unit
  • EP end point
  • FIG. 5 which illustrates another embodiment of the invention, shows a block diagram of a system consisting of a management system (M) and sub/management systems (S/M) and connected through multiple cloud systems (C). The whole system can manage internal communication and data transfers using the FPGA-based PCIe switch (1 ) and send the final data from the cloud system (C) with write/read operations.
  • FIG. 7 A block diagram of the device in which subsystems (S) are managed through a single management system (M) is shown in Figure 7.
  • the management system (M) can directly communicate with one or more subsystems (S).
  • the manager may not have direct access to all subsystems (S). It is possible for the management system (M) to send a command set to the subsystems (S) and perform operations.
  • end-to-end access to all subsystems (S) can be provided through the management system (M).
  • the management system (M) sends the command set directly to the relevant unit or can perform the operation it wants to do directly in the relevant unit.
  • the FPGA-based PCIe switch (1 ) pf the invention the requirement of having any chip on a circuit board is eliminated.
  • using the lanes on the FPGA (F) it is ensured that more than one root unit (RC) communicates with each other.
  • lane control can be performed by using LTSSM (Link Training and Status State Machine) and in case of any problem, the use of troublefree lanes can be continued, in other words, in the event of a breakdown of a device among more than one different device communicating with each other over the FPGA-based PCIe switch (1 ), the addresses of the broken device are turned off and the other devices are notified, allowing the data communication between other devices to be carried out in a healthy way.
  • LTSSM Link Training and Status State Machine
  • the FPGA-based PCIe switch (1 ) subject to the invention is FPGA-based, it can transfer data from end-to-end in real time while providing very low power consumption.
  • the FPGA-based PCI switch (1 ) can connect with devices that support different end-to-end PCIe generations without an interface limit and has a reconfigurable structure.
  • the FPGA-based PCI switch (1) is compatible with all PCIe generations in today's technology and has the design foundations to easily adapt to high-speed generations that may come.

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Abstract

L'invention concerne un commutateur PCIe basé sur un FPGA (1) qui se connecte à de multiples ports et permet une communication de données entre de multiples dispositifs à l'aide du même commutateur PCIe basé sur un FPGA de générations PCIe identique ou différent (1); qui comprend : de multiples blocs logiques de connexion d'interface d'entrée (2) et de multiples blocs logiques de connexion d'interface de sortie (3) dont chacun est configuré pour permettre une communication de données par l'intermédiaire d'une interface de communication de données prédéterminée, des blocs logiques d'adaptateur PCIe (4) configurés pour s'adapter entre des dispositifs connectés électriquement à des blocs logiques de connexion d'interface d'entrée (2) et des blocs logiques de connexion d'interface de sortie (3) et également entre des interfaces de communication qui sont connectées à des ports avec des interfaces de communication de données qui sont situées sur des blocs logiques d'interface de connexion, des blocs logiques de dispositif de réglage de croisement de domaine d'horloge d'entrée (5) configurés pour agencer les domaines de synchronisation de signaux contenant au moins une donnée et des informations d'adresse cible qui entrent des blocs logiques de connexion d'interface (2) dans un domaine de synchronisation primaire, des blocs logiques de dispositif de réglage de croisement de domaine d'horloge de sortie (6) configurés pour agencer le domaine de synchronisation de signaux à transmettre par l'intermédiaire des blocs logiques de connexion d'interface de sortie (3) à un domaine de synchronisation secondaire, au moins une adresse et un bloc logique de réglage de transfert de données (7) configuré pour transmettre les signaux en question à des ports qui sont connectés à des dispositifs prédéterminés qui ont été mis en correspondance avec des informations d'adresse de destination en question selon les informations d'adresse de destination sur les signaux provenant des blocs logiques du dispositif de réglage de croisement de domaine d'horloge d'entrée (5) à l'aide d'une carte d'adressage prédéterminée, et au moins un bloc logique de contrôleur de commutateur (8) configuré pour commander le fonctionnement des blocs logiques en question.
PCT/TR2024/050557 2023-06-08 2024-05-29 Commutateur pcie basé sur un fpga Pending WO2024253618A1 (fr)

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TR2023/006693A TR2023006693A1 (tr) 2023-06-08 2023-06-08 Bi̇r fpga tabanli pcie anahtar
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7934033B2 (en) * 2008-03-25 2011-04-26 Aprius, Inc. PCI-express function proxy
US20120311110A1 (en) * 2011-06-01 2012-12-06 International Business Machines Corporation Re-programming programmable hardware devices without system downtime
US20170177528A1 (en) * 2015-12-22 2017-06-22 Intel Corporation Architecture for software defined interconnect switch

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7934033B2 (en) * 2008-03-25 2011-04-26 Aprius, Inc. PCI-express function proxy
US20120311110A1 (en) * 2011-06-01 2012-12-06 International Business Machines Corporation Re-programming programmable hardware devices without system downtime
US20170177528A1 (en) * 2015-12-22 2017-06-22 Intel Corporation Architecture for software defined interconnect switch

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