WO2024253687A1 - Interconnexion verticale à travers le verre utilisant une couche barrière conductrice - Google Patents

Interconnexion verticale à travers le verre utilisant une couche barrière conductrice Download PDF

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Publication number
WO2024253687A1
WO2024253687A1 PCT/US2023/068035 US2023068035W WO2024253687A1 WO 2024253687 A1 WO2024253687 A1 WO 2024253687A1 US 2023068035 W US2023068035 W US 2023068035W WO 2024253687 A1 WO2024253687 A1 WO 2024253687A1
Authority
WO
WIPO (PCT)
Prior art keywords
tgv
barrier layer
conductive barrier
glass substrate
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2023/068035
Other languages
English (en)
Inventor
Christopher F. Keimel
Chris Nassar
Aric SHOREY
Matthew STROHMAYER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Menlo Microsystems Inc
Original Assignee
Menlo Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Menlo Microsystems Inc filed Critical Menlo Microsystems Inc
Priority to PCT/US2023/068035 priority Critical patent/WO2024253687A1/fr
Priority to KR1020257042221A priority patent/KR20260022324A/ko
Priority to EP23741216.8A priority patent/EP4724382A1/fr
Priority to CN202380098773.5A priority patent/CN121487890A/zh
Publication of WO2024253687A1 publication Critical patent/WO2024253687A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00777—Preserve existing structures from alteration, e.g. temporary protection during manufacturing
    • B81C1/00785—Avoid chemical alteration, e.g. contamination, oxidation or unwanted etching
    • B81C1/00793—Avoid contamination, e.g. absorption of impurities or oxidation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems ; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094—Feed-through, via
    • B81B2207/096—Feed-through, via through the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0183—Selective deposition
    • B81C2201/0188—Selective deposition techniques not provided for in B81C2201/0184 - B81C2201/0187
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/03—Bonding two components
    • B81C2203/033—Thermal bonding
    • B81C2203/036—Fusion bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses

Definitions

  • a copper-based electrical via may be used to communicate an electrical signal into a microelectromechanical system (MEMS) component.
  • the copper-based via may be covered by a conductive metal pad to provide an effective electrical interface to the encapsulated MEMS device and/or an external device or system. Under certain conditions, the conductive metal pad may exhibit corrosion, which detrimentally affects the performance of the MEMS component.
  • the embodiments described herein are directed to an electrically conductive barrier layer applied between the copper through-glass via (TGV) and any associated gold layers, to reduce or eliminate migration of copper through the gold layers, and consequently reduce or eliminate formation of contaminants (e.g., CuO) on surfaces of the gold layers.
  • the invention may be a method of preventing corrosion associated with an electrically-conductive through-glass via (TGV).
  • the method may comprise forming a TGV in a glass substrate for use in a microelectromechanical system (MEMS) device.
  • the TGV may have a first end and a second end, and at least partially comprise copper.
  • the method may further comprise applying a conductive barrier layer on the first end of the TGV and/or the second end of the TGV.
  • the method may further comprise applying a metal layer over the conductive barrier layer.
  • the method may also comprise extending the conductive barrier layer over the first end of the TGV, and over at least a portion of the glass substrate encompassing the end of the TGV, such that the conductive barrier layer overlaps a boundary between the TGV and the glass substrate.
  • the method may further comprise applying the conductive barrier layer using an electroless plating process.
  • the electroless plating technique may be electroless palladium and immersion gold (EPIG).
  • the electroless plating technique may be immersion gold, electroless palladium, and immersion gold (IGEPIG).
  • the electroless plating technique may be Electroless Nickel and Immersion Gold (ENIG).
  • forming the TGV in the glass substrate may further comprise forming a planar TGV in the glass substrate.
  • Forming the TGV in the glass substrate may further comprise forming a pinched TGV in the glass substrate.
  • the invention may be an electrically-conductive through-glass via (TGV) structure that comprises a TGV formed in a glass substrate for use in a microelectromechanical system (MEMS) device.
  • TGV through-glass via
  • MEMS microelectromechanical system
  • the TGV may have a first end and a second end, and at least partially comprise copper.
  • the structure may further comprise a conductive barrier layer applied on the first end of the TGV and/or the second end of the TGV.
  • the structure may further comprise a metal layer disposed over the conductive barrier layer.
  • the conductive barrier layer may extend over the first end of the TGV, and over at least a portion of the glass substrate encompassing the end of the TGV, such that the conductive barrier layer overlaps a boundary between the TGV and the glass substrate.
  • the conductive barrier layer may be applied using an electroless plating process.
  • the electroless plating technique may be electroless palladium and immersion gold (EPIG).
  • the electroless plating technique may be immersion gold, electroless palladium, and immersion gold (IGEPIG).
  • the electroless plating technique may be Electroless Nickel and Immersion Gold (ENIG).
  • the TGV may be a planar TGV.
  • the TGV may be a pinched TGV.
  • the invention may be a microelectromechanical system (MEMS) component that comprises a glass substrate that hosts a MEMS device, a glass lid disposed on the glass substrate and encompassing the MEMS device within a cavity, a through-glass via (TGV) formed in the glass lid.
  • MEMS microelectromechanical system
  • the TGV may have a first end at an exterior of the glass lid, a second end that is electrically coupled to the MEMS device.
  • the TGV may at least partially comprise copper.
  • the MEMS component may further comprise a conductive barrier layer applied on the first end of the TGV and/or the second end of the TGV.
  • the conductive barrier layer may extend over the first end of the TGV, and over at least a portion of the exterior of the glass lid, such that the conductive barrier layer overlaps a boundary between the TGV and the glass lid.
  • FIGs. 1 A and IB illustrate components of a MEMS component.
  • FIG. 2 shows an example of barrier layer placement according to embodiments of the invention.
  • FIGs. 3 A and 3B show cross-sectional and top views of a pinched via.
  • FIGs. 4A, 4B, and 4C show cross-sectional and top views of planar vias.
  • FIGs. 5 A and 5B illustrate details of a barrier layer at the top of a via.
  • FIG. 6 shows barrier layer thickness and coverage characteristics at selected depths of a pinched via.
  • FIGs. 7A and 7B show via corrosion characteristics with and without a barrier layer in place.
  • a microelectromechanical system (MEMS) component may consist of a two-part structure, as shown in FIG. 1 A.
  • the first part comprises a MEMS device structure 10 constructed on a glass substrate 12, and the second part comprises a glass lid or cap 14 that surrounds and covers the MEMS device structure 10, as shown in FIG. IB, to form a hermetically sealed cavity 16 in which the MEMS device structure 10 resides.
  • One or more electrical conductors may pass through the glass lid 14 to the MEMS device structure 10, to provide electrical access to the MEMS device structure 10 from outside the sealed cavity 16.
  • These electrical conductors are in the form of through-glass vias (TGVs) 18 that facilitate the transmission of electrical signals through the glass lid 14 while maintaining the hermeticity of the sealed cavity 16.
  • TSVs through-glass vias
  • the electrically conductive material within the TGV 18 may be copper, with a gold layer 20a coupled to the bottom (i.e., substrate-facing) end of the TGV 18, and a gold layer 20b (external bonding pad) coupled to the top end of the TGV 18.
  • Gold layers 20c are disposed on the substrate 12 and electrically coupled to the MEMS device structure 10.
  • the gold layer 20a at the bottom of the TGV 18 couples to the gold layer 20c on the substrate 12 by thermal-compression bonding, thereby forming the hermetically sealed cavity 16, as shown in FIG. IB.
  • the embodiments described herein are directed to an electrically conductive barrier layer or layers applied between (i) a copper (Cu) through-glass via (TGV) and (ii) each of one or more gold (Au) layers associated with the TGV.
  • the barrier layer is configured to reduce or eliminate migration of Cu from the TGV through one or more associated Au layers.
  • FIG. 2 illustrates an example of barrier layer placement according to the described embodiments.
  • the examples in FIG. 2 are not necessarily drawn to scale, but are used to present conceptual descriptions.
  • the cap 14 comprises a copper-based TGV 18 deployed within a glass lid 14, with a gold layer 20b coupled to the top end of the TGV 18 and a gold layer 20a coupled to the bottom end of the TGV 18.
  • the TGV 18 in this example embodiment is described as being copperbased, it should be understood that in some embodiments the TGV may comprise copper, or a material that is mostly copper (e.g., greater than 95 percent copper) or a material that comprises some smaller portion that is copper (e.g., more than half copper), or a material that comprises less than half copper.
  • Barrier layer 202a is disposed between the TGV 18 and Au layer 20a at the bottom (i.e., substrate-facing) end of the TGV 18.
  • Barrier layer 202b is disposed between the TGV 18 and the Au layer 20b at the top end of the TGV 18.
  • the barrier layer comprises palladium (Pd).
  • the barrier layer may comprise a material such as nickel (Ni) or composites that include Pd and/or Ni, or other materials suitable for blocking Cu migration.
  • the barrier layer should be of a sufficient thickness to prevent Cu migration into an adjacent metal layer (e.g., gold) at elevated temperatures (e.g., 300°C to 400°C for one to two hours).
  • a sufficient thickness of the barrier layer may depend on device characteristics and physical parameters, and may be determined empirically, but a sufficient thickness is generally at least 250nm for Pd, and at least 175nm for Ni.
  • the process of deploying the barrier layer described herein may be integrated into the procedure for fabricating a microelectromechanical system (MEMS) component.
  • the TGV may be fabricated and filled with copper during the MEMS component fabrication.
  • the TGV could take on several forms including pinch vias (as shown in a cross-sectional view in FIG 3 A, a top view in FIG. 3B, and in FIGs. 5A, 5B, and 6), or several versions of planar vias (shown in FIGs. 4A, 4B, and 4C), where “planar” refers to the fact that the metallized top 402 of the via 404 is substantially co-planar with the glass surface 406 (to within manufacturing specifications). Other variations on these designs are also possible.
  • the glass wafers go through a metal finishing step where the conductive barrier layer is deposited or plated on top of the Cu-based via.
  • This may include a pre-treatment of the Cu surface followed by the use of a catalyst, a barrier layer, and a final Au layer.
  • Some cases of EPIG may incorporate a thin Ni or Au layer, for example, between the Cu and Pd, and in other cases the Pd may be plated directly onto the Cu with some pre-treatment (e.g., etching of the Cu).
  • Electroless Nickel and Immersion Gold ENIG
  • EPIG Electroless Palladium and Immersion Gold
  • IGEPIG Immersion Gold
  • IGEPIG Electroless Palladium and Immersion Gold
  • the key attributes are that there is a barrier material (e.g., nickel (Ni) or palladium (Pd) in the above examples) that cover the entire exposed via surface, where the barrier material is of sufficient thickness to prevent Cu migration into the Au at elevated temperatures (e.g. 350-400 C for 1-2 hours).
  • a barrier material e.g., nickel (Ni) or palladium (Pd) in the above examples
  • This also includes a continuous layer of this metal finish over the entire TGV outer surface.
  • An anneal step to remove embedded hydrogen from the coating may also be used.
  • the conductive barrier layer is deposited, additional layers (e.g., Au) are deposited onto the lid wafer and the lid wafer is then bonded to the MEMS substrate in a specific oxygen environment.
  • additional layers e.g., Au
  • the barrier layer provides reliable performance over a range of process and operational environmental parameters (%O 2 , humidity, temperature, etc.).
  • FIG. 5 A illustrates a cross-sectional view of an example pinched via, viewed near the glass substrate surface at the top of the via.
  • the conductive Pd barrier layer is disposed on the outside of the Cu via, and covers the glass-to-copper interface at the via perimeter. It is important to have full coverage of the Pd barrier layer across the entire TGV surface, and to have a uniform thickness. Accomplishing complete coverage is difficult for the pinch via design.
  • the thickness of the barrier layer tends to be greater at the top/outside than it is within the cavity of the pinched via. See, for example, FIG. 6, which shows the percent coverage of the Pd barrier layer at various depths of a pinched via into the glass substrate.
  • FIG. 6 shows the percent coverage of the Pd barrier layer at various depths of a pinched via into the glass substrate.
  • FIG. 6 illustrates that coverage near the top of the pinched via is complete or nearly complete, while coverage deep into the via cavity may be substantially reduced.
  • Techniques such as sonification may be used to drive the Pd into the via cavity, thereby resulting in a thicker and more uniform barrier layer deep into the cavity of the via.
  • Application of the barrier layer as described herein on a planar via tends to result in a barrier layer of uniform thickness, which in turn results in complete or near complete coverage across the entire planar via.
  • FIG. 7A illustrates an example top-view of a via with no Pd barrier (or poor Pd barrier placement)
  • FIG. 7B illustrates an example top-view of a via with substantial Pd barrier layer coverage.
  • the dark circle in the center of the via represents the cavity of the via (see, e.g., FIG. 3 A).
  • FIG. 7A shows a substantial amount of cupric oxide (CuO) corrosion 702 formed about the surface of the via due to copper that has migrated through the gold layer, while FIG. 7B is relatively free of CuO corrosion at the surface of the via due to the presence of the Pd barrier layer.
  • CuO cupric oxide
  • Placement of conductive barrier layers as described herein may be accomplished using various techniques such as electroless plating (e.g., ENIG, EPIG or IGEPIG), sputtering, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), among others.
  • electroless plating e.g., ENIG, EPIG or IGEPIG
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • Chemically-based techniques such as electroless plating tend to produce better results for cavity -based vias (e.g., pinched vias), because chemically- based techniques facilitate propagation of the barrier material into the cavity of the via.
  • sonication techniques may be used to further enhance the distribution of the barrier material into the cavity of the via.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Micromachines (AREA)

Abstract

L'invention concerne un procédé de prévention de la corrosion associée à une interconnexion verticale à travers le verre électroconducteur (TGV) qui peut comprendre la formation d'un TGV dans un substrat de verre destiné à être utilisé dans un dispositif de système microélectromécanique (MEMS). Le TGV a une première extrémité et une seconde extrémité, et comprend au moins partiellement du cuivre. Le procédé peut en outre comprendre l'application d'une couche barrière conductrice sur la première extrémité du TGV et/ou sur la seconde extrémité du TGV, et l'application d'une couche métallique sur la couche barrière conductrice. Le procédé peut en outre comprendre l'extension de la couche barrière conductrice sur la première extrémité du TGV, et sur au moins une partie du substrat en verre englobant l'extrémité du TGV, de telle sorte que la couche barrière conductrice chevauche une limite entre le TGV et le substrat en verre.
PCT/US2023/068035 2023-06-07 2023-06-07 Interconnexion verticale à travers le verre utilisant une couche barrière conductrice Ceased WO2024253687A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/US2023/068035 WO2024253687A1 (fr) 2023-06-07 2023-06-07 Interconnexion verticale à travers le verre utilisant une couche barrière conductrice
KR1020257042221A KR20260022324A (ko) 2023-06-07 2023-06-07 전도성 차단층을 이용한 관통-유리-비아
EP23741216.8A EP4724382A1 (fr) 2023-06-07 2023-06-07 Interconnexion verticale à travers le verre utilisant une couche barrière conductrice
CN202380098773.5A CN121487890A (zh) 2023-06-07 2023-06-07 利用导电阻挡层的玻璃通孔

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2023/068035 WO2024253687A1 (fr) 2023-06-07 2023-06-07 Interconnexion verticale à travers le verre utilisant une couche barrière conductrice

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WO2024253687A1 true WO2024253687A1 (fr) 2024-12-12

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EP (1) EP4724382A1 (fr)
KR (1) KR20260022324A (fr)
CN (1) CN121487890A (fr)
WO (1) WO2024253687A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150353348A1 (en) * 2014-06-10 2015-12-10 Rf Micro Devices, Inc. Glass wafer assembly
US20180254239A1 (en) * 2017-03-01 2018-09-06 Globalfoundries Inc. FORMING METAL CAP LAYER OVER THROUGH-GLASS-VIAS (TGVs)

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150353348A1 (en) * 2014-06-10 2015-12-10 Rf Micro Devices, Inc. Glass wafer assembly
US20180254239A1 (en) * 2017-03-01 2018-09-06 Globalfoundries Inc. FORMING METAL CAP LAYER OVER THROUGH-GLASS-VIAS (TGVs)

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SOMEYA TATSUSHI ET AL: "Deposit properties of new electroless AU/PD/AU process for fine line application", 2018 PAN PACIFIC MICROELECTRONICS SYMPOSIUM (PAN PACIFIC), SMTA, 5 February 2018 (2018-02-05), pages 1 - 6, XP033331681, DOI: 10.23919/PANPACIFIC.2018.8319018 *

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KR20260022324A (ko) 2026-02-19
EP4724382A1 (fr) 2026-04-15

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