WO2024255350A1 - 显示模组及显示装置 - Google Patents

显示模组及显示装置 Download PDF

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Publication number
WO2024255350A1
WO2024255350A1 PCT/CN2024/081491 CN2024081491W WO2024255350A1 WO 2024255350 A1 WO2024255350 A1 WO 2024255350A1 CN 2024081491 W CN2024081491 W CN 2024081491W WO 2024255350 A1 WO2024255350 A1 WO 2024255350A1
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WO
WIPO (PCT)
Prior art keywords
transistor
stage
pixel unit
row
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/081491
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English (en)
French (fr)
Inventor
毛晗
叶利丹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Original Assignee
HKC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Priority to KR1020257040441A priority Critical patent/KR20260005986A/ko
Priority to EP24822308.3A priority patent/EP4730317A1/en
Priority to JP2025553509A priority patent/JP2026507953A/ja
Publication of WO2024255350A1 publication Critical patent/WO2024255350A1/zh
Priority to US19/409,776 priority patent/US20260086414A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1685—Operation of cells; Circuit arrangements affecting the entire cell
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/166—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect
    • G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G02F1/16757—Microcapsules
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G09G2310/021—Double addressing, i.e. scanning two or more lines, e.g. lines 2 and 3; 4 and 5, at a time in a first field, followed by scanning two or more lines in another combination, e.g. lines 1 and 2; 3 and 4, in a second field
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present application relates to the field of display technology, and in particular to a display module and a display device.
  • E-Ink electronic ink
  • electronic ink display panels display images by electrophoresis of charged particles of different colors in the electronic ink in the electric field formed between the upper and lower substrates.
  • this electrophoretic display method makes the response time of electronic ink longer, about 400 milliseconds, far less than that of liquid crystal display panels; due to the slow response speed, the panel refresh rate is low, resulting in obvious "stuttering" when users use it.
  • the present application provides a display module and a display device, aiming to solve the problem of low refresh rate of display devices in the prior art causing image freezes.
  • the display module includes:
  • a pixel unit includes a pixel electrode, a common electrode and a microcapsule structure, wherein the pixel electrode and the common electrode are arranged opposite to each other, the microcapsule structure is arranged between the pixel electrode and the common electrode, and the microcapsule structure includes charged particles;
  • a driving transistor comprising a control terminal, a first terminal and a second terminal, wherein the second terminal is electrically connected to the pixel electrode and is used to drive the pixel unit;
  • a scanning line electrically connected to the control terminal, for providing a scanning signal to the pixel unit
  • a data line electrically connected to the first end, and used to provide a data signal to the pixel electrode
  • the pixel unit includes a first pixel unit and a second pixel unit that are adjacent to each other;
  • the first pixel unit is used to receive a frame of data signals pushed by the data line in the first phase
  • the second pixel unit is used to receive the next frame of data signals pushed by the data line in the second phase, and the first phase is before the second phase.
  • the display module includes a plurality of pixel units, and the plurality of pixel units are arranged in a matrix; in each display cycle,
  • the driving transistors corresponding to the first pixel units of the plurality of rows are turned on in sequence, so that the first pixel units of the plurality of rows receive a frame of data signals pushed by the data lines and display a frame of image;
  • the driving transistors corresponding to the plurality of rows of second pixel units are turned on in sequence, so that the plurality of rows of second pixel units receive the next frame of data signals pushed by the data lines and display the next frame of images.
  • the pixel electrode includes a first pixel electrode and a second pixel electrode adjacent to each other, the first pixel electrode, a common electrode and a microcapsule structure form a first pixel unit, and the second pixel electrode, the same common electrode and the microcapsule structure form a second pixel unit;
  • the driving transistor includes a first transistor and a second transistor, a second end of the first transistor is electrically connected to the first pixel electrode, and a second end of the second transistor is electrically connected to the second pixel electrode.
  • first end of the first transistor and the first end of the second transistor are respectively electrically connected to the same data line;
  • the scan line comprises a first scan line and a second scan line, the first scan line is electrically connected to the control end of the first transistor, and the second scan line is electrically connected to the control end of the second transistor;
  • the first scan line is used to push a scan signal to the first transistor in the first stage
  • the second scan line is used to push a scan signal to the second transistor in the second stage, so that the first pixel unit receives a frame of data signals pushed by the data line in the first stage, and the second pixel unit receives the next frame of data signals pushed by the data line in the second stage.
  • each first scanning line pushes a frame of scanning signals row by row to turn on the first transistors row by row; each data line pushes a frame of data signals to the first pixel unit column by column to display a frame of image;
  • each second scan line pushes the next frame scan signal row by row to turn on the second transistor row by row; each data line pushes the next frame data signal to the second pixel unit column by column to display the next frame image.
  • the first stage After the first stage ends, it will enter the second stage after a preset period of time.
  • control end of the first transistor and the control end of the second transistor are respectively electrically connected to the same scan line;
  • the data line includes a first data line and a second data line, the first data line is electrically connected to the first end of the first transistor, and the second data line is electrically connected to the first end of the second transistor;
  • the scan line is used to push the scan signal to the first transistor, and the first data line is used to push a frame of data signal to the first pixel unit through the first transistor; in the second stage, the scan line is used to push the scan signal to the second transistor, and the second data line is used to push the next frame of data signal to the second pixel unit through the second transistor.
  • each scanning line pushes a frame of scanning signals row by row to turn on the driving transistor row by row; the first data line pushes a frame of data signals row by row to the first pixel unit to display a frame of image; and after each first data line pushes a preset time, each second data line pushes the next frame of data signals column by column to the second pixel unit in advance;
  • each scanning line pushes the next frame scanning signal line by line, and the second pixel unit receives the next frame data signal to display the next frame image.
  • the scan line includes a first scan line and a second scan line, the first scan line is electrically connected to the control end of the first transistor, and the second scan line is electrically connected to the control end of the second transistor;
  • the data line includes a first data line and a second data line, the first data line is electrically connected to the first end of the first transistor, and the second data line is electrically connected to the first end of the second transistor;
  • the first scan line is used to push the scan signal to the first transistor, and the first data line is used to push a frame of data signal to the first pixel unit through the first transistor; in the second stage, the second scan line is used to push the scan signal to the second transistor, and the second data line is used to push the next frame of data signal to the second pixel unit through the second transistor.
  • the first scan line pushes a frame of scan signals row by row to turn on the first transistor row by row; the first data line pushes a frame of data signals to the first pixel unit column by column to display a frame of image;
  • the second scan line pushes the next frame scan signal row by row to turn on the second transistor row by row; the second data line pushes the next frame data signal to the second pixel unit column by column to display the next frame image.
  • the common electrode includes a first common electrode and a second common electrode adjacent to each other, the pixel electrode, the first common electrode and the microcapsule structure form a first pixel unit, and the same pixel electrode, the second common electrode and the microcapsule structure form a second pixel unit;
  • the scan line pushes a scan signal to the driving transistor in the first stage and the second stage; in the first stage, the data line pushes a frame of data signal to the pixel electrode through the first end, and the first common electrode is used to push a first common voltage signal so that the first pixel unit receives a frame of data signal; in the second stage, the data line pushes the next frame of data signal to the pixel electrode through the first end, and the second common electrode is used to push a second common voltage signal so that the second pixel unit receives the next frame of data signal.
  • the scan lines push scan signals row by row to turn on the drive transistors row by row.
  • the first common electrode pushes a frame of common voltage signals;
  • the data lines push a frame of data signals to the pixel electrodes column by column, so that a corresponding electric field is formed in the first pixel unit to display a frame of images;
  • the second common electrode pushes the next frame of common voltage signal, and after a preset time, enters the second stage;
  • the data lines push the next frame of data signals to the pixel electrodes column by column, so that a corresponding electric field is formed in the second pixel unit to display the next frame of images.
  • the pixel electrode includes a first pixel electrode and a second pixel electrode that are adjacent to each other, and the common electrode includes a first common electrode and a second common electrode that are adjacent to each other; the first pixel electrode is disposed opposite to the first common electrode, and forms a first pixel unit with the microcapsule structure; the second pixel electrode is disposed opposite to the second common electrode, and forms a second pixel unit with the microcapsule structure;
  • the driving transistor includes a first transistor and a second transistor, a second end of the first transistor is electrically connected to the first pixel electrode, and a second end of the second transistor is electrically connected to the second pixel electrode.
  • control end of the first transistor and the control end of the second transistor are respectively electrically connected to the same scan line;
  • the data line includes a first data line and a second data line, the first data line is electrically connected to the first end of the first transistor, and the second data line is electrically connected to the first end of the first transistor.
  • the data line is electrically connected to the first end of the second transistor;
  • the scan line is used to push the scan signal to the driving transistor in the first stage and the second stage; in the first stage, the first data line is used to push a frame of data signal to the first pixel electrode through the first transistor, and the first common electrode is used to push the first common voltage signal so that the first pixel unit receives a frame of data signal; in the second stage, the second data line is used to push the next frame of data signal to the second pixel electrode through the second transistor, and the second common electrode is used to push the second common voltage signal so that the second pixel unit receives the next frame of data signal.
  • the scan lines push scan signals row by row to turn on the drive transistors row by row.
  • the first common electrode pushes the first common voltage signal
  • the first data line pushes a frame of data signals to the first pixel unit column by column to display a frame of image
  • the second common electrode pushes the second common voltage signal
  • the second data line pushes the next frame data signal to the second pixel unit column by column to display the next frame image.
  • first end of the first transistor and the first end of the second transistor are respectively electrically connected to the same data line;
  • the scan line comprises a first scan line and a second scan line, the first scan line is electrically connected to the control end of the first transistor, and the second scan line is electrically connected to the control end of the second transistor;
  • the first scan line is used to push the scan signal to the first transistor
  • the data line is used to push a frame of data signal to the first pixel electrode through the first transistor
  • the first common electrode is used to push the first common voltage signal so that the first pixel unit receives a frame of data signal
  • the second scan line is used to push the next frame of data signal to the second pixel electrode through the second transistor
  • the second common electrode is used to push the second common voltage signal so that the second pixel unit receives the next frame of data signal.
  • the first scan line pushes a frame of scan signals row by row to turn on the first transistor row by row;
  • the first common electrode pushes a first common voltage signal, and the data line pushes a frame of data signals to the first pixel unit to display a frame of image;
  • the second scan line pushes the next frame scan signal row by row to turn on the second transistor row by row; the second common electrode pushes the second common voltage signal, and the data line pushes the next frame data signal to the second pixel unit column by column to display the next frame image.
  • the microcapsule structure includes an electrophoretic medium and positively charged particles and negatively charged particles suspended in the electrophoretic medium; the positively charged particles and negatively charged particles are charged particles of different colors.
  • the display device includes:
  • a display module, used for displaying images, the display module is the display module involved in the above technical solution;
  • the control module is electrically connected to the display module and is used to provide a control signal to the display module so that in each display cycle, the display module displays a frame of image in the first stage and displays the next frame of image in the second stage.
  • the present application provides a display module and a display device, wherein the display module includes a plurality of pixel units, each pixel unit includes adjacent first pixel units and second pixel units for displaying images; and within each display cycle, the first pixel unit receives a frame of data signal pushed by the data line in the first stage to display a frame of picture, and the second pixel unit receives the next frame of data signal pushed by the data line in the second stage to display the next frame of picture, so that the display module can display two frames of pictures within one display cycle, and the refresh rate of the display module can be doubled, thereby overcoming the problem of low refresh rate caused by slow response speed of the display module, effectively improving the refresh rate of the display module, and improving the "stuttering" feeling of the picture.
  • FIG1 is a schematic diagram of the structure of a driving substrate of a display module provided by an embodiment of the prior art
  • FIG2a is a schematic structural diagram of a pixel unit provided in the embodiment of FIG1 when no electric field is applied;
  • FIG2 b is a schematic structural diagram of a pixel unit provided in the embodiment of FIG1 when displaying black;
  • FIG2c is a schematic structural diagram of a pixel unit provided in the embodiment of FIG1 when displaying white;
  • FIG3 is a schematic structural diagram of a display module provided in the first embodiment of the present application.
  • FIG4 is a schematic structural diagram of a driving substrate provided in the first embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another driving substrate provided in the first embodiment of the present application.
  • FIG6 is a timing diagram of driving signals of a display module provided in the first embodiment of the present application.
  • FIG7 is a schematic diagram of the structure of a display module provided in a second embodiment of the present application.
  • FIG8 is a schematic structural diagram of a driving substrate provided in a second embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another driving substrate provided in the second embodiment of the present application.
  • FIG10 is a timing diagram of driving signals of a display module provided in the second embodiment of the present application.
  • FIG11 is a schematic structural diagram of a display module provided in a third embodiment of the present application.
  • FIG12 is a schematic structural diagram of a driving substrate provided in a third embodiment of the present application.
  • FIG13 is a timing diagram of driving signals of a display module provided in the third embodiment of the present application.
  • FIG14 is a schematic diagram of a planar structure of a display module provided in a fourth embodiment of the present application.
  • FIG15 is a schematic diagram of a planar structure of another display module provided in the fourth embodiment of the present application.
  • FIG16 is a timing diagram of driving signals of a display module provided in a fourth embodiment of the present application.
  • FIG17 is a schematic diagram of a planar structure of a display module provided in a fifth embodiment of the present application.
  • FIG18 is a timing diagram of driving signals of a display module provided in the fifth embodiment of the present application.
  • FIG19 is a schematic diagram of a planar structure of a display module provided in a sixth embodiment of the present application.
  • FIG20 is a timing diagram of driving signals of a display module provided in a sixth embodiment of the present application.
  • FIG. 21 is a schematic diagram of the structure of a display device provided in one embodiment of the present application.
  • 100a 100-display module; 10a, 10-driving substrate; 11a, 11-substrate; 12a, 12-driving circuit layer; 13a, 13- Pixel electrode; 131-first pixel electrode; 132-second pixel electrode; 14a, 14-driving transistor; 141a, 141-control terminal; 142a, 142-first terminal; 143a, 143-second terminal; 144-first transistor; 145-second transistor; 15a, 15-scanning line; 151-first scanning line; 152-second scanning line; 16a, 16-data line; 161-first data line; 162-second data line; 20a, 20-opposite substrates; 21a, 21-substrates; 22a, 22-common electrodes; 221-first common electrode; 222-second common electrode; 30a, 30-microcapsule structure; 31a, 31-positively charged particles; 32a, 32-negatively charged particles; 40a, 40-pixel units; 41-first pixel unit; 42-second pixel
  • first”, “second”, “third” in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • the features defined as “first”, “second”, “third” can expressly or implicitly include at least one of the features.
  • the meaning of “multiple” is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
  • all directional indications (such as up, down, left, right, front, back%) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly.
  • FIG. 1 is a schematic diagram of the structure of a driving substrate of a display module provided by an embodiment of the prior art
  • FIG. 2a is a schematic diagram of the structure of a pixel unit provided by the embodiment of FIG. 1 when no electric field is applied.
  • an electrophoretic display module 100a includes a driving substrate 10a and a counter substrate 20a that are arranged opposite to each other, and a microcapsule structure 30a arranged therebetween; wherein the driving substrate 10a includes a substrate 11a, a driving circuit layer 12a and an electrode layer, and the electrode layer includes a plurality of pixel electrodes 13a distributed in an array; the counter substrate 20a includes a plurality of common electrodes 22a, wherein the pixel electrodes 13a and the common electrodes 22a that are arranged opposite to each other The microcapsule structure 30a disposed therebetween forms a pixel unit 40a.
  • the driving circuit layer 12a includes a plurality of scanning lines 15 extending along a first direction X, a plurality of data lines 16a extending along a second direction Y, and a plurality of driving transistors 14a, wherein the driving transistors 14a correspond to the pixel units 40a one by one, each scanning line 15 is electrically connected to a control end 141a of the driving transistor 14a of a corresponding row, each data line 16a is electrically connected to a first end 142a of the driving transistor 14a of a corresponding column, and a second end 143a of the driving transistor 14a is electrically connected to a corresponding pixel electrode 13a.
  • the first direction X intersects with the second direction Y, and the first direction X is perpendicular to the second direction Y in the embodiment of the present application.
  • the microcapsule structure 30a arranged between the pixel electrode 13a and the common electrode 22a includes white positively charged particles 31a and black negatively charged particles 32a; when no potential is applied to the pixel electrode 13a and the common electrode 22a, the positively charged particles 31a and the negatively charged particles 32a are randomly distributed in the microcapsule structure 30a, and no image is displayed.
  • FIG. 2b is a schematic diagram of the structure of the pixel unit provided in the embodiment of FIG. 1 when displaying black.
  • a negative potential is applied to the pixel electrode 13a and a positive potential is applied to the common electrode 22a, that is, the potential of the common electrode 22a is higher than the potential of the pixel electrode 13a, and an electric field is formed in the direction from the common electrode 22a to the pixel electrode 13a
  • the positively charged particles 31a move toward the pixel electrode 13a in an "electrophoretic" manner
  • the negatively charged particles 32a move toward the common electrode 22a
  • the pixel unit 40a displays black.
  • FIG. 2c is a schematic diagram of the structure of the pixel unit provided in the embodiment of FIG. 1 when displaying white.
  • a positive potential is applied to the pixel electrode 13a and a negative potential is applied to the common electrode 22a, that is, the potential of the pixel electrode 13a is higher than the potential of the common electrode 22a, and an electric field is formed in the direction from the pixel electrode 13a to the common electrode 22a
  • the negatively charged particles 32a move toward the pixel electrode 13a in an "electrophoretic" manner
  • the positively charged particles 31a move toward the common electrode 22a
  • the pixel unit 40a displays white.
  • the positively charged particles 31a and the negatively charged particles 32a move in an "electrophoretic" manner, so their response speed is usually above 500ms, making the refresh rate of the display module 100a less than 10Hz, the dynamic display effect is poor, and the screen is prone to "stuttering".
  • the display module 100 (see FIG. 3 ) provided in the embodiment of the present application is configured so that each pixel unit 40 includes adjacent first pixel units 41 and second pixel units 42 for displaying images; and in each display cycle T, the first pixel unit 41 receives a frame of data signal pushed by the data line 16 in the first stage T1 to display a frame of picture, and the second pixel unit 42 receives the next frame of data signal pushed by the data line 16 in the second stage T2 to display the next frame of picture, so that the display module 100 can display two frames of picture in one display cycle T, and the refresh rate of the display module 100 can be doubled, thereby overcoming the problem of low refresh rate caused by the slow response speed of the above-mentioned display module 100a, effectively improving the refresh rate of the display module 100a, and improving the "stuttering" feeling of the picture.
  • Figure 3 is a schematic diagram of the structure of the display module provided in the first embodiment of the present application
  • Figure 4 is a schematic diagram of the structure of a driving substrate provided in the first embodiment of the present application
  • Figure 5 is a schematic diagram of the structure of another driving substrate provided in the first embodiment of the present application.
  • a display module 100 is provided, and the display module 100 includes a pixel unit 40, a driving transistor 14, a scanning line 15 and a data line 16.
  • each pixel unit 40 includes a pixel electrode 13, a common electrode 22 and a microcapsule structure 30, the pixel electrode 13 is arranged opposite to the common electrode 22, and the microcapsule structure 30 is arranged between the pixel electrode 13 and the common electrode 22.
  • the microcapsule structure 30 includes an electrophoretic medium and positively charged particles 31 and negatively charged particles 32 suspended in the electrophoretic medium.
  • the positively charged particles 31 and the negatively charged particles 32 are charged particles of different colors, and their specific colors can be set according to actual use needs. There is no specific limitation on this.
  • the positively charged particles 31 and the negatively charged particles 32 are white particles and black particles, respectively, for example.
  • the driving transistor 14 includes a control terminal 141, a first terminal 142 and a second terminal 143.
  • the second terminal 143 is electrically connected to the pixel electrode 13 and is used to drive the pixel electrode 13 so that a corresponding electric field is formed between the pixel electrode 13 and the common electrode 22, so that the charged particles move regularly.
  • the scanning line 15 is electrically connected to the control terminal 141 of the driving transistor 14 so that the scanning line 15 provides a scanning signal to the pixel unit 40 through the driving transistor 14;
  • the data line 16 is electrically connected to the first terminal 142 of the driving transistor 14 so that the data line 16 provides a data signal to the pixel unit 40 through the driving transistor 14, so that the pixel unit 40 displays a corresponding color.
  • control terminal 141 is the gate of the driving transistor 14, the first terminal 142 is the source of the driving transistor 14, and the second terminal 143 is the drain of the driving transistor 14.
  • the driving transistor 14 can be a thin film transistor TFT. The specific type can be selected according to actual needs and is not specifically limited to this.
  • the pixel unit 40 includes a first pixel unit 41 and a second pixel unit 42.
  • the first pixel unit 41 is used to display a frame of the picture in the first stage T1
  • the second pixel unit 42 is used to display the next frame of the picture in the second stage T2
  • the display module 100 can display two frames of the picture in one display cycle T, and the refresh rate of the display module 100 can be doubled, thereby overcoming the problem of low refresh rate caused by the slow response speed of the display module 100a, effectively improving the refresh rate of the display module 100, and improving the "stuttering" feeling of the picture.
  • the pixel electrode 13 includes adjacent first pixel electrodes 131 and second pixel electrodes 132.
  • the first pixel electrode 131, the common electrode 22 and the microcapsule structure 30 form a first pixel unit 41
  • the second pixel electrode 132, the same common electrode 22 and the microcapsule structure 30 form a second pixel unit 42.
  • the driving transistor 14 includes a first transistor 144 and a second transistor 145.
  • the second end 143 of the first transistor 144 is electrically connected to the first pixel electrode 131
  • the second end 143 of the second transistor 145 is electrically connected to the second pixel electrode 132.
  • the data line 16 is arranged between the first pixel unit 41 and the second pixel unit 42 to shorten the wiring length between the data line 16 and the first pixel unit 41 and/or the second pixel unit 42, which is beneficial to the wiring layout; the first end 142 of the first transistor 144 and the first end 142 of the second transistor 145 are electrically connected to the data line 16 respectively, so that the data line 16 provides data signals to the first pixel unit 41 and the second pixel unit 42 respectively.
  • the scan line 15 includes a first scan line 151 and a second scan line 152.
  • the first scan line 151 is electrically connected to the control terminal 141 of the first transistor 144 to control when the first pixel unit 41 can receive the data signal;
  • the second scan line 152 is electrically connected to the control terminal 141 of the second transistor 145 to control when the second pixel unit 42 can receive the data signal.
  • the first scan line 151 and the second scan line 152 can be arranged on the same side of the pixel unit 40, or respectively arranged on opposite sides of the pixel unit 40, which can be arranged according to actual needs, and no specific limitation is made to this.
  • FIG. 6 is a timing diagram of a driving signal of a display module provided in the first embodiment of the present application.
  • a driving method of a display module is provided, and a pixel unit 40 is taken as an example to illustrate.
  • each first scanning line 151 pushes a frame scanning signal Gout1-1, Gout2-1, Gout3-1 row by row, so that the first transistor 144 is turned on row by row.
  • each data line 16 pushes a frame data signal Data1-1, Data2-1, Data3-1 to the first pixel unit 41 column by column during the corresponding first stage T1 period, so that the first transistor 144 is turned on row by row.
  • a pixel unit 41 displays a frame of image; after the first scan line 151 is pushed for a period of time t, it enters the second stage T2, and each second scan line 152 pushes the next frame of scan signals Gout1-2, Gout2-2, and Gout3-2 row by row, so that the second transistor 145 is turned on row by row.
  • each data line 16 pushes the next frame of data signals Data1-2, Data2-2, and Data3-3 to the second pixel unit 42 column by column during the corresponding second stage T2 period, so that the second pixel unit 42 displays the next frame of image.
  • the display module 100 can push two frames of image signals in one display cycle T.
  • the structure of the display module 100 can increase the image refresh rate to twice the conventional refresh rate f, greatly improving the image refresh rate, thereby effectively improving the image "stuttering" feeling of the display module 100a.
  • the time difference t between the first stage T1 and the second stage T2 can be specifically set according to actual needs.
  • Figure 7 is a schematic diagram of the structure of the display module provided by the second embodiment of the present application
  • Figure 8 is a schematic diagram of the structure of a driving substrate provided by the second embodiment of the present application
  • Figure 9 is a schematic diagram of the structure of another driving substrate provided by the second embodiment of the present application.
  • the control end 141 of the first transistor 144 and the control end 141 of the second transistor 145 are respectively electrically connected to the corresponding same scanning line 15 to control when the row of pixel units 40 can receive data signals, that is, a row of pixel units 40 is driven by a scanning line 15; specifically, the data line 16 includes a first data line 161 and a second data line 162, the first data line 161 is electrically connected to the first end 142 of the first transistor 144 to provide a data signal to the first pixel unit 41, and the second data line 162 is electrically connected to the first end 142 of the second transistor 145 to provide a data signal to the second pixel unit 42.
  • the first data line 161 and the second data line 162 may be arranged on opposite sides of the pixel unit 40, or be arranged between the first pixel unit 41 and the second pixel unit 42; of course, the first data line 161 may also be arranged on the outside of the first pixel unit 41, and the second scan line 152 may be arranged between the first pixel unit 41 and the second pixel unit 42; or, the first data line 161 is arranged between the first pixel unit 41 and the second pixel unit 42, and the second data line 162 is arranged on the outside of the second pixel unit 42; the specific arrangement may be made according to actual needs, and no specific limitation is made to this.
  • the scan line 15 is used to push the scan signal to the first transistor 144, and the first data line 161 is used to push a frame of data signal to the first pixel unit 41 through the first transistor 144; in the second stage T2, the scan line 15 is used to push the scan signal to the second transistor 145, and the second data line 162 is used to push the next frame of data signal to the second pixel unit 42 through the second transistor 145.
  • FIG. 10 is a driving signal timing diagram of the display module provided by the second embodiment of the present application. Specifically, the example of the pixel unit 40 with three rows and three columns is still used for explanation.
  • each scanning line 15 pushes a frame of scanning signals Gout1-1, Gout2-1, Gout3-1 row by row, so that the driving transistor 14 is turned on row by row.
  • the first data line 161 pushes a frame of data signals Data1-1, Data2-1, Data3-1 column by column to the first pixel unit 41, so that the first pixel unit 41 displays the frame image; after each first data line 161 pushes for a period of time t1, the second data line 162 pushes the next frame of data signals Data1-2, Data2-2, Data3-2 to the second pixel unit 42 in advance.
  • the second pixel unit 42 Since the scan line 15 has not pushed the next frame scan signal, the second pixel unit 42 does not display the next frame image; after the second data line 162 pushes for a period of time t2, it enters the second stage T2, the scan line 15 pushes the next frame scan signal line by line, and the second pixel unit 42 receives the next frame data signal Data1-2, Data2-2, Data3-2 pushed by the second data line 162, so that the second pixel unit 42 displays the next frame image.
  • the display module 100 can push two frames of image signals within one display cycle T.
  • the structure of the display module 100 can increase the image refresh rate to twice the conventional refresh rate f, greatly improving the image refresh rate, thereby effectively improving the image "stuttering" feeling of the display module 100a.
  • the time difference (t1+t2) between the first stage T1 and the second stage T2 can be specifically set according to actual needs.
  • Figure 11 is a schematic diagram of the structure of the display module provided in the third embodiment of the present application
  • Figure 12 is a schematic diagram of the structure of a driving substrate provided in the third embodiment of the present application.
  • the scan line 15 includes a first scan line 151 and a second scan line 152
  • the first scan line 151 is electrically connected to the control terminal 141 of the first transistor 144
  • the second scan line 152 is electrically connected to the control terminal 141 of the second transistor 145
  • the data line 16 includes a first data line 161 and a second data line 162
  • the first data line 161 is electrically connected to the first terminal 142 of the first transistor 144
  • the second data line 162 is electrically connected to the first terminal 142 of the second transistor 145.
  • the specific setting method of the first scan line 151 and the second scan line 152 is the same as or similar to the specific setting method of the first scan line 151 and the second scan line 152 involved in the above-mentioned first embodiment, and the same technical effect can be achieved;
  • the specific setting method of the first data line 161 and the second data line 162 is the same as or similar to the specific setting method of the first data line 161 and the second data line 162 involved in the above-mentioned second embodiment, and the same technical effect can be achieved.
  • the first scan line 151 is used to push a scan signal to the first transistor 144, and the first data line 161 is used to push a frame of data signal to the first pixel unit 41 through the first transistor 144; in the second stage T2, the second scan line 152 is used to push a scan signal to the second transistor 145, and the second data line 162 is used to push the next frame of data signal to the second pixel unit 42 through the second transistor 145.
  • FIG. 13 is a timing diagram of driving signals of a display module provided in the third embodiment of the present application.
  • the first scan line 151 pushes a frame of scan signals Gout1-1, Gout2-1, and Gout3-1 row by row, so that the first transistor 144 is turned on row by row, and at the same time in this stage, the first data line 161 pushes a frame of data signals Data1-1, Data2-1, and Data3-1 to the first pixel unit 41 column by column, so that the first pixel unit 41 displays a frame of image; after the first scan line 151 pushes for a period of time t, it enters the second stage T2, and the second scan line 152 pushes the next frame of scan signals Gout1-2, Gout2-2, and Gout3-2 row by row, so that the second transistor 145 is turned on row by row, and in this stage, the second data line 16
  • the display module 100 can push two frames of image signals in one display cycle T.
  • the structure of the display module 100 can increase the image refresh rate to twice the conventional refresh rate f, greatly improving the image refresh rate, thereby effectively improving the image "stuttering" feeling of the display module 100a.
  • the time difference t between the first stage T1 and the second stage T2 can be specifically set according to actual needs.
  • Figure 14 is a schematic diagram of the planar structure of a display module provided in the fourth embodiment of the present application
  • Figure 15 is a schematic diagram of the planar structure of another display module provided in the fourth embodiment of the present application.
  • the common electrode 22 includes adjacent first common electrodes 221 and second common electrodes 222.
  • the first common electrode 221 and the second common electrode 222 can be arranged in a direction parallel to the scanning line 15, or can also be arranged in a direction parallel to the data line 16, and can be arranged according to actual needs.
  • the pixel electrode 13, the first common electrode 221 and the microcapsule structure 30 form a first pixel unit 41
  • the same pixel electrode 13 the second common electrode 222 and the microcapsule structure 30 form a second pixel unit 42. That is, in the pixel unit 40, the first pixel unit 41 and the second pixel unit 42 share the pixel electrode 13, the portion of the pixel electrode 13 opposite to the first common electrode 221 and the first common electrode 221 and the microcapsule structure 30 therebetween form the first pixel unit 41, and the portion of the pixel electrode 13 opposite to the second common electrode 222 and the second common electrode 222 and the microcapsule structure 30 therebetween form the second pixel unit 42.
  • the scan line 15 pushes a scan signal to the driving transistor 14 in the first stage T1 and the second stage T2; in the first stage T1, the data line 16 pushes a frame of data signal to the pixel electrode 13 through the first end 142, and the first common electrode 221 is used to push the first common voltage signal Com1, so that the first pixel unit 41 receives a frame of data signal; in the second stage T2, the data line 16 pushes the next frame of data signal to the pixel electrode 13 through the first end 142, and the second common electrode 222 is used to push the second common voltage signal Com2, so that the second pixel unit 42 receives the next frame of data signal.
  • FIG. 16 is a timing diagram of driving signals of a display module provided in the fourth embodiment of the present application.
  • the scan line 15 pushes a frame of scan signals Gout1, Gout2, and Gout3 row by row, and at the same time, the first common electrode 221 pushes a frame of common voltage signal Com1.
  • the data line 16 pushes a frame of data signals Data1-1, Data2-1, and Data3-1 to the pixel electrodes 13 column by column, so that a corresponding electric field is formed in the first pixel unit 41, that is, the data line 16 pushes a frame of data signals Data1-1, Data2-1, and Data3-1 to the first pixel unit 41 column by column, so that the first pixel unit 41 displays a frame of image; after the data line 16 pushes the frame After a period of time t2 of the data signal, the second common electrode 222 pushes a frame of common voltage signal Com2.
  • the data line 16 has not pushed the next frame of data signal, so the corresponding electric field has not been formed in the second pixel unit 42, and the next frame of image is not displayed; after a period of time t3 after the common voltage signal Com2 is pushed, it enters the second stage T2, and the data line 16 pushes the next frame of data signals Data1-2, Data2-2, and Data3-2 to the pixel electrodes 13 column by column to form a corresponding electric field in the second pixel unit 42, that is, the data line 16 pushes the next frame of data signals Data1-2, Data2-2, and Data3-2 to the second pixel unit 42 column by column to make the second pixel unit 42 display the next frame of image.
  • the display module 100 can push two frames of image signals in one display cycle T.
  • the structure of the display module 100 can increase the image refresh rate to twice the conventional refresh rate f, greatly improving the image refresh rate, thereby effectively improving the image "stuttering" feeling of the display module 100a.
  • the time difference (t1+t2+t3) between the first stage T1 and the second stage T2 can be specifically set according to actual needs.
  • the pixel electrode 13 includes adjacent first pixel electrodes 131 and second pixel electrodes 132, and the common electrode 22 includes adjacent first common electrodes 221 and second common electrodes 222;
  • the first pixel electrode 131 is arranged opposite to the first common electrode 221, and forms a first pixel unit 41 with the microcapsule structure 30;
  • the second pixel electrode 132 is arranged opposite to the second common electrode 222, and forms a second pixel unit 42 with the microcapsule structure 30;
  • the driving transistor 14 includes a first transistor 144 and a second transistor 145, the second end 143 of the first transistor 144 is electrically connected to the first pixel electrode 131, and the second end 143 of the second transistor 145 is electrically connected to the second pixel electrode 132.
  • the control terminal 141 of the first transistor 144 and the control terminal 141 of the second transistor 145 are electrically connected to the same scan line 15 respectively;
  • the data line 16 includes a first data line 161 and a second data line 162, the first data line 161 is electrically connected to the first terminal 142 of the first transistor 144, and the second data line 162 is electrically connected to the first terminal 142 of the second transistor 145.
  • the arrangement of the first data line 161 and the second data line 162 can be the same or similar to the specific arrangement of the first data line 161 and the second data line 162 involved in the second embodiment above, and the same technical effect can be achieved;
  • the arrangement of the first common electrode 221 and the second common electrode 222 can be the same or similar to the arrangement of the first common electrode 221 and the second common electrode 222 involved in the fourth embodiment above, and the same technical effect can be achieved; the above details can be referred to the above specific introduction, and will not be repeated here.
  • the scan line 15 is used to push the scan signal to the driving transistor 14 in the first stage T1 and the second stage T2; in the first stage T1, the first data line 161 is used to push a frame of data signal to the first pixel electrode 131 through the first transistor 144, and the first common electrode 221 is used to push the first common voltage signal so that the first pixel unit 41 receives a frame of data signal; in the second stage T2, the second data line 162 is used to push the next frame of data signal to the second pixel electrode 132 through the second transistor 145, and the second common electrode 222 is used to push the second common voltage signal so that the second pixel unit 42 receives the next frame of data signal.
  • FIG. 18 is a timing diagram of the driving signal of the display module provided by the fifth embodiment of the present application. Specifically, the pixel unit 40 is still described as three rows and three columns. In each display period T, the scanning line 15 pushes Gout1, Gout2, and Gout3 row by row to turn on the driving transistor 14 row by row.
  • the first common electrode 221 pushes the first common voltage signal Com1
  • the first data line 161 pushes a frame of data signals Data1-1, Data2-1, and Data3-1 to the first pixel unit 41 column by column, so that the first pixel unit 41 displays a frame of image
  • the second common electrode 222 pushes the second common voltage signal Com2
  • the second data line 162 pushes the next frame of data signals Data1-2, Data2-2, and Data3-2 to the second pixel unit 42, so that the second pixel unit 42 displays the next frame of image.
  • the display module 100 can push two frames of image signals in one display cycle T.
  • the structure of the display module 100 can increase the image refresh rate to twice the conventional refresh rate f, greatly improving the image refresh rate, thereby effectively improving the image "stuttering" feeling of the display module 100a.
  • the time difference t between the first stage T1 and the second stage T2 can be specifically set according to actual needs.
  • FIG. 19 is a schematic diagram of a planar structure of a display module provided in the sixth embodiment of the present application.
  • the first end 142 of the first transistor 144 and the first end 142 of the second transistor 145 are respectively
  • the scanning line 15 includes a first scanning line 151 and a second scanning line 152, the first scanning line 151 is electrically connected to the control terminal 141 of the first transistor 144, and the second scanning line 152 is electrically connected to the control terminal 141 of the second transistor 145.
  • the first pixel unit 41 and the second pixel unit 42 are electrically connected to the same data line 16, respectively, and the first pixel unit 41 and the second pixel unit 42 are electrically connected to the first scanning line 151 and the second scanning line 152, respectively.
  • the arrangement of the first scanning line 151 and the second scanning line 152 can be the same or similar to the specific arrangement of the first scanning line 151 and the second scanning line 152 involved in the first embodiment above, and the same technical effect can be achieved;
  • the arrangement of the first common electrode 221 and the second common electrode 222 can be the same or similar to the arrangement of the first common electrode 221 and the second common electrode 222 involved in the fourth embodiment above, and the same technical effect can be achieved; the above details can refer to the above specific introduction, and will not be repeated here.
  • the first scan line 151 is used to push the scan signal to the first transistor 144
  • the data line 16 is used to push a frame of data signal to the first pixel electrode 131 through the first transistor 144
  • the first common electrode 221 is used to push the first common voltage signal so that the first pixel unit 41 receives a frame of data signal
  • the second scan line 152 is used to push the next frame of data signal to the second pixel electrode 132 through the second transistor 145
  • the second common electrode 222 is used to push the second common voltage signal so that the second pixel unit 42 receives the next frame of data signal.
  • FIG. 20 is a timing diagram of the driving signal of the display module provided in the sixth embodiment of the present application.
  • the first scanning line 151 pushes a frame of scanning signals Gout1-1, Gout2-1, Gout3-1 row by row, so that the first transistor 144 is turned on row by row, and at the same time in this stage period, the first common electrode 221 pushes the first common voltage signal Com1, and the data line 16 pushes a frame of data signals Data1-1, Data2-1, Data3-1 to the first pixel unit 41, so that the first pixel unit 41 displays a Frame image; after the first scan line 151 pushes for a period of time t, it enters the second stage T2, and the second scan line 152 pushes the next frame scan signals Gout1-2, Gout2-2, and Gout3-2 row by row, so that the second transistor 145 is turned on row by row.
  • the second common electrode 222 pushes the second common voltage signal Com2, and the second data line 162 pushes the next frame data signals Data1-2, Data2-2, and Data3-3 column by column to the second pixel unit 42, so that the second pixel unit 42 displays the next frame image.
  • the display module 100 can push two frames of image signals in one display cycle T.
  • the structure of the display module 100 can increase the image refresh rate to twice the conventional refresh rate f, greatly improving the image refresh rate, thereby effectively improving the image "stuttering" feeling of the display module 100a.
  • the time difference t between the first stage T1 and the second stage T2 can be specifically set according to actual needs.
  • FIG21 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • a display device is provided, and the display device includes a display module 100 and a control module 200 .
  • the display module 100 is used to display images.
  • the specific structure and function of the display module 100 are the same or similar to the display module 100 involved in the above embodiment, and can achieve the same technical effect. Please refer to the specific introduction above, which will not be repeated here.
  • control module 200 is electrically connected to the display module 100, and is used to provide control signals to the display module 100, such as clock control signals, power control signals, gate drive signals, source drive signals and other control signals required by the display module 100, so that in each display cycle, the display module 100 displays one frame of image in the first stage T1 and displays the next frame of image in the second stage T2, so that by partitioning the pixel unit 40, the display module 100 can display two frames of image in one display cycle T, thereby greatly improving the refresh rate of the display device and effectively improving the "stuttering" feeling that occurs when the display device displays images.
  • the display device may also include a backlight module, which is arranged relative to the display module 100 to provide a backlight source to the display module 100.
  • a backlight module is arranged relative to the display module 100 to provide a backlight source to the display module 100.
  • the backlight module is turned on to provide light source to the display module 100, so that the display device can be used in multiple scenarios and can adjust the backlight intensity in different light environments to provide fill light to the display module 100, so that the display device always maintains the best display effect, thereby improving user comfort.

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Abstract

一种显示模组(100)及显示装置，显示模组(100)包括像素单元(40)，像素单元(40)包括像素电极(13)、公共电极(22)和微囊结构(30)，像素电极(13)和公共电极(22)相对设置，微囊结构(30)设置于像素电极(13)与公共电极(22)之间；驱动晶体管(14)，包括控制端(141)、第一端(142)和第二端(143)，第二端(143)与像素电极(13)电连接，扫描线(15)与控制端(141)电连接，数据线(16)与第一端(142)电连接。像素单元(40)包括相邻的第一像素单元(41)和第二像素单元(42)；在每个显示周期(T)内，第一像素单元(41)用于在第一阶段(T1)接收数据线(16)推送的一帧数据信号，第二像素单元(42)用于在第二阶段(T2)接收数据线(16)推送的下一帧数据信号；第一阶段(T1)在第二阶段(T2)之前。显示模组(100)可有效提高刷新率，改善画面"卡顿"感。

Description

显示模组及显示装置
相关申请的交叉引用
本申请基于2023年6月16日提交的中国专利申请202310717687X主张其优先权，此处通过参照引入其全部的记载内容。
技术领域
本申请涉及显示技术领域，特别是涉及一种显示模组及显示装置。
背景技术
随着显示行业的发展，越来越多的人对显示面板的显示效果提出了更高的需求。其中，电子墨水(E-Ink)显示面板因其独特的反光显示模式，逐渐进入了大众视野，其在显示市场的规模越来越大。
通常，电子墨水显示面板通过电子墨水中的不同颜色的带电粒子在上下基板之间形成的电场中做电泳运动而显示图像。然而，这种电泳显示方式使得电子墨水的响应时间较长，约400毫秒左右，远不及液晶显示面板；由于响应速度慢，因此存在面板刷新率较低，导致用户在使用时可以明显感觉到“卡顿”。
发明内容
本申请提供一种显示模组及显示装置，旨在解决现有技术中显示装置存在刷新率低导致画面卡顿的问题。
为了解决上述技术问题，本申请提供的第一个技术方案为：提供一种显示模组。该显示模组包括：
像素单元，包括像素电极、公共电极和微囊结构，像素电极和公共电极相对设置，微囊结构设置于像素电极与公共电极之间，微囊结构包括带电粒子；
驱动晶体管，包括控制端、第一端和第二端，第二端与像素电极电连接，用于驱动像素单元；
扫描线，与控制端电连接，用于向像素单元提供扫描信号；
数据线，与第一端电连接，用于向像素电极提供数据信号；
其中，像素单元包括相邻的第一像素单元和第二像素单元；
在每个显示周期内，第一像素单元用于在第一阶段接收数据线推送的一帧数据信号，第二像素单元用于在第二阶段接收数据线推送的下一帧数据信号，且第一阶段在第二阶段之前。
其中，显示模组包括多个像素单元，多个像素单元呈矩阵排布；其中，在每个显示周期内，
在第一阶段，多行第一像素单元对应的驱动晶体管依序开启，以使多行第一像素单元接收数据线推送的一帧数据信号，显示一帧图像；
在第二阶段，多行第二像素单元对应的驱动晶体管依序开启，以使多行第二像素单元接收数据线推送的下一帧数据信号，显示下一帧图像。
其中，像素电极包括相邻的第一像素电极和第二像素电极，第一像素电极与公共电极以及微囊结构形成第一像素单元，第二像素电极与同一公共电极以及微囊结构形成第二像素单元；
驱动晶体管包括第一晶体管和第二晶体管，第一晶体管的第二端与第一像素电极电连接，第二晶体管的第二端与第二像素电极电连接。
其中，第一晶体管的第一端和第二晶体管的第一端分别与同一条数据线电连接；
扫描线包括第一扫描线和第二扫描线，第一扫描线与第一晶体管的控制端电连接，第二扫描线与第二晶体管的控制端电连接；
在每个显示周期内，第一扫描线用于在第一阶段向第一晶体管推送扫描信号，第二扫描线用于在第二阶段向第二晶体管推送扫描信号，以使第一像素单元在第一阶段接收数据线推送的一帧数据信号，第二像素单元在第二阶段接收数据线推送的下一帧数据信号。
其中，在每个显示周期内，
在第一阶段，每条第一扫描线逐行推送一帧扫描信号，以使第一晶体管逐行开启；每条数据线逐列推送一帧数据信号至第一像素单元，以显示一帧图像；
在第二阶段，每条第二扫描线逐行推送下一帧扫描信号，以使第二晶体管逐行开启；每条数据线逐列推送下一帧数据信号至第二像素单元，以显示下一帧图像。
其中，第一阶段结束后经过预设时长后进入第二阶段。
其中，第一晶体管的控制端和第二晶体管的控制端分别与同一条扫描线电连接；
数据线包括第一数据线和第二数据线，第一数据线与第一晶体管的第一端电连接，第二数据线与所第二晶体管的第一端电连接；
在每个显示周期内，在第一阶段，扫描线用于向第一晶体管推送扫描信号，第一数据线用于通过第一晶体管向第一像素单元推送一帧数据信号；在第二阶段，扫描线用于向第二晶体管推送扫描信号，第二数据线用于通过第二晶体管向第二像素单元推送下一帧数据信号。
其中，在每个显示周期内，
在第一阶段，每条扫描线逐行推送一帧扫描信号，以使驱动晶体管逐行开启；第一数据线向第一像素单元逐行推送一帧数据信号，以显示一帧图像；且在每一条第一数据线推送预设时间后，每条第二数据线向第二像素单元逐列预先推送下一帧数据信号；
在第二阶段，每条扫描线逐行推送下一帧扫描信号，第二像素单元接收下一帧数据信号，以显示下一帧图像。
其中，扫描线包括第一扫描线和第二扫描线，第一扫描线与第一晶体管的控制端电连接，第二扫描线与所第二晶体管的控制端电连接；
数据线包括第一数据线和第二数据线，第一数据线与第一晶体管的第一端电连接，第二数据线与所第二晶体管的第一端电连接；
在每个显示周期内，在第一阶段，第一扫描线用于向第一晶体管推送扫描信号，第一数据线用于通过第一晶体管向第一像素单元推送一帧数据信号；在第二阶段，第二扫描线用于向第二晶体管推送扫描信号，第二数据线用于通过第二晶体管向第二像素单元推送下一帧数据信号。
其中，在每个显示周期内，
在第一阶段，第一扫描线逐行推送一帧扫描信号，以使第一晶体管逐行开启；第一数据线向第一像素单元逐列推送一帧数据信号，以显示一帧图像；
在第二阶段，第二扫描线逐行推送下一帧扫描信号，以使第二晶体管逐行开启；第二数据线向第二像素单元逐列推送下一帧数据信号，以显示下一帧图像。
其中，公共电极包括相邻的第一公共电极和第二公共电极，像素电极与第一公共电极以及微囊结构形成第一像素单元，同一像素电极与第二公共电极以及微囊结构形成第二像素单元；
在每个显示周期内，扫描线在第一阶段和第二阶段向驱动晶体管推送扫描信号；在第一阶段，数据线通过第一端向像素电极推送一帧数据信号，第一公共电极用于推送第一公共电压信号，以使第一像素单元接收一帧数据信号；在第二阶段，数据线通过第一端向像素电极推送下一帧数据信号，第二公共电极用于推送第二公共电压信号，以使第二像素单元接收下一帧数据信号。
其中，在每个显示周期内，扫描线逐行推送扫描信号，以使驱动晶体管逐行开启，
在第一阶段，第一公共电极推送一帧公共电压信号；数据线逐列向像素电极推送一帧数据信号，以使第一像素单元中形成相应的电场，以显示一帧图像；
在数据线推送数据信号经过预设时长后，第二公共电极推送下一帧公共电压信号，并经过预设时长后，进入第二阶段；
在第二阶段，数据线向像素电极逐列推送下一帧数据信号，以使第二像素单元中形成相应的电场，以显示下一帧图像。
其中，像素电极包括相邻的第一像素电极和第二像素电极，公共电极包括相邻的第一公共电极和第二公共电极；第一像素电极与第一公共电极相对设置，且与微囊结构形成第一像素单元；第二像素电极与第二公共电极相对设置，且与微囊结构形成第二像素单元；
驱动晶体管包括第一晶体管和第二晶体管，第一晶体管的第二端与第一像素电极电连接，第二晶体管的第二端与第二像素电极电连接。
其中，第一晶体管的控制端和第二晶体管的控制端分别与同一条扫描线电连接；
数据线包括第一数据线和第二数据线，第一数据线与第一晶体管的第一端电连接，第二数 据线与所第二晶体管的第一端电连接；
在每个显示周期内，扫描线用于在第一阶段和第二阶段向驱动晶体管推送扫描信号；在第一阶段，第一数据线用于通过第一晶体管向第一像素电极推送一帧数据信号，第一公共电极用于推送第一公共电压信号，以使第一像素单元接收一帧数据信号；在第二阶段，第二数据线用于通过第二晶体管向第二像素电极推送下一帧数据信号，第二公共电极用于推送第二公共电压信号，以使第二像素单元接收下一帧数据信号。
其中，在每个显示周期内，扫描线逐行推送扫描信号，以使驱动晶体管逐行开启，
在第一阶段，第一公共电极推送第一公共电压信号，第一数据线逐列向第一像素单元推送一帧数据信号，以显示一帧图像；
在第二阶段，第二公共电极推送第二公共电压信号，第二数据线逐列向第二像素单元推送下一帧数据信号，以显示下一帧图像。
其中，第一晶体管的第一端和第二晶体管的第一端分别与同一条数据线电连接；
扫描线包括第一扫描线和第二扫描线，第一扫描线与第一晶体管的控制端电连接，第二扫描线与所第二晶体管的控制端电连接；
在每个显示周期内，在第一阶段，第一扫描线用于向第一晶体管推送扫描信号，数据线用于通过第一晶体管向第一像素电极推送一帧数据信号，第一公共电极同于推送第一公共电压信号，以使第一像素单元接收一帧数据信号；在第二阶段，第二扫描线用于通过第二晶体管向第二像素电极推送下一帧数据信号，第二公共电极用于推送所第二公共电压信号，以使第二像素单元接收下一帧数据信号。
其中，在每个显示周期内，
在第一阶段，第一扫描线逐行推送一帧扫描信号，以使第一晶体管逐行开启；第一公共电极推送第一公共电压信号，数据线向第一像素单元推送一帧数据信号，以显示一帧图像；
在第二阶段，第二扫描线逐行推送下一帧扫描信号，以使第二晶体管逐行开启；第二公共电极推送第二公共电压信号，数据线向第二像素单元逐列推送下一帧数据信号，以显示下一帧图像。
其中，微囊结构包括电泳介质和悬浮于电泳介质中的正电粒子和负电粒子；正电粒子和负电粒子为不同颜色的带电粒子。
为了解决上述技术问题，本申请提供的第二个技术方案为：提供一种显示装置。显示装置包括：
显示模组，用于显示图像，显示模组为如上述技术方案所涉及的显示模组；
控制模块，与显示模组电连接，用于向显示模组提供控制信号，以在每个显示周期内，使显示模组在第一阶段显示一帧图像，在第二阶段显示下一帧图像。
本申请的有益效果：区别于现有技术，本申请提供了一种显示模组及显示装置，该显示模组包括多个像素单元，每个像素单元包括相邻的第一像素单元和第二像素单元，以用于显示图像；并通过在每个显示周期内，使第一像素单元在第一阶段接收数据线推送的一帧数据信号，以显示一帧画面，使第二像素单元在第二阶段接收数据线推送的下一帧数据信号，以显示下一帧画面，使得该显示模组可在一个显示周期内显示两帧画面，可使该显示模组的刷新率提高一倍，从而克服显示模组响应速度较慢导致的刷新率较低的问题，有效提高了该显示模组的刷新率，改善画面的“卡顿”感。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出任何创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是现有技术一实施例提供的显示模组的驱动基板的结构示意图；
图2a是图1实施例提供的像素单元在不施加电场时的结构示意图；
图2b是图1实施例提供的像素单元在显示黑色时的结构示意图；
图2c是图1实施例提供的像素单元在显示白色时的结构示意图；
图3是本申请第一实施例提供的显示模组的结构示意图；
图4是本申请第一实施例提供的一驱动基板的结构示意图；
图5是本申请第一实施例提供的另一驱动基板的结构示意图；
图6是本申请第一实施例提供的显示模组的驱动信号时序图；
图7是本申请第二实施例提供的显示模组的结构示意图；
图8是本申请第二实施例提供的一驱动基板的结构示意图；
图9是本申请第二实施例提供的另一驱动基板的结构示意图；
图10是本申请第二实施例提供的显示模组的驱动信号时序图；
图11是本申请第三实施例提供的显示模组的结构示意图；
图12是本申请第三实施例提供的一驱动基板的结构示意图；
图13是本申请第三实施例提供的显示模组的驱动信号时序图；
图14是本申请第四实施例提供的一显示模组的平面结构示意图；
图15是本申请第四实施例提供的另一显示模组的平面结构示意图；
图16是本申请第四实施例提供的显示模组的驱动信号时序图；
图17是本申请第五实施例提供的显示模组的平面结构示意图；
图18是本申请第五实施例提供的显示模组的驱动信号时序图；
图19是本申请第六实施例提供的显示模组的平面结构示意图；
图20是本申请第六实施例提供的显示模组的驱动信号时序图；
图21是本申请一实施例提供的显示装置的结构示意图。
附图标记：
100a、100-显示模组；10a、10-驱动基板；11a、11-衬底；12a、12-驱动电路层；13a、13-
像素电极；131-第一像素电极；132-第二像素电极；14a、14-驱动晶体管；141a、141-控制端；142a、142-第一端；143a、143-第二端；144-第一晶体管；145-第二晶体管；15a、15-扫描线；151-第一扫描线；152-第二扫描线；16a、16-数据线；161-第一数据线；162-第二数据线；20a、20-对设基板；21a、21-基板；22a、22-公共电极；221-第一公共电极；222-第二公共电极；30a、30-微囊结构；31a、31-正电粒子；32a、32-负电粒子；40a、40-像素单元；41-第一像素单元；42-第二像素单元；200-控制模块；T-显示周期；T1-第一阶段；T2-第二阶段，X-第一方向，Y-第二方向。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”、“第三”的特征可以明示或者隐含地包括至少一个该特征。本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。本申请实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
下面结合附图和实施例对本申请进行详细的说明。
请参阅图1和图2a，图1是现有技术一实施例提供的显示模组的驱动基板的结构示意图，图2a是图1实施例提供的像素单元在不施加电场时的结构示意图。在现有技术中，电泳显示模组100a包括相对设置的驱动基板10a和对设基板20a以及设置于二者之间的微囊结构30a；其中，驱动基板10a包括衬底11a、驱动电路层12a和电极层，电极层包括多个呈阵列分布的像素电极13a；对设基板20a包括多个公共电极22a，其中，相对设置的像素电极13a和公共电极22a 与设置于二者之间的微囊结构30a形成像素单元40a。具体地，驱动电路层12a包括多条沿第一方向X延伸的扫描线15、多条沿第二方向Y延伸的数据线16a以及多个驱动晶体管14a，驱动晶体管14a与像素单元40a一一对应，每条扫描线15与对应行的驱动晶体管14a的控制端141a电连接，每条数据线16a与对应列的驱动晶体管14a的第一端142a电连接，驱动晶体管14a的第二端143a与对应的像素电极13a电连接。其中，第一方向X与第二方向Y相交，本申请实施例中以第一方向X与第二方向Y垂直为例进行说明。
如图2a所示，设置于像素电极13a与公共电极22a之间的微囊结构30a包括白色的正电粒子31a和黑色的负电粒子32a；当像素电极13a和公共电极22a不施加电位时，正电粒子31a和负电粒子32a随机分布于微囊结构30a中，不显示图像。
请参阅图2b，图2b是图1实施例提供的像素单元在显示黑色时的结构示意图。当像素电极13a施加负电位，公共电极22a施加正电位时，即公共电极22a的电位高于像素电极13a的电位，形成从公共电极22a到像素电极13a方向的电场时，正电粒子31a以“电泳”方式向像素电极13a移动，负电粒子32a向公共电极22a移动，此时像素单元40a显示黑色。
请参阅图2c，图2c是图1实施例提供的像素单元在显示白色时的结构示意图。当像素电极13a施加正电位，公共电极22a施加负电位时，即像素电极13a的电位高于公共电极22a的电位，形成从像素电极13a到公共电极22a方向的电场时，负电粒子32a以“电泳”方式相像素电极13a移动，正电粒子31a向公共电极22a移动，此时像素单元40a显示白色。
在上述显示模式中，正电粒子31a和负电粒子32a是以“电泳”方式移动的，因此其响应速度通常在500ms以上，使得显示模组100a的刷新率小于10Hz，动态显示效果较差，容易出现画面“卡顿”感。
本申请实施例提供的显示模组100(见图3)，通过使每个像素单元40包括相邻的第一像素单元41和第二像素单元42，以用于显示图像；并在每个显示周期T内，使第一像素单元41在第一阶段T1接收数据线16推送的一帧数据信号，以显示一帧画面，使第二像素单元42在第二阶段T2接收数据线16推送的下一帧数据信号，以显示下一帧画面，使得该显示模组100可在一个显示周期T内显示两帧画面，可使该显示模组100的刷新率提高一倍，从而克服上述显示模组100a响应速度较慢导致的刷新率较低的问题，有效提高了显示模组100a的刷新率，改善画面的“卡顿”感。
下面结合附图和实施例对本申请进行详细地说明。
请参阅图3-5，图3是本申请第一实施例提供的显示模组的结构示意图，图4是本申请第一实施例提供的一驱动基板的结构示意图，图5是本申请第一实施例提供的另一驱动基板的结构示意图。在本实施例中，提供一种显示模组100，该显示模组100包括像素单元40、驱动晶体管14、扫描线15和数据线16。其中，多个像素单元40呈阵列排布，每个像素单元40包括像素电极13、公共电极22和微囊结构30，像素电极13与公共电极22相对设置，微囊结构30设置于像素电极13与公共电极22之间。具体地，微囊结构30包括电泳介质和悬浮于电泳介质中的正电粒子31和负电粒子32，正电粒子31和负电粒子32为不同颜色的带电粒子，其具体颜色可根据实际使用需要进行设置，对此不作具体限制，在本申请实施例中，以正电粒子31和负电粒子32分别为白色粒子和黑色粒子为例进行说明。
其中，驱动晶体管14包括控制端141、第一端142和第二端143，第二端143与像素电极13电连接，用于驱动像素电极13，以使像素电极13与公共电极22之间形成对应的电场，从而使带电粒子有规律地移动。其中，扫描线15与驱动晶体管14的控制端141电连接，以使扫描线15通过驱动晶体管14向像素单元40提供扫描信号；数据线16与驱动晶体管14的第一端142电连接，以使数据线16通过驱动集体管向像素单元40提供数据信号，使得像素单元40显示相应颜色。具体地，控制端141为驱动晶体管14的栅极，第一端142为驱动晶体管14的源极，第二端143为驱动晶体管14的漏极，驱动晶体管14具体可为薄膜晶体管TFT，具体类型可根据实际需要选择，对此不做具体限制。
在本实施例中，像素单元40包括第一像素单元41和第二像素单元42，显示模组100显示图像时，在每个显示周期T内，第一像素单元41用于在第一阶段T1显示一帧画面，第二像素单元42用于在第二阶段T2显示下一帧画面，使得该显示模组100可在一个显示周期T内显示两帧画面，可使该显示模组100的刷新率提高一倍，从而克服显示模组100a响应速度较慢导致的刷新率较低的问题，有效提高了该显示模组100的刷新率，改善画面的“卡顿”感。
具体地，在每个像素单元40中，像素电极13包括相邻的第一像素电极131和第二像素电 极132，第一像素电极131与公共电极22以及微囊结构30形成第一像素单元41，第二像素电极132与同一公共电极22以及微囊结构30形成第二像素单元42。驱动晶体管14包括第一晶体管144和第二晶体管145，第一晶体管144的第二端143与第一像素电极131电连接，第二晶体管145的第二端143与第二像素电极132电连接。具体地，数据线16设置于第一像素单元41与第二像素单元42之间，以缩短数据线16与第一像素单元41和/或第二像素单元42之间的走线长度，有利于走线布局；第一晶体管144的第一端142和第二晶体管145的第一端142分别与该数据线16电连接，以使数据线16分别向第一像素单元41和第二像素单元42提供数据信号。
具体地，扫描线15包括第一扫描线151和第二扫描线152，第一扫描线151与第一晶体管144的控制端141电连接，以用于控制第一像素单元41在何时能够接收数据信号；第二扫描线152与第二晶体管145的控制端141电连接，以用于控制第二像素单元42何时能够接收数据信号。具体地，如图4和图5所示，第一扫描线151和第二扫描线152可设置于像素单元40的同一侧，或分别设置于像素单元40的相对两侧，具体可根据实际需求进行设置，对此不作具体限定。
请参阅图6，图6是本申请第一实施例提供的显示模组的驱动信号时序图。在本实施例中，提供一种显示模组的驱动方法，以像素单元40为三行三列为例进行说明，在每个显示周期T内，在第一阶段T1，每条第一扫描线151逐行推送一帧扫描信号Gout1-1、Gout2-1、Gout3-1，以使第一晶体管144逐行开启，同时，每条数据线16在对应的第一阶段T1时期内逐列推送一帧数据信号Data1-1、Data2-1、Data3-1至第一像素单元41，以使第一像素单元41显示一帧图像；在第一扫描线151推送一段时间t后，进入第二阶段T2，每条第二扫描线152逐行推送下一帧扫描信号Gout1-2、Gout2-2、Gout3-2，以使第二晶体管145逐行开启，同时，每条数据线16在对应的第二阶段T2时期内逐列推送下一帧数据信号Data1-2、Data2-2、Data3-3至第二像素单元42，以使第二像素单元42显示下一帧图像。
通过上述驱动方式，使得该显示模组100可在一个显示周期T内推送两帧图像信号，相比于常规的电泳显示模组100a的刷新率f，该显示模组100的结构可将图像刷新率提高至常规刷新率f的两倍，大大提高了图像刷新率，从而有效改善显示模组100a出现的图像“卡顿”感。在本实施例中，每个显示周期T中，第一阶段T1与第二阶段T2之间的时间差t具体可根据实际需要进行设置。
请参阅图7-9，图7是本申请第二实施例提供的显示模组的结构示意图，图8是本申请第二实施例提供的一驱动基板的结构示意图，图9是本申请第二实施例提供的另一驱动基板的结构示意图。与第一实施例不同的是，在本实施例中，同一行像素单元40中，第一晶体管144的控制端141和第二晶体管145的控制端141分别与对应的同一条扫描线15电连接，以用于控制该行像素单元40何时能够接收数据信号，即，一行像素单元40通过一条扫描线15驱动；具体地，数据线16包括第一数据线161和第二数据线162，第一数据线161与第一晶体管144的第一端142电连接，以用于向第一像素单元41提供数据信号，第二数据线162与所第二晶体管145的第一端142电连接，以用于向第二像素单元42提供数据信号。具体地，如图8和图9所示，在本实施例中，每个像素单元40中，第一数据线161和第二数据线162可设置于像素单元40的相对两侧，或者设置于第一像素单元41和第二像素单元42之间；当然，第一数据线161也可设置于第一像素单元41的外侧，第二扫描线152可设置于第一像素单元41与第二像素单元42之间；或者，第一数据线161设置于第一像素单元41与第二像素单元42之间，第二数据线162设置于第二像素单元42的外侧；具体可根据实际需要进行设置，对此不做具体限制。
具体地，在每个显示周期T内，在第一阶段T1，扫描线15用于向第一晶体管144推送扫描信号，第一数据线161用于通过第一晶体管144向第一像素单元41推送一帧数据信号；在第二阶段T2，扫描线15用于向第二晶体管145推送扫描信号，第二数据线162用于通过第二晶体管145向第二像素单元42推送下一帧数据信号。
请参阅图10，图10是本申请第二实施例提供的显示模组的驱动信号时序图。具体地，仍然以像素单元40为三行三列为例进行说明，在每个显示周期T内，在第一阶段T1，每条扫描线15逐行推送一帧扫描信号Gout1-1、Gout2-1、Gout3-1，以使驱动晶体管14逐行开启，同时，在该阶段时期内，第一数据线161向第一像素单元41逐列推送一帧数据信号Data1-1、Data2-1、Data3-1，以使第一像素单元41显示该帧图像；在每一条第一数据线161推送一段时间t1后，第二数据线162向第二像素单元42预先推送下一帧数据信号Data1-2、Data2-2、Data3-2，此时， 由于扫描线15还未推送下一帧扫描信号，因此第二像素单元42不显示下一帧图像；在第二数据线162推送一段时间t2后，进入第二阶段T2，扫描线15逐行推送下一帧扫描信号，第二像素单元42接收第二数据线162推动的下一帧数据信号Data1-2、Data2-2、Data3-2，以使第二像素单元42显示下一帧图像。
通过上述驱动方式，使得该显示模组100可在一个显示周期T内，可推送两帧图像信号，相比于常规的电泳显示模组100a的刷新率f，该显示模组100的结构可将图像刷新率提高至常规刷新率f的两倍，大大提高了图像刷新率，从而有效改善显示模组100a出现的图像“卡顿”感。在本实施例中，每个显示周期T中，第一阶段T1与第二阶段T2之间的时间差(t1+t2)具体可根据实际需要进行设置。
请参阅图11-12，图11是本申请第三实施例提供的显示模组的结构示意图，图12是本申请第三实施例提供的一驱动基板的结构示意图。与第一实施例和第二实施例不同的是，在本实施例中，扫描线15包括第一扫描线151和第二扫描线152，第一扫描线151与第一晶体管144的控制端141电连接，第二扫描线152与所第二晶体管145的控制端141电连接；数据线16包括第一数据线161和第二数据线162，第一数据线161与第一晶体管144的第一端142电连接，第二数据线162与所第二晶体管145的第一端142电连接。其中，第一扫描线151和第二扫描线152的具体设置方式与上述第一实施例中所涉及的第一扫描线151和第二扫描线152的具体设置方式相同或相似，且可实现相同的技术效果；第一数据线161和第二数据线162的具体设置方式与上述第二实施例中所涉及的第一数据线161和第二数据线162的具体设置方式相同或相似，且可实现相同的技术效果，具体可参考上文介绍，此处不再赘述。
具体地，在每个显示周期T内，在第一阶段T1，第一扫描线151用于向第一晶体管144推送扫描信号，第一数据线161用于通过第一晶体管144向第一像素单元41推送一帧数据信号；在第二阶段T2，第二扫描线152用于向第二晶体管145推送扫描信号，第二数据线162用于通过第二晶体管145向第二像素单元42推送下一帧数据信号。
请参阅图13，图13是本申请第三实施例提供的显示模组的驱动信号时序图。具体地，仍然以像素单元40为三行三列为例进行说明，在每个显示周期T内，在第一阶段T1，第一扫描线151逐行推送一帧扫描信号Gout1-1、Gout2-1、Gout3-1，以使第一晶体管144逐行开启，同时在该阶段时期内，第一数据线161向第一像素单元41逐列推送一帧数据信号Data1-1、Data2-1、Data3-1，以使第一像素单元41显示一帧图像；在第一扫描线151推送一段时间t后，进入第二阶段T2，第二扫描线152逐行推送下一帧扫描信号Gout1-2、Gout2-2、Gout3-2，以使第二晶体管145逐行开启，在该阶段时期内，第二二数据线16向第二像素单元42逐列推送下一帧数据信号Data1-2、Data2-2、Data3-2，以使第二像素单元42显示下一帧图像。
通过上述驱动方式，使得该显示模组100在一个显示周期T内，可推送两帧图像信号，相比于常规的电泳显示模组100a的刷新率f，该显示模组100的结构可将图像刷新率提高至常规刷新率f的两倍，大大提高了图像刷新率，从而有效改善显示模组100a出现的图像“卡顿”感。在本实施例中，每个显示周期T中，第一阶段T1与第二阶段T2之间的时间差t具体可根据实际需要进行设置。
请参阅图14-15，图14是本申请第四实施例提供的一显示模组的平面结构示意图，图15是本申请第四实施例提供的另一显示模组的平面结构示意图。在本实施例中，公共电极22包括相邻的第一公共电极221和第二公共电极222，第一公共电极221与第二公共电极222可沿平行于扫描线15的方向设置，或者也可沿平行于数据线16的方向设置，具体可根据实际需要进行设置。其中，像素电极13与第一公共电极221和微囊结构30形成第一像素单元41，同一像素电极13与第二公共电极222和微囊结构30形成第二像素单元42。即，在该像素单元40中，第一像素单元41和第二像素单元42共用像素电极13，与第一公共电极221相对的部分像素电极13和第一公共电极221以及二者之间的微囊结构30形成第一像素单元41，与第二公共电极222相对的部分像素电极13和第二公共电极222以及二者之间的微囊结构30形成第二像素单元42。
具体地，在每个显示周期T内，扫描线15在第一阶段T1和第二阶段T2向驱动晶体管14推送扫描信号；在第一阶段T1，数据线16通过第一端142向像素电极13推送一帧数据信号，第一公共电极221用于推送第一公共电压信号Com1，以使第一像素单元41接收一帧数据信号；在第二阶段T2，数据线16通过第一端142向像素电极13推送下一帧数据信号，第二公共电极222用于推送第二公共电压信号Com2，以使第二像素单元42接收下一帧数据信号。
请参阅图16，图16是本申请第四实施例提供的显示模组的驱动信号时序图。具体地，仍然 以像素单元40为三行三列为例进行说明，在每个显示周期T内，扫描线15逐行推送一帧扫描信号Gout1、Gout2、Gout3，同时，第一公共电极221推送一帧公共电压信号Com1，在Com1信号推送一段时间t1后，数据线16逐列向像素电极13逐列推送一帧数据信号Data1-1、Data2-1、Data3-1，以使第一像素单元41中形成相应的电场，即数据线16逐列向第一像素单元41推送一帧数据信号Data1-1、Data2-1、Data3-1，以使第一像素单元41显示一帧图像；在数据线16推送该帧数据信号一段时间t2后，第二公共电极222推送一帧公共电压信号Com2，此时数据线16还未推送下一帧数据信号，因此第二像素单元42中还未形成相应电场，不显示下一帧图像；在公共电压信号Com2推送一段时间后t3后，进入第二阶段T2，数据线16向像素电极13逐列推送下一帧数据信号Data1-2、Data2-2、Data3-2，以使第二像素单元42中形成相应的电场，即数据线16逐列向第二像素单元42推送下一帧数据信号Data1-2、Data2-2、Data3-2，以使第二像素单元42显示下一帧图像。
通过上述驱动方式，使得该显示模组100在一个显示周期T内，可推送两帧图像信号，相比于常规的电泳显示模组100a的刷新率f，该显示模组100的结构可将图像刷新率提高至常规刷新率f的两倍，大大提高了图像刷新率，从而有效改善显示模组100a出现的图像“卡顿”感。在本实施例中，每个显示周期T中，第一阶段T1与第二阶段T2之间的时间差(t1+t2+t3)具体可根据实际需要进行设置。
请参阅图17，图17是本申请第五实施例提供的显示模组的平面结构示意图。在本实施例中，像素电极13包括相邻的第一像素电极131和第二像素电极132，公共电极22包括相邻的第一公共电极221和第二公共电极222；第一像素电极131与第一公共电极221相对设置，且与微囊结构30形成第一像素单元41；第二像素电极132与第二公共电极222相对设置，且与微囊结构30形成第二像素单元42；驱动晶体管14包括第一晶体管144和第二晶体管145，第一晶体管144的第二端143与第一像素电极131电连接，第二晶体管145的第二端143与第二像素电极132电连接。第一晶体管144的控制端141和第二晶体管145的控制端141分别与同一条扫描线15电连接；数据线16包括第一数据线161和第二数据线162，第一数据线161与第一晶体管144的第一端142电连接，第二数据线162与所第二晶体管145的第一端142电连接。具体地，第一数据线161和第二数据线162的设置方式可与上文第二实施例中所涉及的第一数据线161和第二数据线162的具体设置方式相同或相似，且可实现相同的技术效果；第一公共电极221和第二公共电极222的设置方式可与上文第四实施例中所涉及的第一公共电极221和第二公共电极222的设置方式相同或相似，且可实现相同的技术效果；以上具体可参考上文具体介绍，此处不再赘述。
具体地，在每个显示周期T内，扫描线15用于在第一阶段T1和第二阶段T2向驱动晶体管14推送扫描信号；在第一阶段T1，第一数据线161用于通过第一晶体管144向第一像素电极131推送一帧数据信号，第一公共电极221用于推送第一公共电压信号，以使第一像素单元41接收一帧数据信号；在第二阶段T2，第二数据线162用于通过第二晶体管145向第二像素电极132推送下一帧数据信号，第二公共电极222用于推送第二公共电压信号，以使第二像素单元42接收下一帧数据信号。
请参阅图18，图18是本申请第五实施例提供的显示模组的驱动信号时序图。具体地，仍然以像素单元40为三行三列为例进行说明，在每个显示周期T内，扫描线15逐行推送Gout1、Gout2、Gout3，以使驱动晶体管14逐行开启，在第一阶段T1内，第一公共电极221推送第一公共电压信号Com1，同时，第一数据线161逐列向第一像素单元41推送一帧数据信号Data1-1、Data2-1、Data3-1，以使第一像素单元41显示一帧图像；在第一数据线161推送该帧数据信号一段时间t后，进入第二阶段T2，第二公共电极222推送第二公共电压信号Com2,同时，第二数据线162向第二像素单元42推送下一帧数据信号Data1-2、Data2-2、Data3-2，以使第二像素单元42显示下一帧图像。
通过上述驱动方式，使得该显示模组100在一个显示周期T内，可推送两帧图像信号，相比于常规的电泳显示模组100a的刷新率f，该显示模组100的结构可将图像刷新率提高至常规刷新率f的两倍，大大提高了图像刷新率，从而有效改善显示模组100a出现的图像“卡顿”感。在本实施例中，每个显示周期T中，第一阶段T1与第二阶段T2之间的时间差t具体可根据实际需要进行设置。
请参阅图19，图19是本申请第六实施例提供的显示模组的平面结构示意图。与第五实施例不同的是，在本实施例中，第一晶体管144的第一端142和第二晶体管145的第一端142分别 与同一条数据线16电连接；扫描线15包括第一扫描线151和第二扫描线152，第一扫描线151与第一晶体管144的控制端141电连接，第二扫描线152与所第二晶体管145的控制端141电连接。即，在本实施例中，第一像素单元41和第二像素单元42分别与同一条数据线16电连接，第一像素单元41和第二像素单元42分别与第一扫描线151和第二扫描线152电连接。其中，第一扫描线151和第二扫描线152的设置方式可与上文第一实施例中所涉及的第一扫描线151和第二扫描线152的具体设置方式相同或相似，且可实现相同的技术效果；第一公共电极221和第二公共电极222的设置方式可与上文第四实施例中所涉及的第一公共电极221和第二公共电极222的设置方式相同或相似，且可实现相同的技术效果；以上具体可参考上文具体介绍，此处不再赘述。
具体地，在每个显示周期T内，在第一阶段T1，第一扫描线151用于向第一晶体管144推送扫描信号，数据线16用于通过第一晶体管144向第一像素电极131推送一帧数据信号，第一公共电极221同于推送第一公共电压信号，以使第一像素单元41接收一帧数据信号；在第二阶段T2，第二扫描线152用于通过第二晶体管145向第二像素电极132推送下一帧数据信号，第二公共电极222用于推送所第二公共电压信号，以使第二像素单元42接收下一帧数据信号。
请参阅图20，图20是本申请第六实施例提供的显示模组的驱动信号时序图。具体地，仍然以像素单元40为三行三列为例进行说明，在每个显示周期T内，在第一阶段T1，第一扫描线151逐行推送一帧扫描信号Gout1-1、Gout2-1、Gout3-1，以使第一晶体管144逐行开启，同时在该阶段时期内，第一公共电极221推送第一公共电压信号Com1，数据线16向第一像素单元41推送一帧数据信号Data1-1、Data2-1、Data3-1，以使第一像素单元41显示一帧图像；在第一扫描线151推送一段时间t后，进入第二阶段T2，第二扫描线152逐行推送下一帧扫描信号Gout1-2、Gout2-2、Gout3-2，以使第二晶体管145逐行开启，同时在该阶段时期内，第二公共电极222推送第二公共电压信号Com2，第二数据线162向第二像素单元42逐列推送下一帧数据信号Data1-2、Data2-2、Data3-3，以使第二像素单元42显示下一帧图像。
通过上述驱动方式，使得该显示模组100在一个显示周期T内，可推送两帧图像信号，相比于常规的电泳显示模组100a的刷新率f，该显示模组100的结构可将图像刷新率提高至常规刷新率f的两倍，大大提高了图像刷新率，从而有效改善显示模组100a出现的图像“卡顿”感。在本实施例中，每个显示周期T中，第一阶段T1与第二阶段T2之间的时间差t具体可根据实际需要进行设置。
请参阅图21，图21是本申请一实施例提供的显示装置的结构示意图。在本实施例中，提供一种显示装置，该显示装置包括显示模组100和控制模块200。
其中，显示模组100用于显示图像，该显示模组100的具体结构和功能与上文实施例中所涉及的显示模组100相同或相似，且可实现相同的技术效果，具体可参考上文具体介绍，此处不再赘述。
其中，控制模块200与显示模组100电连接，用于向显示模组100提供控制信号，例如时钟控制信号、电源控制信号、栅极驱动信号、源极驱动信号等显示模组100所需的控制信号，以在每个显示周期内，使该显示模组100在第一阶段T1显示一帧图像，在第二阶段T2显示下一帧图像，从而通过对像素单元40进行分区控制使得该显示模组100能够实现在一个显示周期T内显示两帧图像，从而大大提高该显示装置的刷新率，有效改善显示装置显示图像时出现的“卡顿”感。
在具体实施例中，该显示装置还可包括背光模组，背光模组与显示模组100相对设置，以用于向显示模组100提供背光源，以在该显示装置所处环境光线较暗时，开启背光模组，从而向显示模组100提供光源，使得该显示装置可在多场景下使用，且能够在不同的光线环境下，调节背光强度，对显示模组100进行补光，使显示装置始终保持最佳显示效果，从而提高用户使用舒适度。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (19)

  1. 一种显示模组，包括：
    像素单元，包括像素电极、公共电极和微囊结构，所述像素电极和所述公共电极相对设置，所述微囊结构设置于所述像素电极与所述公共电极之间，所述微囊结构包括带电粒子；
    驱动晶体管，包括控制端、第一端和第二端，所述第二端与所述像素电极电连接，用于驱动所述像素单元；
    扫描线，与所述控制端电连接，用于向所述像素单元提供扫描信号；
    数据线，与所述第一端电连接，用于向所述像素电极提供数据信号；
    其中，所述像素单元包括相邻的第一像素单元和第二像素单元；
    在每个显示周期内，所述第一像素单元用于在第一阶段接收所述数据线推送的一帧所述数据信号，所述第二像素单元用于在第二阶段接收所述数据线推送的下一帧所述数据信号，且所述第一阶段在所述第二阶段之前。
  2. 根据权利要求1所述的显示模组，其中，所述显示模组包括多个像素单元，多个所述像素单元呈矩阵排布；其中，在每个所述显示周期内，
    在所述第一阶段，多行所述第一像素单元对应的所述驱动晶体管依序开启，以使多行所述第一像素单元接收所述数据线推送的一帧所述数据信号，显示一帧图像；
    在所述第二阶段，多行所述第二像素单元对应的所述驱动晶体管依序开启，以使多行所述第二像素单元接收所述数据线推送的下一帧所述数据信号，显示下一帧图像。
  3. 根据权利要求2所述的显示模组，其中，所述像素电极包括相邻的第一像素电极和第二像素电极，所述第一像素电极与所述公共电极以及所述微囊结构形成所述第一像素单元，所述第二像素电极与同一所述公共电极以及所述微囊结构形成所述第二像素单元；
    所述驱动晶体管包括第一晶体管和第二晶体管，所述第一晶体管的所述第二端与所述第一像素电极电连接，所述第二晶体管的所述第二端与所述第二像素电极电连接。
  4. 根据权利要求3所述的显示模组，其中，所述第一晶体管的所述第一端和所述第二晶体管的所述第一端分别与同一条所述数据线电连接；
    所述扫描线包括第一扫描线和第二扫描线，所述第一扫描线与所述第一晶体管的所述控制端电连接，所述第二扫描线与所第二晶体管的所述控制端电连接；
    在每个所述显示周期内，所述第一扫描线用于在所述第一阶段向所述第一晶体管推送所述扫描信号，所述第二扫描线用于在所述第二阶段向所述第二晶体管推送所述扫描信号，以使所述第一像素单元在所述第一阶段接收所述数据线推送的一帧所述数据信号，所述第二像素单元在所述第二阶段接收所述数据线推送的下一帧所述数据信号。
  5. 根据权利要求4所述的显示模组，其中，在每个所述显示周期内，
    在所述第一阶段，每条所述第一扫描线逐行推送一帧所述扫描信号，以使所述第一晶体管逐行开启；每条所述数据线逐列推送一帧所述数据信号至所述第一像素单元，以显示一帧图像；
    在所述第二阶段，每条所述第二扫描线逐行推送下一帧所述扫描信号，以使所述第二晶体管逐行开启；每条所述数据线逐列推送下一帧所述数据信号至所述第二像素单元，以显示下一帧图像。
  6. 根据权利要求5所述的显示模组，其中，所述第一阶段结束后经过预设时长后进入所述第二阶段。
  7. 根据权利要求3所述的显示模组，其中，所述第一晶体管的所述控制端和所述第二晶体管的所述控制端分别与同一条所述扫描线电连接；
    所述数据线包括第一数据线和第二数据线，所述第一数据线与所述第一晶体管的所述第一端电连接，所述第二数据线与所述第二晶体管的所述第一端电连接；
    在每个所述显示周期内，在所述第一阶段，所述扫描线用于向所述第一晶体管推送所述扫描信号，所述第一数据线用于通过所述第一晶体管向所述第一像素单元推送一帧所述数据信号；在所述第二阶段，所述扫描线用于向所述第二晶体管推送所述扫描信号，所述第二数据线用于通过所述第二晶体管向所述第二像素单元推送下一帧所述数据信号。
  8. 根据权利要求7所述的显示模组，其中，在每个所述显示周期内，
    在所述第一阶段，每条所述扫描线逐行推送一帧所述扫描信号，以使所述驱动晶体管逐行开启；所述第一数据线向所述第一像素单元逐行推送一帧所述数据信号，以显示一帧图像；且在每一条所述第一数据线推送预设时间后，每条所述第二数据线向所述第二像素单元逐列预先推送下一帧所述数据信号；
    在所述第二阶段，每条所述扫描线逐行推送下一帧所述扫描信号，所述第二像素单元接收所述下一帧数据信号，以显示下一帧图像。
  9. 根据权利要求3所述的显示模组，其中，所述扫描线包括第一扫描线和第二扫描线，所述第一扫描线与所述第一晶体管的所述控制端电连接，所述第二扫描线与所第二晶体管的所述控制端电连接；
    所述数据线包括第一数据线和第二数据线，所述第一数据线与所述第一晶体管的所述第一端电连接，所述第二数据线与所第二晶体管的所述第一端电连接；
    在每个所述显示周期内，在所述第一阶段，所述第一扫描线用于向所述第一晶体管推送所述扫描信号，所述第一数据线用于通过所述第一晶体管向所述第一像素单元推送一帧所述数据信号；在所述第二阶段，所述第二扫描线用于向所述第二晶体管推送所述扫描信号，所述第二数据线用于通过所述第二晶体管向所述第二像素单元推送下一帧所述数据信号。
  10. 根据权利要求9所述的显示模组，其中，在每个所述显示周期内，
    在所述第一阶段，所述第一扫描线逐行推送一帧所述扫描信号，以使所述第一晶体管逐行开启；所述第一数据线向所述第一像素单元逐列推送一帧所述数据信号，以显示一帧图像；
    在所述第二阶段，所述第二扫描线逐行推送下一帧所述扫描信号，以使所述第二晶体管逐行开启；所述第二数据线向所述第二像素单元逐列推送下一帧所述数据信号，以显示下一帧图像。
  11. 根据权利要求2所述的显示模组，其中，所述公共电极包括相邻的第一公共电极和第二公共电极，所述像素电极与所述第一公共电极以及所述微囊结构形成所述第一像素单元，同一所述像素电极与所述第二公共电极以及所述微囊结构形成所述第二像素单元；
    在每个所述显示周期内，所述扫描线在所述第一阶段和所述第二阶段向所述驱动晶体管推送所述扫描信号；在第一阶段，所述数据线通过所述第一端向所述像素电极推送一帧所述数据信号，所述第一公共电极用于推送第一公共电压信号，以使所述第一像素单元接收一帧所述数据信号；在第二阶段，所述数据线通过所述第一端向所述像素电极推送下一帧所述数据信号，所述第二公共电极用于推送第二公共电压信号，以使所述第二像素单元接收下一帧所述数据信号。
  12. 根据权利要求11所述的显示模组，其中，在每个所述显示周期内，所述扫描线逐行推送所述扫描信号，以使所述驱动晶体管逐行开启，
    在所述第一阶段，所述第一公共电极推送一帧所述公共电压信号；所述数据线逐列向所述像素电极推送一帧所述数据信号，以使所述第一像素单元中形成相应的电场，以显示一帧图像；
    在所述数据线推送所述数据信号经过预设时长后，所述第二公共电极推送下一帧所述公共电压信号，并经过预设时长后，进入所述第二阶段；
    在所述第二阶段，所述数据线向所述像素电极逐列推送下一帧所述数据信号，以使所述第二像素单元中形成相应的电场，以显示下一帧图像。
  13. 根据权利要求2所述的显示模组，其中，所述像素电极包括相邻的第一像素电极和第二像素电极，所述公共电极包括相邻的第一公共电极和第二公共电极；所述第一像素电极与所述第一公共电极相对设置，且与所述微囊结构形成所述第一像素单元；所述第二像素电极与所述第二公共电极相对设置，且与所述微囊结构形成所述第二像素单元；
    所述驱动晶体管包括第一晶体管和第二晶体管，所述第一晶体管的所述第二端与所述第一像素电极电连接，所述第二晶体管的所述第二端与所述第二像素电极电连接。
  14. 根据权利要求13所述的显示模组，其中，所述第一晶体管的所述控制端和所述第二晶体管的所述控制端分别与同一条所述扫描线电连接；
    所述数据线包括第一数据线和第二数据线，所述第一数据线与所述第一晶体管的所述第一端电连接，所述第二数据线与所第二晶体管的所述第一端电连接；
    在每个所述显示周期内，所述扫描线用于在所述第一阶段和所述第二阶段向所述驱动晶 体管推送所述扫描信号；在所述第一阶段，所述第一数据线用于通过所述第一晶体管向所述第一像素电极推送一帧所述数据信号，所述第一公共电极用于推送第一公共电压信号，以使所述第一像素单元接收一帧所述数据信号；在所述第二阶段，所述第二数据线用于通过所述第二晶体管向所述第二像素电极推送下一帧所述数据信号，所述第二公共电极用于推送第二公共电压信号，以使所述第二像素单元接收下一帧所述数据信号。
  15. 根据权利要求14所述的显示模组，其中，在每个所述显示周期内，所述扫描线逐行推送所述扫描信号，以使所述驱动晶体管逐行开启，
    在所述第一阶段，所述第一公共电极推送所述第一公共电压信号，所述第一数据线逐列向所述第一像素单元推送一帧所述数据信号，以显示一帧图像；
    在所述第二阶段，所述第二公共电极推送所述第二公共电压信号，所述第二数据线逐列向所述第二像素单元推送下一帧所述数据信号，以显示下一帧图像。
  16. 根据权利要求13所述的显示模组，其中，所述第一晶体管的所述第一端和所述第二晶体管的所述第一端分别与同一条所述数据线电连接；
    所述扫描线包括第一扫描线和第二扫描线，所述第一扫描线与所述第一晶体管的所述控制端电连接，所述第二扫描线与所第二晶体管的所述控制端电连接；
    在每个所述显示周期内，在第一阶段，所述第一扫描线用于向所述第一晶体管推送所述扫描信号，所述数据线用于通过所述第一晶体管向所述第一像素电极推送一帧所述数据信号，所述第一公共电极同于推送第一公共电压信号，以使所述第一像素单元接收一帧所述数据信号；在第二阶段，所述第二扫描线用于通过所述第二晶体管向所述第二像素电极推送下一帧所述数据信号，所述第二公共电极用于推送所第二公共电压信号，以使所述第二像素单元接收下一帧所述数据信号。
  17. 根据权利要求16所述的显示模组，其中，在每个所述显示周期内，
    在所述第一阶段，所述第一扫描线逐行推送一帧所述扫描信号，以使所述第一晶体管逐行开启；所述第一公共电极推送所述第一公共电压信号，所述数据线向所述第一像素单元推送一帧所述数据信号，以显示一帧图像；
    在所述第二阶段，所述第二扫描线逐行推送下一帧所述扫描信号，以使所述第二晶体管逐行开启；所述第二公共电极推送所述第二公共电压信号，所述数据线向所述第二像素单元逐列推送下一帧所述数据信号，以显示下一帧图像。
  18. 根据权利要求1所述的显示模组，其中，所述微囊结构包括电泳介质和悬浮于所述电泳介质中的正电粒子和负电粒子；所述正电粒子和所述负电粒子为不同颜色的所述带电粒子。
  19. 一种显示装置，其中，包括：
    显示模组，用于显示图像，所述显示模组为如权利要求1所述的显示模组；
    控制模块，与所述显示模组电连接，用于向所述显示模组提供控制信号，以在每个显示周期内，使所述显示模组在第一阶段显示一帧图像，在第二阶段显示下一帧图像。
PCT/CN2024/081491 2023-06-16 2024-03-13 显示模组及显示装置 Ceased WO2024255350A1 (zh)

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