WO2024255575A1 - 开关机模块 - Google Patents

开关机模块 Download PDF

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Publication number
WO2024255575A1
WO2024255575A1 PCT/CN2024/095434 CN2024095434W WO2024255575A1 WO 2024255575 A1 WO2024255575 A1 WO 2024255575A1 CN 2024095434 W CN2024095434 W CN 2024095434W WO 2024255575 A1 WO2024255575 A1 WO 2024255575A1
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WIPO (PCT)
Prior art keywords
power
unit
output
signal
condition
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Ceased
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PCT/CN2024/095434
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English (en)
French (fr)
Inventor
许锦龙
李瑞平
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Shanghai Xinlong Semiconductor Technology Co Ltd
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Shanghai Xinlong Semiconductor Technology Co Ltd
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Publication of WO2024255575A1 publication Critical patent/WO2024255575A1/zh
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention relates to the technical field of integrated circuits, and in particular to a switch module.
  • the prior art has the problem that low energy consumption in the shutdown state and high accuracy in responding to the startup signal cannot be achieved at the same time.
  • the object of the present invention is to provide a power on/off module to solve the problem in the prior art that low energy consumption in a shutdown state and high precision in responding to a power on signal cannot be taken into account at the same time.
  • the present invention provides a switch module applied to a total circuit, the total circuit includes the switch module and a functional module, the switch module includes a switch enable terminal, a starter module and an enable voltage comparison submodule.
  • the starter module is used to obtain external power supply.
  • the starter module determines with a first accuracy whether the signal of the power on/off enable terminal meets a first Power-on condition; if the first power-on condition is met, the external power supply is converted into an internal power supply to directly or indirectly drive the enable voltage comparison submodule and the functional module to be powered; if the first power-on condition is not met, the power supply of the enable voltage comparison submodule and the functional module is directly or indirectly cut off.
  • the enable voltage comparison submodule After the enable voltage comparison submodule is powered on, it determines with a second accuracy whether the signal at the power on/off enable terminal meets the second power-on condition; if it meets the second power-on condition, it outputs a control signal to drive at least a part of the functional modules to start up; if it does not meet the second power-on condition, it outputs a control signal to drive at least a part of the functional modules not to start up or to shut down.
  • the starter module When the first startup condition is not met, the starter module maintains its own judgment function with a first energy consumption; when the enable voltage comparison submodule is powered on, the enable voltage comparison submodule maintains its own judgment function with a second energy consumption.
  • the first accuracy is lower than the second accuracy, and the first energy consumption is lower than the second energy consumption.
  • the power on/off module further includes an output submodule.
  • the output submodule When the output submodule is powered, the output submodule obtains the output signal of the enable voltage comparison submodule, and outputs a power on/off signal after eliminating oscillation.
  • the starter module is also used to, if the first startup condition is met, convert the external power supply into an internal power supply to directly or indirectly drive the output submodule to be powered; if the first startup condition is not met, directly or indirectly cut off the power supply of the output submodule.
  • the starter module includes a first judgment unit and a power conversion unit.
  • the power conversion unit when the external power supply is connected, has at least the following working states: non-working state, semi-working state and normal working state; in the non-working state, the power conversion unit outputs electric energy with a power not exceeding the first energy consumption; in the semi-working state, the power conversion unit outputs electric energy with a power exceeding the first energy consumption, and the output electric energy at least does not meet the power demand and voltage demand of the functional module; in the normal working state, the electric energy output by the power conversion unit meets the power demand and voltage demand of the total circuit.
  • the first judgment unit judges with the first accuracy whether the signal of the power-on/off enable terminal meets the first power-on condition; if it does not meet the first power-on condition, the power conversion unit is driven to switch to the non-working state; if it meets the first power-on condition, the power conversion unit is driven to switch to the normal working state; if the result is other circumstances, the power conversion unit is driven to switch to the semi-working state.
  • the starter module further includes a second judgment unit, the second judgment unit
  • the source acquisition end is connected to the internal power output end of the power conversion unit; when the power conversion unit works in the semi-working state or the normal working state and the energy supply line between the power conversion unit and the second judgment unit is not disconnected or shielded, the second judgment unit can work normally.
  • the second judgment unit judges whether the signal of the power-on/off enable terminal meets the first power-on condition; if it does not meet the first power-on condition, the power conversion unit is driven to switch to the non-working state; if it meets the first power-on condition, the power conversion unit is driven to switch to the normal working state; in the event of power failure, the second judgment unit does not hinder the switching of the working state of the power conversion unit.
  • the power conversion unit switches to the normal working state.
  • the starter module further includes a shutdown unit, and an input end of the shutdown unit is connected to an output end of the switch module.
  • the closing unit shields the control effect of the second determination unit on the power conversion unit.
  • the enabling voltage comparison submodule includes a reference voltage generating unit and a third judging unit.
  • the reference voltage generating unit when the reference voltage generating unit is powered on, the reference voltage generating unit is used to output a reference voltage with the second precision, and the reference voltage is set based on the second power-on condition.
  • the third judgment unit When the third judgment unit is powered on, the third judgment unit directly or indirectly compares the output signal of the reference voltage generating unit and the signal of the power on/off enable terminal with the second accuracy, and when the size relationship changes, the signal output by the third judgment unit changes.
  • the reference voltage includes a first reference voltage and a second reference voltage
  • the reference voltage generating unit obtains a signal that can indicate whether the overall circuit is currently in a power-on state or a power-off state.
  • the reference voltage generating unit When the reference voltage generating unit is powered on, if the overall circuit is currently in a power-on state, the reference voltage generating unit outputs the second reference voltage; if the overall circuit is currently in a power-off state, the reference voltage generating unit outputs the first reference voltage.
  • the first reference voltage is greater than the second reference voltage.
  • the output submodule includes a charging and discharging unit and an output unit.
  • the charging and discharging unit is used to delay the output signal of the enabling voltage comparison submodule.
  • the output unit is inputted, and the oscillation of the output signal of the enabling voltage comparison submodule is filtered out.
  • the output unit determines its own output signal based at least on the output signal of the enable voltage comparison submodule.
  • the output unit determines its own output signal based on the output signal of the enable voltage comparison submodule and the signal of the power on/off enable terminal.
  • the output submodule further includes a blocking unit, which is used to block the influence of the charging and discharging unit on the internal components of the enabling voltage comparison submodule and/or to increase the driving capability of the output signal of the enabling voltage comparison submodule.
  • a blocking unit which is used to block the influence of the charging and discharging unit on the internal components of the enabling voltage comparison submodule and/or to increase the driving capability of the output signal of the enabling voltage comparison submodule.
  • the present invention provides a power on/off module, wherein the power on/off module includes a power on/off enable terminal, a starter module and an enable voltage comparison submodule.
  • the starter module determines whether the signal of the power on/off enable terminal meets the power on condition with lower accuracy and lower energy consumption, and supplies power to or stops supplying power to other modules according to a preset logic.
  • the enable voltage comparison submodule After the enable voltage comparison submodule is powered on, it determines whether the signal of the power on/off enable terminal meets the power on condition with higher accuracy, and starts or shuts down other modules according to a preset logic.
  • the standby energy consumption of the starter module is less than the minimum energy consumption for the enable voltage comparison submodule to work normally. With such a configuration, the working characteristics of each submodule are reasonably utilized, and both the shutdown energy consumption and the response accuracy are taken into account, thereby solving the problem that the two cannot be taken into account at the same time in the prior art.
  • FIG1 is a schematic structural diagram of a switch module according to an embodiment of the present invention.
  • FIG2 is a circuit diagram of a power on/off module according to an embodiment of the present invention.
  • FIG. 3 is a waveform diagram of an embodiment of the present invention.
  • 1-on/off enable terminal 2-start submodule; 3-enable voltage comparison submodule; 4-output submodule;
  • the singular forms “a”, “an” and “the” include plural objects, the term “or” is generally used to include “and/or”, the term “several” is generally used to include “at least one”, and the term “at least two” is generally used to include “two or more”.
  • the terms “first”, “second”, and “third” are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
  • the features defined as “first”, “second”, and “third” may explicitly or implicitly include one or at least two of the features, “one end” and “the other end” and “the proximal end” and “the distal end” generally refer to two corresponding parts, which include not only the endpoints, and the terms “installed”, “connected”, and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements.
  • an element disposed on another element generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements may be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element may be in any orientation such as inside, outside, above, below or on one side of another element, unless otherwise clearly indicated in the content.
  • the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
  • the core idea of the present invention is to provide a power on/off module to solve the problem in the prior art that low energy consumption in the shutdown state and high precision in responding to the power on signal cannot be taken into account at the same time.
  • the present invention provides a switch module, which is applied to a general circuit
  • the general circuit includes the switch module and a functional module (not shown)
  • the switch module includes a switch enable terminal 1, a starter module 2 and an enable voltage comparison submodule 3. Since the switch module can be applied to general circuits with different functions in different occasions, the specific functions of the functional modules are not limited.
  • the starter module 2 is used to obtain an external power source VCC.
  • the starter module 2 determines with a first accuracy whether the signal EN of the switch enable terminal 1 meets the first start-up condition; if the first start-up condition is met, the external power supply VCC is converted into the internal power supply VDD to directly or indirectly drive the enable voltage comparison submodule 3 and the functional module to be powered; if the first start-up condition is not met, the power supply of the enable voltage comparison submodule 3 and the functional module is directly or indirectly cut off.
  • Drive should be understood as the intention of the relevant module to output a control signal, but in actual situations, if the subsequent purpose is not achieved due to other reasons (such as the intervention of a higher-level control logic, or a circuit failure, etc.), it should also be understood as meeting the description, and “drive” in the subsequent content is understood in the same way.
  • the first power-on condition should be understood as the voltage of the enable terminal being greater than a certain value.
  • the first power-on condition is approximately >1.4V (specifically VD1+VT1, the relevant meanings of VD1 and VT1 are introduced later).
  • the enabling voltage comparison submodule 3 After the enabling voltage comparison submodule 3 is powered, it determines with a second precision whether the signal EN of the power on/off enabling terminal 1 meets the second power-on condition; if it meets the second power-on condition, it outputs a control signal to drive at least a part of the functional modules to power on; if it does not meet the second power-on condition, it outputs a control signal to drive at least a part of the functional modules not to power on or to power off.
  • the first precision is 0.1V level
  • the second precision is 0.01V level.
  • the second power-on condition is >1.6V.
  • the design purpose of the total circuit includes: when the total circuit is not started, if the signal EN is less than 1.6V, the total circuit is expected not to start, and if the signal EN is greater than 1.6V, the total circuit is expected to start.
  • the logic of how to shut down the total circuit will be described later.
  • any circuit cannot switch states exactly when the signal exceeds 1.6V. It often operates according to the following logic: when EN ⁇ a, the total circuit does not start; when EN > b, the total circuit starts; when a ⁇ EN ⁇ b, the state of the total circuit is uncontrollable and unpredictable.
  • the size of the interval [a, b] can also be called the response accuracy, and the smaller the size, the higher the accuracy.
  • this embodiment divides the power-on condition into the first power-on condition and the second power-on condition; the first power-on condition is set to >1.4V; the second power-on condition includes: if the total circuit is in an unpowered state, it will be powered on if >1.6V, otherwise it will not be powered on.
  • the first power-on condition and the first power-on condition may also be The two startup conditions are set to be the same.
  • the starter module 2 maintains its own judgment function with the first energy consumption; when the enable voltage comparison submodule is powered, the enable voltage comparison submodule 3 maintains its own judgment function with the second energy consumption.
  • the first energy consumption and the second energy consumption are measured by the current size. The first energy consumption is at the pA ⁇ nA level, and the second energy consumption is at the uA level.
  • the first accuracy is lower than the second accuracy, and the first energy consumption is lower than the second energy consumption.
  • this embodiment divides the startup of the total circuit into two independent processes, namely, each module is powered on and each module receives a startup signal.
  • the two processes are controlled by modules with different precision and energy consumption, and the internal power supply is turned off during the shutdown phase so that the energy consumption of the total circuit is limited to the startup module 2, thereby reducing energy consumption from a structural perspective.
  • the energy consumption is further reduced by reducing the precision of the startup module 2, but the overall precision of the switch module is guaranteed by the enable voltage comparison submodule 3; thus, low energy consumption in the shutdown state and high precision in responding to the startup signal are taken into account.
  • the power on/off module further includes an output submodule 4 .
  • the output submodule 4 obtains the output signal of the enable voltage comparison submodule 3 , and outputs a power on/off signal after eliminating oscillation.
  • the starter module 2 is also used to, if the first startup condition is met, convert the external power supply VCC into an internal power supply VDD to directly or indirectly drive the output submodule 4 to be powered; if the first startup condition is not met, directly or indirectly cut off the power supply of the output submodule 4.
  • Such a configuration optimizes the output signal and avoids oscillation caused when the signal stays at a critical value, thereby causing the problem of frequent switching of the total circuit.
  • FIG. 1 shows a preferred implementation method, where the starter module 2 includes a first judgment unit 21 and a power conversion unit 22 .
  • the power conversion unit 22 When connected to the external power source VCC, the power conversion unit 22 has at least the following features: The following working states: non-working state, semi-working state and normal working state; in the non-working state, the power conversion unit 22 outputs electric energy with a power not exceeding the first energy consumption; in the semi-working state, the power conversion unit 22 outputs electric energy with a power exceeding the first energy consumption, and the output electric energy at least does not meet the power demand and voltage demand of the functional module; in the normal working state, the electric energy output by the power conversion unit 22 meets the power demand and voltage demand of the total circuit.
  • the first judgment unit 21 judges with the first accuracy whether the signal EN of the power-on/off enable terminal 1 meets the first power-on condition; if it does not meet the first power-on condition, the power conversion unit 22 is driven to switch to the non-working state; if the result is between meeting the first power-on condition and not meeting the first power-on condition, the power conversion unit 22 is driven to switch to the semi-working state; if it meets the first power-on condition, the power conversion unit 22 is driven to switch to the normal working state.
  • the result between meeting the first power-on condition and not meeting the first power-on condition should be understood as the correctness of the current judgment result cannot be guaranteed due to the judgment accuracy of the first judgment unit 21.
  • This description also implies that the first judgment unit 21 is an analog circuit judgment logic.
  • the working state of the power conversion unit 22 includes the semi-working state, which is a technical feature set in conjunction with the first precision. If the working state of the power conversion unit 22 does not include the semi-working state, it means that additional logic and structure need to be set in the power conversion unit 22 to ensure that the working state of the power conversion unit 22 has the characteristics of a digital circuit. Therefore, the fact that the power conversion unit 22 includes the semi-working state does not mean that the starter module 2 must have the characteristics of low energy consumption, but it brings more options for the starter module 2 to achieve low energy consumption, so that the starter module 2 can choose a low energy consumption solution.
  • the starter module 2 also includes a second judgment unit 24, and the power acquisition end of the second judgment unit 24 is connected to the internal power output end 23 of the power conversion unit 22; when the power conversion unit 22 works in the semi-working state or the normal working state and the power supply line between the power conversion unit 22 and the second judgment unit 24 is not disconnected or shielded, the second judgment unit 24 can work normally. That is to say, the energy consumption of the normal operation of the second judgment unit 24 is higher than the first energy consumption, but lower than the energy consumption required for the normal operation of the total circuit.
  • the second determination unit 24 determines whether the signal EN of the power on/off enable terminal 2 meets the first power on condition; if it does not meet the first power on condition, The power conversion unit 22 is driven to switch to the non-working state; if the first power-on condition is met, the power conversion unit 22 is driven to switch to the normal working state; in the case of power failure, the second judgment unit 24 does not hinder the switching of the working state of the power conversion unit 22. In other words, the judgment accuracy of the second judgment unit 24 is actually higher than the first accuracy. When the judgment result of the first judgment unit 21 is between meeting the first power-on condition and not meeting the first power-on condition, the judgment result of the second judgment unit 24 is meeting the first power-on condition. The difference in the judgment results of the two is not contradictory, but is caused by different accuracy.
  • the external performance of the power component is: the working state of the power component does not include the semi-working state.
  • the starter module 2 further includes a shutdown unit 25, and the input end of the shutdown unit 25 is connected to the output end of the switch module.
  • the closing unit 25 shields the control effect of the second judgment unit 24 on the power conversion unit 22, and the working state of the power conversion unit 22 is switched to a semi-working state. This configuration can speed up the shutdown process.
  • FIG2 shows a preferred implementation method.
  • the starter module 2 includes a first diode D1, a second diode D2, a first enhancement-type PMOS tube PM1, a second enhancement-type PMOS tube PM2, a third enhancement-type PMOS tube PM3, a fourth enhancement-type PMOS tube PM4, a fifth enhancement-type PMOS tube PM5, a first enhancement-type NMOS tube NM1, a second enhancement-type NMOS tube NM2, a third enhancement-type NMOS tube NM3, a first depletion-type NMOS tube DNM1, a second depletion-type NMOS tube DNM2, a first voltage clamping circuit CLAMP1, a second voltage clamping circuit CLAMP2, a third voltage clamping circuit CLAMP3 and a Schmitt trigger SMT1.
  • the first voltage clamp circuit CLAMP1, the second voltage clamp circuit CLAMP2 and the third voltage clamp circuit CLAMP3 are configured to try to draw a small amount of current, typically 1uA or less. If the current does not reach the above value, the voltage across the circuit is very low, close to 0V. If the inflow current is greater than the above value, the voltage can be clamped. At the same time, when the inflow current changes greatly, the voltage at both ends does not change much (for example, when the inflow current is 1uA to 100uA, the voltage at both ends does not change more than 1V).
  • This circuit can be implemented in many ways. The simplest method is to connect a voltage zener diode in parallel with a large resistor.
  • Depletion-type NMOS the threshold voltage VT of this type of MOS is less than 0V, so by connecting GATE and SOURCE together, current can be pulled at the DRAIN end.
  • the specific amount of pulled current can be set by setting its width-to-length ratio.
  • DNM1 to DNM3 in Figure 2 can all be regarded as a current source.
  • the first depletion-type NMOS tube DNM1, the second depletion-type NMOS tube DNM2, and the third depletion-type NMOS tube DNM3 (DNM3 belongs to the enable voltage comparison submodule 3, which is introduced in advance here) can also be replaced by resistors.
  • the first diode D1, the first voltage clamping circuit CLAMP1 and the first enhancement mode NMOS transistor NM1 constitute the first judgment unit 21; the first enhancement mode PMOS transistor PM1, the second enhancement mode PMOS transistor PM2, the third enhancement mode PMOS transistor PM3, the first depletion mode NMOS transistor DNM1, the second depletion mode NMOS transistor DNM2, the second voltage clamping circuit CLAMP2 and the third enhancement mode NMOS transistor NM3 constitute the power conversion unit 22, wherein the source of the third enhancement mode NMOS transistor NM3 is configured as the internal power output terminal 23.
  • the second enhancement mode NMOS transistor NM2, the fourth enhancement mode PMOS transistor PM4, the second diode D2, the third voltage clamping circuit CLAMP3 and the Schmitt trigger SMT1 constitute the second judgment unit 24.
  • the fifth enhancement mode PMOS transistor PM5 constitutes the shutdown unit.
  • the working principle of the promoter module 2 is described as follows.
  • VD1 is the forward conduction voltage drop of the first diode D1 (the first diode D1 can be realized by other means, such as using the body diode of the MOS tube, etc.), and VT1 is the turn-on threshold voltage of NM1.
  • the VGS1 voltage of the high-voltage NMOS tube NM1 is less than its turn-on voltage VT1.
  • the voltage at the V1 end i.e., the gate of NM2 or the output end of the Schmitt trigger SMT1
  • the voltage at the V1 end is also less than the turn-on voltage VT2 of the high-voltage NMOS tube NM2
  • NM2 cannot be turned on
  • the high-voltage PMOS tube PM1 cannot be turned on at this time
  • PM2 of the same type as PM1 and forming a current mirror with it cannot be turned on either. Therefore, the GATE end of the high-voltage NMOS tube NM3 is pulled to a very low voltage by CLAMP2, and NM3 cannot be turned on either.
  • NM1 As the EN pin voltage rises, the current of NM1 rises, and the currents of PM1 and PM2 also begin to rise.
  • the current of PM2 rises to be sufficient to drive CLAMP2
  • the VGS voltage of NM3 is greater than VT3 (the turn-on threshold of NM3, ignoring the back gate effect here)
  • NM3 starts to turn on (at this time, it still corresponds to the judgment result of the first judgment unit 21 being between meeting the first startup condition and not meeting the first startup condition).
  • the SOURCE of NM3 is the power supply voltage VDD of the following circuit module, and the typical value of VDD voltage is less than 5V.
  • DNM2 is a depletion-type NMOS tube, which is used as a current source here to set the working current of the low-voltage PMOS tube PM3.
  • PM5 is used to turn off the current mirror composed of PM3 and PM4.
  • the output signal VOFF of the switch module is high level, PM5 is not turned on.
  • VOFF is low level, PM5 is turned on, and PM3 and PM4 have no current, so as to quickly shut down the power conversion unit 22.
  • the enabling voltage comparison submodule 3 includes a reference voltage generating unit 31 and a third judging unit 32 .
  • the reference voltage generating unit 31 When the reference voltage generating unit is powered on, the reference voltage generating unit 31 is used to output a reference voltage with the second precision, and the reference voltage is set based on the second power-on condition.
  • the third judgment unit 32 When the third judgment unit is powered on, the third judgment unit 32 directly or indirectly compares the output signal of the reference voltage generating unit with the signal of the power on/off enable terminal with the second accuracy.
  • the size of the signal EN when the size relationship changes, the signal output by the third judgment unit 32 changes. For example, when the former is greater than the latter, the third judgment unit 32 outputs a high level; when the former is less than the latter, the third judgment unit 32 outputs a low level.
  • the situation where the two are equal can be arbitrarily set according to the characteristics of the component itself.
  • the reference voltage includes a first reference voltage and a second reference voltage
  • the reference voltage generation unit 31 obtains a signal that can indicate whether the total circuit is currently in an on state or an off state.
  • the reference voltage generation unit 31 obtains the output signal of the third judgment unit 32 based on the signal conversion unit 33.
  • the output signal of the switch module can also be obtained as a basis for judgment.
  • the reference voltage generating unit 31 When the reference voltage generating unit is powered on, if the overall circuit is currently in the on state, the reference voltage generating unit 31 outputs the second reference voltage; if the overall circuit is currently in the off state, the reference voltage generating unit 31 outputs the first reference voltage.
  • the first reference voltage is greater than the second reference voltage.
  • the first reference voltage is 1.6V
  • the second reference voltage is 1.2V
  • the enable voltage comparison submodule 3 includes a bandgap reference voltage component BG1, a first transmission gate TG1, a second transmission gate TG2, a first transistor Q1 of a PNP type, a second transistor Q2 of a PNP type, a sixth enhancement type PMOS transistor PM6, a seventh enhancement type PMOS transistor PM7 and a comparator COMP1.
  • the first transmission gate TG1 is configured such that when the high level enable end of the first transmission gate TG1 receives a high level and the low level enable end of the first transmission gate TG1 receives a low level, the input end and the output end of the first transmission gate TG1 are turned on, otherwise, the input end and the output end of the first transmission gate TG1 are turned off.
  • the working principle of the second transmission gate TG2 is the same as that of the first transmission gate TG1.
  • the enabling voltage comparison submodule 3 further includes a first inverter INV1 .
  • the first inverter INV1 appears to be subordinate to the output submodule 4 , in the field of electrical technology, it is common and understandable that one component is subordinate to two functional submodules.
  • the bandgap reference voltage component BG1, the first transmission gate TG1 and the second transmission gate TG2 constitute the reference voltage generating unit 31, and the high level enable end of the first transmission gate TG1 and the low level enable end of the second transmission gate TG2 are connected and configured as the first control end of the reference voltage generating unit 31, and the low level enable end of the first transmission gate TG1 and the high level enable end of the second transmission gate TG2 are connected and configured as the second control end of the reference voltage generating unit 31.
  • the first transistor Q1, the second transistor Q2, the sixth enhancement mode PMOS transistor PM6, the seventh enhancement mode PMOS transistor PM7 and the comparator COMP1 constitute the third judgment unit 32.
  • the gates of PM6 and PM7 are used to obtain a bias voltage VPBS, and in one embodiment, are connected to the gate of PM4 (not shown).
  • the first inverter INV1 constitutes the signal conversion unit 33 .
  • the signal conversion unit 33 may not be provided, or a signal conversion function may be provided inside the reference voltage generation unit 31 .
  • the second control terminal of the reference voltage generating unit 31 is used to obtain the output signal VC of the comparator COMP1
  • the first control terminal of the reference voltage generating unit 31 is used to obtain the inverted signal VCB of the output signal of the comparator COMP1 .
  • the VCB signal is converted by the signal conversion unit 33 .
  • BG1 is a bandgap reference circuit. In other embodiments, it can be replaced with a reference voltage generating circuit based on other principles.
  • the bandgap reference circuit can generate a stable reference voltage and current source.
  • the power supply voltage of BG1 is VDD.
  • BG1 outputs two voltage sources, namely the first reference voltage ENH and the first reference voltage ENL, wherein the voltage of ENH is greater than ENL.
  • ENH is used to set the system startup voltage
  • ENL is used to set the system shutdown voltage.
  • TG1 and TG2 are transmission gates, which are controlled by a pair of inverse signals VC and VCB.
  • VENTH is the voltage at the output end of the reference voltage generating unit 31.
  • PM6 and PM7 are low-voltage PMOS transistors of the same type and size, forming a current mirror; VPBS is its bias voltage source. In different embodiments, this signal can be generated by itself through conventional bias technology, or it can be connected to the GATE terminal of other PMOS current mirrors, such as the GATE terminal of PM4.
  • VM VENTH+VEB
  • VP VEN+VEB
  • VM is the inverting terminal voltage of the comparator COMP1
  • VP is the non-inverting terminal voltage of the comparator COMP1.
  • VEN is also greater than VEHTH, and vice versa.
  • COMP1 is a comparator used to compare the voltages of VP and VM. When VP is greater than VM (i.e. When VEN is greater than VENTH), VC is at a high level, otherwise it is at a low level. It should be noted that in different embodiments, the specific position of the comparator COMP1 and the connection mode of the positive terminal and the negative terminal can be set according to different needs, and FIG2 only shows one possibility.
  • VEN When VEN is greater than VENH, the switch module outputs a power-on signal to start the functional module of the total circuit. When VEN is less than VENL, the switch module outputs a power-off signal to shut down other modules in the circuit and turn off the circuit at the same time, achieving a technical effect of almost zero shutdown current.
  • VEN voltage When the VEN voltage is between VENL and VENH, the system maintains its previous state. There is a window between VENH and VENL, which can effectively avoid false triggering.
  • VENL and VENH are both generated by a bandgap reference circuit, their accuracy is relatively high.
  • the bias current and type of Q1 and Q2 are also the same, so VEB of Q1 and Q2 can also be considered to be the same, thereby achieving a high-precision enable control voltage.
  • the output submodule 4 includes a charging and discharging unit 42 and an output unit 43 .
  • the charging and discharging unit 42 is used to delay the output signal of the enabling voltage comparison submodule 3 from entering the output unit 43 , and filter out the oscillation of the output signal of the enabling voltage comparison submodule 3 .
  • the output unit 43 determines its own output signal based at least on the output signal of the enable voltage comparison submodule 3 .
  • the output unit 43 determines its own output signal based on the output signal of the enable voltage comparison submodule 3 and the signal EN of the switch enable terminal. This configuration further improves the accuracy of the switch module and prevents erroneous actions caused by sudden changes in a single signal.
  • the output submodule 4 further includes a blocking unit 41, which is used to block the influence of the charging and discharging unit 42 on the internal components of the enabling voltage comparison submodule 3, and/or to increase the driving capability of the output signal of the enabling voltage comparison submodule 3.
  • a blocking unit 41 which is used to block the influence of the charging and discharging unit 42 on the internal components of the enabling voltage comparison submodule 3, and/or to increase the driving capability of the output signal of the enabling voltage comparison submodule 3.
  • the output submodule 4 includes: the seventh enhancement mode PMOS tube PM7, the fourth enhancement mode NMOS tube NM4, the third depletion mode NMOS tube DNM3, the second triode Q2, the first inverter INV1, the second inverter INV2, the third inverter INV3, the charge and discharge resistor R1, the charge and discharge capacitor C1, the SR trigger SRFF1 and the power-on reset component (not shown).
  • the trigger SRFF1 is powered by VDD (not shown).
  • Q2 and PM7 are common modules of the enable voltage comparison submodule 3 and the output submodule 4.
  • the first inverter INV1, the second inverter INV2 and the third inverter INV3 constitute the blocking unit 41.
  • the charge and discharge resistor R1 and the charge and discharge capacitor C1 constitute the charge and discharge unit 42.
  • the seventh enhancement-mode PMOS transistor PM7, the fourth enhancement-mode NMOS transistor NM4, the third depletion-mode NMOS transistor DNM3, the second transistor Q2, the power-on reset component and the SR trigger SRFF1 constitute the output unit 43, wherein the base of the second transistor Q2 is configured as an input terminal of the output unit 43, and the inverting output terminal of the SR trigger SRFF1 is configured as the output terminal of the output unit 43.
  • SR trigger SRFF1 The working logic of the SR trigger SRFF1 can be understood based on common knowledge in the art and will not be described in detail here.
  • the output unit 43 uses some components of the enable voltage comparison submodule 3 to obtain the signal EN of the power enable end.
  • an input end for obtaining the signal EN of the power enable end may also be independently set.
  • the barrier unit 41 may also be configured in other forms, or, if it is confirmed that the barrier unit 41 is not necessary, it may not be configured.
  • NM4 is an enhanced low-voltage NMOS
  • DNM3 is a depletion-type NMOS
  • VT4 is the turn-on threshold voltage of NM4.
  • VEN2 is slightly smaller than VEN, and the difference between the two is generally around 0.1 to 0.3V.
  • R1 and C1 form a charging circuit, which is used as a shutdown delay.
  • the RC time constant can be adjusted to adjust the time from VEN triggering shutdown to the time when the circuit of the present invention is turned off.
  • VEN is lower than VENTH
  • VC outputs a low level
  • V3 outputs a high level
  • C1 is charged for a certain period of time through R1.
  • the S end of SRFF1 is a high level, and the EN2 voltage at this time is a low level, so the output VOFF of the SR trigger SRFF1 is a low level, which controls PM5 in STAGE1 to conduct, so that PM4 has no current, EN1 drops, V1 outputs a low level, NM2 is not turned on, and because VENL is less than VD+VT1, NM1 is also not turned on, and the system is completely shut down.
  • the power-on reset component is used to prevent the initial state of the SR trigger from being abnormal. Under the influence of the power-on reset component, when the SR trigger is powered on, the initial state of the inverting output terminal is to output a high level.
  • FIG3 is a working waveform diagram of an embodiment of the present invention.
  • the top part is VCC flowing into The current of the total circuit, the voltage of the EN pin in the middle, and the output signal VCB of the first inverter INV1 below. It can be considered that the signal of VCB can reflect the signal of VOFF.
  • VEN has not reached 1.6V, that is, VENH is set
  • the shutdown signal VCB is high. This signal can be used to control the functional module to shut down/not start up; when VEN reaches 1.6V, VCB becomes low and the shutdown signal is released.
  • VEN When VEN is in the falling stage, at about 1.2V, that is, the VEHL voltage, VCB appears at a short high level, indicating that the shutdown threshold has been reached. After that, the overall circuit is turned off, and the VCC current IVCC drops rapidly to achieve the shutdown function.
  • this embodiment fully meets the design expectations and performs well in both energy consumption and response accuracy.
  • the present embodiment provides a power on/off module.
  • the power on/off module includes a power on/off enable terminal, a starter module, and an enable voltage comparison submodule.
  • the starter module determines whether the signal of the power on/off enable terminal meets the power on condition with lower precision and lower energy consumption, and supplies power to or stops supplying power to other modules according to a preset logic.
  • the enable voltage comparison submodule After the enable voltage comparison submodule is powered on, it determines whether the signal of the power on/off enable terminal meets the power on condition with higher precision, and starts or shuts down other modules according to a preset logic.
  • the standby energy consumption of the starter module is less than the minimum energy consumption for the enable voltage comparison submodule to work normally. With such a configuration, the working characteristics of each submodule are reasonably utilized, and both the shutdown energy consumption and the response accuracy are taken into account, thereby solving the problem that the two cannot be taken into account at the same time in the prior art.

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Abstract

本发明提供了一种开关机模块。所述开关机模块包括开关机使能端、启动子模块和使能电压比较子模块。所述启动子模块以较低精度和较低能耗判断所述开关机使能端的信号是否符合开机条件，并根据预设逻辑为其他模块供电或者停止供电。所述使能电压比较子模块得电后，以较高精度判断所述开关机使能端的信号是否符合所述开机条件，并根据预设逻辑启动或关闭其他模块。所述启动子模块的待机能耗小于所述使能电压比较子模块能够正常工作的最小能耗。如此配置，合理利用各子模块的工作特性，兼顾了关机能耗和响应精度，解决了现有技术中存在的两者不能兼顾的问题。

Description

开关机模块 技术领域
本发明涉及集成电路技术领域，特别涉及一种开关机模块。
背景技术
日常使用的电器都具有待机功能，对于待机功能具有两个要求，第一是要求待机时消耗的电能尽可能少；第二是对于开机控制信号的响应精度要尽可能高。
如果产品的关机、待机时的能耗过高，很容易降低产品的竞争力，在商业竞争中，处于不利的地位；对于电池供电设备而言，由于电源系统总是与电池两端接触，如果系统的关机电流过大，则会导致电池在一定的时间后，因电源系统的关机电流导致电池电量的耗尽，这也会导致其产品的竞争力下降。
如果对于开机控制信号的响应精度不够，则容易造成控制效果不够理想，无法实现特定需求的问题。
现有技术中，往往采用如下技术手段：对于参与开机判断的模块，在任何时刻都保持一定的电流，从而使得该模块可以随时响应使能信号，并具有一定的响应精度。但是这样的方案会导致关机状态下电路的电流仍然处于uA级别。
总之，现有技术中存在关机状态下的低能耗和响应开机信号的高精度无法兼顾的问题。
发明内容
本发明的目的在于提供一种开关机模块，以解决现有技术中存在的关机状态下的低能耗和响应开机信号的高精度无法兼顾的问题。
为了解决上述技术问题，本发明提供了一种开关机模块，应用于一总电路，所述总电路包括所述开关机模块和功能模块，所述开关机模块包括开关机使能端、启动子模块和使能电压比较子模块。
其中，所述启动子模块用于获取外部电源。
所述启动子模块以第一精度判断所述开关机使能端的信号是否符合第一 开机条件；若符合所述第一开机条件，则将所述外部电源转化为内部电源直接或者间接地驱使所述使能电压比较子模块和所述功能模块得电；若不符合所述第一开机条件，则直接或者间接地切断所述使能电压比较子模块和所述功能模块的电源。
所述使能电压比较子模块得电后，以第二精度判断所述开关机使能端的信号是否符合第二开机条件；若符合所述第二开机条件，则输出控制信号驱使至少一部分的所述功能模块开机；若不符合所述第二开机条件，则输出控制信号驱使至少一部分的所述功能模块不开机或者关机。
当不符合所述第一开机条件时，所述启动子模块以第一能耗维持自身的判断功能；当所述使能电压比较子模块得电时，所述使能电压比较子模块以第二能耗维持自身的判断功能。
所述第一精度低于所述第二精度，所述第一能耗小于所述第二能耗。
可选的，所述开关机模块还包括输出子模块，当所述输出子模块得电时，所述输出子模块获取所述使能电压比较子模块的输出信号，消除振荡后输出开关机信号。
所述启动子模块还用于，若符合所述第一开机条件，则将所述外部电源转化为内部电源直接或者间接地驱使所述输出子模块得电；若不符合所述第一开机条件，则直接或者间接地切断所述输出子模块的电源。
可选的，所述启动子模块包括第一判断单元和电源转化单元。
其中，当连接所述外部电源后，所述电源转化单元至少具有如下工作状态：非工作状态、半工作状态和正常工作状态；在所述非工作状态时，所述电源转化单元以不超过所述第一能耗的功率输出电能；在半工作状态时，所述电源转化单元以超过所述第一能耗的功率输出电能，且输出的电能至少不满足所述功能模块的功率需求和电压需求；在所述正常工作状态时，所述电源转化单元输出的电能满足所述总电路的功率需求和电压需求。
当没有其他控制逻辑介入时，所述第一判断单元以所述第一精度判断所述开关机使能端的信号是否符合所述第一开机条件；若不符合所述第一开机条件，则驱使所述电源转化单元切换至所述非工作状态；若符合所述第一开机条件，则驱使所述电源转化单元切换至所述正常工作状态；若结果为其他情况，则驱使所述电源转化单元切换至所述半工作状态。
可选的，所述启动子模块还包括第二判断单元，所述第二判断单元的电 源获取端与所述电源转化单元的内部电源输出端连接；所述电源转化单元工作于所述半工作状态或者所述正常工作状态且所述电源转化单元与所述第二判断单元的供能线路未被断开或屏蔽时，所述第二判断单元均能正常工作。
当没有其他控制逻辑介入时，所述第二判断单元判断所述开关机使能端的信号是否符合第一开机条件；若不符合所述第一开机条件，则驱使所述电源转化单元切换至所述非工作状态；若符合所述第一开机条件，则驱使所述电源转化单元切换至所述正常工作状态；在失电情况下，所述第二判断单元不阻碍所述电源转化单元的所述工作状态的切换。
当所述第一判断单元驱使所述电源转化单元切换至所述半工作状态，且所述第二判断单元驱使所述电源转化单元切换至所述正常工作状态时，所述电源转化单元切换至所述正常工作状态。
可选的，所述启动子模块还包括关闭单元，所述关闭单元的输入端与所述开关机模块的输出端连接。
当所述开关机模块的输出端输出关机信号时，所述关闭单元屏蔽所述第二判断单元对所述电源转化单元的控制效果。
可选的，所述使能电压比较子模块包括参考电压生成单元和第三判断单元。
其中，当所述参考电压生成单元得电时，所述参考电压生成单元用于以所述第二精度输出参考电压，所述参考电压基于所述第二开机条件设置。
当所述第三判断单元得电时，所述第三判断单元以所述第二精度直接或者间接地比较所述参考电压生成单元的输出信号和所述开关机使能端的信号的大小，当大小关系发生转换时，所述第三判断单元输出的信号发生转变。
可选的，所述参考电压包括第一参考电压和第二参考电压，所述参考电压生成单元获取能够指示所述总电路当前处于开机状态还是关机状态的信号。
当所述参考电压生成单元得电时，若所述总电路当前处于开机状态，则所述参考电压生成单元输出所述第二参考电压；若所述总电路当前处于关机状态，则所述参考电压生成单元输出所述第一参考电压。
所述第一参考电压大于所述第二参考电压。
可选的，所述输出子模块包括充放电单元和输出单元。
其中，所述充放电单元用于延迟所述使能电压比较子模块的输出信号进 入所述输出单元，并滤除所述使能电压比较子模块的输出信号的振荡。
所述输出单元至少基于所述使能电压比较子模块的输出信号确定自身的输出信号。
可选的，所述输出单元基于所述使能电压比较子模块的输出信号以及所述开关机使能端的信号确定自身的输出信号。
可选的，所述输出子模块还包括阻隔单元，所述阻隔单元用于阻隔所述充放电单元对所述使能电压比较子模块的内部元件的影响，和/或，增加所述使能电压比较子模块的输出信号的驱动能力。
与现有技术相比，本发明提供的一种开关机模块中，所述开关机模块包括开关机使能端、启动子模块和使能电压比较子模块。所述启动子模块以较低精度和较低能耗判断所述开关机使能端的信号是否符合开机条件，并根据预设逻辑为其他模块供电或者停止供电。所述使能电压比较子模块得电后，以较高精度判断所述开关机使能端的信号是否符合所述开机条件，并根据预设逻辑启动或关闭其他模块。所述启动子模块的待机能耗小于所述使能电压比较子模块能够正常工作的最小能耗。如此配置，合理利用各子模块的工作特性，兼顾了关机能耗和响应精度，解决了现有技术中存在的两者不能兼顾的问题。
附图说明
本领域的普通技术人员将会理解，提供的附图用于更好地理解本发明，而不对本发明的范围构成任何限定。其中：
图1是本发明一实施例的开关机模块的结构示意图；
图2是本发明一实施例的开关机模块的电路图；
图3是本发明一实施例的波形图。
附图中：
1-开关机使能端；2-启动子模块；3-使能电压比较子模块；4-输出子模块；
21-第一判断单元；22-电源转化单元；23-内部电源输出端；24-第二判断单元；25-关闭单元；31-参考电压生成单元；32-第三判断单元；33-信号转换单元；41-阻隔单元；42-充放电单元；43-输出单元。
具体实施方式
为使本发明的目的、优点和特征更加清楚，以下结合附图和具体实施例对本发明作进一步详细说明。需说明的是，附图均采用非常简化的形式且未按比例绘制，仅用以方便、明晰地辅助说明本发明实施例的目的。此外，附图所展示的结构往往是实际结构的一部分。特别的，各附图需要展示的侧重点不同，有时会采用不同的比例。
如在本发明中所使用的，单数形式″一″、″一个″以及″该″包括复数对象，术语″或″通常是以包括″和/或″的含义而进行使用的，术语″若干″通常是以包括″至少一个″的含义而进行使用的，术语″至少两个″通常是以包括″两个或两个以上″的含义而进行使用的，此外，术语″第一″、″第二″、″第三″仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有″第一″、″第二″、″第三″的特征可以明示或者隐含地包括一个或者至少两个该特征，″一端″与″另一端″以及″近端″与″远端″通常是指相对应的两部分，其不仅包括端点，术语″安装″、″相连″、″连接″应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。此外，如在本发明中所使用的，一元件设置于另一元件，通常仅表示两元件之间存在连接、耦合、配合或传动关系，且两元件之间可以是直接的或通过中间元件间接的连接、耦合、配合或传动，而不能理解为指示或暗示两元件之间的空间位置关系，即一元件可以在另一元件的内部、外部、上方、下方或一侧等任意方位，除非内容另外明确指出外。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
本发明的核心思想在于提供一种开关机模块，以解决现有技术中存在的关机状态下的低能耗和响应开机信号的高精度无法兼顾的问题。
以下参考附图进行描述。
请参考图1，本发明提供了一种开关机模块，应用于一总电路，所述总电路包括所述开关机模块和功能模块(未图示)，所述开关机模块包括开关机使能端1、启动子模块2和使能电压比较子模块3。由于本开关机模块可以应用于不同场合不同功能的总电路，因此对所述功能模块的具体功能不进行限制。
其中，所述启动子模块2用于获取外部电源VCC。
所述启动子模块2以第一精度判断所述开关机使能端1的信号EN是否符合第一开机条件；若符合所述第一开机条件，则将所述外部电源VCC转化为内部电源VDD直接或者间接地驱使所述使能电压比较子模块3和所述功能模块得电；若不符合所述第一开机条件，则直接或者间接地切断所述使能电压比较子模块3和所述功能模块的电源。″驱使″应当理解为相关模块输出控制信号的意图，但是在实际情况中因为其他原因(例如有更高级别的控制逻辑介入，或者，电路出现故障等)导致后续目的未实现的，也应当理解为符合描述，后续内容中″驱使″按照相同的思路进行理解。
所述第一开机条件应当理解为使能端的电压大于某个值，为了便于理解，在本实施例中，所述第一开机条件约为＞1.4V(具体为VD1+VT1，VD1和VT1的相关含义在后文中介绍)。
所述使能电压比较子模块3得电后，以第二精度判断所述开关机使能端1的信号EN是否符合第二开机条件；若符合所述第二开机条件，则输出控制信号驱使至少一部分的所述功能模块开机；若不符合所述第二开机条件，则输出控制信号驱使至少一部分的所述功能模块不开机或者关机。在本申请中，所述第一精度为0.1V级别，所述第二精度为0.01V级别。
为了便于理解，在本实施例中，所述第二开机条件为＞1.6V。
在理想情况下，所述总电路的设计目的包括：当所述总电路未启动时，若信号EN＜1.6V，期望所述总电路不启动，若信号EN＞1.6V，期望所述总电路启动。当所述总电路启动后，如何关闭所述总电路的逻辑在后文中进行描述。
但是在实际情况中，任何形式的电路都无法恰好在信号越过1.6V的时候进行状态转换，往往按照如下逻辑运行：当EN＜a时，所述总电路不启动，当EN＞b时，所述总电路启动，当a＜EN＜b时，所述总电路的状态不可控，不可预知。区间[a,b]的大小也可以称为响应精度，越小精度越高。
基于上述设计目的，本实施例将开机条件拆分为所述第一开机条件和所述第二开机条件；将所述第一开机条件设置为＞1.4V；所述第二开机条件包括：若所述总电路处于未开机状态，＞1.6V则开机，否则不开机。
可以理解的，本发明通过修改各元件的参数可以将上述的1.6V和1.4V修改为其他值，此处仅为举例说明。
可以理解的，在不同的实施例中，也可以将所述第一开机条件和所述第 二开机条件设置为相同。
当不符合所述第一开机条件时，所述启动子模块2以第一能耗维持自身的判断功能；当所述使能电压比较子模块得电时，所述使能电压比较子模块3以第二能耗维持自身的判断功能。在本申请中，以电流大小衡量所述第一能耗和第二能耗。所述第一能耗为pA～nA级别，所述第二能耗为uA级别。
所述第一精度低于所述第二精度，所述第一能耗小于所述第二能耗。
可以理解的，在本实施例中，并不认为只要精度变低就能降低能耗，而是认为，当精度降低时，可供选择的元件和结构变多，从而可以选择能耗相对较低的方案实现低精度的响应，即降低精度带来了选择更多方案的可能性，从而降低了能耗。
如此配置，本实施例将所述总电路的启动拆分为两个独立的过程，分别为各模块得电以及各模块接受到开机信号。两个过程又通过不同精度不同能耗的模块加以控制，并在关机阶段关闭所述内部电源使得所述总电路的能耗仅限于所述启动子模块2，从结构上降低了能耗。另一方面，通过降低所述启动子模块2的精度以进一步降低能耗，但是又通过所述使能电压比较子模块3保证了所述开关机模块整体的精度；从而兼顾了关机状态下的低能耗和响应开机信号的高精度。
请继续参考图1，所述开关机模块还包括输出子模块4，当所述输出子模块得电时，所述输出子模块4获取所述使能电压比较子模块3的输出信号，消除振荡后输出开关机信号。
所述启动子模块2还用于，若符合所述第一开机条件，则将所述外部电源VCC转化为内部电源VDD直接或者间接地驱使所述输出子模块4得电；若不符合所述第一开机条件，则直接或者间接地切断所述输出子模块4的电源。
如此配置，优化输出信号，避免信号停留于临界值时产生的振荡，进而导致所述总电路频繁开关的问题。
基于上述发明思想，本领域技术人员可以设置不同形式的功能单元以实现上述的启动子模块2、使能电压比较子模块3和输出子模块4。
图1示出了一种较优的实现方式，所述启动子模块2包括第一判断单元21和电源转化单元22。
其中，当连接所述外部电源VCC后，所述电源转化单元22至少具有如 下工作状态：非工作状态、半工作状态和正常工作状态；在所述非工作状态时，所述电源转化单元22以不超过所述第一能耗的功率输出电能；在半工作状态时，所述电源转化单元22以超过所述第一能耗的功率输出电能，且输出的电能至少不满足所述功能模块的功率需求和电压需求；在所述正常工作状态时，所述电源转化单元22输出的电能满足所述总电路的功率需求和电压需求。
当没有其他控制逻辑介入时，所述第一判断单元21以所述第一精度判断所述开关机使能端1的信号EN是否符合所述第一开机条件；若不符合所述第一开机条件，则驱使所述电源转化单元22切换至所述非工作状态；若结果介于符合所述第一开机条件和不符合所述第一开机条件之间，则驱使所述电源转化单元22切换至所述半工作状态；若符合所述第一开机条件，则驱使所述电源转化单元22切换至所述正常工作状态。
结果介于符合所述第一开机条件和不符合所述第一开机条件之间应当理解为，受限于所述第一判断单元21的判断精度，无法保证当前的判断结果的正确性。此描述也暗含了所述第一判断单元21是一种模拟电路判断逻辑。
可以理解的，所述电源转化单元22的工作状态包括所述半工作状态是与所述第一精度配合设置的技术特征。若所述电源转化单元22的工作状态不包括所述半工作状态，则意味着所述电源转化单元22中需要设置额外逻辑和结构以保证所述电源转化单元22的工作状态具有数字电路的特征。因此，所述电源转化单元22包括所述半工作状态并不意味着所述启动子模块2一定具有低能耗的特性，但是为所述启动子模块2实现低能耗带来更多的方案选择，从而使得所述启动子模块2可以选择低能耗的方案。
所述半工作状态对所述总电路的工作效率带来了一定的制约。因此，在一个较优的实施例中，所述启动子模块2还包括第二判断单元24，所述第二判断单元24的电源获取端与所述电源转化单元22的内部电源输出端23连接；所述电源转化单元22工作于所述半工作状态或者所述正常工作状态且所述电源转化单元22与所述第二判断单元24的供能线路未被断开或屏蔽时，所述第二判断单元24均能正常工作。也就是说所述第二判断单元24正常工作的能耗高于所述第一能耗，但是低于所述总电路正常工作所需要的能耗。
当没有其他控制逻辑介入时，所述第二判断单元24判断所述开关机使能端2的信号EN是否符合所述第一开机条件；若不符合所述第一开机条件，则 驱使所述电源转化单元22切换至所述非工作状态；若符合所述第一开机条件，则驱使所述电源转化单元22切换至所述正常工作状态；在失电情况下，所述第二判断单元24不阻碍所述电源转化单元22的所述工作状态的切换。也就是说，所述第二判断单元24的判断精度实际上高于所述第一精度。当所述第一判断单元21的判断结果介于符合所述第一开机条件和不符合所述第一开机条件之间时，所述第二判断单元24的判断结果为符合所述第一开机条件，两者判断结果不同并非是矛盾的，而是由于精度不同引起的。
若将所述电源转化单元22和所述第二判断单元24看作一个整体，称为电源组件，则所述电源组件对外的表现为：所述电源组件的工作状态不包括所述半工作状态。
此处还要强调所述第一判断单元21和所述第二判断单元24的控制优先级。当所述第一判断单元21驱使所述电源转化单元22切换至所述半工作状态，且所述第二判断单元24驱使所述电源转化单元22切换至所述正常工作状态时，所述电源转化单元22切换至所述正常工作状态。
考虑到关机效率，所述启动子模块2还包括关闭单元25，所述关闭单元25的输入端与所述开关机模块的输出端连接。
当所述开关机模块的输出端输出关机信号时，所述关闭单元25屏蔽所述第二判断单元24对所述电源转化单元22的控制效果，此刻所述电源转化单元22的工作状态切换至半工作状态。如此配置，可以加快关机进程。
基于上述各单元的功能描述，本领域技术人员可以设置相关的电路结构，在图2中示出了一种较优的实现方式。
请参考图2，所述启动子模块2包括第一二极管D1、第二二极管D2、第一增强型PMOS管PM1、第二增强型PMOS管PM2、第三增强型PMOS管PM3、第四增强型PMOS管PM4、第五增强型PMOS管PM5、第一增强型NMOS管NM1、第二增强型NMOS管NM2、第三增强型NMOS管NM3、第一耗尽型NMOS管DNM1、第二耗尽型NMOS管DNM2、第一电压钳位电路CLAMP1、第二电压钳位电路CLAMP2、第三电压钳位电路CLAMP3和施密特触发器SMT1。
其中，第一电压钳位电路CLAMP1、第二电压钳位电路CLAMP2和第三电压钳位电路CLAMP3被配置为，会尝试拉取少量电流，典型值1uA或者以下，如果电流达不到上述值，则该电路两端的电压非常低，近似于0V，如果 流入的电流大于上述值，则可以进行电压钳位，同时流入的电流变化较大时，其两端电压变化不大(如：流入电流1uA～100uA，其两端电压变化不超过1V)。这种电路可以用很多种方法实现，最简单的方法就是稳压二极管与大电阻的并联。
耗尽型NMOS，该类型的MOS的阈值电压VT小于0V，所以把GATE与SOURCE接在一起就可以在DRAIN端拉取电流，具体的拉取电流多少可以通过设置其宽长比，图2中的DNM1～DNM3均可以看成一个电流源。在对于实施效果要求较低的场合或者工艺不允许的场合，第一耗尽型NMOS管DNM1、第二耗尽型NMOS管DNM2、第三耗尽型NMOS管DNM3(DNM3从属于所述使能电压比较子模块3，此处先提前介绍)也可以用电阻替代。
上述元件的具体连接关系可以参考图2进行理解，在此不进行赘述。
其中，所述第一二极管D1、所述第一电压钳位电路CLAMP1和第一增强型NMOS管NM1构成所述第一判断单元21；所述第一增强型PMOS管PM1、所述第二增强型PMOS管PM2、所述第三增强型PMOS管PM3、所述第一耗尽型NMOS管DNM1、所述第二耗尽型NMOS管DNM2、第二电压钳位电路CLAMP2和第三增强型NMOS管NM3构成所述电源转化单元22，其中，所述第三增强型NMOS管NM3的源极被配置为所述内部电源输出端23。所述第二增强型NMOS管NM2、所述第四增强型PMOS管PM4、所述第二二极管D2、所述第三电压钳位电路CLAMP3和施密特触发器SMT1构成所述第二判断单元24。所述第五增强型PMOS管PM5构成所述关闭单元。
所述启动子模块2的工作原理介绍如下。
当EN引脚电压远小于VD1+VT1时，NM1无法开启。其中VD1为第一二极管D1的正向导通压降(第一二极管D1可以通过其他的方式实现，如利用MOS管的体二极管等)，VT1为NM1的开启阈值电压。高压NMOS管NM1的VGS1电压小于其开启电压VT1。同时，如果V1端(即NM2的栅极或施密特触发器SMT1的输出端)电压也小于高压NMOS管NM2的开启电压VT2，则NM2无法开启，进而此时高压PMOS管PM1无法导通，与PM1同类型且与之组成电流镜的PM2也无法导通，故高压NMOS管NM3的GATE端被CLAMP2拉到非常低的电压，NM3也无法导通。从上面的描述可以看出，EN脚电压为低电平时，VCC端的电流无法流入电路中，此时电路的工作电流几乎为零(只存在器件的漏电电流，通常可以忽略)，此时所述启动子模块2的 能耗非常小。
当EN引脚电压上升到略大于VD1+VT1时(对应于所述第一判断单元21的判断结果介于符合所述第一开机条件和不符合所述第一开机条件之间)，NM1开始导通，此时PM1与PM2开始轻微导通(nA级别)，但PM2的电流还不足以提供CLAMP2的工作电流，故CLAMP2的电压较低，NM3无法导通，后级电路无供电。
随着EN引脚电压的上升，NM1的电流上升，同时PM1、PM2的电流也开始上升，当PM2的电流上升到足以驱动CLAMP2，同时NM3的VGS电压大于VT3(NM3的开启阈值，此处忽略背栅效应)时，NM3开始导通(此时仍然对应于所述第一判断单元21的判断结果介于符合所述第一开机条件和不符合所述第一开机条件之间)。
NM3的SOURCE即为后面电路模块的供电电压VDD，VDD电压典型值小于5V。DNM2为耗尽型NMOS管，此处用作电流源，用于设置低压PMOS管PM3的工作电流，PM4与PM3组成电流镜，PM4为二极管D2提供偏置电流。在不考虑PM5的前提下，随着VEN电压上升，EN1的电压也上升，此时VEN1＝VEN+VD2，VEN1上升达到施密特触发器SMT1的上升阈值电压后，V1输出高电平，V1输出高电平后，NM2会彻底导通。
也即，只要VEN超过VT1+VD1，该电路可以瞬间达到稳定的工作状态，其中NM1/PM1/PM2的电流上限由DNM1设定，NM3的GATE电压及VDD的电压由CLAMP2的钳位电压V2决定，VDD的电压可以粗略的写成VDD＝V2-VT3(忽略了NM3的GATE过驱动电压与背栅效应)。由于有了电流、电压的限制，可以防止电路超出正常工作范围而损坏。
PM5用于关掉PM3与PM4组成的电流镜，正常工作时，所述开关机模块的输出信号VOFF为高电平，PM5不导通，当需要关机时，VOFF为低电平，PM5导通，PM3、PM4无电流。从而快速关闭所述电源转化单元22。
请继续参考图1，所述使能电压比较子模块3包括参考电压生成单元31和第三判断单元32。
其中，当所述参考电压生成单元得电时，所述参考电压生成单元31用于以所述第二精度输出参考电压，所述参考电压基于所述第二开机条件设置。
当所述第三判断单元得电时，所述第三判断单元32以所述第二精度直接或者间接地比较所述参考电压生成单元的输出信号和所述开关机使能端的信 号EN的大小，当大小关系发生转换时，所述第三判断单元32输出的信号发生转变。例如，当前者＞后者时，所述第三判断单元32输出高电平；当前者＜后者时，所述第三判断单元32输出低电平。两者相等的情况可以根据元件自身的特性任意设置。
为了防止所述总电路在特定情况下发生振荡，所述参考电压包括第一参考电压和第二参考电压，所述参考电压生成单元31获取能够指示所述总电路当前处于开机状态还是关机状态的信号。例如，在图1所示的实施例中，所述参考电压生成单元31基于所述信号转换单元33获取所述第三判断单元32的输出信号。在其他实施例中，也可以获取所述开关机模块的输出信号作为判断依据。
当所述参考电压生成单元得电时，若所述总电路当前处于开机状态，则所述参考电压生成单元31输出所述第二参考电压；若所述总电路当前处于关机状态，则所述参考电压生成单元31输出所述第一参考电压。
所述第一参考电压大于所述第二参考电压。
在一实施例中，所述第一参考电压为1.6V，所述第二参考电压为1.2V。
请参考图2，所述使能电压比较子模块3包括带隙基准电压组件BG1、第一传输门TG1、第二传输门TG2、型号为PNP型的第一三极管Q1、型号为PNP型的第二三极管Q2、第六增强型PMOS管PM6、第七增强型PMOS管PM7和比较器COMP1。所述第一传输门TG1被配置为，当所述第一传输门TG1的高电平使能端接收到高电平且所述第一传输门TG1的低电平使能端接收到低电平时，所述第一传输门TG1的输入端和输出端之间导通，否则，所述第一传输门TG1的输入端和输出端之间关断。所述第二传输门TG2的工作原理与所述第一传输门TG1的工作原理相同。
所述使能电压比较子模块3还包括第一反相器INV1，虽然在图2中，所述第一反相器INV1看起来从属于输出子模块4，但是在电气技术领域，一个元件从属于两个功能子模块是常见且能够被理解的。
其中，所述带隙基准电压组件BG1、所述第一传输门TG1和所述第二传输门TG2构成所述参考电压生成单元31，而所述第一传输门TG1的高电平使能端和所述第二传输门TG2的低电平使能端连接并被配置为所述参考电压生成单元31的第一控制端，所述第一传输门TG1的低电平使能端和所述第二传输门TG2的高电平使能端连接并被配置为所述参考电压生成单元31的第二 控制端。所述第一三极管Q1、所述第二三极管Q2、所述第六增强型PMOS管PM6、所述第七增强型PMOS管PM7和所述比较器COMP1构成所述第三判断单元32。其中PM6和PM7的栅极用于获取一偏置电压VPBS，在一实施例中，与PM4的栅极连接(未图示)。
所述第一反相器INV1构成所述信号转换单元33，在不同的实施例中，也可以不设置所述信号转换单元33，或者，在所述参考电压生成单元31内部设置信号转换功能。
所述参考电压生成单元31的第二控制端用于获取所述比较器COMP1的输出信号VC，所述参考电压生成单元31的第一控制端用于获取所述比较器COMP1的输出信号的反相信号VCB。VCB信号由所述信号转换单元33转换而来。
BG1为带隙基准电路，在其他实施例中，可以替换为其他原理的基准电压生成电路，带隙基准电路可生成稳定的基准电压、电流源，BG1的供电电压为VDD，BG1输出两个电压源，分别为所述第一参考电压ENH和所述第一参考电压ENL，其中ENH的电压大于ENL，ENH用于设定系统的开机电压，ENL用于设定系统的关机电压。
TG1与TG2为传输门，使用一对反向的信号VC和VCB控制。当VC为高电平，VCB为低电平时，TG2导通，TG1关断，故VENTH＝VENL；反之，当VC为低电平，VCB为高电平时，TG1导通，TG2关断，此时VENTH＝VENH。VENTH为所述参考电压生成单元31输出端的电压。
PM6与PM7为同类型同尺寸的低压PMOS管，组成电流镜；VPBS为其偏置电压源，在不同的实施例中，该信号可以通过常规的偏置技术自行产生，也可以接于其他的PMOS的电流镜的GATE端，如PM4的GATE端。Q1与Q2为同尺寸同类型的PNP三极管，PM6与PM7分别为Q1和Q2提供偏置电流。由于流过Q1与Q2的电流相同，Q1与Q2的尺寸、类型也相同，故可以认为Q1的VEB1与Q2的VEB2相同，即：VEB1＝VEB2＝VEB。
此时有：VM＝VENTH+VEB，VP＝VEN+VEB。VM为所述比较器COMP1的反相端电压，VP为所述比较器COMP1的正相端电压。
从上面的分析可以知道，VP大于VM时，VEN也大于VEHTH，反之亦然。
COMP1为比较器，用于比较VP与VM的电压，当VP大于VM时(即 VEN大于VENTH时)，VC为高电平，反之为低电平。需要注意的是，在不同的实施例中，所述比较器COMP1的具体位置，正相端和反相端的连接方式可以根据不同的需要进行设置，图2仅示出其中的一种可能性。
当VEN大于VENH时，所述开关机模块输出开机信号，用于开启所述总电路的所述功能模块，当VEN小于VENL时，所述开关机模块输出关机信号，用于关断电路中的其他模块，同时关掉本电路，实现关机电流几乎为零的技术效果。当VEN电压处于VENL和VENH之间时，系统保持之前的状态。VENH与VENL存在窗口，可以有效的避免误触发。另外VENH要大于VD1+VT1同时留有一定的余量，典型值为VENH＞＝1.6V；VENL要小于VD1+VT1同时留有一定的余量，典型值为VENL＜＝1.2V。
由于VENL与VENH均由带隙基准电路生成，故其精度相对较高，同时Q1、Q2的偏置电流、类型也相同，故Q1与Q2的VEB也可以认为相同，从而可以实现高精度的使能控制电压。
请继续参考图1，进一步地，所述输出子模块4包括充放电单元42和输出单元43。
其中，所述充放电单元42用于延迟所述使能电压比较子模块3的输出信号进入所述输出单元43，并滤除所述使能电压比较子模块3的输出信号的振荡。
所述输出单元43至少基于所述使能电压比较子模块3的输出信号确定自身的输出信号。
进一步地，所述输出单元43基于所述使能电压比较子模块3的输出信号以及所述开关机使能端的信号EN确定自身的输出信号。如此配置，进一步提高所述开关机模块的准确性，防止单个信号的突变导致的错误动作。
较优地，所述输出子模块4还包括阻隔单元41，所述阻隔单元41用于阻隔所述充放电单元42对所述使能电压比较子模块3的内部元件的影响，和/或，增加所述使能电压比较子模块3的输出信号的驱动能力。
请继续参考图2，所述输出子模块4包括：所述第七增强型PMOS管PM7、第四增强型NMOS管NM4、第三耗尽型NMOS管DNM3、所述第二三极管Q2、所述第一反相器INV1、第二反向器INV2、第三反向器INV3、充放电电阻R1、充放电电容C1、SR触发器SRFF1和上电复位组件(未图示)。所述第一反相器INV1、所述第二反向器INV2、所述第三反向器INV3和所述SR 触发器SRFF1由VDD供电(未图示)。Q2和PM7为所述使能电压比较子模块3和所述输出子模块4的共有模块。
其中，所述第一反相器INV1、所述第二反向器INV2和所述第三反向器INV3构成所述阻隔单元41。充放电电阻R1和充放电电容C1构成所述充放电单元42。所述第七增强型PMOS管PM7、所述第四增强型NMOS管NM4、所述第三耗尽型NMOS管DNM3、所述第二三极管Q2、所述上电复位组件和所述SR触发器SRFF1构成所述输出单元43，其中，所述第二三极管Q2的基极被配置为所述输出单元43的一个输入端，所述SR触发器SRFF1的反相输出端被配置为所述输出单元43的输出端。
所述SR触发器SRFF1的工作逻辑可以根据本领域公知常识进行理解，在此不进行展开描述。
在本实施例中，所述输出单元43利用了所述使能电压比较子模块3的部分元件以获取所述开关机使能端的信号EN，在其他实施例中，也可以独立地设置用于获取所述开关机使能端的信号EN的输入端。
在其他的实施例中，所述阻隔单元41也可以设置为其他的形式，或者，经确认不需要设置所述阻隔单元41的，也可以不设置。
NM4为增强型低压NMOS，DNM3为耗尽型NMOS，NM3与DNM3用于成生电压EN2，以供后级使用，其中：VEN2＝VEN+VEB2-VT4。VT4为NM4的开启阈值电压，一般情况下，VEN2略小于VEN，两者差距一般在0.1～0.3V左右。
R1与C1组成充电电路，用于作为关机的延时，可以调整RC时间常数，来调整VEN触发关机后到本发明的电路关掉的时间。当VEN低于VENTH时，VC输出低电平，V3输出高电平，通过R1对C1充电若干时间，V4电压上升达到SR触发器的触发阈值后，SRFF1的S端为高电平，同时此时的EN2电压为低电平，故SR触发器SRFF1的输出VOFF为低电平，控制STAGE1中的PM5导通，使PM4无电流，EN1下降，V1输出低电平，NM2不导通，由于VENL小于VD+VT1，故NM1也不导通，系统彻底关机。
所述上电复位组件，用于防止所述SR触发器的初始状态异常，所述SR触发器在所述上电复位组件的影响下，上电时，反相输出端的初始状态为输出高电平。
请参考图3，本发明一实施例的工作波形图。其中最上方的是VCC流入 所述总电路的电流，中间的是EN引脚的电压，下面的是第一反相器INV1的输出信号VCB，可以认为VCB的信号能够反映VOFF的信号。
由图3可以看出：在EN脚电压VEN远小于VD1+VT1(0s～0.25s，1.75s～2s)时，VCC的电流小于1nA，可以实现几乎为0的关机电流。
VEN上升阶段，大约在1.4V时，内部电路开始工作，表现为IVCC直线上升，但由于VEN没有达到1.6V时，即设置的VENH，关机信号VCB为高电平，使用该信号可以控制所述功能模块关机/不开机；当VEN达到1.6V时，VCB变为低电平，关机信号解除。
VEN在下降阶段，大约在1.2V时，即VEHL电压，VCB出现短暂的高电平，指示达到了关机阈值，之后总体电路关掉，VCC电流IVCC迅速下降，实现关机功能。
由图3可以看出，本实施例完全符合设计预期，在能耗和响应精度两个方面均表现较佳。
综上所述，本实施例提供了一种开关机模块。所述开关机模块包括开关机使能端、启动子模块和使能电压比较子模块。所述启动子模块以较低精度和较低能耗判断所述开关机使能端的信号是否符合开机条件，并根据预设逻辑为其他模块供电或者停止供电。所述使能电压比较子模块得电后，以较高精度判断所述开关机使能端的信号是否符合所述开机条件，并根据预设逻辑启动或关闭其他模块。所述启动子模块的待机能耗小于所述使能电压比较子模块能够正常工作的最小能耗。如此配置，合理利用各子模块的工作特性，兼顾了关机能耗和响应精度，解决了现有技术中存在的两者不能兼顾的问题。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于本发明技术方案的保护范围。

Claims (15)

  1. 一种开关机模块，其特征在于，应用于一总电路，所述总电路包括所述开关机模块和功能模块，所述开关机模块包括开关机使能端、启动子模块和使能电压比较子模块；其中，
    所述启动子模块用于获取外部电源；
    所述启动子模块以第一精度判断所述开关机使能端的信号是否符合第一开机条件；若符合所述第一开机条件，则将所述外部电源转化为内部电源直接或者间接地驱使所述使能电压比较子模块和所述功能模块得电；若不符合所述第一开机条件，则直接或者间接地切断所述使能电压比较子模块和所述功能模块的电源；
    所述使能电压比较子模块得电后，以第二精度判断所述开关机使能端的信号是否符合第二开机条件；若符合所述第二开机条件，则输出控制信号驱使至少一部分的所述功能模块开机；若不符合所述第二开机条件，则输出控制信号驱使至少一部分的所述功能模块不开机或者关机；
    当不符合所述第一开机条件时，所述启动子模块以第一能耗维持自身的判断功能；当所述使能电压比较子模块得电时，所述使能电压比较子模块以第二能耗维持自身的判断功能；
    所述第一精度低于所述第二精度，所述第一能耗小于所述第二能耗。
  2. 根据权利要求1所述的开关机模块，其特征在于，所述开关机模块还包括输出子模块，当所述输出子模块得电时，所述输出子模块获取所述使能电压比较子模块的输出信号，消除振荡后输出开关机信号；
    所述启动子模块还用于，若符合所述第一开机条件，则将所述外部电源转化为内部电源直接或者间接地驱使所述输出子模块得电；若不符合所述第一开机条件，则直接或者间接地切断所述输出子模块的电源。
  3. 根据权利要求1所述的开关机模块，其特征在于，所述启动子模块包括第一判断单元和电源转化单元；其中，
    当连接所述外部电源后，所述电源转化单元至少具有如下工作状态：非工作状态、半工作状态和正常工作状态；在所述非工作状态时，所述电源转化单元以不超过所述第一能耗的功率输出电能；在半工作状态时，所述电源转化单元以超过所述第一能耗的功率输出电能，且输出的电能至少不满足所 述功能模块的功率需求和电压需求；在所述正常工作状态时，所述电源转化单元输出的电能满足所述总电路的功率需求和电压需求；
    当没有其他控制逻辑介入时，所述第一判断单元以所述第一精度判断所述开关机使能端的信号是否符合所述第一开机条件；若不符合所述第一开机条件，则驱使所述电源转化单元切换至所述非工作状态；若符合所述第一开机条件，则驱使所述电源转化单元切换至所述正常工作状态；若结果为其他情况，则驱使所述电源转化单元切换至所述半工作状态。
  4. 根据权利要求3所述的开关机模块，其特征在于，所述启动子模块还包括第二判断单元，所述第二判断单元的电源获取端与所述电源转化单元的内部电源输出端连接；所述电源转化单元工作于所述半工作状态或者所述正常工作状态且所述电源转化单元与所述第二判断单元的供能线路未被断开或屏蔽时，所述第二判断单元均能正常工作；
    当没有其他控制逻辑介入时，所述第二判断单元判断所述开关机使能端的信号是否符合所述第一开机条件；若不符合所述第一开机条件，则驱使所述电源转化单元切换至所述非工作状态；若符合所述第一开机条件，则驱使所述电源转化单元切换至所述正常工作状态；在失电情况下，所述第二判断单元不阻碍所述电源转化单元的所述工作状态的切换；
    当所述第一判断单元驱使所述电源转化单元切换至所述半工作状态，且所述第二判断单元驱使所述电源转化单元切换至所述正常工作状态时，所述电源转化单元切换至所述正常工作状态。
  5. 根据权利要求4所述的开关机模块，其特征在于，所述启动子模块还包括关闭单元，所述关闭单元的输入端与所述开关机模块的输出端连接；
    当所述开关机模块的输出端输出关机信号时，所述关闭单元屏蔽所述第二判断单元对所述电源转化单元的控制效果。
  6. 根据权利要求1所述的开关机模块，其特征在于，所述使能电压比较子模块包括参考电压生成单元和第三判断单元，其中，
    当所述参考电压生成单元得电时，所述参考电压生成单元用于以所述第二精度输出参考电压，所述参考电压基于所述第二开机条件设置；
    当所述第三判断单元得电时，所述第三判断单元以所述第二精度直接或者间接地比较所述参考电压生成单元的输出信号和所述开关机使能端的信号的大小，当大小关系发生转换时，所述第三判断单元输出的信号发生转变。
  7. 根据权利要求6所述的开关机模块，其特征在于，所述参考电压包括第一参考电压和第二参考电压，所述参考电压生成单元获取能够指示所述总电路当前处于开机状态还是关机状态的信号；
    当所述参考电压生成单元得电时，若所述总电路当前处于开机状态，则所述参考电压生成单元输出所述第二参考电压；若所述总电路当前处于关机状态，则所述参考电压生成单元输出所述第一参考电压；
    所述第一参考电压大于所述第二参考电压。
  8. 根据权利要求2所述的开关机模块，其特征在于，所述输出子模块包括充放电单元和输出单元；其中，
    所述充放电单元用于延迟所述使能电压比较子模块的输出信号进入所述输出单元，并滤除所述使能电压比较子模块的输出信号的振荡；
    所述输出单元至少基于所述使能电压比较子模块的输出信号确定自身的输出信号。
  9. 根据权利要求8所述的开关机模块，其特征在于，所述输出单元基于所述使能电压比较子模块的输出信号以及所述开关机使能端的信号确定自身的输出信号。
  10. 根据权利要求8所述的开关机模块，其特征在于，所述输出子模块还包括阻隔单元，所述阻隔单元用于阻隔所述充放电单元对所述使能电压比较子模块的内部元件的影响，和/或，增加所述使能电压比较子模块的输出信号的驱动能力。
  11. 根据权利要求4所述的开关机模块，其特征在于，所述第一判断单元包括第一二极管、第一电压钳位电路和第一增强型NMOS管；所述电源转化单元包括第一增强型PMOS管、第二增强型PMOS管、第三增强型PMOS管、第一耗尽型NMOS管、第二耗尽型NMOS管、第二电压钳位电路和第三增强型NMOS管。
  12. 根据权利要求11所述的开关机模块，其特征在于，所述第三增强型NMOS管的源极被配置为所述内部电源输出端。
  13. 根据权利要求5所述的开关机模块，其特征在于，所述第二判断单元包括第二增强型NMOS管、第四增强型PMOS管、第二二极管、第三电压钳位电路和施密特触发器；所述关闭单元包括第五增强型PMOS管。
  14. 根据权利要求10所述的开关机模块，其特征在于，所述阻隔单元包括 第一反相器、第二反向器和第三反向器；所述充放电单元包括充放电电阻和充放电电容；所述输出单元包括第七增强型PMOS管、第四增强型NMOS管、第三耗尽型NMOS管、第二三极管、上电复位组件和SR触发器。
  15. 根据权利要求14所述的开关机模块，其特征在于，所述第二三极管的基极被配置为所述输出单元的一个输入端，所述SR触发器的反相输出端被配置为所述输出单元的输出端。
PCT/CN2024/095434 2023-06-16 2024-05-27 开关机模块 Ceased WO2024255575A1 (zh)

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