WO2024255935A1 - Onduleur cmos à seuil proche à faible bruit de scintillement - Google Patents

Onduleur cmos à seuil proche à faible bruit de scintillement Download PDF

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Publication number
WO2024255935A1
WO2024255935A1 PCT/CZ2023/000029 CZ2023000029W WO2024255935A1 WO 2024255935 A1 WO2024255935 A1 WO 2024255935A1 CZ 2023000029 W CZ2023000029 W CZ 2023000029W WO 2024255935 A1 WO2024255935 A1 WO 2024255935A1
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WO
WIPO (PCT)
Prior art keywords
inverter
node
output
ring oscillator
ring
Prior art date
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Ceased
Application number
PCT/CZ2023/000029
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English (en)
Inventor
Jan Bělohoubek
Róbert LORENCZ
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Czech Technical University In Prague
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Czech Technical University In Prague
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Filing date
Publication date
Application filed by Czech Technical University In Prague filed Critical Czech Technical University In Prague
Priority to PCT/CZ2023/000029 priority Critical patent/WO2024255935A1/fr
Publication of WO2024255935A1 publication Critical patent/WO2024255935A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators

Definitions

  • the disclosed invention of a low flicker noise near-threshold CMOS inverter relates to the flicker noise suppression in CMOS, and represents the CMOS structure decreasing the flicker noise in general, and to low-noise CMOS ring oscillators utilizing the disclosed low flicker noise near-threshold CMOS inverter in particular.
  • the present invention also relates to the implementation of the CMOS inverter into control gate and ring oscillator.
  • CMOS Complementary metal-oxide-semiconductor
  • TRNG True Random Number Generators
  • PAF Physical Unclonable Functions
  • PLL Phase Locked Loop
  • the ring oscillators are typically based on the CMOS inverter structure.
  • the flicker noise is caused by impurities in the semiconductor device channel, and variations in charge trapping.
  • the flicker noise could also be increased by semiconductor degradation caused e.g. by aging or ionizing radiation.
  • the flicker noise is significant, and it dominates over white (temperature) noise in lower frequencies for upstream CMOS technology nodes. Flicker noise commonly dominates over white noise up to tens of Mhz and its significance increases for recent technology nodes, as reported e.g. in the patent US10295583B2.
  • the flicker noise in the ring oscillator translates into phase noise or jitter.
  • the above disadvantages are suppressed by the circuit structure that decreases the flicker noise by choosing the operating point of the CMOS inverter circuit in the near-threshold region for the switching device and near the saturation region for the static pull-up or pull-down device respectively.
  • the operating point is chosen in such a way, that the flicker noise is decreased significantly.
  • the choice of the operating point in the region with a low flicker level is problematic due to CMOS's complementary nature, where only PMOS or NMOS flicker noise contribution is suppressed ideally, however, the disclosed connection represents a highly efficient way to limit flicker noise contribution from both PMOS and NMOS.
  • the inverter circuit comprises semi-standard connections of PMOS and NMOS transistors. One of the complementary parts serves as a static pull-up or memei-down network respectively, while the other part as a dynamic switching part.
  • the NMOS transistor is connected by its source terminal to the inverter ground node VSS and by the drain terminal to the inverter output.
  • the gate terminal of the NMOS transistor is the inverter input node.
  • the PMOS transistor drain terminal is connected to the inverter output node, but its source terminal is connected to the SUB node.
  • the PMOS gate terminal is connected to the REF node.
  • the SUB node voltage V(SUB) is chosen in such a way, that it is lower than circuit nominal supply voltage V(VDD), but higher than the threshold voltage of the PMOS transistor V(THP): V(VDD) » V(SUB) > V(THP).
  • the REF node voltage is chosen in such a way, that it is lower than the V(SUB) voltage: V(SUB) > V(REF). Typically, V(REF) ⁇ 0.5 * V(SUB).
  • the NMOS inverter is connected by its source terminal to the inverter ground node VSS and by the drain terminal to the inverter output.
  • the gate terminal of the NMOS is connected to the REF node.
  • the PMOS inverter drain terminal is connected to the inverter output node, its source terminal is connected to the SUB node.
  • the PMOS gate terminal is the inverter input node.
  • the SUB node voltage V(SUB) is chosen in such a way, that it is lower than circuit nominal supply voltage V(VDD), but higher than the threshold voltage of the PMOS transistor V(THP): V(VDD) » V(SUB) > V(THP).
  • the REF node voltage is chosen in such a way, that it is lower than the threshold voltage of the NMOS transistor V(THN: V(REF) ⁇ V(THN). Typically, V(REF) ⁇ 0.5 * V(THN).
  • the property of the disclosed solution embodiment is that the near-threshold operation decreases the oscillation frequency - high oscillation frequencies could not be achieved, however short rings could be used for higher frequencies leading to small area footprint, while the disadvantage of the disclosed solution embodiment is, the lower noise immunity in the near-subthreshold region.
  • the Low Flicker Noise Near-Threshold CMOS Inverter comprises a semi-standard connections of PMOS transistor and NMOS transistor, where the NMOS transistor is connected by its source terminal S to the ground VSS node, and by its drain terminal D to the inverter output Y, while the PMOS transistor drain terminal D is connected to the inverter output Y.
  • the gate terminal G of the NMOS transistor is connected to the inverter input IN, and the source terminal S of the PMOS transistor is connected to the SUB node, and the PMOS transistor gate terminal G is connected to the REF node.
  • the gate terminal G of the PMOS transistor is connected to the inverter input IN node, and the source terminal S of the PMOS transistor is connected to the SUB node, and the NMOS transistor gate terminal G is connected to the REF node.
  • the inverter is configured is such a way that multiple transistors of the same type are connected in parallel or in series to the PMOS transistor or NMOS transistor, while their gate terminals G are connected to REF node and/or IN node respectively.
  • the invention also relates to a control gate comprising the CMOS inverter structure according to this invention.
  • control gate is configured in such a way that typically two, but at least one of the gate terminals G of PMOS and NMOS transistors placed in parallel or in series to the transistors in the inverter structure are bonded together creating a second input of the control gate, where the control gate implements a basic logic function, typically NAND.
  • the invention relates to a ring oscillator comprising an odd number of three or more inverters according to this invention, which are connected in the ring in such a way that the output Y of one of inverters in the ring is the output of the ring oscillator OUT.
  • the invention also relates to a ring oscillator comprising an even number of two or more inverters according to this invention and one control gate provided with the inverters and connected in the ring, wherein the output of one of inverters or the output of the control gate in the ring is the output of the ring oscillator OUT, and one of the control gate inputs is connected to the output of one of inverter outputs in the ring, and the second input of the control gate is the enable signa! ENA of the ring oscillator.
  • Fig. 1 illustrates the embodiment of the standard inverter-based ring oscillator with the incorporated control signal.
  • Fig. 3 illustrates the structure of the CMOS inverter, while Fig. 4 discloses the principle of the disclosed solution.
  • Fig. 5 gives an example of how the disclosed solution could be incorporated into a standard digital design.
  • Fig. 6 describes how the operation point of CMOS devices in the disclosed inverter is limited in a particular case.
  • Fig. 5 illustrates, how the disclosed solution could be incorporated into a standard CMOS digital design represented by a counter 302 in the VDD domain characterized by the nominal supply voltage provided through the VDD node 102.
  • the counter 302 is connected by its input to the output 303 of the comparator 301 in the VDD domain.
  • the comparator 301 inputs are reference input REF 122 and inverterbased ring oscillator 120 output OUT 102 located in the SUB supply voltage domain characterized by a near-threshold supply voltage provided through the SUB node 121. Both supply domains have a common ground VSS node 103.
  • Fig. 6 describes how the limited operation point of CMOS devices in the disclosed inverter limits the flicker noise RMS in a particular realization of the disclosed inverter in the sky 130 technology.
  • the inverter-based ring oscillator 120 comprises an odd count of inverters 101 chained in the ring in a standard way, following the structure of the ring oscillator 100 or 200 in Fig. 1 , or Fig. 2 respectively, where the output of the first is connected to the input of another, and one of the inverter outputs is the output of the ring oscillator OUT node 102.
  • the inverter 101 is the disclosed solution shown in Fig. 4 with the operating point chosen near the threshold region compared to the standard CMOS inverter in Fig. 3.
  • the disclosed inverter operation region reduction is shown in Fig. 6.
  • the disclosed Inverter 101 is composed of a PMOS transistor 111 connected by its source terminal S to the SUB node 121, by its gate terminal G to the reference input REF 122, and by its drain terminal D to the inverter output Y 113, and by an NMOS transistor 112 connected by its drain terminal D to the inverter output Y 113, by its gate terminal G to the inverter input IN 114, and by its source terminal S to the ground VSS node 103-
  • the disclosed solution has good industrial applicability, for example, in the creation of cryptographic primitives like ring-oscillator-based random number generators (TRNGs) or physically unclonable functions (PUFs), especially in low- power application-specific integrated circuits (ASICs).
  • TRNGs ring-oscillator-based random number generators
  • PAFs physically unclonable functions
  • ASICs application-specific integrated circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne la conception d'un onduleur à seuil proche supprimant le bruit de scintillement. L'onduleur est actionné à proximité du seuil, et ainsi son point de fonctionnement, déterminé par la connexion à la région de seuil proche, supprime efficacement le plancher de bruit de scintillement pour des dispositifs CMOS à canal court. Deux variantes de la connexion sont possibles : l'une avec le réseau PMOS d'excursion haute statique, et une autre avec un réseau NMOS d'excursion basse statique. La partie, qui est choisie pour être statique, réduit de manière plus significative sa contribution au bruit de scintillement.
PCT/CZ2023/000029 2023-06-16 2023-06-16 Onduleur cmos à seuil proche à faible bruit de scintillement Ceased WO2024255935A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CZ2023/000029 WO2024255935A1 (fr) 2023-06-16 2023-06-16 Onduleur cmos à seuil proche à faible bruit de scintillement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CZ2023/000029 WO2024255935A1 (fr) 2023-06-16 2023-06-16 Onduleur cmos à seuil proche à faible bruit de scintillement

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2609681B1 (fr) 2010-08-24 2015-07-22 Marvell World Trade Ltd. Oscillateur en anneau à cmos et à faible bruit
US10295583B2 (en) 2015-04-16 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit for measuring flicker noise and method of using the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2609681B1 (fr) 2010-08-24 2015-07-22 Marvell World Trade Ltd. Oscillateur en anneau à cmos et à faible bruit
US10295583B2 (en) 2015-04-16 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit for measuring flicker noise and method of using the same

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
ASSAD A.: "Phase noise and jitter in CMOS ring oscillators", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 41, no. 8, 2006, pages 1803 - 1816
CHANG, JIMMINABIDI, A. AVISVVANATHAN, C. R: "Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures", IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, vol. 41, 1971, pages 111 - 1965
NG H-T ET AL: "CMOS CURRENT STEERING LGOIC FOR LOW-VOLTAGE MIXED-SIGNAL INTEGRATEDCIRCUITS", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 5, no. 3, 1 September 1997 (1997-09-01), pages 301 - 308, XP000701407, ISSN: 1063-8210, DOI: 10.1109/92.609873 *
SINGHAI SHREY ET AL: "Process Sensor Using Current-Steering Logic Inverter based Ring Oscillator", 2022 IEEE 19TH INDIA COUNCIL INTERNATIONAL CONFERENCE (INDICON), IEEE, 24 November 2022 (2022-11-24), pages 1 - 5, XP034297071, DOI: 10.1109/INDICON56171.2022.10039927 *

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