WO2024257095A1

WO2024257095A1 - Phase shifter

Info

Publication number: WO2024257095A1
Application number: PCT/IL2024/050576
Authority: WO
Inventors: Eran Socher; Natan ERSHENGOREN
Original assignee: Ramot at Tel Aviv University Ltd
Current assignee: Ramot at Tel Aviv University Ltd
Priority date: 2023-06-11
Filing date: 2024-06-10
Publication date: 2024-12-19
Anticipated expiration: 2025-12-11
Also published as: EP4725076A1

Abstract

A phase shifter including: an upconversion mixer configured to receive a local oscillator (LO) signal having a LO frequency, and configured to receive and multiply a radio frequency (RF) input signal with the LO signal to produce a modulated signal having two sidebands around the LO frequency, an intermediate IF sideband having frequency below the LO and an image sideband; a filter connected to and configured to receive the modulated signal from the upconversion mixer and to attenuate a range of frequencies corresponding to the image sideband to select and output the intermediate frequency (IF) sideband signal; and a downconversion mixer configured to receive and multiply the IF sideband signal with a phase shifted LO signal to produce an output signal including a phase shifted version of the RF input signal.

Description

PHASE SHIFTER

RELATED APPLICATIONS

This application is an International Patent Application, which claims the benefit of priority of US Provisional Patent Application No. 63/472,310 filed 11 June 2023.

TECHNOLOGICAL FIELD

The present disclosure, in some embodiments, thereof, relates to a radio frequency (RF) phase shifter and, more particularly, but not exclusively, to a RF wideband phase shifter.

BACKGROUND ART

Background art, where each art is individually incorporated in its entirety by reference, includes the below list. In the following document these arts are referred to by number e.g. number in square brackets.

[1] Y. Gong, M. -K. Cho and J. D. Cressler, "A bi-directional, X-band 6-Bit phase shifter for phased array antennas using an active DPDT switch," 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2017, pp. 288-291.

[2] A. Hirai, T. Fujiwara, M. Tsuru, K. Mori and M. Shimozawa, "Vector- Sum Phase Shifter Using a Tunable Active gm-C Polyphase Filter," in IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 10, pp. 4091-4102, Oct. 2020.

[3] K. Kibaroglu, M. Sayginer and G. M. Rebeiz, "A Low-Cost Scalable 32- Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a $2\times 2$ Beamformer Flip-Chip Unit Cell," in IEEE Journal of Solid-State Circuits, vol. 53, no. 5, pp. 1260-1274, May 2018.

[4] K. -J. Koh and G. M. Rebeiz, "A 6-18 GHz 5-bit active phase shifter," 2010 IEEE MTT-S International Microwave Symposium, 2010.

[5] F. Qiu, H. Zhu, W. Che and Q. Xue, "A Simplified Vector-Sum Phase Shifter Topology With Low Noise Figure and High Voltage Gain," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 7, pp. 966-974, July 2022. [6] O. Kazan, Z. Hu, L. Li, A. Alhamed and G. M. Rebeiz, "An 8-Channel 5- 33-GHz Transmit Phased Array Beamforming IC With 10.8-14.7-dBm Psat for CC -, XX -, KuKu -, and KaKa -Band SATCOM," in IEEE Transactions on Microwave Theory and Techniques.

[7] S. Li and G. M. Rebeiz, "A 134-149 GHz IF Beamforming Phased-Array Receiver Channel with 6.4-7.5 dB NF Using CMOS 45nm RFSOI," 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2020, pp. 103-106.

[8] S. Afroz and Kwang-Jin Koh, "90° hybrid-coupler based phaseinterpolation phase-shifter for phased-array applications at W-band and beyond," 2016 IEEE MTT-S International Microwave Symposium (IMS), 2016, pp. 1-4.

Acknowledgement of the above references herein is not to be inferred as meaning that these are in any way relevant to the patentability of the presently disclosed subject matter.

GENERAL DESCRIPTION

Following is a non-exclusive list of some exemplary embodiments of the disclosure. The present disclosure also includes embodiments which include fewer than all the features in an example and embodiments using features from multiple examples, even if not listed below.

Example 1. A phase shifter comprising: an upconversion mixer configured to receive a local oscillator (LO) signal having a LO frequency, and configured to receive and multiply a radio frequency (RF) input signal with said LO signal to produce a modulated signal having two sidebands around said LO frequency, an intermediate (IF) sideband having frequency below said LO and an image sideband; a filter connected to and configured to receive said modulated signal from said upconversion mixer and to attenuate a range of frequencies corresponding to said image sideband to select and output said IF sideband signal; and a downconversion mixer configured to receive and multiply said IF sideband signal with a phase shifted LO signal to produce an output signal comprising a phase shifted version of said RF input signal.

Example 2. The phase shifter according to Example 1, wherein said LO signal and said phase shifted LO signal are coherent. Example 3. The phase shifter according to any one of Examples 1-2, comprising a LO source configured to provide said LO signal and said phase shifted LO signal.

Example 4. The phase shifter according to any one of Examples 1-3, wherein said filter is an active filter.

Example 5. The phase shifter according to any one of Examples 1-3, wherein said filter is a tunable filter, being configured to receive a control signal which adjusts parameters of said filter.

Example 6. The phase shifter according to any one of Examples 3-5, wherein said LO source is a tunable frequency source, being configured to receive a control signal which adjusts frequency of said LO signal and said phase shifted LO signal.

Example 7. The phase shifter according to any one of Examples 4-6, wherein said filter comprises at least two amplification stages.

Example 8. The phase shifter according to Example 5, wherein said at least two amplification stages include one or both of a cross couple amplification stage and a cascode amplification stage.

Example 9. The phase shifter according to Example 5, wherein said at least two amplification stages include a cross couple amplification stage receiving said IF sideband signal followed a cascode amplification stage outputting a filtered signal towards said downconversion mixer.

Example 10. The phase shifter according to any one of Examples 5-9, wherein said filter comprises one or more interstage transformer.

Example 11. The phase shifter according to Example 10, wherein said one or more interstage transformer comprises a filter input transformer connecting said upconversion mixer and said filter.

Example 12. The phase shifter according to any one of Examples 10-11, wherein said one or more interstage transformer comprises a first interstage transformer connecting said at least two amplification stages.

Example 13. The phase shifter according to Example 12, wherein said first interstage transformer is a low-k transformer.

Example 14. The phase shifter according to any one of Examples 10-13, wherein said one or more interstage transformer comprises a second interstage transformer connecting a second of said at least two amplification stages to upconversion mixer.

Example 15. The phase shifter according to Example 14, wherein said second interstage transformer is a low-k transformer.

Example 16. The phase shifter according to any one of Examples 4-9, wherein said LO source comprises an oscillator circuitry configured to generate said LO signal and a voltage modulator configured to phase shift said LO signal to provide said phase shifted LO signal.

Example 17. The phase shifter according to Example 16, wherein said voltage modulator is configured to receive a control signal and to phase shift said LO signal according to said control signal.

Example 18. The phase shifter according to any one of Examples 16-17, wherein said oscillator circuitry comprises a quadrature voltage controlled oscillator (QVCO).

Example 19. The phase shifter according to Example 18, wherein QVCO is a magnetically coupled QVCO.

Example 20. The phase shifter according to Example 19, wherein said voltage modulator comprises at least two variable gain amplifiers (VGAs).

Example 21. The phase shifter according to any one of Examples 18-19, wherein said LO source comprises: a first buffer connecting said QVCO and said upconversion mixer; and a second buffer connecting said QVCO and said voltage modulator.

Example 22. The phase shifter according to any one of Examples 1-21, wherein one or both of said upconversion mixer and said downconversion mixer comprise a common gate differential input stage.

Example 23. The phase shifter according to any one of Examples 1-22, wherein one or both of said upconversion mixer and said downconversion mixer comprise peaking inductors.

Example 24. A method of wideband phase shifting comprising: receiving an input radiofrequency (RF) signal; up-converting said RF signal by multiplication with a local oscillator (LO) signal having a LO frequency, to produce a modulated signal; filtering said modulated signal to attenuate a sideband to said LO frequency to produce an intermediate frequency (IF) signal having frequencies higher than frequencies of said RF signal and lower than said LO frequency; down-converting said IF signal by multiplication with a phase shifted LO signal to provide a phase shifted version of said input RF signal.

Example 25. The method according to Example 24, comprising generating said LO signal and said phase shifted LO signal.

Example 26. The method according to any one of Examples 24-25, wherein said LO signal and said phase shifted LO signal are coherent.

Example 27. The method according to any one of Examples 25-26, wherein said generating is by a selected phase, said phase shifted version of said input RF signal being phase shifted by said selected phase.

Example 28. The method according to any one of Examples 25-27, wherein said generating comprises receiving a control signal specifying said selected phase.

Unless otherwise defined, all technical and/or scientific terms used within this document have meaning as commonly understood by one of ordinary skill in the art/s to which the present disclosure pertains. Methods and/or materials similar or equivalent to those described herein can be used in the practice and/or testing of embodiments of the present disclosure, and exemplary methods and/or materials are described below. Regarding exemplary embodiments described below, the materials, methods, and examples are illustrative and are not intended to be necessarily limiting.

Some embodiments of the present disclosure are embodied as a system, method, or computer program product. For example, some embodiments of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” and/or “system.”

Implementation of the method and/or system of some embodiments of the present disclosure can involve performing and/or completing selected tasks manually, automatically, or a combination thereof. According to actual instrumentation and/or equipment of some embodiments of the method and/or system of the present disclosure, several selected tasks could be implemented by hardware, by software or by firmware and/or by a combination thereof, e.g., using an operating system. For example, hardware for performing selected tasks according to some embodiments of the present disclosure could be implemented as a chip or a circuit. As software, selected tasks according to some embodiments of the present disclosure could be implemented as a plurality of software instructions being executed by a computational device e.g., using any suitable operating system.

In some embodiments, one or more tasks according to some exemplary embodiments of method and/or system as described herein are performed by a data processor, such as a computing platform for executing a plurality of instructions. Optionally, the data processor includes a volatile memory for storing instructions and/or data and/or a non-volatile storage e.g., for storing instructions and/or data. Optionally, a network connection is provided as well. User interface/s e.g., display/s and/or user input device/s are optionally provided.

Some embodiments of the present disclosure may be described below with reference to flowchart illustrations and/or block diagrams. For example illustrating exemplary methods and/or apparatus (systems) and/or and computer program products according to embodiments of the present disclosure. It will be understood that each step of the flowchart illustrations and/or block of the block diagrams, and/or combinations of steps in the flowchart illustrations and/or blocks in the block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general -purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart steps and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer readable medium that can direct a computer (e.g., in a memory, local and/or hosted at the cloud), other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium can be used to produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be run by one or more computational device to cause a series of operational steps to be performed e.g., on the computational device, other programmable apparatus and/or other devices to produce a computer implemented process such that the instructions which execute provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

Some of the methods described herein are generally designed only for use by a computer, and may not be feasible and/or practical for performing purely manually, by a human expert. A human expert who wanted to manually perform similar tasks, might be expected to use different methods, e.g., making use of expert knowledge and/or the pattern recognition capabilities of the human brain, potentially more efficient than manually going through the steps of the methods described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to better understand the subject matter that is disclosed herein and to exemplify how it may be carried out in practice, embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

FIG. 1 A is a simplified schematic illustration of a phase shifter, according to some embodiments of the disclosure;

FIGs. 1B-E are simplified schematics signals in a frequency domain, according to some embodiments of the disclosure;

FIG. 2 is a simplified schematic of a LO source, according to some embodiments of the disclosure;

FIG. 3 is a simplified schematic of a method of phase shifting, according to some embodiments of the disclosure;

FIG. 4 is simplified schematic of a phase shifter, according to some embodiments of the disclosure;

FIG. 5 is a simplified schematic of a portion of a phase shifter according to some embodiments of the disclosure;

FIG. 6 is a simplified schematic of a half CG input stage, according to some embodiments of the disclosure;

FIG. 7 is a simplified schematic lumped elements equivalent model for an input balun, according to some embodiments of the disclosure; FIG. 8 is a simplified schematic of a down-conversion mixer, according to some embodiments of the disclosure;

FIG. 9 is a simplified schematic of an output balun, according to some embodiments of the disclosure;

FIG. 10 is a simplified schematic of a filter, according to some embodiments of the disclosure;

FIG. 11 is a simplified schematic of a quadrature LO signal generator, according to some embodiments of the disclosure;

FIG. 12 is a simplified schematic of a buffer, according to some embodiments of the disclosure;

FIG. 13 is a simplified schematic of a buffer, according to some embodiments of the disclosure;

FIG. 14A is a simplified schematic of a vector modulator, according to some embodiments of the disclosure;

FIG. 14B is a simplified schematic of phase quadrature control mapping, according to some embodiments of the disclosure;

FIG. 15A is a microphotograph of a fabricated die, according to some embodiments of the disclosure;

FIG. 15B is a processed version of the microphotograph of FIG. 15 A, according to some embodiments of the disclosure

FIG. 16 illustrates measured and simulated (dashed) return losses of the input and output ports for all 7 bit states, according to some embodiments of the disclosure;

FIG. 17 illustrates measured and simulated (dashed) gain for all 7 bit states, according to some embodiments of the disclosure;

FIG. 18 illustrates a measured 7 bit phase response relative to 0° state, according to some embodiments of the disclosure;

FIG. 19 illustrates Amplitude RMS error and Phase RMS error, according to some embodiments of the disclosure; and

FIG. 20 is a simplified schematic of a phased array system, according to some embodiments of the disclosure. In some embodiments, although non-limiting, in different figures, like numerals are used to refer to like elements, for example, element 108 in FIG. 1 corresponding to element 408 in FIG. 4.

DETAILED DESCRIPTION OF EMBODIMENTS

Overview

A broad aspect of some embodiments of the disclosure relates to phase shifting, where a local oscillator (LO) is used to up-convert a radio frequency (RF) input signal to an intermediate frequency (IF) which is above the frequency of the input signal but below that of the LO. A phase shifted LO signal is then used to down-convert the IF signal to provide a phase shifted version of the RF input signal.

Modulation of the RF signal (e.g. by multiplication of the signal with the LO e.g. at an upconversion mixer) may produce a signal having both an IF portion and an image band with higher frequency than the LO. In some embodiments, the phase shifter includes a filter to reduce the modulated RF input signal (the RF signal which has been up- converted by the LO and which may include both the IF portion and the image band thereof) to provide the IF signal (e.g. without the image band or where the image band has been attenuated) for down-conversion. Where down-conversion, in some embodiments is where the phase shifted LO signal is multiplied, e.g. at a downconversion mixer, with the IF signal (modulated filtered input signal) to provide an RF phase shifted output signal. Where, in some embodiments, the filter attenuates the image band from the modulated RF signal. For example, to reduce image band phase shift interference on phase shift of the outputted phase shifted RF signal.

In some embodiments, the filter is an active filter providing, as well as attenuation of non-desired frequencies (e.g. frequencies of the image band), amplification to the IF portion of the modulated signal.

In some embodiments, the filter includes more than one amplification stage. For example, 2-3 amplification stages. In an exemplary embodiment, the filter includes a cross couple amplification stage and a cascode amplification stage. The filter may be non-tunable.

Alternatively, in some embodiments, the filter is tunable, where frequencies attenuated and/or amplified by the filter may be adjustable e.g. via a control signal to the filter. A potential benefit of the filter being tunable, for example, being the ability to tune attenuation frequencies of the filter to real image band, for example, as opposed to an expected image band determined using expected LO and/or RF signal frequencies, tuning of the filter may be used to compensate for non-ideal behavior/s e.g. fabrication mismatch, where fabricated component/s have param eter/s varying from expected and/or designed according to limitations of fabrication accuracies. Tuning may be alternatively or additionally used to compensate for variation in system param eter/s associated with temperature changes and/or fluctuation of electrical supply to the system (e.g. voltage variations).

In some embodiments, the phase shifter may be used for a wide range of input frequency signals, also herein termed being a “wideband” phase shifter, the frequencies being, e.g. 2-24GHz, 2-18GHz, 6-18GHz, and 6-22 GHz, or lower or higher or intermediate ranges or frequencies. In some embodiments, these input frequencies are catered to by the phase shifter without adjustment and/or tuning e.g. of the LO.

In an exemplary embodiment, the phase shifter is designed for use with an input bandwidth of 6-22 GH.

In some embodiments, the LO is a mm-wave local oscillator e.g. having frequency of 50-100GHz, or about 84 GHz, or lower or higher or intermediate ranges or frequencies.

Although description in this document is with generally with respect to phase shifting of RF frequency signals, it should be understood that embodiments described herein may be used in phase shifting of input signals having other frequencies, e.g. lower than RF frequencies. In particular, in some embodiments where the phase shifter is used to shift phase for lower frequencies, one or more of the passive elements (e.g. inductors, resistors) and/or impedance matching circuitry (e.g. transformers in the exemplary described phase shifter herein), may be replaced by transistor-implemented equivalents potentially reducing footprint of the circuit.

A potential benefit of using a LO for phase shifting for a bandwidth (range of input signal frequencies) is that filtering and phase shifting is performed for narrowband signals (e.g. a narrowband around the LO frequency) which are higher in frequency than that of the input RF frequencies. Where, in some embodiments, narrowband is defined as the bandwidth being up to 10% of the LO frequency. In some embodiments, the upconversion and downconversion mixers as well as any input stage and/or output stage circuitry operates for the entire bandwidth which may be wideband e.g. as detailed above.

In some embodiments, the LO signal and the phase shifted LO signal are coherent e.g. have a single source. In some embodiments phase shifting of the LO is performed by a quadrature voltage-controlled oscillator (QVCO) and a vector modulator (VM) (also herein termed “interpolation circuit”). In some embodiments, LO phase shifting circuitry is on-chip e.g. a same chip (also herein termed “integrated circuit”) which hosts one or more of upconversion circuitry, filtering circuitry, and downconversion circuitry. In some embodiments, the QVCO is a magnetically coupled QVCO. Potential advantage/s of which include reduced power consumption and/or improved oscillation performance (e.g. in comparison to that of an actively coupled QVCO having a higher number of interconnections).

In some embodiments, the LO source includes buffers on one or both sides of the QVCO. For example, on an upconversion side between the QVCO and the upconversion mixer. For example, on a downconversion side between the QVCO and the vector modulator. A potential benefit of the buffer/s is maintained consistency of the LO oscillation frequency upon loading of the upconversion mixer and/or vector modulator.

In some embodiments, the LO source is tunable e.g. to compensate for fabrication inaccuracies and/or for example, where the filter is non-tunable. Tuning of the LO potentially ensures accuracy of filtering of the image band from the modulated signal e.g. the IF signal is tuned (by tuning of the LO) to the pass-band of the filter e.g. where the filter is non-tunable.

In some embodiments, the phase shifter includes one or more differential stage and/or differential circuitry. In an exemplary embodiment, each element of the phase shifter includes differential circuitry. A potential benefit being independence of functionality of the circuitry from grounding.

In some embodiments, impedance matching circuitry is employed between one or more elements of the phase shifter. Where, in some embodiments, impedance matching circuitry between element/s includes a transformer. A potential benefit of use of transformer/s as impedance matching circuitry is ease of biasing through center taps of coupled inductors of the transformer. In some embodiments, inductors and/or capacitors are used to provide impedance matching circuitry. In some embodiments, phase shifters as described in this document are used in one or more of X-, Ku-, and K-band phased arrays.

In some embodiments, phase shifters as described in this document are used as RF frontends (e.g. for phased array systems) for one or more of high-data-rate broadband communications, high-resolution radar, and precise positioning. For example, for used in one or more of, weather monitoring, air traffic control, marine vessel traffic management, the defense and military sectors, and vehicle speed detection e.g. for law enforcement.

In some embodiments, the technique of phase shifting as described in this document is used for generating wideband QAM signals (quadrature amplitude modulation). Where, for example, in some embodiments, wideband amplitude control is added to the phase control feature of the phase shifter. For example where amplitude control may be implemented at variable gain amplifiers of the LO source e.g. by using variable gain amplifiers (e.g. I Q VGAs) to control both phase and amplitude of the combined signal and amplitude as well.

Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the following description and/or illustrated in the drawings and/or the Examples. The invention is capable of other embodiments or of being practiced or carried out in various ways.

Exemplary phase shifter

FIG. 1 A is a simplified schematic illustration of a phase shifter 100, according to some embodiments of the disclosure.

FIGs. 1B-E are simplified schematics signals in a frequency domain, according to some embodiments of the disclosure.

In some embodiments, FIGs. 1B-D illustrate signals at different portions of the phase shifter, where like numerals on FIG. 1 A and FIGs. 1B-D, in some embodiments, indicate connection between the frequency domain signal illustrations and the circuit stage.

Referring to FIG. 1A, in some embodiments, phase shifter 100 includes a upconversion mixer 104, a downconversion mixer 112, a filter 108, and a LO source 116. Referring to both FIG. 1A and FIGs. 1B-E: In some embodiments, a LO signal fro produced by LO source 116 is used to modulate a RF input signal f_RF 102 (having RF frequency/ies) received at an input 136 to provide a signal 106 including a higher intermediate frequency (IF) band f_RF-f_LO 106. Where, in some embodiments, modulation is performed by an upconversion mixer 104 receiving both the LO signal and the RF signal 102.

Modulated signal 106 then passes through filter 108 which attenuates an image band 107 (including frequencies fRF+fLo).

Then the same LO frequency is used again (e.g. provided by LO source 116) though with a phase shift f_LO+Φ, to down-convert the filtered signal 110 back into an RF output signal 114 which is phase shifted from the RF input signal 102 has RF frequency/ies of the RF input signal 102 e.g., for outputting through an output 146.

In some embodiments, phase shifter 100 includes control circuitry 164 which may be hosted on-chip or which may include portion/s which are off-chip. Control circuitry may provide control signals to one or more of LO source 116 and filter 108.

In some embodiments, LO source 116 receives one or more control signal 117 e.g. from control circuitry 164.

LO source control signal/s 117 may include a phase shift control signal, where a phase shift Φ to the phase shifted LO signal f_LO+Φ (e.g. and thereby to RF input signal 102 to provide the outputted RF phase shifted signal 114) may be generated at LO source 116 based on the phase shift control signal. The phase shift control signal may be generated and provided to LO source 116 by control circuitry 164.

If signals (e.g. RF input signal and/or LO signal) are modeled as complex signals, the up and down conversion steps would yield an ideal phase shifter at the RF band, for example, according to:

where k_LOup and k_LOdown depend on the LO amplitude and mixer 104 topologies.

However, in practice, signals are real, so considering the input RF signal as:

Assuming an LO signal used for upconversion:

Multiplying the input RF signal v_RFin of 3.5 with the LO signal v_LOup of 3.6 a resulting mm-wave IF signal takes the form of:

where A_IF = A_RFink_LOup.

Possible harmonic effects that result in the IF signals well outside the band of interest are neglected here.

If subsequent downconversion of the signal is performed using the same LO frequency, but phase shifted:

The relevant terms in the original RF band become:

Without filtering, the same RF frequency is achieved for two up/down conversion processes. The first is (f_RF + f_LO) — f_LO and the second is f_LO — (f_LO — f_RF). Thus, the phase shift in each term has an opposite sign. The total phase shift at the output, without filtering, is therefore ideally completely rejected except for singular cases. For the phase shifting concept to work, in some embodiments, one of the contributions of the modulated RF signal is filtered out at the IF domain. For example, by filter 108.

To be able to amplify the lower IF band (f_L0 — f_RF), and reject the higher IF band (f_LO + f_RF ), the RF band must have a minimum RF frequency, which would be half the two IF band separation. The RF output signal would then take the form of:

With the 2f_LO — f_RF term easily filtered out, leaving the original RF band phase shifted exactly by (p, independent of frequency.

In reality, rejection of the image higher IF band is finite compared with the desired lower IF band, resulting in an output RF signal comprised of two contributions at f_RF with two different amplitudes, A_D and A_I respectively, with opposite phases:

where image rejection is defined as:

The sum can be visually represented as phasors, which theoretically represents a phenomenon that occurs at the output of the downconversion mixer. Thus, trigonometry yields that the resulting total phase of the output, including the image, is given according to:

Defining the phase error as yields:

Optionally, in some embodiments, one or more portion of phase shifter 100 is tuned. Where, for example, frequency response of the portion/s are adjusted according to a control signal which may be generated by control circuitry 164.

In some embodiments, filter 108 is tunable, receiving a filter control signal 166 from control circuitry 164. Where, in some embodiments, filter 108 frequency response/s are controlled to compensate for nonideal behavior e.g. associated with fabrication accuracy limitations, LO frequency fluctuation and/or inaccuracy, and/or temperature and/or supply voltage variations.

Exemplary LO source

FIG. 2 is a simplified schematic of a LO source 216, according to some embodiments of the disclosure.

In some embodiments, LO source 216 is employed as LO source 116 for phase shifter 100 FIG. 1.

In some embodiments, LO source 216 includes a single LO circuitry 120. A potential benefit being that both LO signals, original ILO, and phase shifted to+cp are coherent.

In some embodiments, LO circuitry 220 produces a fixed frequency signal. Alternatively, in some embodiments, the local oscillator is tunable. Where, in some embodiments, LO circuitry 220 includes a voltage controlled local oscillator. Where, for example, LO circuitry 220 receives a LO tuning control signal 217a, for example, from a controller (e.g. controller 164 FIG. 1). In some embodiments, tuning of the LO source includes one or more feature as described regarding quadrature LO signal generator 1120, FIG. 11. In some embodiments, LO circuitry 220 includes a quadrature voltage controlled local oscillator (QVCO) e.g. a single QVCO configured to provide quadrature oscillator signals e.g. two coherent oscillator signals out of phase with each other.

In some embodiments, QVCO 220 is a free-running QVCO lacking a phase locking loop. Without wanting to be bound by theory, it is theorized that use of a single QVCO enables a free-running QVCO without a phase locking loop. A potential benefit of a free-running QVCO and/or a QVCO without a phase locking loop is potentially reduced layout area requirement/s and/or power requirement/s.

In some embodiments, a phase shift to the LO signal is provided by a vector modulator (VM) 230. Where, in some embodiments, VM 230 receives a phase shift control signal 217b, a phase shift to the LO signal by VM 230 being based on and/or controlled by control signal 217b.

In some embodiments, the phase shift to the LO signal is in addition to that provided by the two signals produced by the QVCO. Where the LO signal is provided by a simple oscillator (e.g. voltage controlled oscillator), the phase change may solely be supplied by VM 230.

A potential advantage of a QVCO (e.g. in comparison to a simple VCO LO) is that QVCO provides control of to 360° LO phase shift e.g. through the use of vector modulation (e.g. at VM 230). Where, for example, the QVCO produces signals having phase difference of one of 0, 90, 180, and 270 degrees and VM 230 provides additional phase shifts of less than 90 degrees to interpolate between these angles and thereby provide control up to a wide range of phase angles e.g. up to 360°.

FIG. 2 In some embodiments, VM 230 includes two variable gain amplifiers (VGAs). In some embodiments, VGAs enable control of gain to in-phase (I) and quadrature phase (Q) portions of the LO. Where the gain control, with summing of the of the I and Q portions enables control of amplitude and phase of the LO signal. The VGA infrastructure enabling phase shifting of the LO with constant amplitude but also quadrature amplitude modulation QAM. In some embodiments, the VGAs are designed using Gilbert cells. In some embodiments, the VGAs are driven by quadrature oscillator signals from QVCO 420.

In some embodiments, LO source 216 includes one or more buffer 234, 236. For example, an upconversion side buffer 234 between QVCO 220 and the upconversion mixer 104. For example, on a downconversion side between QVCO 220 and VM 230. A potential benefit of buffer/s 234, 236 is consistency of the LO oscillation frequency e.g. upon loading of upconversion mixer 104 (FIG. 1 A) and/or vector modulator 230. In some embodiments, one or both of buffers include a differential pair having an inductive load. Where the buffer differential pair receives bias from outputs of QVCO 220.

Exemplary phase shifting method

FIG. 3 is a simplified schematic of a method of phase shifting, according to some embodiments of the disclosure.

At 300, in some embodiments, a radio frequency (RF) input signal is received.

At 302, in some embodiments the RF input signal is multiplied with a local oscillator (LO) to produce a modulated signal.

At 304, in some embodiments, the modulated signal is filtered to provide an intermediate frequency (IF) signal.

At 306, in some embodiments, the IF signal is multiplied with a phase shifted local oscillator signal to produce a phase shifted version of the RF input signal which may then be outputted.

Exemplary phase shifter structure

FIG. 4 is simplified schematic of a phase shifter 400, according to some embodiments of the disclosure.

In some embodiments, phase shifter 400 includes one or more of an upconversion mixer 404, a filter 408, a LO source 416, and a downconversion mixer 438, one or more of which having one or more feature of corresponding elements upconversion mixer 104, filter 108, LO source 116, and downconversion mixer 138 respectively of phase shifter 100 FIG. 1.

In some embodiments, upconversion mixer 404 includes an active mixer. A potential advantage of an active mixer (e.g. providing amplification as well as mixing) is a reduced LO amplitude requirement on the LO signal input to mixer/s e.g. in comparison to a mixer without amplification. Potential advantage/s of mixer 404 being active include the ability of the mixer to compensate for losses (e.g. interconnect and/or matching network losses) and/or the ability to adjust (e.g. amplify) the local oscillator and/or input signal levels.

In some embodiments, filter 408 is an active filter and may include more than one amplification stage. For example, 2-5, or 2-3, or lower or higher or intermediate numbers of amplification stages, or in an exemplary embodiment, 2 amplification stages; first amplification stage 422, and second amplification stage 424.

In some embodiments, filter amplification stages 422, 424 include one or more cross couple stage. In some embodiments, amplification stages 422, 424 include one or more cascode stage. In some embodiments, amplification stages 422, 424 include a cross couple stage and a cascode stage. In an exemplary embodiment, first amplification stage 422 includes a cross couple stage and second amplification stage 424 includes a cascode stage (alternatively, in some embodiments, the first amplification stage 422 includes a cascode and the second a cross couple).

In some embodiments, filter 408 includes impedance matching circuitry e.g. connecting filter element/s. For example, impedance matching circuitry between amplification stages 422, 424 and/or at an input to the filter (e.g. between upconversion mixer 404 and filter 408) and/or at an output of the filter (e.g. between filter 408 and downconversion mixer 412). In some embodiments, one or more of the impedance matching circuitry/ies includes a transformer. For example, in some embodiments, filter 408 includes a first interstage transformer 440 XF₂. For example, in some embodiments, filter 408 includes a second interstage transformer 442 XF3. For example, in some embodiments, filter 408 includes a third interstage transformer 444 XF4.

In some embodiments, first interstage transformer 440 is a low-k transformer. Where, k is 0.1-0.5, or lower or higher or intermediate values or ranges. Where low-k refers to relatively weaker coupling between inductors of the transformer, to increase bandwidth of the transformer. In some embodiments, implemented by positioning the inductor coil centers further apart and/or non-concentrically e.g. the inductor conductor portions overlapping less.

A potential advantage of low-k transformer 440 being attenuation of the effect of capacitance at an output of up-convertor 460 (e.g. at frequency/ies of interest). Potential advantages of attenuation of the effect of capacitance include one or more of relaxing of voltage headroom issues (where “headroom” may refer to ability for amplification to be as expected according to amplifier features instead of limited by voltage supply to the amplifier), raising of the conversion gain and operation bandwidth. In some embodiments, transformer 440 is designed to load an input of the filter amplifier stage with optimal input impedance. In some embodiments phase shifter 400 includes a LO source 416 configured to generate both a LO signal I'LO and a phase shifted LO signal fLo+<|>. For example, according to one or more feature as described regarding and/or illustrated in FIG. 2.

In some embodiments, LO source 416 includes an oscillator e.g. including oscillator circuitry (e.g. voltage controlled oscillator VCO e.g. QVOC) or circuitry configured to receive an oscillator signal (e.g. from off-chip e.g. a hybrid structure).

In some embodiments, LO source 416 includes circuitry (e.g. including a vector modulator 430) configured to receive and phase shift the oscillator signal/s according to a received control signal (for example, a phase shift control signal e.g. including one or more features of phase shift control 217b signal FIG. 2) .

In some embodiments, the oscillator signal is generated and/or received and then converted into a quadrature oscillator signal e.g. by an on-chip QVOC 420. Where, in some embodiments, a received oscillator signal from an off-chip source, is converted into a quadrature oscillator signal on-chip.

In some embodiments, LO source 416 includes one or more buffers 450, 452. Where, in some embodiments, a upconversion side buffer 450 includes driver circuitry 434 and optionally, a transformer 448 XF₇. Where, in some embodiments, a voltage modulator side buffer 452 includes driver circuitry 426 and, optionally, transformers 428 XF₈ XF₉. In some embodiments, vector modulator 430 includes variable gain amplifiers VGAs 430 VGAi VGA2. In some embodiments, LO source 416 includes a VM output transformer 432 XF10.

In some embodiments, vector modulator 430 poses a variable load to LO source 416. Where, potentially, state selection of VM 430 may detune the LO frequency. In some embodiments, to prevent loading of the QVCO (e.g. by the VM) QVCO is isolated from dynamic changes in the following stages e.g. to prevent influences on its performance:

In some embodiments, QVCO includes two buffers buffer 450, buffer 452 Where, in some embodiments, buffer design isolates QVCOs and, in some embodiments, provide amplification to QVCO signals e.g. power-divided signals for up-conversion and/or down-conver si on .

In some embodiments, amplifiers for both buffers 450, 454 have a same device size and/or biasing. In some embodiments, buffer gates are connected directly to output nodes of the QVCO potentially simplifying layout and/or avoiding additional interconnects. In some embodiments, buffers include a CS (common source) amplifier topology e.g. associated with CGD (gate-drain capacitance) feedback.

In some embodiments, phase shifter 400 includes a downconversion mixer 412. Where, in some embodiments, downconversion mixer 412 is an active mixer e.g. including amplification circuitry.

In some embodiments, phase shifter 400 includes input circuitry 418 and/or output circuitry 414. In some embodiments, one or both of the circuitries 418, 414 convert single- ended signals to differential signals. In some embodiments, one or both of circuitries 418, 414 are designed for compatibility with external element/s.

For example, in design of an exemplary chip (e.g. as described in the “Exemplary measurement results” section of this document) measurement setup limitations required use of a single-ended output. Where an active balun 428 was added as a final stage. Active balun 428, in some embodiments, includes a differential input and a PMOS active load (e.g. despite potential associated linearity limitation/s).

Optionally, in some embodiments, phase shifter 400 includes an output balun 438. Which, in some embodiments, is an active output balun 438. Where, in some embodiments, output balun 438 is disposed between an output of downconversion mixer 412 and a phase shifter output 446.

Optionally, in some embodiments, input circuitry 418 includes an input balun 418. Which, in some embodiments, is a passive input balun 418 (also referred to in this document as XFi). Where, in some embodiments, input balun 418 is disposed between a phase shifter input 436 receiving an input signal 402 and upconversion mixer 404. In some embodiments, input balun 418 is implemented with transformer circuitry (e.g. as illustrated in FIG. 15 A). Alternatively, in some embodiments, input balun 458 is implemented using resistors and transistors which reduces chip area required for the input balun but potentially associated with one or more of increased noise, reduced linearity, and higher power consumption.

Exemplary Upconversion Mixer

FIG. 5 is a simplified schematic of a portion of a phase shifter 500 according to some embodiments of the disclosure.

FIG. 5, in some embodiments, illustrates an exemplary upconversion mixer 504, connected to an input balun 518 and to an interstage transformer 540. Where upconversion mixer 504, in some embodiments, is employed as upconversion mixer 104 of phase shifter 100 FIG. 1.

Where upconversion mixer 504, in some embodiments, is employed as upconversion mixer 404 of phase shifter 400 FIG. 4.

Where input balun 518 and/or interstage transformer 540, in some embodiments, are employed, respectively as input balun 418 and/or interstage transformer 440 of phase shifter 400 FIG. 4. In some embodiments, mixer 504 is an active mixer.

In some embodiments, a Gilbert cell type mixer is used in upconversion mixer 504. Where Gilbert cell type mixers generally are frequency mixers which produce output signals which are proportional to the product of two input signals. Where the input and outputs may be differential signals.

In some embodiments, a modified Gilbert cell is used, a potential advantage of which is extended operational bandwidth (e.g. in comparison to a conventional Gilbert cell). In some embodiments, mixer 504 is a Gilbert cell mixer with a common gate (CG) input stage 554 e.g. as opposed to a common source (CS) stage of a conventional Gilbert cell.

In some embodiments, mixer 504 includes an RF input stage 554 and a LO stage 556 (e.g. an LO quad including four transistors M_3-6).

In some embodiments, upconversion mixer 504 includes circuitry configured to compensate parasitic capacitance between RF input stage 554 and LO stage 566, which potentially degrades performance bandwidth of the upconversion mixer, for example, compensating circuitry including serial peaking inductors Li, L2.

In some embodiments, upconversion mixer 504 includes shunt inductors. Where, in some embodiments, the shunt inductor/s are realized using a second coil of the input balun 518.

FIG. 6 is a simplified schematic of a half CG input stage, according to some embodiments of the disclosure.

Input impedance for half CG input stage of FIG. 6 may be derived as:

At a resonance frequency, the input impedance will be approximately 1/gm, e.g. from equation (3.15), providing broadband impedance matching. Exemplary input circuitry

In some embodiments, a phase shifter according to embodiments of this disclosure includes input circuitry.

For example, in some embodiments, an input RF signal fRF is a single-ended signal which is converted into a differential input by input circuitry e.g. for compatibility with double-balanced element/s of the phase shifter.

Referring back to FIG. 5, in some embodiments, an input balun XFi 518 transforms a single-ended signal VIN (e.g. corresponding to input signal 402 FIG. 4) into a differential signal.

In some embodiments, input balun 518 performs signal transformation. In some embodiments, input balun (e.g. input balun second coils) includes shunt inductors (e.g. to compensate parasitic capacitance of upconversion mixer differential CG input stage 554).

In some embodiments, (e.g. depending on realized layout size and/or shape of input balun 518 on a phase shifter integrated circuit (IC)), input balun parasitics (e.g. parasitic capacitance) are taken into account when designing input balun 518.

FIG. 7 is a simplified schematic lumped elements equivalent model 758 for an input balun, according to some embodiments of the disclosure.

In some embodiments, equivalent lumped model 758 is built by fitting model performance parameter curves to simulation parameters for the input balun.

A mutual resistive coupling factor kR_e and a reactive coupling factor ki_m may be calculated according to:

where Z₁₂, Z₂₂, Z₁₁ are Z parameters of two port network transformer, M is mutual inductance of the transformer, and Lp with Ls are inductances of the primary and secondary coils respectively.

Without wanting to be bound by theory, it is theorized that the mutual reactive coupling factor ki_m equals a mutual magnetic coupling factor Z₁₂ at low frequencies, but kim deviates from the latter at high frequencies due to the parasitic capacitances between the primary and secondary coils and between the coils and substrate. The mutual resistive coupling factor k_Re approaches zero at very low frequencies where the coupling between inductors Lp, Ls is predominantly inductive. At high frequencies, however, k_Re assumes a finite nonzero value e.g. associated with the parasitic capacitances (between the primary and secondary coils and between the coils and substrate) and/or eddy currents in the substrate.

Exemplary up-convertor to filter interstage transformer

Referring back to FIG. 5, in some embodiments, a phase shifter according to embodiments of this disclosure includes an interstage transformer 540 (also herein termed “XF₂”) connecting an up-convertor and a filter (e.g. up-convertor 104 and filter 108 FIG. 100, e.g. up-convertor 404 and filter 408 FIG. 400).

Peaking inductors L1.2 (also herein termed “interstage inductors”), with the parasitic capacitance of upconversion mixer 504 transistors M_1-2, M_3-6, form a π network. Where the π network results in a peaking in frequency response, potentially associated with RF input signal bandwidth extension.

In some embodiments, interstage transformer 540 XF₂ is a low-k transformer. A potential advantage of which is improved mixer performance, due to the output LO transistor capacitance (e.g. capacitance of capacitors M_3-6). Where low-k transformer 540 may cancel and/or compensate for the output LO transistor capacitance at the frequencies of interest. This capacitance, in some embodiments, is additionally or alternatively moderated by reducing a size of the LO transistors M_3-6. However, this is a design decision, regarding a tradeoff as reducing the size of LO switches (transistors) is associated with increasing a noise figure of the mixer.

Potentially, XF₂ transformer one or more of; relaxes voltage headroom issues, raises a conversion gain and/or operation bandwidth e.g. by attenuating the capacitance at the output node (VUP+, Vup.). In some embodiments, XF₂ transformer is designed to load the input of a successive stage (e.g. filter 408 e.g. amplifier 422) with optimal input impedance. Where, for example, the transformer provides conjugate impedance matching between the output of the previous stage to the input of the next stage

Exemplary downconversion mixer

FIG. 8 is a simplified schematic of a downconversion mixer 812, according to some embodiments of the disclosure. In some embodiments, downconversion mixer 812 includes one or more feature of upconversion mixer 504 FIG. 5. Where downconversion mixer 812 differs from upconversion mixer 504, in some embodiments, at a load stage.

In some embodiments, downconversion mixer 812 includes an IF input stage 862 and a LO stage 860. Where, in some embodiments, an IF differential signal Vcas+ Vcas- (e.g. outputted by a filter e.g. filter 408 FIG. 4) is applied to gates of transistors M15-16 of IF input stage 862.

In some embodiments, downconversion mixer 812 includes peaking inductors

L5-6 e.g. to compensate for drain capacitances of switching quad 860. A potential benefit of peaking inductors L5-6 is improvement of an operation band of outputted RF frequencies from the mixer and/or received IF frequencies (e.g. as it is theorized that parasitic capacitance at the output of the switching transistors reduces the operation band).

Exemplary output balun

FIG. 9 is a simplified schematic of an output balun, according to some embodiments of the disclosure.

In some embodiments output balun 938 is an exemplary implementation of output balun 438 FIG. 4. In some embodiments, output balun 938 is an active output balun 938. A potential benefit of output balun 938 is simple realization in the frequencies of interest, without having additional matching networks.

In some embodiments, a size of the transistors M_21-22 and M_23-24 is tuned so that an output real impedance part, together with parasitic pad resistance, will match an output load impedance of an output port 946.

Exemplary Filter

In some embodiments, filter 1008 is an exemplary implementation of filter 108 FIG. 1 and/or filter 408 FIG. 4.

In some embodiments, filter 1008 is an active filter. In some embodiments, active filter circuit 1008 has two amplifier stages 1022, 1024 one of which is cross-coupled 1022, and the second is a cascode amplifier 1024. In some embodiments, amplifier stage/s 1022, 1024 are developed using a conjugate matching technique to suppress the image signal (e.g. image signal 107 FIG. 1C) from the input signal after the upconverting mixer while amplifying the desired signal.

In some embodiments, filter 1008 includes interstage circuitry/ies XF3 1042, XF4 1044. Where, in some embodiments, interstage circuitry/ies includes transformers. A potential benefit of transformers for interstage matching is compact layout and a good common-mode rejection ratio. Alternatively, in some embodiments, one or more interstage circuitry is replaced by inductors and/or capacitors.

However, suppression may be a partial solution since filtering may not be ideal, small terms of the signal expected to be suppressed may be present at the output of the filter. These terms may be non-uniform across the wideband, non-uniformity being (it is theorized) determined by how near the image signal is aligned with the LO e.g. how close the image signal is to the LO in the frequency domain. It is theorized that, as the input RF signal gets closer in frequency to that of the LO, suppression efficiency of filtering of the image band drops.

In some embodiments, this issue may be mitigated by using a relationship between two signals. For example, where a gain of the filter is used to minimize influence of unwanted distortions according to (3.12), which describes the relationship between the IF signal amplitudes.

Considering equation (3.14) we can rewrite for phase error Δφ:

The signals A_D and A_I are the outputs of the phase shifter and their ratio R was previous described in this document (e.g. see equation 3.12).

Equation (3.19) indicates that influence of the image signal on the phase error may be reduced with increasing R. In practice, the ratio R may be made large according to performance of the active filter enhancing A_D » A_I. In some embodiments, the downconverting mixer also increases rejection ratio R e.g. associated with limited input bandwidth of the down-converting mixer i.e. the down-converting mixer may further reduce the image portion of the signal further as its bandwidth does not include the image band signal. A maximum of (3.18) occurs when Δφ Simulated results for the relation R

showed minimal difference in R between 45, 135, 225, 315 degree phase states.

It should be noted, though, that the vector modulator circuit may contribute to the phase error e.g. associated with IQ imbalance of the QVCO.

Exemplary quadrature LO signal generation

FIG. 11 is a simplified schematic of a quadrature LO signal generator 1120, according to some embodiments of the disclosure.

In some embodiments, LO signal generator includes a magnetically coupled W- band QVCO 1120. Where, in some embodiments, W-band is defined as a microwave part of the electromagnetic spectrum ranging from 75 to 110 GHz, having a wavelength of 2.7-4 mm.

Potential advantages of magnetically coupled QVCO 1120 include one or more of lower noise contribution (e.g. as compared to using active coupling devices), reduced core physical size, and reduced the parasitic effects (e.g. associated with interconnections between active devices). These potential advantages may potentially enhance QVCO performance e.g. in terms of oscillation frequency and required loss compensation with negative resistance.

In some embodiments, QVCO 1120 includes two LC VCO cores (also herein termed “VCO units”). Where, in some embodiments, the LC VCO cores are coupled with passive transformer coupling e.g. by transformers XF5 XF+. In some embodiments, the VCO units include cross-coupled transistors M_25-28, transformers XF_5-6, and transistors M_29-32 connected to varactor control IQVCO-, IQVCO+, QQVCO-, QQVCO+ and tunable current sources Ii, IQ (e.g. realized with transistors).

In some embodiments, (for example, where a filter circuit of the phase shifter is a non-tunable circuit), varactors may provide LO frequency fine-tuning for adjustment of the upconverted band e.g. for proper filtering in the active filter circuit. Where, in some embodiments, the fine-tuning enables compensation for fabrication mismatch. LO frequency tuning may be employed where the filter circuit is tunable e.g. for increased control and/or fine tuning.

Instead of coupling transistors, which are utilized in conventional QVCO topologies to introduce coupling, in some embodiments, passive structures, transformers XF₅ and XF₆, are used. In embodiments, for example, where the phase shifter is employed with lower input frequencies (e.g. not RF), conventional coupling transistors are used.

In some embodiments, a transformer locking mechanism resembles that of an active topology. In some embodiments, a primary coil of one or both transformers XF5, XF₆ acts as an inductor in the LC tank, resonating with output node capacitance at the drains of the transistors M_25-28. It is theorized that this generates an oscillation signal at the output of the first VCO core, which is magnetically coupled from the primary coil to the secondary coil, which is connected to the cross-coupled transistor sources of the second core. Potentially, this connection creates a weak strength loop between cores with a 90° phase shift. Loop strength, in some embodiments, is controlled by physical transformer parameters, e.g. one or more of; a number and/or size of the loops, a metal layer of implementation of the loops, and a metal width of the loops implementation.

It is theorized that the secondary coil degenerates the cross-coupled transistors M_27-28, potentially lowering the gain. The degeneration may result in a larger transconductance required for startup, compensation of which may degrade the power efficiency of the QVCO. In some embodiments, transformer and associated secondary coil degeneration is employed, a potential benefit of which is enhanced transistor linearity, potentially improves PN (phase noise) performance. In some embodiments, a current source is utilized to control power consumption.

In some embodiments, for operation of the modulation circuit, which implements the W-band PS (phase shift), phase and amplitude imbalance of the QVCO output signals are minimized. Where, in some embodiments, layout is designed to keep a QVCO structure symmetric, e.g. potentially minimizing mismatches between signal passes. Post layout simulations determined a maximal quadrature-phase imbalance of about 5° with maximal amplitude voltage variation of less than 5%.

A SRF (self resonant frequency) of the transformer is higher than the oscillation frequency e.g. associated with one or more of performance of the transformer simulated stand-alone and, in the oscillator, transformer loaded with additional tuning capacitance generated by transistors M_29-32 and different parasitic capacitance sources like drains of the M25-28 and gates of the buffers, the interconnections of the oscillator core. These parasitic effects may degrade the oscillation frequency and/or a quality factor of the tank potentially affecting oscillation amplitude and/or bandwidth. Exemplary buffer circuitry

FIG. 12 is a simplified schematic of a buffer 1252, according to some embodiments of the disclosure;

In some embodiments, buffer 1250 provides quadrature signals to a vector modulator (e.g. VM 430 FIG. 4) and, in some embodiments, performs amplification. In some embodiments, buffer 1252 is loaded with two separate transformers XF₈, XF₉. Where transformers, in some embodiments, are each connected to a differential input (of two differential inputs) of the vector modulator.

In some embodiments, a phase shifter (e.g. phase shifter 100 and/or phase shifter 200) includes a buffer 1252 disposed between a QVCO and a vector modulator.

FIG. 13 is a simplified schematic of a buffer 1252, according to some embodiments of the disclosure.

In some embodiments, buffer 1252 is positioned between (e.g. connecting) a QVCO (e.g. QVCO 420 FIG. 4) and an upconversion mixer (e.g. mixer 412 FIG. 4).

Buffer 1252, in some embodiments, provides an LO signal directly to the upconversion mixer, the input of which, in some embodiments, is differential. Therefore, in some embodiments, a quadrature input signal is converted at the buffer output to a single differential signal. In some embodiments, conversion is by a transformer XF₇ 1228.

In some embodiments, one or more buffer transformer XF₈, XF₉, XF₇ perform matching e.g. XF₈, XF₉, to the inputs of the vector modulator e.g. XF₇ to LO transistors of the up-conversion mixer.

Exemplary vector modulator

FIG. 14A is a simplified schematic of a vector modulator 1430, according to some embodiments of the disclosure.

In some embodiments, vector modulator 1430 illustrates an exemplary implementation of vector modulator 230 FIG. 2 and/or vector modulator 430 FIG. 4.

The conventional vector modulator (VM) type active PS can achieve a high phase resolution by interpolating quadrature phases in a continuous way. Numerous works confirmed the effectiveness of this topology in the area of high-frequency phased-array systems, e.g. according to [7] or [8], where low phase and amplitude error was reported. In some embodiments, a VM of phase shifters described in this document is implemented according to one or more feature of [7] and/or [8],

In some embodiments, VM 1430 is configured to combine control signals e.g. including I/Q signals received from a buffered QVCO (e.g. QVCO 420 FIG. 4) and generates a differential LO signal for the downconversion mixer, with controllable amplitude and/or phase levels.

Where, in some embodiments, a magnitude of the I and Q channels, is used to control amplitude or phase: In some embodiments, vector modulator 1430 includes of two variable gain amplifiers (VGAs). Combination of two VGAs, in some embodiments enables providing of polarity inversion, e.g. controlling phase shifting quadrant.

In some embodiments, biasing voltage of transistors M41-44 is used to control a DC current of signal input transistors M45-52. The biasing voltage controlling gain of signal input transistors M45-52 e.g. potentially providing desired levels I and Q signals at the output of the VGA.

The modulated VGAs output signal is then summed in current and transformed to voltage in a VM output transformer XF10 1232. Where VM output transformer 1232, in some embodiments, is designed to deliver sufficient and/or clean LO voltage swing to the downconversion mixer.

Mathematically, gain of the phase shifter may be derived using square-law gain dependency as in (3.20), at the condition that control of M42 and M44 is 0 V.

where k_n is transconductance parameter of the input devices M45-46 and M49-50, given by:

Then the output phase can be described by:

In PSK (phase shift keying) modulation mode, the overall circuit current consumption remains unchanged to keep constant gain across all phase states.

Exemplary measurement results

A 6-22 GHz full 3600 phase shifter using a ~84 GHz LO and 62-78 GHz IF range was demonstrated in 65nm CMOS. A chip was fabricated using TSMC 65nm CMOS technology with one polycrystalline and 9 metal layers (1P9M).

Measurements indicated that the fabricated phase shifter achieves phase error <1.050 and amplitude error <0.2dB for 7 -bit resolution with a power consumption of 158 mW (including buffers) and core area of 0.26 mm².

FIG. 15A is a microphotograph of a fabricated die, according to some embodiments of the disclosure.

FIG. 15B is a processed version of the microphotograph of FIG. 15 A, according to some embodiments of the disclosure.

Indicated individually in FIG. 15B are large footprint components such as transformers/baluns XF1-10 and inductors L_1-6. Intervening transistor based regions are also indicated including an upconversion mixer 1504, a LO source circuitry 1520, filter amplification stages 1522, 1524, and down conversion mixer 1512.

Referring to FIG. 15 A, the size of the chip, excluding DC pads 1578, 1580 and RF pads 1582, 1584, is 0.35x0.740 mm². Where, as illustrated in FIG. 15A, the chip is 740x350pm. As can be seen from the die micrograph, FIGs. 15A-B, the layout has a symmetric structure. Where in some embodiments, a general symmetrical about one axis layout is provided by inductors L_1-2 and L_5-6 having similar size and layout, where transformers XF₂ -4 are arranged for example linearly therebetween. The symmetric structure potentially minimizing mismatch/es and/or imbalance/s in the differential signals.

FIG.15A visually can be divided into two parts. A first (upper in FIG. 15 A) part, enclosed by half rectangle 2, is responsible for the LO generation and distribution, while a second (bottom in FIG. 15 A) part, enclosed by half rectangle 1, from GSG (groundsignal -ground) RF pads 1584 from the left (in FIG. 15 A) to the GSG RF pads from the right 1582 (in FIG. 15 A), handle the RF signal flow.

The manufacture die was measured using a probe station and network analyzer. A MATLAB script and GPIB (general purpose interface bus) connection were used for measurement automatization by controlling individual transistor biasing in the vector modulator.

FIG. 16 illustrates measured and simulated (dashed) return losses of the input and output ports for all 7 bit states, according to some embodiments of the disclosure. FIG. 17 illustrates measured and simulated (dashed) gain for all 7 bit states, according to some embodiments of the disclosure.

FIG. 18 illustrates a measured 7 bit phase response relative to 0° state, according to some embodiments of the disclosure.

FIG. 19 illustrates Amplitude RMS error (solid line) and Phase RMS error (dashed line), according to some embodiments of the disclosure.

In the 6-22 GHz bandwidth, amplitude error is less than 0.2 dB, while phase error is less than 1.1°.

The circuit was characterized for 7 bit resolution. The measured return losses at the ports show correlation with the simulations, e.g. as shown in FIG. 16, considering process variation and the broad band target.

The measurements of the reflected coefficient change minimally over the phase state. It is reasonable as the input reflection Si l mainly depends on the up-conversion mixer, and output reflection S22 depends on the output balun. Some variation might be the result of temperature and drift throughout the measurements over states. In the operation band, SI 1 kept less than -10 dB, and S22 was less than -6.5 dB.

The overall circuit gain, shown in FIG. 17, has the same correlation pattern as return losses. A 3dB bandwidth magnitude performance was observed between 7.2-19 GHz.

The normalized 7 bit phase response is shown in FIG. 18. The measured state control settings appear to not be frequency-dependent, a potential advantage, considering future use and/or integration of the circuit. These results confirm accuracy of the VM operation at the LO frequency and validates the wideband phase shifting concept e.g. as detailed herein.

Measured and processed data compared to the state-of-the-art circuits are represented in Table 1 :

* Approximated from the plot on Fig. 14 (j) of [4],

This comparison shows that, compared to the state of the art, measured results offer the highest phase resolution and bandwidth, lowest phase and gain errors whilst sporing a compact area. Power consumption is higher, it is theorized, to provide positive gain across the wide bandwidth driving a 50 Ohm load.

Exemplary application/s

FIG. 20 is a simplified schematic of a phased array system 2000, according to some embodiments of the disclosure.

In some embodiments, phased array system 2000 includes a plurality of phase shifters 2100 according to one or more features as described in this document.

System 2000, in some embodiments, includes a plurality of; antennas 2074, amplifiers 2072, and phase shifters 2100.

System 2000 in some embodiments, is a beamforming transmitter where component 2070 is a power divider, and component 2068 a transmitter. Each phase shifter 2100, for example, receiving a portion of a data signal from a power divider 2070, and passing a phase shifted signal (as shifted according to a control signal 2017 received from controller 2064) for amplification and transmission at an associated amplifier 2072 and antenna 2074 respectively.

Illustrated in FIG. 20 is increasing phase shift at phase shifters 2100 moving from left to right of the figure, enabling, for example, directing of a beam at an angle 9 as illustrated, without movement of antennas 2074. System 2000 may also be used as a beamforming receiver, where antennas 2074, and amplifiers 2072 transfer a received beam to phase shifters 2100 for recovery of a data signal at power combiner 2070.

In some embodiments, system 2000 includes a controller 2064 which generates and provides control signals 2017 to phase shifters 2100. Control signals 2017 may include phase shift control signals (e.g. including one or more feature as described regarding phase shift control signal 117 FIG. 1 and/or phase shift control signal 217b FIG. 2).

Optionally, in some embodiments, control signals 2017 include additionally or alternatively to other control signal/s include filter tuning control signals (e.g. including one or more feature as described regarding filter tuning signal 166 FIG. 1), the filter tuning control signals, for example, in addition to phase shift control signals.

Optionally, in some embodiments, control signals 2017 additionally or alternatively to other control signal/s include LO tuning control signal/s.

General

As used within this document, the term “about” refers to±20%

The terms “comprises”, “comprising”, “includes”, “including”, “having” and their conjugates mean “including but not limited to”.

The term “consisting of’ means “including and limited to”.

As used herein, singular forms, for example, “a”, “an” and “the” include plural references unless the context clearly dictates otherwise.

Within this application, various quantifications and/or expressions may include use of ranges. Range format should not be construed as an inflexible limitation on the scope of the present disclosure. Accordingly, descriptions including ranges should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within the stated range and/or subrange, for example, 1, 2, 3, 4, 5, and 6. Whenever a numerical range is indicated within this document, it is meant to include any cited numeral (fractional or integral) within the indicated range. It is appreciated that certain features which are (e.g., for clarity) described in the context of separate embodiments, may also be provided in combination in a single embodiment. Where various features of the present disclosure, which are (e.g., for brevity) described in a context of a single embodiment, may also be provided separately or in any suitable sub-combination or may be suitable for use with any other described embodiment. Features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

Although the present disclosure has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, this application intends to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.

All references (e.g., publications, patents, patent applications) mentioned in this specification are herein incorporated in their entirety by reference into the specification, e.g., as if each individual publication, patent, or patent application was individually indicated to be incorporated herein by reference. Citation or identification of any reference in this application should not be construed as an admission that such reference is available as prior art to the present disclosure. In addition, any priority document(s) and/or documents related to this application (e.g., co-filed) are hereby incorporated herein by reference in its/their entirety.

Where section headings are used in this document, they should not be interpreted as necessarily limiting.

Claims

CLAIMS:

1. A phase shifter comprising: an upconversion mixer configured to receive a local oscillator (LO) signal having a LO frequency, and configured to receive and multiply a radio frequency (RF) input signal with said LO signal to produce a modulated signal having two sidebands around said LO frequency, an intermediate (IF) sideband having frequency below said LO and an image sideband; a filter connected to and configured to receive said modulated signal from said upconversion mixer and to attenuate a range of frequencies corresponding to said image sideband to select and output said IF sideband signal; and a downconversion mixer configured to receive and multiply said IF sideband signal with a phase shifted LO signal to produce an output signal comprising a phase shifted version of said RF input signal.

2. The phase shifter according to claim 1, wherein said LO signal and said phase shifted LO signal are coherent.

3. The phase shifter according to any one of claims 1-2, comprising a LO source configured to provide said LO signal and said phase shifted LO signal.

4. The phase shifter according to any one of claims 1-3, wherein said filter is an active filter.

5. The phase shifter according to any one of claims 1-3, wherein said filter is a tunable filter, being configured to receive a control signal which adjusts parameters of said filter.

6. The phase shifter according to any one of claims 3-5, wherein said LO source is a tunable frequency source, being configured to receive a control signal which adjusts frequency of said LO signal and said phase shifted LO signal.

7. The phase shifter according to any one of claims 4-6, wherein said filter comprises at least two amplification stages.

8. The phase shifter according to claim 5, wherein said at least two amplification stages include one or both of a cross couple amplification stage and a cascode amplification stage.

9. The phase shifter according to claim 5, wherein said at least two amplification stages include a cross couple amplification stage receiving said IF sideband signal followed a cascode amplification stage outputting a filtered signal towards said downconversion mixer.

10. The phase shifter according to any one of claims 5-9, wherein said filter comprises one or more interstage transformer.

11. The phase shifter according to claim 10, wherein said one or more interstage transformer comprises a filter input transformer connecting said upconversion mixer and said filter.

12. The phase shifter according to any one of claims 10-11, wherein said one or more interstage transformer comprises a first interstage transformer connecting said at least two amplification stages.

13. The phase shifter according to claim 12, wherein said first interstage transformer is a low-k transformer.

14. The phase shifter according to any one of claims 10-13, wherein said one or more interstage transformer comprises a second interstage transformer connecting a second of said at least two amplification stages to upconversion mixer.

15. The phase shifter according to claim 14, wherein said second interstage transformer is a low-k transformer.

16. The phase shifter according to any one of claims 4-9, wherein said LO source comprises an oscillator circuitry configured to generate said LO signal and a voltage modulator configured to phase shift said LO signal to provide said phase shifted LO signal.

17. The phase shifter according to claim 16, wherein said voltage modulator is configured to receive a control signal and to phase shift said LO signal according to said control signal.

18. The phase shifter according to any one of claims 16-17, wherein said oscillator circuitry comprises a quadrature voltage controlled oscillator (QVCO).

19. The phase shifter according to claim 18, wherein QVCO is a magnetically coupled QVCO.

20. The phase shifter according to claim 19, wherein said voltage modulator comprises at least two variable gain amplifiers (VGAs).

21. The phase shifter according to any one of claims 18-19, wherein said LO source comprises: a first buffer connecting said QVCO and said upconversion mixer; and a second buffer connecting said QVCO and said voltage modulator.

22. The phase shifter according to any one of claims 1-21, wherein one or both of said upconversion mixer and said downconversion mixer comprise a common gate differential input stage.

23. The phase shifter according to any one of claims 1 -22, wherein one or both of said upconversion mixer and said downconversion mixer comprise peaking inductors.

24. A method of wideband phase shifting comprising: receiving an input radiofrequency (RF) signal; up-converting said RF signal by multiplication with a local oscillator (LO) signal having a LO frequency, to produce a modulated signal; filtering said modulated signal to attenuate a sideband to said LO frequency to produce an intermediate frequency (IF) signal having frequencies higher than frequencies of said RF signal and lower than said LO frequency; down-converting said IF signal by multiplication with a phase shifted LO signal to provide a phase shifted version of said input RF signal.

25. The method according to claim 24, comprising generating said LO signal and said phase shifted LO signal.

26. The method according to any one of claims 24-25, wherein said LO signal and said phase shifted LO signal are coherent.

27. The method according to any one of claims 25-26, wherein said generating is by a selected phase, said phase shifted version of said input RF signal being phase shifted by said selected phase.

28. The method according to any one of claims 25-27, wherein said generating comprises receiving a control signal specifying said selected phase.