WO2025020775A1 - Substrat d'affichage et appareil d'affichage - Google Patents

Substrat d'affichage et appareil d'affichage Download PDF

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Publication number
WO2025020775A1
WO2025020775A1 PCT/CN2024/099767 CN2024099767W WO2025020775A1 WO 2025020775 A1 WO2025020775 A1 WO 2025020775A1 CN 2024099767 W CN2024099767 W CN 2024099767W WO 2025020775 A1 WO2025020775 A1 WO 2025020775A1
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WIPO (PCT)
Prior art keywords
pixel circuit
pixel
circuit
light
display area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/099767
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English (en)
Chinese (zh)
Inventor
周宏军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Filing date
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025020775A1 publication Critical patent/WO2025020775A1/fr
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

Definitions

  • This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device.
  • OLED Organic light emitting diodes
  • QLED quantum dot light emitting diodes
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the present embodiment provides a display substrate, comprising: a substrate, a driving circuit layer and a light-emitting structure layer.
  • the substrate comprises a first display area and a second display area, and the first display area is located on at least one side of the second display area.
  • the driving circuit layer is located in the first display area, and comprises a plurality of first pixel circuits and a plurality of second pixel circuits.
  • the light-emitting structure layer is located on a side of the driving circuit layer away from the substrate, and comprises a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area.
  • At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements
  • at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements.
  • the size of at least one first pixel circuit is different from the size of at least one second pixel circuit.
  • the plurality of first pixel circuits have the same size
  • the plurality of second pixel circuits have the same size
  • the plurality of first pixel circuits have a size different from that of the plurality of second pixel circuits.
  • the driving circuit layer further includes: a plurality of invalid pixel circuits; a size of at least one invalid pixel circuit among the plurality of invalid pixel circuits is smaller than a size of the at least one first pixel circuit.
  • the plurality of second pixel circuits are arranged at intervals between the plurality of first pixel circuits in the first direction.
  • the length of the at least one first pixel circuit in the first direction is greater than the length of the at least one second pixel circuit in the first direction
  • the length of the at least one first pixel circuit in the second direction is less than the length of the at least one second pixel circuit in the second direction
  • the first direction intersects the second direction.
  • the driving circuit layer further includes: a plurality of invalid pixel circuits, the plurality of invalid pixel circuits are arranged between the plurality of first pixel circuits at intervals in the first direction, and at least one of the plurality of invalid pixel circuits is adjacent to the at least one second pixel circuit in the second direction.
  • the length of the at least one invalid pixel circuit in the first direction is the same as the length of the at least one second pixel circuit in the first direction, and the length of the at least one invalid pixel circuit in the second direction is less than the length of the at least one a length of the first pixel circuit in the second direction.
  • the sum of the length of the at least one invalid pixel circuit in the second direction and the length of an adjacent second pixel circuit in the second direction is 1.8 to 2.2 times the length of the at least one first pixel circuit in the second direction.
  • the at least one second pixel circuit and the at least one invalid pixel circuit are arranged at intervals in the second direction.
  • Four first pixel circuits and one invalid pixel circuit are arranged at intervals in the first direction, or four first pixel circuits and one second pixel circuit are arranged at intervals in the first direction; or four first pixel circuits, one invalid pixel circuit, four first pixel circuits and one second pixel circuit are arranged at intervals in the first direction.
  • the sum of four times the length of the at least one first pixel circuit in the first direction and the length of the at least one invalid pixel circuit in the first direction is 1.8 to 2.2 times the length of the at least one first pixel circuit in the second direction.
  • the plurality of first pixel circuits, the plurality of second pixel circuits, and the plurality of invalid pixel circuits of the driving circuit layer are divided into a plurality of circuit repetition units, each circuit repetition unit comprising: a plurality of first pixel circuits arranged in two rows and four columns, a second pixel circuit and an invalid pixel circuit arranged in two rows and one column.
  • the second pixel circuit and the invalid pixel circuit are located on the same side of the plurality of first pixel circuits, or, within the circuit repetition unit, the second pixel circuit and the invalid pixel circuit are located in the middle of four columns of first pixel circuits; or, the second pixel circuit and the invalid pixel circuit are located in the middle of one column of first pixel circuits and three columns of first pixel circuits.
  • the arrangement order of the second pixel circuits and the invalid pixel circuits in the second direction in adjacent circuit repetition units in the first direction is different.
  • one second pixel circuit is electrically connected to one second light emitting element; or, two second light emitting elements emitting light of the same color are electrically connected to the same second pixel circuit.
  • the plurality of second light-emitting elements include: a plurality of second light-emitting elements emitting red light, a plurality of second light-emitting elements emitting blue light, and a plurality of second light-emitting elements emitting green light.
  • the second pixel circuit connected to the second light-emitting elements emitting green light is located on a side of the second pixel circuit connected to the second light-emitting elements emitting red light and blue light close to the second display area.
  • the second pixel circuit connected to the second light-emitting elements emitting red light is located on a side of the second pixel circuit connected to the second light-emitting elements emitting blue light close to the second display area.
  • two adjacent second light emitting elements emitting green light located in the same column are electrically connected to the same second pixel circuit; two second light emitting elements emitting blue light located in different columns of adjacent rows are electrically connected to the same second pixel circuit, and two second light emitting elements emitting red light located in different columns of adjacent rows are electrically connected to the same second pixel circuit.
  • One of the two second light emitting elements emitting blue light and one of the two second light emitting elements emitting red light are located in the same row and in the same column as the other second light emitting element emitting red light; the other second light emitting element emitting blue light is located in the same column as the one second light emitting element emitting red light and in the same row as the other second light emitting element emitting red light.
  • the driving circuit layer in a direction perpendicular to the display substrate, includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on a substrate.
  • the semiconductor layer includes at least: an active layer of transistors of the plurality of first pixel circuits and the plurality of second pixel circuits.
  • the first conductive layer includes at least: gate electrodes of transistors of the plurality of first pixel circuits and a first electrode of a storage capacitor, and gate electrodes of transistors of the plurality of second pixel circuits and a first electrode of a storage capacitor.
  • the second conductive layer includes at least: a second electrode of a storage capacitor of the plurality of first pixel circuits and the plurality of second pixel circuits.
  • the third conductive layer includes at least: a plurality of connection electrodes.
  • the fourth conductive layer includes at least: a data line and a first power line.
  • the first display area includes: a transition area located at at least one side of the second display area and a sub-display area located at at least one side of the transition area, and the plurality of second pixel circuits are located in the transition area.
  • the plurality of second pixel circuits are located in the transition area and the sub-display area.
  • the light transmittance of the first display area is less than that of the second display area; or, the light transmittance of a sub-display area of the first display area is less than or equal to the light transmittance of the transition area, and the light transmittance of the transition area is less than that of the second display area.
  • a pixel density of the first display area is greater than or equal to a pixel density of the second display area.
  • this embodiment provides a display device, including the display substrate as described above, and a sensor located on a non-display surface side of the display substrate, wherein the orthographic projection of the sensor on the display substrate overlaps with the second display area of the display substrate.
  • the present embodiment provides a display substrate, comprising: a substrate, a driving circuit layer and a light-emitting structure layer.
  • the substrate comprises a first display area and a second display area, and the first display area is located on at least one side of the second display area.
  • the driving circuit layer is located in the first display area, and comprises a plurality of first pixel circuits and a plurality of second pixel circuits.
  • the light-emitting structure layer is located on a side of the driving circuit layer away from the substrate, and comprises a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area.
  • At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements
  • at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements.
  • the area of at least one first pixel circuit is different from the area of at least one second pixel circuit.
  • the driving circuit layer further includes: a plurality of invalid pixel circuits; an area of at least one invalid pixel circuit among the plurality of invalid pixel circuits is smaller than an area of the at least one first pixel circuit.
  • the plurality of second pixel circuits are arranged at intervals between the plurality of first pixel circuits in the first direction.
  • the length of the at least one first pixel circuit in the first direction is greater than the length of the at least one second pixel circuit in the first direction
  • the length of the at least one first pixel circuit in the second direction is less than the length of the at least one second pixel circuit in the second direction
  • the first direction intersects the second direction.
  • the driving circuit layer further includes: a plurality of invalid pixel circuits, the plurality of invalid pixel circuits being arranged between the plurality of first pixel circuits at intervals in the first direction, and at least one of the plurality of invalid pixel circuits being adjacent to the at least one second pixel circuit in the second direction.
  • the length of the at least one invalid pixel circuit in the first direction is the same as the length of the at least one second pixel circuit in the first direction, and the length of the at least one invalid pixel circuit in the second direction is less than the length of the at least one first pixel circuit in the second direction.
  • FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG2 is a schematic diagram of a planar structure of a display area of a display substrate according to at least one embodiment of the present disclosure
  • FIG3 is a schematic diagram of a partial structure of a display substrate according to at least one embodiment of the present disclosure.
  • FIG4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a partial schematic diagram of a first display area according to at least one embodiment of the present disclosure.
  • FIG6 is a partial plan view of a first display area according to at least one embodiment of the present disclosure.
  • FIG7 is a schematic plan view of the display substrate after the semiconductor layer is formed in FIG6;
  • FIG8A is a schematic plan view of the display substrate after the first conductive layer is formed in FIG6 ;
  • FIG8B is a schematic diagram of the first conductive layer in FIG8A ;
  • FIG9A is a schematic plan view of the display substrate after the second conductive layer is formed in FIG6 ;
  • FIG9B is a schematic diagram of the second conductive layer in FIG9A ;
  • FIG10 is a schematic plan view of the display substrate after the third insulating layer is formed in FIG6 ;
  • FIG11A is a schematic plan view of the display substrate after the third conductive layer is formed in FIG6 ;
  • FIG11B is a schematic diagram of the third conductive layer in FIG11A ;
  • FIG12 is a schematic plan view of the display substrate after the fifth insulating layer is formed in FIG6 ;
  • FIG13 is a schematic diagram of the fourth conductive layer in FIG6;
  • FIG14 is a schematic diagram showing the connection between a second pixel circuit and a second light-emitting element according to at least one embodiment of the present disclosure
  • FIG15 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • FIG16 is another connection diagram of a second pixel circuit and a second light-emitting element according to at least one embodiment of the present disclosure
  • FIG17 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • FIG18 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • FIG19 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • FIG20 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • FIG21 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • FIG22 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • FIG23 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • FIG24 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • FIG25 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • FIG26 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • FIG. 27 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 28 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 29 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source.
  • a channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • the gate electrode may also be called a control electrode.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • the "light transmittance" in the present disclosure refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body to its incident light flux.
  • the size of A refers to the size of the orthographic projection of A on the substrate.
  • the size of A may include at least one of the following: the length of the orthographic projection of A on the substrate along the first direction, the length of the orthographic projection of A on the substrate along the second direction, and the area of the orthographic projection of A on the substrate; wherein the first direction may be perpendicular to the second direction.
  • the size of A may include at least one of the following: the radius of the orthographic projection of A on the substrate, and the area of the orthographic projection of A on the substrate.
  • the external pixel circuit method refers to setting the pixel circuit connected to the light-emitting element in the under-screen camera area in the normal display area, and improving the light transmittance of the under-screen camera area by arranging the light-emitting element and the pixel circuit separately. Since there is no pixel circuit in the under-screen camera area, there is no other light-shielding layer in this area except the anode of the light-emitting element, so a higher light transmittance can be achieved. However, as the pixel density (PPI, Pixels Per Inch) of the display device increases, the compression space of the pixel circuit in the normal display area becomes smaller, making the compression of the pixel circuit more and more difficult. For example, when the PPI of the display device is greater than 430PPI, there is insufficient space for setting the pixel circuit in the normal display area, which cannot meet the market demand for high-PPI full-screen display devices.
  • PPI Pixels Per Inch
  • This embodiment provides a display substrate and a display device, which can be helpful in realizing a full-screen display product with a high PPI.
  • the present embodiment provides a display substrate, comprising: a substrate, a driving circuit layer and a light-emitting structure layer.
  • the substrate comprises a first display area and a second display area, and the first display area is located on at least one side of the second display area.
  • the driving circuit layer is located in the first display area, and comprises a plurality of first pixel circuits and a plurality of second pixel circuits.
  • the light-emitting structure layer is located on a side of the driving circuit layer away from the substrate, and comprises a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area.
  • At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements
  • at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements.
  • the size of at least one first pixel circuit is different from the size of at least one second pixel circuit.
  • the size of the pixel circuit refers to the size of the positive projection of the pixel circuit on the substrate.
  • the size of the positive projection of the pixel circuit on the substrate can be understood as the size of the circumscribed rectangle of the active layer of the pixel circuit.
  • the size of the pixel circuit may include: the length of the pixel circuit along the first direction and the length along the second direction.
  • the size of the first pixel circuit is different from the size of the second pixel circuit and may include at least one of the following: the length of the first pixel circuit and the second pixel circuit along the first direction is different; the length of the first pixel circuit and the second pixel circuit along the second direction is different; the area of the positive projection of the first pixel circuit and the second pixel circuit on the substrate is different.
  • the first direction intersects with the second direction, for example, the first direction may be perpendicular to the second direction.
  • the area of the positive projection of the pixel circuit on the substrate may be roughly the product of the length of the pixel circuit along the first direction and the length along the second direction.
  • the display substrate provided in this embodiment without increasing the area of the second display area (that is, without increasing the number of second pixel circuits), is beneficial to increasing the setting space of the first pixel circuit by setting the first pixel circuit and the second pixel circuit of different sizes, thereby facilitating meeting the high PPI requirement of the first display area.
  • the sizes of the plurality of first pixel circuits in the first display area may be the same, the sizes of the plurality of second pixel circuits may be the same, and the sizes of the plurality of first pixel circuits may be different from the sizes of the plurality of second pixel circuits.
  • the sizes of the plurality of first pixel circuits may be consistent, the sizes of the plurality of second pixel circuits to be consistent, and performing size partitioning design on the first pixel circuits and the second pixel circuits, it is beneficial to increase the setting space of the first pixel circuit without increasing the area of the second display area, thereby facilitating meeting the high PPI requirements of the first display area.
  • the driving circuit layer may further include: a plurality of invalid pixel circuits, and the size of at least one invalid pixel circuit may be smaller than the size of at least one first pixel circuit.
  • the length of the invalid pixel circuit along the first direction may be smaller than the length of the first pixel circuit along the first direction; or, the length of the invalid pixel circuit along the second direction may be smaller than the length of the second pixel circuit along the second direction; or, the length of the invalid pixel circuit along the first direction may be smaller than the length of the first pixel circuit along the first direction, and the length of the invalid pixel circuit along the second direction may be smaller than the length of the first pixel circuit along the first direction.
  • the reduced occupied space of the invalid pixel circuit can be used to set the first pixel circuit and the second pixel circuit.
  • a plurality of second pixel circuits are arranged between a plurality of first pixel circuits at intervals in the first direction.
  • the length of at least one first pixel circuit in the first direction may be greater than the length of at least one second pixel circuit in the first direction
  • the length of at least one first pixel circuit in the second direction may be less than the length of at least one second pixel circuit in the second direction
  • the first direction intersects the second direction.
  • the ratio of the length of the first pixel circuit in the first direction to the length of the second pixel circuit in the first direction may be less than 1.5
  • the ratio of the length of the second pixel circuit in the second direction to the length of the first pixel circuit in the second direction may be less than 1.5.
  • This example can increase the setting space of the first pixel circuit in the first direction by compressing the size of the second pixel circuit along the first direction.
  • a plurality of invalid pixel circuits may be arranged between a plurality of first pixel circuits at intervals in the first direction, and at least one invalid pixel circuit may be adjacent to at least one second pixel circuit in the second direction.
  • the length of at least one invalid pixel circuit in the first direction may be substantially the same as the length of at least one second pixel circuit in the first direction, and the length of at least one invalid pixel circuit in the second direction may be less than the length of at least one first pixel circuit in the second direction.
  • the setting space of the second pixel circuit in the second direction may be increased, and by compressing the size of the invalid pixel circuit along the first direction, the setting space of the first pixel circuit in the first direction may be increased.
  • FIG1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure.
  • the display substrate may include: a display area AA and a peripheral area BB surrounding the periphery of the display area AA.
  • the display area AA of the display substrate may include: a first display area A1 and a second display area A2.
  • the first display area A1 may at least partially surround the second display area A2.
  • the second display area A2 may be located in the middle of the top of the display area AA, and the first display area A1 may surround the second display area A2.
  • this embodiment is not limited to this.
  • the second display area A2 may be located in other positions such as the upper left corner or the upper right corner of the display area AA, and the first display area A1 may surround at least one side of the second display area A2.
  • the display area AA may be a rectangle, such as a rounded rectangle.
  • the second display area A2 may be a circle or an ellipse. However, this embodiment is not limited thereto.
  • the second display area A2 may be a rectangle, a semicircle, a pentagon, or other shapes.
  • the second display area A2 may be a light-transmitting display area, which may also be referred to as a Full Display with Camera (FDC) area, configured to display images and transmit light; the first display area A1 may be a normal display area, configured to display images.
  • the orthographic projection of a sensor e.g., hardware such as a camera
  • the second display area A2 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the second display area A2.
  • this embodiment is not limited thereto.
  • the second display area A2 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the inscribed circle of the second display area A2.
  • the pixel density of the first display area A1 may be greater than or equal to the pixel density of the second display area A2.
  • the pixel density of the first display area A1 may be equal to the pixel density of the second display area A2. This embodiment is not limited to this.
  • the ratio of the resolution of the second display area A2 to the resolution of the first display area A1 may be about 0.8 to 1.2.
  • the resolution of the second display area A2 may be substantially the same as the resolution of the first display area A1. This embodiment is not limited to this.
  • FIG. 2 is a schematic diagram of a planar structure of a display area of a display substrate according to at least one embodiment of the present disclosure.
  • the display area may include a plurality of pixel units P, and at least one pixel unit P may include: a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 and a fourth sub-pixel P4 emitting a third color light.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light.
  • each sub-pixel may include a circuit unit and a light-emitting element
  • the circuit unit may include at least a pixel circuit
  • the pixel circuit is respectively connected to a scan line, a data line, and a light-emitting control line
  • the pixel circuit may be configured to receive a data voltage transmitted by the data line under the control of the scan line and the light-emitting control line, and output a corresponding current to the light-emitting element.
  • the light-emitting elements in at least one sub-pixel are respectively connected to the pixel circuit of the sub-pixel, and the light-emitting element is configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel.
  • the pixel circuit may include multiple transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.
  • T refers to a thin film transistor
  • C refers to a capacitor
  • the number before T represents the number of thin film transistors in the circuit
  • the number before C represents the number of capacitors in the circuit.
  • the multiple transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In other examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.
  • multiple transistors in a pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors.
  • the active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide semiconductor Oxide
  • Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc.
  • the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element may be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • the shape of the light-emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the light-emitting elements of the four sub-pixels of a pixel unit may be arranged in horizontal parallel, vertical parallel, or in a square manner.
  • this embodiment is not limited to this.
  • a pixel unit may include three sub-pixels, and the light-emitting elements of the three sub-pixels may be arranged in horizontal parallel, vertical parallel, or in a herringbone manner.
  • FIG3 is a schematic diagram of a partial structure of a display substrate of at least one embodiment of the present disclosure.
  • the display substrate may include at least: a plurality of pixel circuits and a plurality of first light-emitting elements 52 located in the first display area A1, and a plurality of second light-emitting elements 54 located in the second display area A2.
  • the plurality of pixel circuits in the first display area A1 may include: a plurality of first pixel circuits 51, a plurality of second pixel circuits 53, and a plurality of invalid pixel circuits 55.
  • At least one first pixel circuit 51 among the plurality of first pixel circuits 51 may be electrically connected to at least one first light emitting element 52 among the plurality of first light emitting elements 52, and at least one first pixel circuit 51 may be electrically connected to at least one first light emitting element 52 among the plurality of first light emitting elements 52.
  • the orthographic projection of the circuit 51 on the substrate may at least partially overlap with the orthographic projection of at least one first light-emitting element 52 on the substrate.
  • the first pixel circuit 51 may be configured to provide a driving signal to the connected first light-emitting element 52 to drive the corresponding first light-emitting element 52 to emit light.
  • the plurality of first pixel circuits 51 and the plurality of first light-emitting elements 52 may be in a one-to-one relationship, that is, one first pixel circuit 51 may be electrically connected to one first light-emitting element 52, configured to drive the connected first light-emitting element 52 to emit light; or, the plurality of first pixel circuits 51 and the plurality of first light-emitting elements 52 may be in a one-to-many relationship, that is, one first pixel circuit 51 may be electrically connected to multiple first light-emitting elements 52, configured to drive the connected multiple first light-emitting elements 52 to emit light; or, the plurality of first pixel circuits 51 and the plurality of first light-emitting elements 52 may be in a many-to-one relationship, that is, multiple first pixel circuits may be electrically connected to one first light-emitting element 52, configured to drive the first light-emitting element 52 to emit light.
  • At least one second pixel circuit 53 of the plurality of second pixel circuits 53 located in the first display area A1 can be electrically connected to at least one second light-emitting element 54 of the plurality of second light-emitting elements 54 located in the second display area A2 through a conductive connection line 61.
  • the second pixel circuit 53 can be configured to provide a driving signal to the connected second light-emitting element 54 to drive the corresponding second light-emitting element 54 to emit light.
  • the plurality of second pixel circuits 53 and the plurality of second light-emitting elements 54 can be in a one-to-one relationship, or a one-to-many relationship, or a many-to-one relationship.
  • a second pixel circuit 53 can be electrically connected to a plurality of second light-emitting elements 54 emitting light of the same color, and configured to drive the plurality of second light-emitting elements 54 emitting light of the same color to emit light. Since the second light-emitting element 54 and the second pixel circuit 53 are located in different areas, there may be no overlapping portion between the orthographic projection of at least one second pixel circuit 53 on the substrate and the orthographic projection of at least one second light-emitting element 54 on the substrate. By arranging the second pixel circuit 53 in the first display area A1, it is beneficial to improve the light transmittance of the second display area A2.
  • the conductive connecting line 61 can be made of a transparent conductive material (e.g., indium tin oxide (ITO)) to maximize the light transmittance of the second display area A2.
  • ITO indium tin oxide
  • the light emitting area of a single second light emitting element 54 may be smaller than the light emitting area of a single first light emitting element 52. That is, the light emitting area of the first light emitting element 52 may be larger than the light emitting area of the second light emitting element 54.
  • the light emitting area of a single light emitting element may correspond to the area of the pixel opening of the pixel definition layer.
  • a light-transmitting area may be provided between adjacent second light emitting elements 54. For example, a plurality of light-transmitting areas may be connected to each other to form a continuous light-transmitting area separated by a plurality of second light emitting elements 54.
  • a plurality of second pixel circuits 53 may be arranged at intervals between a plurality of first pixel circuits 51, and a plurality of invalid pixel circuits 55 may be arranged at intervals between a plurality of first pixel circuits 51.
  • a plurality of first pixel circuits 51 may be arranged between two adjacent second pixel circuits 53 in the first direction X, and a plurality of first pixel circuits 51 may be arranged between two adjacent invalid pixel circuits 55.
  • At least one invalid pixel circuit 55 and at least one second pixel circuit 53 may be arranged at intervals in the second direction Y.
  • the invalid pixel circuit 55 and the second pixel circuit 53 may be located in the same column.
  • the invalid pixel circuit 55 may be beneficial to improving the uniformity of components of multiple film layers in the etching process.
  • the invalid pixel circuit 55 may have substantially the same structure as the second pixel circuit 53 in its row or column, except that it is not electrically connected to any light-emitting element.
  • the first display area A1 is provided with not only the first pixel circuit 51 electrically connected to the first light-emitting element 52, but also the second pixel circuit 53 electrically connected to the second light-emitting element 54, the number of pixel circuits in the first display area A1 is greater than the number of first light-emitting elements 52.
  • the area for setting the newly added pixel circuit can be obtained by reducing the size of the first pixel circuit 51 in the first direction X.
  • the size of the pixel circuit in the first direction X can be smaller than the size of the first light-emitting element in the first direction X.
  • the original h columns of pixel circuits can be compressed along the first direction X to add a new column of pixel circuit arrangement space, and the space occupied by the h columns of pixel circuits before compression and the h+1 columns of pixel circuits after compression can be the same.
  • h can be an integer greater than 1. In this example, h can be equal to 2 or 4. However, this embodiment is not limited to this.
  • the second pixel circuit 53 and the invalid pixel circuit 55 may be disposed in the first display area A1 on both sides (e.g., left and right sides) of the second display area A2 along the first direction X, and the second pixel circuit and the invalid pixel circuit may not be disposed in the first display area A1 on both sides (e.g., upper and lower sides) of the second display area A2 along the second direction Y, or only the invalid pixel circuit may be disposed.
  • This embodiment is not limited to this.
  • FIG4 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure.
  • the pixel circuit of this example may be a 7T1C structure.
  • the pixel circuit of this example may include: a first transistor T1 to a seventh transistor T7.
  • the pixel circuit may be electrically connected to a scan line GL, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2.
  • the light emitting element EL may include an anode, a cathode, and an organic light emitting layer located between the anode and the cathode.
  • the first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit
  • the first voltage signal VDD is greater than the second voltage signal VSS.
  • the scan line GL can be configured to provide a scan signal SCAN to the pixel circuit
  • the data line DL can be configured to provide a data signal to the pixel circuit
  • the emission control line EML can be configured to provide an emission control signal EM to the pixel circuit
  • the first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit
  • the second reset control line RST2 can be configured to provide a second reset signal RESET2 to the pixel circuit.
  • the second reset control line RST2 can be connected to the scan line GL to be input with the scan signal SCAN. That is, the second reset signal RESET2(n) received by the n-th row of pixel circuits is the scan signal SCAN(n) received by the n-th row of pixel circuits.
  • this embodiment is not limited to this.
  • the second reset control signal line RST2 can be input with a second reset control signal RESET2 different from the scan signal SCAN.
  • the first reset control line RST1 can be connected to the scan line GL of the n-1-th row of pixel circuits to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be achieved.
  • the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.
  • the third transistor T3 may also be referred to as a driving transistor.
  • the gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3.
  • the first transistor T1 may also be referred to as a first reset transistor, configured to reset the gate of the third transistor T3.
  • the gate of the second transistor T2 is electrically connected to the scan line GL, the first electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3.
  • the second transistor T2 may also be referred to as a threshold compensation transistor.
  • the gate of the fourth transistor T4 is electrically connected to the scan line GL, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3.
  • the fourth transistor T4 may also be referred to as a data write transistor.
  • the gate of the fifth transistor T5 is electrically connected to the light emitting control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3.
  • the fifth transistor T5 can also be called a first light emitting control transistor.
  • the gate of the sixth transistor T6 is electrically connected to the light emitting control line EML, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light emitting element EL.
  • the sixth transistor T6 can also be called a second light emitting control transistor.
  • the gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light emitting element EL.
  • the seventh transistor T7 can also be called
  • the first electrode of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.
  • the cathode of the light emitting element EL is electrically connected to the second power line PL2.
  • the first node N1 is the connection point of the storage capacitor Cst
  • the first transistor T1, the third transistor T3 and the second transistor T2 the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3,
  • the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.
  • the operation process of the pixel circuit may include: a first stage, a second stage, and a third stage.
  • the second reset control line RST2 and the scan line GL transmitting the same signal are used as an example for description.
  • the first stage is called the reset stage.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, which turns on the first complex transistor T1
  • the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, which initializes the first node N1 and clears the original data voltage in the storage capacitor Cst.
  • the scan signal SCAN provided by the scan line GL is a high-level signal
  • the light control signal EM provided by the light control line EML is a high-level signal, which turns off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the light-emitting element EL does not emit light.
  • the second stage is called the data writing stage or the threshold compensation stage.
  • the scanning signal SCAN provided by the scanning line GL is a low level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the light control signal EM provided by the light control line EML are both high level signals
  • the data line DL outputs the data signal.
  • the driving transistor T3 since the first electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on.
  • the scanning signal SCAN is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst, and the voltage of the first electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata-
  • the seventh transistor T7 is turned on, so that the second initial signal (i.e., anode reset signal) provided by the second initial signal line INIT2 is provided to the anode of the light emitting element EL, the anode of the light emitting element EL is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the light emitting element EL is ensured not to emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, so that the first transistor T1 is turned off.
  • the light emitting control signal EM provided by the light emitting control line EML is a high level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third stage is called the light-emitting stage.
  • the light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal
  • the scanning signal SCAN provided by the scanning line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals.
  • the light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the first voltage signal VDD output by the first power line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light-emitting element EL to emit light.
  • the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [VDD-Vdata] 2 ;
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vdata is the data voltage output by the data line DL
  • VDD is the first voltage signal output by the first power line PL1.
  • the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.
  • FIG5 is a partial schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • a second pixel circuit 53 or an invalid pixel circuit 55 is arranged for every four first pixel circuits 51 in the first direction X.
  • This example can arrange the second pixel circuit 53 and the invalid pixel circuit 55 by compressing the pixel circuit in the first direction X.
  • FIG5 is illustrated by taking a circuit repeating unit of the first display area as an example.
  • the circuit repeating unit of this example may include: two rows and five columns of pixel circuits, wherein a plurality of first pixel circuits 51 are arranged in two rows and four columns, a second pixel circuit 53 and an invalid pixel circuit 55 are arranged in two rows and one column, and the invalid pixel circuit 55 may be located on one side of the second pixel circuit 53 in the second direction Y.
  • Multiple circuit repeating units in the first display area may be arranged in an array along the first direction X and the second direction Y.
  • a row of pixel circuits includes a plurality of pixel circuits arranged along the first direction X
  • a column of pixel circuits includes a plurality of pixel circuits arranged along the second direction Y.
  • the sizes of the plurality of first pixel circuits 51 in the first display area may be the same, the sizes of the plurality of second pixel circuits 53 may be the same, and the sizes of the plurality of invalid pixel circuits 55 may be the same.
  • the sizes of the first pixel circuit 51, the second pixel circuit 53, and the invalid pixel circuit 55 may be different from each other.
  • the length of the first pixel circuit 51 along the first direction X can be recorded as b, and the length along the second direction Y can be recorded as a; the length of the second pixel circuit 53 along the first direction X can be recorded as d1, and the length along the second direction Y can be recorded as c1; the length of the invalid pixel circuit 55 along the first direction X can be recorded as f1, and the length along the second direction Y can be recorded as e1.
  • the length b of the first pixel circuit 51 along the first direction X can be greater than the length d1 of the second pixel circuit 53 along the first direction X, and the length d1 of the second pixel circuit 53 along the first direction X can be the same as the length f1 of the invalid pixel circuit 55 along the first direction X.
  • the length a of the first pixel circuit 51 along the second direction Y can be less than the length c1 of the second pixel circuit 53 along the second direction Y, and greater than the length e1 of the invalid pixel circuit 55 along the second direction Y.
  • the length c1 of the second pixel circuit 53 along the second direction Y may be less than 1.5 times the length a of the first pixel circuit 51 along the second direction Y, that is, the ratio of c1 to a may be less than 1.5.
  • the length b of the first pixel circuit 51 along the first direction X may be less than 1.5 times the length d1 of the second pixel circuit 53 along the first direction X, that is, the ratio of b to d1 may be less than 1.5.
  • the size limitation of this example can reduce the excessive winding of the wiring extending along the first direction and the second direction to affect the signal load, which is conducive to ensuring the display effect.
  • the second pixel circuit can be increased by simplifying the invalid pixel circuit 55 or reducing the occupied space of the invalid pixel circuit 55.
  • the occupied space of the second pixel circuit 53 along the second direction Y can be reduced, so that the occupied space of the second pixel circuit 53 along the first direction X can be reduced on the basis of ensuring the driving effect of the second pixel circuit 53.
  • the arrangement space of the pixel circuit along the first direction X can be increased, which can be conducive to meeting the high PPI requirement.
  • the arrangement space of the first pixel circuit can be increased without increasing the area of the second display area (that is, without increasing the number of second pixel circuits), so as to meet the high PPI requirement of the first display area.
  • Figure 6 is a partial plan view of the first display area of at least one embodiment of the present disclosure.
  • Figure 6 illustrates a partial structure of the driving circuit layer of the first display area.
  • a plurality of circuit units sequentially arranged along the first direction X may be referred to as a unit row
  • a plurality of circuit units sequentially arranged along the second direction Y may be referred to as a unit column.
  • the first display area may include: a first circuit area A11 and a second circuit area A12 arranged at intervals along a first direction X.
  • the first circuit area A11 may be provided with a plurality of unit columns (e.g., four unit columns), and the second circuit area A12 may be provided with one unit column.
  • the plurality of unit columns of the first circuit area A11 may include a plurality of first circuit units, each of which may include at least: a first pixel circuit and a wiring electrically connected to the first pixel circuit.
  • a unit column of the second circuit area A12 may include: a second circuit unit and an invalid circuit unit arranged at intervals, the invalid circuit unit may include: an invalid pixel circuit and a wiring connected to the invalid pixel circuit.
  • the second circuit unit may include: a second pixel circuit and a wiring electrically connected to the second pixel circuit.
  • a circuit repeating unit composed of circuit units arranged in two rows and five columns (for example, including the Nth column to the N+4th column and the Mth row and the M+1th row) is used as an example for illustration.
  • the Nth column, the N+1th column, the N+2th column and the N+3th column circuit units include: a plurality of first circuit units;
  • the N+4th column circuit unit includes: second circuit units and invalid circuit units arranged at intervals along the second direction Y.
  • the following is an example of the structure of the first pixel circuit of the Nth column and the Mth row, the invalid pixel circuit of the N+4th column and the M+1th row.
  • the first display area may include at least: a substrate, and a driving circuit layer, a conductive connection layer, and a light emitting structure layer sequentially disposed on the substrate.
  • the driving circuit layer may include at least: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of invalid pixel circuits.
  • the circuit structures of the first pixel circuit, the second pixel circuit, and the invalid pixel circuit may all be 7T1C structures as shown in FIG4.
  • the first pixel circuit may include: a first transistor 11 to a seventh transistor 17 and a storage capacitor 18.
  • the second pixel circuit may include: a first transistor 21 to a seventh transistor 27 and a storage capacitor 28.
  • the invalid pixel circuit may include: a first transistor 31 to a seventh transistor 37 and a storage capacitor 38.
  • the conductive connection layer may include at least a plurality of conductive connection lines, and the conductive connection lines may be configured to extend to the second display area to electrically connect the corresponding second pixel circuit and the second light emitting element located in the second display area.
  • the light emitting structure layer may include at least: a plurality of first light emitting elements located in the first display area and a plurality of second light emitting elements located in the second display area, the plurality of first light emitting elements may be electrically connected to the plurality of first pixel circuits, and the plurality of second light emitting elements and the plurality of second pixel circuits may be electrically connected through a plurality of conductive connection lines.
  • the structure of the first display area of the display substrate of this example is illustrated by the preparation process of the display substrate.
  • the “patterning process” mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the “thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the “thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one “pattern”.
  • the term "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously by the same patterning process.
  • the "thickness" of a layer is the dimension of the film layer in a direction perpendicular to the display substrate.
  • “the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the preparation process of the display substrate may include the following operations.
  • the substrate may be a rigid substrate or a flexible substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together.
  • the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the water and oxygen resistance of the substrate.
  • PI polyimide
  • PET polyethylene terephthalate
  • a surface-treated polymer soft film a surface-treated polymer soft film
  • the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the water and oxygen resistance of the substrate.
  • a semiconductor thin film is deposited on a substrate, and the semiconductor thin film is patterned by a patterning process to form a semiconductor layer disposed on the substrate.
  • the active layer of each transistor may include: a first region, a second region, and a channel region between the first region and the second region.
  • the material of the semiconductor layer may include, for example, polysilicon.
  • the channel region may not be doped with impurities and has semiconductor properties.
  • the first region and the second region may be doped regions on both sides of the channel region, doped with impurities, and therefore have conductivity.
  • the impurities may vary depending on the type of transistor.
  • the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor.
  • the portion of the active layer between the transistors may be interpreted as a wiring doped with impurities, which may be used to electrically connect the transistors.
  • the material of the semiconductor layer may include amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO) and other materials.
  • a-IGZO amorphous indium gallium zinc oxide material
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • This embodiment may be applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • FIG7 is a schematic plan view of the display substrate after the semiconductor layer is formed in FIG6.
  • the semiconductor layer of the first circuit unit may include at least: active layers of multiple transistors of the first pixel circuit (for example, including the first active layer 110 of the first transistor of the first pixel circuit of the present row, the second active layer 120 of the second transistor, the third active layer 130 of the third transistor, the fourth active layer 140 of the fourth transistor, the fifth active layer 150 of the fifth transistor, the sixth active layer 160 of the sixth transistor, and the seventh active layer 170 of the seventh transistor of the first pixel circuit of the previous row).
  • the active layers of the seven transistors of the first pixel circuit may be an integrated structure connected to each other.
  • the semiconductor layer of the second circuit unit may include at least: active layers of multiple transistors of the second pixel circuit (for example, including the first active layer 210 of the first transistor of the second pixel circuit of the present row, the second active layer 220 of the second transistor, the third active layer 230 of the third transistor, the fourth active layer 240 of the fourth transistor, the fifth active layer 250 of the fifth transistor, and the sixth active layer 260 of the sixth transistor), and the seventh active layer 370 of the seventh transistor of the invalid pixel circuit of the previous row.
  • the active layers of the seven transistors of the second pixel circuit may be an integrated structure connected to each other.
  • the semiconductor layer of the invalid circuit unit may include at least: active layers of multiple transistors of the invalid pixel circuit (for example, including the first active layer 310 of the first transistor of the invalid pixel circuit of this row, the second active layer 320 of the second transistor, the third active layer 330 of the third transistor, the fourth active layer 340 of the fourth transistor, the fifth active layer 350 of the fifth transistor, and the sixth active layer 360 of the sixth transistor), and the seventh active layer 270 of the seventh transistor of the second pixel circuit of the previous row.
  • the active layers of the seven transistors of the invalid pixel circuit may be an integrated structure connected to each other.
  • the invalid pixel circuit and the second pixel circuit may be spaced apart in the second direction Y.
  • the seventh active layer of the seventh transistor of the invalid pixel circuit can extend to the second circuit unit, and the seventh active layer of the seventh transistor of the second pixel circuit can extend to the invalid circuit unit.
  • the seventh active layer of the seventh transistor of a row of first pixel circuits can extend to the first circuit unit of the next row.
  • the arrangement of the active layers of the pixel circuits in the first display area of this example can be conducive to the compact arrangement of the pixel circuits, thereby saving space.
  • the first active layers 110, 210, and 310 may be approximately in an “n” shape
  • the second active layers 120, 220, and 320 and the sixth active layers 160, 260, and 360 may be approximately in an “L” shape
  • the third active layers 130, 230, and 330 may be approximately in an “ ⁇ ” shape
  • the fourth active layers 140, 240, and 340 the fifth active layers 150, 250, and 350
  • the seventh active layers 170, 270, and 370 may be approximately in an “I” shape.
  • This embodiment is not limited thereto.
  • the first region of the first active layer 110 of the first pixel circuit, the first region of the fourth active layer 140, the first region of the fifth active layer 150, and the first region of the seventh active layer 170 can be separately provided.
  • the second region of the first active layer 110 of the first pixel circuit can also serve as the first region of the second active layer 120.
  • the first region of the third active layer 130 can also serve as the second region of the fourth active layer 140 and the second region of the fifth active layer 150; the second region of the third active layer 130 can also serve as the second region of the second active layer 120 and the first region of the sixth active layer 160; the second region of the sixth active layer 160 can also serve as the first region of the seventh active layer 170.
  • the structures of the active layers of the invalid pixel circuit and the second pixel circuit are similar to those of the active layer of the first pixel circuit, so they are not described in detail here.
  • the circumscribed rectangle of the active layer of the first pixel circuit may have a first length L11 along the first direction X, and the first length L11 may be understood as the distance between the left edge and the right edge of the circumscribed rectangle of the first pixel circuit.
  • the circumscribed rectangle of the active layer of the second pixel circuit may have a second length L12 along the first direction X, and the second length L12 may be understood as the distance between the left edge and the right edge of the circumscribed rectangle of the second pixel circuit.
  • the circumscribed rectangle of the active layer of the invalid pixel circuit may have a third length L13 along the first direction X, and the third length L13 may be understood as the distance between the left edge and the right edge of the circumscribed rectangle of the invalid pixel circuit.
  • the third length L13 and the second length L12 may be substantially the same, and the first length L11 may be greater than the second length L12.
  • the length b of the first pixel circuit along the first direction X may be greater than or equal to the first length L11
  • the length d1 of the second pixel circuit along the first direction X may be greater than or equal to the second length L12
  • the length f1 of the invalid pixel circuit along the first direction X may be greater than or equal to the third length L13.
  • the circumscribed rectangle of the active layer of the first pixel circuit may have a fourth length L21 along the second direction Y, and the fourth length L21 may be understood as the distance between the circumscribed edge of the first active layer 110 of the first pixel circuit of the present row and the circumscribed edge of the first active layer of the first pixel circuit of the next row in the second direction Y.
  • the circumscribed rectangle of the active layer of the second pixel circuit may have a fifth length L22 along the second direction Y, and the fifth length L22 may be understood as the distance between the circumscribed edge of the first active layer 210 of the second pixel circuit and the circumscribed edge of the first active layer 310 of the next row of invalid pixel circuits in the second direction Y.
  • the circumscribed rectangle of the active layer of the invalid pixel circuit may have a sixth length L23 along the second direction Y, and the sixth length L23 may be understood as the distance between the circumscribed edge of the first active layer 310 of the invalid pixel circuit and the circumscribed edge of the first active layer 210 of the next row of second pixel circuits in the second direction Y.
  • the fourth length L21 may be greater than the sixth length L23, and the fifth length L22 may be greater than the fourth length L21.
  • the fifth length L22 may be greater than the fourth length L21, and the fourth length L21 to be greater than the sixth length L23, it is advantageous to provide the reduced occupied space of the invalid pixel circuit in the second direction Y to the second pixel circuit, so as to use the occupied space of the second pixel circuit along the second direction Y to compensate for the reduced occupied space in the first direction X.
  • the fourth length L21 may be the length a of the first pixel circuit in the second direction Y
  • the fifth length L22 may be the length a of the first pixel circuit in the second direction Y
  • the sixth length L22 may be a length c1 of the second pixel circuit in the second direction Y
  • the sixth length L23 may be a length e1 of the invalid pixel circuit in the second direction Y.
  • a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer.
  • the first conductive layer may also be referred to as a first gate metal layer.
  • FIG8A is a schematic plan view of the display substrate after the first conductive layer is formed in FIG6.
  • FIG8B is a schematic view of the first conductive layer in FIG8A.
  • the first conductive layer of the first circuit unit may include at least: gates of multiple transistors of the first pixel circuit (for example, the gates of the first transistor 11 to the sixth transistor 16 of the first pixel circuit of the current row, and the gate of the seventh transistor of the first pixel circuit of the previous row) and the first electrode 181 of the storage capacitor, the first reset control line (for example, the first reset control line RST1(m) or RST1(m+1) or RST1(m+2)), the scan line (for example, the scan line GL(m) or GL(m+1)), and the light emitting control line (for example, the light emitting control line EML(m) or EML(m+1)).
  • the first reset control line for example, the first reset control line RST1(m) or RST1(m+1) or RST1(
  • the first conductive layer of the second circuit unit may include at least: gates of multiple transistors of the second pixel circuit (for example, gates of the first transistor 21 to the sixth transistor 26 of the second pixel circuit of the present row, the first plate 281 of the storage capacitor), the gate of the seventh transistor 37 of the invalid pixel circuit of the previous row, a first reset control line (for example, the first reset control line RST1(m) or RST1(m+1) or RST1(m+2)), a scan line (for example, a scan line GL(m) or GL(m+1)), and a light-emitting control line (for example, a light-emitting control line EML(m) or EML(m+1)).
  • a first reset control line for example, the first reset control line RST1(m) or RST1(m+1) or RST1(m+2
  • a scan line for example, a scan line GL(m) or GL(m+1)
  • a light-emitting control line for
  • the first conductive layer of the invalid circuit unit may include at least: gates of multiple transistors of the invalid pixel circuit (for example, gates of the first transistor 31 to the sixth transistor 36 of the invalid pixel circuit of this row, the first plate 381 of the storage capacitor), the gate of the seventh transistor 27 of the second pixel circuit of the previous row, a first reset control line (for example, the first reset control line RST1(m) or RST1(m+1) or RST1(m+2)), a scan line (for example, a scan line GL(m) or GL(m+1)), and a light-emitting control line (for example, a light-emitting control line EML(m) or EML(m+1)).
  • a first reset control line for example, the first reset control line RST1(m) or RST1(m+1) or RST1(m+2
  • a scan line for example, a scan line GL(m) or GL(m+1)
  • a light-emitting control line for example
  • the first reset control line RST1(m) is located on one side of the scan line GL(m) in the second direction Y.
  • the scan line GL(m) is located on one side of the light emitting control line EML(m) in the second direction Y.
  • the first plate 181 of the storage capacitor of the first pixel circuit of the Mth row and the first plate 381 of the storage capacitor of the invalid pixel circuit may be arranged at intervals along the first direction X and located between the light emitting control line EML(m) and the scan line GL(m) in the second direction Y.
  • the first plate 181 of the storage capacitor of the first pixel circuit of the M+1th row and the first plate 281 of the storage capacitor of the second pixel circuit may be arranged at intervals along the first direction X and located between the light emitting control line EML(m+1) and the scan line GL(m+1) in the second direction Y.
  • the shapes of the first reset control lines RST1(m), RST1(m+1), and RST1(m+2) can be roughly zigzag lines extending along the first direction X.
  • the area where the first reset control line RST1(m) overlaps with the first active layer of the first transistor 11 of the first pixel circuit of the current row can be used as the gate of the first transistor 11 of the dual-gate structure
  • the area where the first reset control line RST1(m) overlaps with the seventh active layer of the seventh transistor of the first pixel circuit of the previous row can be used as the gate of the seventh transistor.
  • the area where the first reset control line RST1(m) overlaps with the first active layer of the first transistor 31 of the invalid pixel circuit of the current row can be used as the gate of the first transistor 31 of the dual-gate structure, and the area where the first reset control line RST1(m) overlaps with the seventh active layer of the seventh transistor of the second pixel circuit of the previous row can be used as the gate of the seventh transistor.
  • the area where the first reset control line RST1(m+1) overlaps with the first active layer of the first transistor 21 of the second pixel circuit of the current row can be used as the gate of the first transistor 21 of the dual-gate structure, and the area where the first reset control line RST1(m+1) overlaps with the seventh active layer of the seventh transistor of the invalid pixel circuit of the previous row can be used as the gate of the seventh transistor.
  • the shape of the scan lines GL(m) and GL(m+1) can be roughly a zigzag shape with the main part extending along the first direction X.
  • the area where the scan line GL(m) overlaps with the second active layer of the second transistor 12 of the first pixel circuit of the row can be used as the first gate of the second transistor 12 of the dual-gate structure, and the area where the scan line GL(m) overlaps with the fourth active layer of the fourth transistor 14 of the first pixel circuit of the row can be used as the gate of the fourth transistor 14.
  • the area where the scan line GL(m) overlaps with the second active layer of the second transistor 32 of the invalid pixel circuit of the row can be used as the first gate of the second transistor 32 of the dual-gate structure, and the area where the scan line GL(m) overlaps with the fourth active layer of the fourth transistor 34 of the invalid pixel circuit of the row can be used as the gate of the fourth transistor 34.
  • the area where the scan line GL(m+1) overlaps with the second active layer of the second transistor 22 of the second pixel circuit of the row can be used as the first gate of the second transistor 22 of the dual-gate structure, and the area where the scan line GL(m+1) overlaps with the fourth active layer of the fourth transistor 24 of the second pixel circuit of the row can be used as the gate of the fourth transistor 24.
  • a first protrusion 191 may be provided on one side of the scan line GL(m) away from the first reset control line RST1(m).
  • the shape of the first protrusion 191 may be substantially rectangular.
  • the first end of the first protrusion 191 is connected to the scan line GL(m), and the second end of the first protrusion 191 extends toward the first electrode 181 of the storage capacitor.
  • the area where the first protrusion 191 overlaps with the second active layer of the second transistor 12 of the first pixel circuit of the row may serve as the second gate of the second transistor 12 of the dual-gate structure.
  • the scan line GL(m) and the first protrusion 191 may be an integrated structure connected to each other.
  • a second protrusion 192 may be provided on one side of the scan line GL(m+1) away from the first reset control line RST1(m+1).
  • the shape of the second protrusion 192 may be substantially rectangular.
  • the first end of the second protrusion 192 is connected to the scan line GL(m+1), and the second end of the second protrusion 192 extends in the direction of the first electrode plate 281 of the storage capacitor.
  • the area where the second protrusion 192 overlaps with the second active layer of the second transistor 22 of the second pixel circuit of this row may serve as the second gate of the second transistor 22 of the dual-gate structure.
  • the scan line GL(m+1) and the second protrusion 192 may be an integral structure connected to each other.
  • the shape of the second protrusion 192 may be substantially the same as that of the first protrusion 191, and the size of the second protrusion 192 may be less than or equal to the size of the first protrusion 191.
  • the length of the second protrusion 192 along the first direction X may be less than or equal to the length of the first protrusion 191 along the first direction X
  • the length of the second protrusion 192 along the second direction Y may be greater than or equal to the length of the first protrusion 191 along the second direction Y.
  • a third protrusion 193 may be provided on one side of the scan line GL(m) away from the first reset control line RST1(m).
  • the shape of the third protrusion 193 may be substantially rectangular.
  • the first end of the third protrusion 193 is connected to the scan line GL(m), and the second end of the third protrusion 193 extends in the direction of the first electrode plate 381 of the storage capacitor.
  • the area where the third protrusion 193 overlaps with the second active layer of the second transistor 32 of the invalid pixel circuit of this row may serve as the second gate of the second transistor 32 of the dual-gate structure.
  • the scan line GL(m) and the third protrusion 193 may be an integral structure connected to each other.
  • the shape and size of the third protrusion 193 may be substantially the same as the shape and size of the second protrusion 192.
  • the shape of the first plate 181 of the storage capacitor of the first pixel circuit can be roughly rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the first plate 181 on the substrate and the orthographic projection of the third active layer of the third transistor 13 on the substrate can at least partially overlap, and the first plate 181 can serve as the first electrode (i.e., the lower plate) of the storage capacitor of the first pixel circuit and the gate of the third transistor 13 at the same time.
  • the shape of the first plate 281 of the storage capacitor of the second pixel circuit can be roughly rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the first plate 281 on the substrate and the orthographic projection of the third active layer of the third transistor 23 on the substrate can at least partially overlap, and the first plate 281 can simultaneously serve as the first electrode (i.e., the lower plate) of the storage capacitor of the second pixel circuit and the gate of the third transistor 23.
  • the length L33 of the first plate 281 along the first direction X can be less than the length L31 of the first plate 181 along the first direction X, and the length L34 of the first plate 281 along the second direction Y can be greater than the length L32 of the first plate 181 along the second direction Y.
  • the shape of the first plate 381 of the storage capacitor of the invalid pixel circuit is It can be roughly rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the first electrode plate 381 on the substrate can at least partially overlap with the orthographic projection of the third active layer of the third transistor 33 on the substrate, and the first electrode plate 381 can simultaneously serve as the first electrode (i.e., the lower electrode plate) of the storage capacitor of the invalid pixel circuit and the gate of the third transistor 33.
  • the length L35 of the first electrode plate 381 along the first direction X can be less than the length L31 of the first electrode plate 181 along the first direction X, for example, it can be equal to the length L33 of the first electrode plate 281 along the first direction X; the length L36 of the first electrode plate 381 along the second direction Y can be less than the length L34 of the first electrode plate 281 along the second direction Y, for example, it can be less than the length L32 of the first electrode plate 181 along the second direction Y.
  • the shape of the light emitting control lines EML(m) and EML(m+1) may be substantially a straight line extending along the first direction X.
  • the area where the light emitting control line EML(m) overlaps with the fifth active layer of the fifth transistor 15 of the first pixel circuit of the present row can be used as the gate of the fifth transistor 15, and the area where the light emitting control line EML(m) overlaps with the sixth active layer of the sixth transistor 16 of the first pixel circuit of the present row can be used as the gate of the sixth transistor 16.
  • the area where the light emitting control line EML(m) overlaps with the fifth active layer of the fifth transistor 35 of the invalid pixel circuit of the present row can be used as the gate of the fifth transistor 35, and the area where the light emitting control line EML(m) overlaps with the sixth active layer of the sixth transistor 36 of the invalid pixel circuit of the present row can be used as the gate of the sixth transistor 36.
  • the area where the light emitting control line EML(m+1) overlaps with the fifth active layer of the fifth transistor 25 of the second pixel circuit of the present row can be used as the gate of the fifth transistor 25, and the area where the light emitting control line EML(m+1) overlaps with the sixth active layer of the sixth transistor 26 of the second pixel circuit of the present row can be used as the gate of the sixth transistor 26.
  • the same type of routing lines extending along the first direction X in the invalid circuit unit can be moved a certain distance (e.g., 2 microns) in the second direction Y to achieve compression of the length of the invalid pixel circuit in the second direction Y.
  • the semiconductor layer can be conductorized using the first conductive layer as a shield, and the semiconductor layer in the area shielded by the first conductive layer can form channel regions of seven transistors of the first pixel circuit, seven transistors of the second pixel circuit, and seven transistors of the invalid pixel circuit, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first and second areas of the seven transistors of the first pixel circuit, the first and second areas of the seven transistors of the second pixel circuit, and the first and second areas of the seven transistors of the invalid pixel circuit can all be conductorized.
  • a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed, and the second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer.
  • the second conductive layer may also be referred to as a second gate metal layer.
  • FIG9A is a plan view schematic diagram of the display substrate after the second conductive layer is formed in FIG6.
  • FIG9B is a schematic diagram of the second conductive layer in FIG9A.
  • the second conductive layer of the first circuit unit may include at least: a second plate 182 of the storage capacitor of the first pixel circuit, a first initial signal line (e.g., a first initial signal line INIT1(m) or INIT1(m+1)), and a second initial signal line (e.g., a second initial signal line INIT2(m-1) or INIT2(m)).
  • the second conductive layer of the second circuit unit may include at least: a second plate 282 of the storage capacitor of the second pixel circuit, a first initial signal line (e.g., a first initial signal line INIT1(m) or INIT1(m+1)), and a second initial signal line (e.g., a second initial signal line INIT2(m-1) or INIT2(m)).
  • the second conductive layer of the invalid circuit unit may include at least: a second plate 382 of the storage capacitor of the invalid pixel circuit, a first initial signal line (for example, the first initial signal line INIT1(m) or INIT1(m+1)), and a second initial signal line (for example, the second initial signal line INIT2(m-1) or INIT2(m)).
  • the positive projection of the second initial signal line INIT2(m-1) on the substrate is located on one side of the first reset control line RST1(m) in the second direction Y.
  • the first initial signal line INIT1(m) may be located on one side of the second initial signal line INIT2(m-1) in the opposite direction of the second direction Y.
  • the second electrode of the storage capacitor of the first pixel circuit of the Mth row The plate 182 and the second plate 382 of the storage capacitor of the invalid pixel circuit may be arranged at intervals along the first direction X and located on one side of the first initial signal line INIT1 (m) in the opposite direction of the second direction Y.
  • the orthographic projection of the second initial signal line INIT2(m) on the substrate is located on one side of the first reset control line RST1(m+1) in the second direction Y.
  • the first initial signal line INIT1(m+1) may be located on one side of the second initial signal line INIT2(m) in the opposite direction of the second direction Y.
  • the second plate 182 of the storage capacitor of the first pixel circuit and the second plate 282 of the storage capacitor of the second pixel circuit of the M+1th row may be arranged at intervals along the first direction X and located on one side of the first initial signal line INIT1(m+1) in the opposite direction of the second direction Y.
  • the second initial signal line INIT2(m-1) and the first initial signal line INIT1(m) may be shaped substantially like a zigzag line with the main portion extending along the first direction X.
  • the structures of the second initial signal line INIT2(m+1) and the first initial signal line INIT1(m+2) are as described above, and are not described in detail here.
  • a fourth protrusion 194 may be provided on a side of the first initial signal line INIT1(m) close to the second initial signal line INIT2(m-1), and the shape of the fourth protrusion 194 may be substantially rectangular.
  • the first end of the fourth protrusion 194 is connected to the first initial signal line INIT1(m), and the second end of the fourth protrusion 194 extends in the direction of the second initial signal line INIT2(m-1).
  • the fourth protrusion 194 may be located between the first region of the first active layer and the first region of the adjacent seventh active layer.
  • the fourth protrusion 194 and the first initial signal line INIT1(m) may be an integral structure connected to each other.
  • the size of the fourth protrusion 194 in the invalid pixel circuit may be smaller than the size of the fourth protrusion 194 in the first circuit unit.
  • a fifth protrusion 195 may be provided on one side of the first initial signal line INIT1(m) away from the second initial signal line INIT2(m-1), and the shape of the fifth protrusion 195 may be substantially rectangular.
  • the fifth protrusion 195 and the fourth protrusion 194 may be arranged at intervals along the first direction X.
  • the length of the fifth protrusion 195 along the first direction X may be less than the length of the fourth protrusion 194 along the first direction X.
  • the first end of the fifth protrusion 195 is connected to the first initial signal line INIT1(m), and the second end of the fifth protrusion 195 extends in the direction of the second plate 182 or 382 of the storage capacitor.
  • the fifth protrusion 195 may be located between the first region of the second active layer of the first pixel circuit (or the invalid pixel circuit) and the first region of the fourth active layer.
  • the fifth protrusion 195 and the first initial signal line INIT1(m) may be an integral structure connected to each other. This example helps to shield the influence of other signals on the fourth transistor by providing the fifth protrusion 195.
  • the size of the fifth protrusion 195 within the ineffective circuit unit may be smaller than the size of the fifth protrusion 195 within the first circuit unit.
  • a fourth protrusion 194 may be provided on a side of the first initial signal line INIT1(m+1) close to the second initial signal line INIT2(m), and the shape of the fourth protrusion 194 may be substantially rectangular.
  • a fifth protrusion 195 may be provided on a side of the first initial signal line INIT1(m+1) away from the second initial signal line INIT2(m).
  • the size of the fifth protrusion in the second circuit unit may be smaller than the size of the fifth protrusion in the first circuit unit, and the size of the fourth protrusion in the second circuit unit may be smaller than the size of the fourth protrusion in the first circuit unit.
  • the second plate 182 of the storage capacitor of the first pixel circuit may partially overlap with the orthographic projection of the first plate 181 on the substrate.
  • the second plate 182 may have a first opening K1, the first opening K1 may be substantially rectangular, and the orthographic projection of the first opening K1 on the substrate may be located within the orthographic projection range of the first plate 181 on the substrate.
  • the first plate of the storage capacitor of the first pixel circuit may serve as a first electrode of the storage capacitor, and the second plate of the storage capacitor may serve as a second electrode of the storage capacitor.
  • the second plate 282 of the storage capacitor of the second pixel circuit may partially overlap with the orthographic projection of the first plate 281 on the substrate.
  • the second plate 282 may have a second opening K2, which may be approximately rectangular, and the orthographic projection of the second opening K2 on the substrate may be located within the orthographic projection range of the first plate 281 on the substrate.
  • the first plate of the storage capacitor of the second pixel circuit may serve as the first electrode of the storage capacitor, and the second plate of the storage capacitor may serve as the second electrode of the storage capacitor.
  • the size of the second opening K2 may be smaller than The size of the first opening K1, for example, the length of the second opening K2 along the first direction X may be smaller than the length of the first opening K1 along the first direction X, and the length of the second opening K2 along the second direction Y may be greater than or equal to the length of the first opening K1 along the second direction Y.
  • the second plate 382 of the storage capacitor of the invalid pixel circuit may partially overlap with the orthographic projection of the first plate 381 on the substrate.
  • the second plate 382 may have a third opening K3, the third opening K3 may be approximately rectangular, and the orthographic projection of the third opening K3 on the substrate may be located within the orthographic projection range of the first plate 381 on the substrate.
  • the first plate of the storage capacitor of the invalid pixel circuit may serve as a first electrode of the storage capacitor, and the second plate of the storage capacitor may serve as a second electrode of the storage capacitor.
  • the size of the third opening K3 may be smaller than the size of the first opening K1.
  • the length of the third opening K3 along the first direction X may be smaller than the length of the first opening K1 along the first direction X
  • the length of the third opening K3 along the second direction Y may be smaller than the length of the first opening K1 along the second direction Y.
  • the second plate 182 (or 282 or 382) may be provided with a plate connection line 183 on one side of the first direction X or on one side in the opposite direction of the first direction X.
  • the first end of the plate connection line 183 may be connected to the second plate of the present circuit unit, and the second end may be connected to the second plate of the adjacent circuit unit after extending along the first direction X or in the opposite direction of the first direction X, so that the second plates of adjacent circuit units on a unit row may be connected to each other.
  • the second plate 182 of the first pixel circuit in the first circuit unit may be connected to the second plate 382 of the invalid pixel circuit through the plate connection line 183, or may be connected to the second plate 282 of the second pixel circuit through the plate connection line 183.
  • the plate connection line 183 and the second plates 182, 282 and 382 may be an integrated structure connected to each other.
  • the second electrodes (including second electrodes 182, 282 and 382) of the integrated structure of multiple circuit units in this example can be reused as transverse traces extending along the first direction X for transmitting the first voltage signal, which can not only ensure that the multiple second electrodes in a unit row have the same potential, but also reduce the voltage drop of the first voltage signal, which is beneficial to improving the uniformity of the display substrate and ensuring the display effect.
  • a third insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the third insulating film is patterned by a patterning process to form a third insulating layer.
  • a plurality of vias are provided in the third insulating layer of each circuit unit.
  • the third insulating layer may also be referred to as an interlayer insulating layer.
  • FIG10 is a schematic plan view of the display substrate after the third insulating layer is formed in FIG6.
  • the plurality of vias of the first circuit unit may include at least: the first via V1 to the tenth via V10.
  • the plurality of vias of the second circuit unit may include at least: the eleventh via V11 to the twentieth via V20.
  • the plurality of vias of the invalid circuit unit may include at least: the twenty-first via V21 to the thirtieth via V30.
  • the third insulating layer, the second insulating layer, and the first insulating layer in the first via hole V1 to the sixth via hole V6, the eleventh via hole V11 to the sixteenth via hole V16, and the twenty-first via hole V21 to the twenty-sixth via hole V26 can be removed to expose a portion of the surface of the semiconductor layer.
  • the third insulating layer and the second insulating layer in the seventh via hole V7, the seventeenth via hole V17, and the twenty-seventh via hole V27 can be removed to expose a portion of the surface of the first conductive layer.
  • the third insulating layer in the eighth via hole V8 to the tenth via hole V10, the eighteenth via hole V18 to the twentieth via hole V20, and the twenty-eighth via hole V28 to the thirtieth via hole V30 can be removed to expose a portion of the surface of the second conductive layer.
  • a third conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the third conductive film is patterned using a patterning process to form a third conductive layer disposed on the third insulating layer.
  • the third conductive layer may also be referred to as a first source-drain metal layer.
  • FIG. 11A is a schematic plan view of the display substrate after the third conductive layer is formed in FIG. 6.
  • FIG. 11B is a schematic view of the third conductive layer in FIG. 11A.
  • the third conductive layer of the first circuit unit may include at least: a plurality of connection electrodes of the first pixel circuit (for example, including the first connection electrode 401 to the sixth connection electrode 406).
  • the third conductive layer of the second circuit unit may include at least: a plurality of connection electrodes (for example, including the tenth connection electrode 401 to the sixth connection electrode 406).
  • the third conductive layer of the ineffective circuit unit may include at least: a plurality of connecting electrodes (eg, including the twenty-first connecting electrode 421 to the thirty-sixth connecting electrode 426).
  • the third conductive layer of the first display area may further include: a first auxiliary wiring 45.
  • the first auxiliary wiring 45 may be located at the junction of adjacent circuit unit rows.
  • the first auxiliary wiring 45 may be roughly in the shape of a zigzag line extending along the first direction X.
  • the first auxiliary wiring 45 may be configured to transmit a first voltage signal or a second voltage signal line to ensure the uniformity of the first voltage signal or the second voltage signal in the first display area.
  • the first auxiliary wiring 45 may be configured to be electrically connected to the data line and the data fan-out line extending to the peripheral area, so that the data fan-out line of the peripheral area is wound in the first display area, which is conducive to achieving a narrow frame.
  • the shape of the first connection electrode 401 may be substantially a strip shape extending along the first direction X.
  • One end of the first connection electrode 401 may be electrically connected to the first region of the first active layer of the first pixel circuit through the first via hole V1, and the other end may be electrically connected to the fourth protrusion 194 through the eighth via hole V8 to achieve electrical connection with the first initial signal line INIT1(m).
  • the shape of the second connection electrode 402 may be substantially a strip shape extending along the second direction Y.
  • One end of the second connection electrode 402 may be electrically connected to the first region of the second active layer of the first pixel circuit through the second via hole V2, and the other end may be electrically connected to the first electrode plate 181 of the storage capacitor of the first pixel circuit through the seventh via hole V7.
  • the shape of the third connection electrode 403 may be substantially rectangular.
  • the third connection electrode 403 may be electrically connected to the first region of the fourth active layer of the first pixel circuit through the third via hole V3.
  • the shape of the fourth connection electrode 404 can be substantially 9-shaped.
  • the fourth connection electrode 404 can be electrically connected to the first region of the fifth active layer of the first pixel circuit through the fifth via hole V5, and can also be electrically connected to the second plate 182 of the storage capacitor of the first pixel circuit through the ninth via hole V9.
  • the shape of the fifth connection electrode 405 may be substantially rectangular.
  • the fifth connection electrode 405 may be electrically connected to the second region of the sixth active layer of the first pixel circuit through the fourth via hole V4.
  • the shape of the sixth connection electrode 406 may be substantially a strip shape extending along the second direction Y.
  • One end of the sixth connection electrode 406 may be electrically connected to the first region of the seventh active layer of the first pixel circuit of the previous row through the sixth via hole V6, and the other end may be electrically connected to the second initial signal line INIT2(m-1) through the tenth via hole V10.
  • the shape of the eleventh connection electrode 411 may be substantially a strip shape extending along the first direction X.
  • One end of the eleventh connection electrode 411 may be electrically connected to the first region of the first active layer of the second pixel circuit through the eleventh via hole V11, and the other end may be electrically connected to the fourth protrusion 194 through the eighteenth via hole V18, thereby achieving electrical connection with the first initial signal line INIT1(m+1).
  • the shape of the twelfth connection electrode 412 may be substantially a strip shape extending along the second direction Y.
  • One end of the twelfth connection electrode 412 may be electrically connected to the first region of the second active layer of the second pixel circuit through the twelfth via hole V12, and the other end may be electrically connected to the first electrode plate 281 of the storage capacitor of the second pixel circuit through the seventeenth via hole V17.
  • the shape of the thirteenth connection electrode 413 may be substantially rectangular.
  • the thirteenth connection electrode 413 may be electrically connected to the first region of the fourth active layer of the second pixel circuit through the thirteenth via hole V13.
  • the shape of the fourteenth connection electrode 414 may be substantially 9-shaped.
  • the fourteenth connection electrode 414 may be electrically connected to the first region of the fifth active layer of the second pixel circuit through the fifteenth via hole V15, and may also be electrically connected to the second electrode plate 282 of the storage capacitor of the second pixel circuit through the nineteenth via hole V19.
  • the shape of the fifteenth connection electrode 415 may be substantially rectangular.
  • the fifteenth connection electrode 415 may be electrically connected to the second region of the sixth active layer of the second pixel circuit through the fourteenth via hole V14.
  • the shape of the sixteenth connection electrode 416 may be substantially a bar shape extending along the second direction Y.
  • One end of the sixteenth connection electrode 416 may be electrically connected to the first region of the seventh active layer of the invalid pixel circuit in the previous row through the sixteenth via hole V16 , and the other end may be electrically connected to the second initial signal line INIT2 (m) through the twentieth via hole V20 .
  • the shape of the twenty-first connection electrode 421 may be substantially a strip shape extending along the first direction X.
  • One end of the twenty-first connection electrode 421 may be electrically connected to the first region of the first active layer of the invalid pixel circuit through the twenty-first via hole V21, and the other end may be electrically connected to another fourth protrusion 194 through the twenty-eighth via hole V28 to achieve electrical connection with the first initial signal line INIT1(m).
  • the shape of the twenty-second connection electrode 422 may be substantially a strip shape extending along the second direction Y.
  • One end of the twenty-second connection electrode 422 may be electrically connected to the first region of the second active layer of the invalid pixel circuit through the twenty-second via hole V22, and the other end may be electrically connected to the first electrode plate 381 of the storage capacitor of the invalid pixel circuit through the twenty-seventh via hole V27.
  • the shape of the twenty-third connection electrode 423 may be substantially rectangular.
  • the twenty-third connection electrode 423 may be electrically connected to the first region of the fourth active layer of the ineffective pixel circuit through the twenty-third via hole V23.
  • the shape of the twenty-fourth connection electrode 424 can be substantially in the shape of a letter "9".
  • the twenty-fourth connection electrode 424 can be electrically connected to the first region of the fifth active layer of the invalid pixel circuit through the twenty-fifth via hole V25, and can also be electrically connected to the second electrode plate 382 of the storage capacitor of the invalid pixel circuit through the twenty-ninth via hole V29.
  • the shape of the twenty-fifth connection electrode 425 may be substantially rectangular.
  • the twenty-fifth connection electrode 425 may be electrically connected to the second region of the sixth active layer of the ineffective pixel circuit through the twenty-fourth via hole V24.
  • the shape of the twenty-sixth connection electrode 426 may be substantially a strip shape extending along the second direction Y.
  • One end of the twenty-sixth connection electrode 426 may be electrically connected to the first region of the seventh active layer of the second pixel circuit of the previous row through the twenty-sixth via hole V26, and the other end may be electrically connected to the second initial signal line INIT2(m-1) through the thirtieth via hole V30.
  • a fourth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and then a fifth insulating film is coated, and the fifth insulating film and the fourth insulating film are patterned in sequence using a patterning process to form a fourth insulating layer and a fifth insulating layer.
  • the fourth insulating layer and the fifth insulating layer of each circuit unit may be provided with a plurality of vias.
  • the fourth insulating layer may also be referred to as a passivation layer
  • the fifth insulating layer may also be referred to as a first planarization layer.
  • FIG12 is a schematic plan view of the display substrate after the fifth insulating layer is formed in FIG6.
  • the plurality of vias of the first circuit unit may include at least: a thirty-first via V31, a thirty-second via V32, and a thirty-third via V33.
  • the plurality of vias of the second circuit unit may include at least: a thirty-fourth via V34, a thirty-fifth via V35, and a thirty-sixth via V36.
  • the plurality of vias of the invalid circuit unit may include at least: a thirty-seventh via V37, a thirty-eighth via V38, and a thirty-ninth via V39.
  • the fifth insulating layer and the fourth insulating layer within the thirty-first via V31 to the thirty-ninth via V39 may be removed to expose a portion of the surface of the third conductive layer.
  • a fourth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive film is patterned using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer.
  • the fourth conductive layer may also be referred to as a second source-drain metal layer.
  • FIG13 is a schematic diagram of the fourth conductive layer in FIG6.
  • the fourth conductive layer of the first circuit unit may include at least: a first anode connection electrode 441, a data line 46, and a first power line 47.
  • the fourth conductive layer of the second circuit unit may include at least: a second anode connection electrode 442, a data line 48, and a first power line 49.
  • the fourth conductive layer of the invalid circuit unit may include at least: a third anode connection electrode 443, a data line 48, and a first power line 49.
  • the shape of the first anode connection electrode 441 may be substantially rectangular, and the corners of the rectangle may be chamfered.
  • the first anode connection electrode 441 may be electrically connected to the fifth connection electrode 405 through the thirty-third via hole V33 to achieve electrical connection with the sixth transistor of the first pixel circuit.
  • the second anode connection electrode 442 may be substantially rectangular in shape.
  • the second anode connection electrode 442 may be electrically connected to the fifteenth connection electrode 415 through the thirty-sixth via hole V36 to achieve electrical connection to the sixth transistor of the second pixel circuit.
  • the shape of the third anode connection electrode 443 may be substantially rectangular.
  • the third anode connection electrode 443 may be electrically connected to the twenty-fifth connection electrode 425 through the thirty-ninth via hole V39 to achieve electrical connection with the sixth transistor of the invalid pixel circuit.
  • the shape of the first power lines 47 and 49 can be roughly a fold line extending along the second direction Y.
  • the first power line 47 can be electrically connected to the fourth connection electrode 404 through the thirty-second via V32 to achieve electrical connection with the fifth transistor of the first pixel circuit and the second plate of the storage capacitor.
  • the positive projection of the first power line 47 on the substrate can cover the positive projection of the second connection electrode 402 on the substrate. Since the second connection electrode 402 connects the second area of the first active layer of the first pixel circuit, the first area of the second active layer, the gate of the third transistor and the first plate of the storage capacitor, the second connection electrode 402 can serve as the first node of the first pixel circuit.
  • the first power line 47 can realize the transmission of a constant first voltage signal, can shield the influence of other signals in the first pixel circuit on the first node, avoid other signals (such as data voltage jump) from affecting the voltage of the first node of the first pixel circuit, and can improve the display effect.
  • the first power line 49 can be electrically connected to the fourteenth connection electrode 414 through the thirty-fifth via V35 to achieve electrical connection with the fifth transistor of the second pixel circuit and the second plate of the storage capacitor.
  • the positive projection of the first power line 49 on the substrate can cover the positive projection of the twelfth connection electrode 412 on the substrate. Since the twelfth connection electrode 412 connects the second area of the first active layer of the second pixel circuit, the first area of the second active layer, the gate of the third transistor and the first plate of the storage capacitor, the twelfth connection electrode 412 can serve as the first node of the second pixel circuit.
  • the first power line 49 can realize the transmission of a constant first voltage signal, can shield the influence of other signals in the second pixel circuit on the first node, avoid other signals (such as data voltage jump) from affecting the voltage of the first node of the second pixel circuit, and can improve the display effect.
  • the first power line 49 may also be electrically connected to the twenty-fourth connection electrode 424 through the thirty-eighth via hole V38.
  • the orthographic projection of the first power line 49 on the substrate may cover the orthographic projection of the twenty-second connection electrode 422 on the substrate.
  • the first power line 49 may shield the influence of other signals in the invalid pixel circuit on the first node of the invalid pixel circuit.
  • the shape of the data lines 46 and 48 can be substantially a straight line extending along the second direction Y.
  • the data line 46 can be electrically connected to the third connection electrode 403 through the thirty-first via hole V31 to achieve electrical connection with the fourth transistor of the first pixel circuit, and is configured to provide a data signal to the first pixel circuit.
  • the data line 48 can be electrically connected to the thirteenth connection electrode 413 through the thirty-fourth via hole V34 to achieve electrical connection with the fourth transistor of the second pixel circuit, and is configured to provide a data signal to the second pixel circuit.
  • the data line 48 can also be electrically connected to the twenty-third connection electrode 423 through the thirty-seventh via hole V37 to achieve electrical connection with the fourth transistor of the invalid pixel circuit.
  • a driving circuit layer may be formed in the first display area of the display substrate.
  • the driving circuit layer may include: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fifth insulating layer, and a fourth conductive layer disposed on a substrate.
  • the second display area may include the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer stacked on the substrate.
  • the conductive connection layer may include a first connection layer, a second connection layer, and a third connection layer sequentially arranged in a direction away from the substrate.
  • a sixth insulating layer may be arranged on the side of the first connection layer close to the driving circuit layer, a seventh insulating layer may be arranged between the first connection layer and the second connection layer, and a seventh insulating layer may be arranged between the second connection layer and the third connection layer.
  • An eighth insulating layer may be disposed between the connection layers, and a ninth insulating layer may be disposed on the side of the third connection layer away from the substrate.
  • the sixth insulating layer may also be referred to as a second flat layer
  • the seventh insulating layer may also be referred to as a third flat layer
  • the eighth insulating layer may also be referred to as a fourth flat layer
  • the ninth insulating layer may also be referred to as a fifth flat layer.
  • the first connection layer, the second connection layer, and the third connection layer may each include a plurality of conductive connection lines.
  • the first connection layer may also include: a fourth anode connection electrode located in the first circuit unit and electrically connected to the first anode connection electrode, a fifth anode connection electrode located in the second circuit unit and electrically connected to the second anode connection electrode, and a sixth anode connection electrode located in the invalid circuit unit and electrically connected to the third anode connection electrode.
  • the second connection layer may also include: a seventh anode connection electrode located in the first circuit unit and electrically connected to the fourth anode connection electrode, an eighth anode connection electrode located in the second circuit unit and electrically connected to the fifth anode connection electrode, and a ninth anode connection electrode located in the invalid circuit unit and electrically connected to the sixth anode connection electrode.
  • the third connection layer may also include: a tenth anode connection electrode located in the first circuit unit and electrically connected to the seventh anode connection electrode, an eleventh anode connection electrode located in the second circuit unit and electrically connected to the eighth anode connection electrode, and a twelfth anode connection electrode located in the invalid circuit unit and electrically connected to the ninth anode connection electrode.
  • the first pixel circuit may be electrically connected to the first light-emitting element through the first anode connection electrode, the fourth anode connection electrode, the seventh anode connection electrode, and the tenth anode connection electrode.
  • the second pixel circuit can be electrically connected to the conductive connection line through the second anode connection electrode, the fifth anode connection electrode, the eighth anode connection electrode and the eleventh anode connection electrode, and electrically connected to the second light-emitting element through the conductive connection line; or it can be electrically connected to the conductive connection line through the second anode connection electrode and the fifth anode connection electrode; or it can be electrically connected to the conductive connection line through the second anode connection electrode, the fifth anode connection electrode and the eighth anode connection electrode.
  • the invalid pixel circuit can be electrically connected to the third anode connection electrode, the sixth anode connection electrode, the ninth anode connection electrode and the twelfth anode connection electrode, but not electrically connected to the light-emitting element.
  • This example can ensure the pattern uniformity of the first connection layer, the second connection layer and the third connection layer by setting the third anode connection electrode, the sixth anode connection electrode, the ninth anode connection electrode and the twelfth anode connection electrode, which is beneficial to the preparation of the film layer.
  • the second display area may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a first connection layer, a seventh insulating layer, a second connection layer, an eighth insulating layer, a third connection layer, and a ninth insulating layer stacked on the substrate.
  • the conductive connection layer of the display substrate may include one or two connection layers.
  • an anode film is deposited on a substrate on which the aforementioned pattern is formed, and the anode film is patterned by a patterning process to form an anode layer; subsequently, a pixel definition film is coated on the substrate on which the aforementioned pattern is formed, and a pixel definition layer is formed by masking, exposure, and development processes.
  • the pixel definition layer is formed with a plurality of pixel openings exposing the anode layer. Subsequently, an organic light-emitting layer is formed in the aforementioned pixel openings, and the organic light-emitting layer is connected to the anode.
  • a cathode film is deposited, and the cathode film is patterned by a patterning process to form a cathode layer, and the cathode layer is electrically connected to the organic light-emitting layer.
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer.
  • the fifth insulating layer to the ninth insulating layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode layer can be made of a reflective material such as a metal, and the cathode layer can be made of a transparent conductive material. However, this embodiment is not limited to this.
  • the structure of the display substrate and its preparation process in this embodiment are merely exemplary.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the fourth insulating layer or the fourth insulating layer can be omitted.
  • the number of the conductive connection layers is reduced. This embodiment is not limited to this.
  • the preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment, and can be well compatible with existing preparation processes.
  • the process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.
  • the display substrate of this embodiment increases the occupied space of the second pixel circuit by reducing the occupied space of the invalid pixel circuit. It can reduce the occupied space of the second pixel circuit along the first direction while ensuring the driving effect of the second pixel circuit, which is beneficial to increase the arrangement space of the first pixel circuit along the first direction, and is beneficial to meeting the high PPI requirements of the first display area without increasing the area of the second display area.
  • FIG14 is a schematic diagram of the connection between the second pixel circuit and the second light-emitting element of at least one embodiment of the present disclosure.
  • a second pixel circuit 53 can be configured to drive two second light-emitting elements 54 that emit the same color light.
  • the second display area A2 may include: a plurality of second light-emitting elements that emit red light (R), a plurality of second light-emitting elements that emit blue light (B), and a plurality of second light-emitting elements that emit green light (G).
  • the anodes of the two second light-emitting elements 54 emitting red light in the second display area A2 are electrically connected, they are electrically connected to a second pixel circuit 53 of the first display area through the same conductive connecting line 61, and the two second light-emitting elements 54 emitting red light can be located in adjacent columns of different rows.
  • the anodes of the two second light-emitting elements 54 emitting blue light in the second display area A2 are electrically connected and then electrically connected to a second pixel circuit 53 in the first display area through the same conductive connecting line 61.
  • the two second light-emitting elements 54 emitting blue light can be located in different rows and adjacent columns.
  • One of the second light-emitting elements 54 emitting blue light and one of the second light-emitting elements 54 emitting red light can be located in the same row and in the same column as the other second light-emitting element 54 emitting red light.
  • the other second light-emitting element 54 emitting blue light and the one of the second light-emitting elements 54 emitting red light can be located in the same column and in the same row as the other second light-emitting element 54 emitting red light.
  • the anodes of the two second light-emitting elements 54 emitting green light in the second display area A2 are electrically connected and then electrically connected to a second pixel circuit 53 in the first display area through the same conductive connecting line 61.
  • the two second light-emitting elements 54 emitting green light are located in the same column and adjacent rows.
  • Two adjacent second light emitting elements emitting green light and located in the same column in the second display area A2 can be driven by the same second pixel circuit 53
  • two second light emitting elements emitting red light and located in different columns of adjacent rows in the second display area A2 can be driven by the same second pixel circuit 53
  • two second light emitting elements emitting blue light and located in different columns of adjacent rows in the second display area A2 can be driven by the same second pixel circuit 53.
  • this embodiment is not limited to this.
  • two adjacent second light emitting elements emitting green light and located in the same column can be driven by the same second pixel circuit.
  • the second pixel circuit connected to the second light emitting element emitting green light can be located on the side of the second pixel circuit connected to the second light emitting element emitting blue light and red light close to the second display area A2, and the second pixel circuit connected to the second light emitting element emitting red light is located on the side of the second pixel circuit connected to the second light emitting element emitting blue light close to the second display area.
  • the connection method of this example can ensure the lighting effect of the second display area A2.
  • the arrangement of the first pixel circuit, the second pixel circuit and the invalid pixel circuit in this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • FIG. 15 is another partial schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • a circuit repeating unit of the first display area may include: two rows and five columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and four columns, a second pixel circuit 53 and an invalid pixel circuit 55 may be arranged in two rows and one column, and the second pixel circuit 53 may be located on one side of the invalid pixel circuit 55 in the second direction Y.
  • the length of the second pixel circuit 53 along the first direction X may be less than the length of the first pixel circuit 51 along the first direction X
  • the length of the second pixel circuit 53 along the second direction Y may be greater than the length of the first pixel circuit 51 along the second direction Y
  • the length of the first pixel circuit 51 along the second direction Y may be greater than the length of the invalid pixel circuit 55 along the second direction Y.
  • the plurality of circuit repeating units of the first display area may be arranged in an array along the first direction X and the second direction Y.
  • the remaining description of the display substrate of this example may refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • FIG16 is another connection diagram of the second pixel circuit and the second light-emitting element of at least one embodiment of the present disclosure.
  • the first display area may include: a plurality of first circuit repeating units as shown in FIG5 and a plurality of second circuit repeating units as shown in FIG15.
  • the first circuit repeating unit and the second circuit repeating unit may be arranged at intervals along the first direction X. In the second direction Y, the first circuit repeating unit and the second circuit repeating unit may be arranged at intervals, or a plurality of first circuit repeating units may be arranged in a column, and a plurality of second circuit repeating units may be arranged in a column. This embodiment is not limited to this.
  • a second light-emitting element 54 of the second display area A2 is electrically connected to a second pixel circuit 53, and a second pixel circuit 53 can be configured to drive a second light-emitting element 54 to emit light.
  • the second pixel circuit 53 connected to the second light-emitting element 54 emitting green light (G) can be located on the side of the second pixel circuit 53 connected to the second light-emitting element 54 emitting blue light (B) and red light (R) close to the second display area A2, and the second pixel circuit 53 connected to the second light-emitting element 54 emitting red light (R) can be located on the side of the second pixel circuit 53 connected to the second light-emitting element 54 emitting blue light (B) close to the second display area A2.
  • multiple second light-emitting elements in the same row can be electrically connected to multiple second pixel circuits 53 in the same row through multiple conductive connecting lines 61.
  • first circuit repeating unit and the second circuit repeating unit are arranged in the first direction, it is possible to facilitate the arrangement of the conductive connecting line of a single second pixel circuit driving a single second light-emitting element, and to facilitate the display uniformity of the display substrate.
  • this embodiment is not limited to this.
  • multiple first circuit repeating units can be arranged in a row, and multiple second circuit repeating units can be arranged in another row.
  • FIG17 is another partial schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • a circuit repetition unit of the first display area may include: two rows and five columns of pixel circuits, wherein the second pixel circuit 53 and the invalid pixel circuit 55 may be arranged in a column, and the unit column where the second pixel circuit 53 and the invalid pixel circuit 55 are located is located in the middle of the unit column where the first pixel circuit 51 is located.
  • Two unit columns where the first pixel circuit 51 is located are arranged on one side of the first direction X of the unit column where the second pixel circuit 53 and the invalid pixel circuit 55 are located, and the other two unit columns where the first pixel circuit 51 is located are arranged on the other side.
  • the rest of the description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • FIG18 is another partial schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • a circuit repetition unit of the first display area may include: two rows and five columns of pixel circuits, wherein the second pixel circuit 53 and the invalid pixel circuit 55 are arranged in one column, and the unit column where the second pixel circuit 53 and the invalid pixel circuit 55 are located may be located between a unit column where the first pixel circuit 51 is located and three unit columns where the first pixel circuit 51 is located.
  • the remaining description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • FIG19 is another partial schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • the first display area may include: a first circuit repeating unit as shown in FIG5 and a second circuit repeating unit as shown in FIG15.
  • the first circuit repeating unit and the second circuit repeating unit may be arranged at intervals.
  • the first circuit repeating unit and the second circuit repeating unit may be arranged at intervals; or, a plurality of first circuit repeating units may be arranged in a row along the first direction X, and a plurality of second circuit repeating units may be arranged in another row along the first direction.
  • the rest of the description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • FIG20 is another partial schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • a circuit repetition unit of the first display area may include: six rows and five columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in six rows and four columns, three second pixel circuits 53 and three invalid pixel circuits 55 may be arranged in six rows and four columns, Arranged in six rows and one column, one invalid pixel circuit 55, three second pixel circuits 53 and two invalid pixel circuits 55 may be arranged in sequence along the second direction Y.
  • the rest of the description of the display substrate of this example can refer to the description of the above embodiment, so it is not repeated here.
  • FIG21 is another partial schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • a circuit repetition unit of the first display area may include: two rows and three columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, a second pixel circuit 53 and an invalid pixel circuit 55 may be arranged in two rows and one column, and the invalid pixel circuit 55 may be located on one side of the second pixel circuit 53 along the second direction Y.
  • FIG21 illustrates two circuit repetition units arranged along the first direction X. The rest of the description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • FIG. 22 is another partial schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • the first display area may include: a first circuit repeating unit and a second circuit repeating unit.
  • FIG. 22 illustrates a first circuit repeating unit and a second circuit repeating unit arranged along the first direction X.
  • the first circuit repeating unit may include: two rows and three columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, a second pixel circuit 53 and an invalid pixel circuit 55 may be arranged in two rows and one column, and the invalid pixel circuit 55 may be located on one side of the second pixel circuit 53 along the second direction Y.
  • the second circuit repeating unit may include: two rows and three columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, a second pixel circuit 53 and an invalid pixel circuit 55 may be arranged in two rows and one column, and the second pixel circuit 53 may be located on one side of the invalid pixel circuit 55 along the second direction Y.
  • the remaining description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • FIG23 is another partial schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • a plurality of second pixel circuits 53 and a plurality of invalid pixel circuits 55 may be arranged between a plurality of first pixel circuits 51 at intervals in the second direction Y.
  • at least one first pixel circuit 51 (such as two first pixel circuits 51) may be arranged between two adjacent second pixel circuits 53 in the second direction Y
  • at least one first pixel circuit 51 (such as two first pixel circuits 51) may be arranged between two adjacent invalid pixel circuits 55 in the second direction Y.
  • the second pixel circuits and the invalid pixel circuits may be arranged by performing pixel circuit compression in the second direction Y.
  • a circuit repetition unit in the first display area may include: three rows and two columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, an invalid pixel circuit 55 and a second pixel circuit 53 may be arranged in one row and two columns, and the invalid pixel circuit 55 may be located on one side of the second pixel circuit 53 in the first direction X.
  • FIG23 illustrates two circuit repetition units arranged along the first direction X.
  • the length of the first pixel circuit 51 along the first direction X can be recorded as b, and the length along the second direction Y can be recorded as a; the length of the second pixel circuit 53 along the first direction X can be recorded as d2, and the length along the second direction Y can be recorded as c2; the length of the invalid pixel circuit 55 along the first direction X can be recorded as f2, and the length along the second direction Y can be recorded as e2.
  • the length b of the first pixel circuit 51 along the first direction X can be less than the length d2 of the second pixel circuit 53 along the first direction X.
  • the length d2 of the second pixel circuit 53 along the first direction X can be less than 1.5 times the length b of the first pixel circuit 51 along the first direction X, that is, the ratio of d2 to b can be less than 1.5.
  • the length a of the first pixel circuit 51 along the second direction Y can be greater than the length c2 of the second pixel circuit 53 along the second direction Y.
  • the length a of the first pixel circuit 51 along the second direction Y can be less than 1.5 times the length c2 of the second pixel circuit 53 along the second direction Y, that is, the ratio of a to c2 can be less than 1.5.
  • the length f2 of the invalid pixel circuit 55 along the first direction X may be smaller than the length b of the first pixel circuit 51 along the first direction X, and the length e2 of the invalid pixel circuit 55 along the second direction Y may be substantially the same as the length c2 of the second pixel circuit 53 along the second direction Y.
  • the occupied space of the invalid pixel circuit 55 along the first direction can be increased, and the occupied space of the second pixel circuit along the second direction can be reduced, thereby facilitating the increase of the arrangement space of the first pixel circuit in the second direction.
  • the arrangement space of the first pixel circuit can be increased without increasing the area of the second display area (that is, without increasing the number of second pixel circuits), so as to facilitate the first display area. High PPI demand.
  • FIG. 24 is another partial schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • the first display area may include: a first circuit repeating unit and a second circuit repeating unit.
  • FIG. 22 illustrates a first circuit repeating unit and a second circuit repeating unit arranged along the first direction X.
  • the first circuit repeating unit may include: three rows and two columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, a second pixel circuit 53 and an invalid pixel circuit 55 may be arranged in one row and two columns, and the invalid pixel circuit 55 may be located on one side of the second pixel circuit 53 along the first direction X.
  • the second circuit repeating unit may include: three rows and two columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, a second pixel circuit 53 and an invalid pixel circuit 55 may be arranged in one row and two columns, and the second pixel circuit 53 may be located on one side of the invalid pixel circuit 55 along the first direction X.
  • the remaining description of the display substrate of this example may refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • FIG. 25 is another partial schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • the first display area may include: a first circuit repeating unit and a second circuit repeating unit.
  • FIG. 25 illustrates a first circuit repeating unit and a second circuit repeating unit arranged along the first direction X.
  • the first circuit repeating unit may include: three rows and two columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, a second pixel circuit 53 and an invalid pixel circuit 55 may be arranged in one row and two columns, and the second pixel circuit 53 may be located on one side of the invalid pixel circuit 55 along the first direction X.
  • the second circuit repeating unit may include: three rows and two columns of pixel circuits, wherein a plurality of first pixel circuits 51 may be arranged in two rows and two columns, a second pixel circuit 53 and an invalid pixel circuit 55 may be arranged in one row and two columns, and the invalid pixel circuit 55 may be located on one side of the second pixel circuit 53 along the first direction X.
  • the remaining description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • FIG26 is another partial schematic diagram of the first display area of at least one embodiment of the present disclosure.
  • this example can arrange the second pixel circuit and the invalid pixel circuit by compressing the pixel circuit in both the first direction X and the second direction Y.
  • first direction X four first pixel circuits 51 are arranged alternately with one second pixel circuit 53a or invalid pixel circuit 55a
  • second direction Y one first pixel circuit 51 is arranged alternately with one second pixel circuit 53b or invalid pixel circuit 55b.
  • this embodiment is not limited to this.
  • the lengths of the second pixel circuit 53a and the invalid pixel circuit 55a arranged between the first pixel circuits 51 along the first direction X along the first direction X may be substantially the same and less than the length of the first pixel circuit 51 along the first direction X
  • the length of the second pixel circuit 53a along the second direction Y may be greater than the length of the first pixel circuit 51 along the second direction Y
  • the length of the invalid pixel circuit 55a along the second direction Y may be less than the length of the first pixel circuit 51 along the second direction Y.
  • the lengths of the second pixel circuit 53b and the invalid pixel circuit 55b arranged between the first pixel circuits 51 along the second direction Y may be substantially the same and less than the length of the first pixel circuit 51 along the second direction Y, the length of the second pixel circuit 53b along the first direction X may be greater than the length of the first pixel circuit 51 along the first direction X, and the length of the invalid pixel circuit 55b along the first direction X may be less than the length of the first pixel circuit 51 along the first direction X.
  • this example can increase the arrangement space of the second pixel circuit in the first direction or the second direction by reducing the occupied space of the invalid pixel circuit, thereby reducing the arrangement space of the first pixel circuit in the second direction or the first direction, so that the arrangement space of the first pixel circuit can be increased without increasing the area of the second display area (that is, without increasing the number of second pixel circuits), so as to facilitate meeting the high PPI requirements of the first display area.
  • the rest of the description of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, so it is not repeated here.
  • FIG27 is another schematic diagram of a display substrate of at least one embodiment of the present disclosure.
  • the first display area A1 of the display substrate may include: a transition area A12 and a sub-display area A11.
  • the transition area A12 may surround the second display area A2.
  • the second display area A2 may be circular, and the transition area A12 may be roughly annular.
  • the sub-display area A11 may include a plurality of first pixel circuits and a plurality of first light-emitting elements
  • the transition area A12 may include a plurality of first pixel circuits, a plurality of second pixel circuits, a plurality of invalid pixel circuits, and a plurality of first light-emitting elements.
  • the second display area A2 may include a plurality of second light emitting elements.
  • the light transmittance of the first display area A1 may be less than the light transmittance of the second display area A2.
  • the light transmittance of the sub-display area A11 of the first display area A1 may be less than the light transmittance of the transition area A12, and the light transmittance of the transition area A12 may be less than the light transmittance of the second display area A2.
  • this embodiment is not limited to this.
  • a plurality of second pixel circuits may be located in the transition area and the sub-display area, and the light transmittance of the sub-display area may be the same as the light transmittance of the transition area.
  • the display effect of the sub-display area can be guaranteed, which is conducive to achieving high PPI in the sub-display area.
  • the arrangement of the first pixel circuit, the second pixel circuit and the invalid pixel circuit in the transition area of this example can refer to the description of the previous embodiment, so it will not be repeated here.
  • FIG28 is another schematic diagram of a display substrate of at least one embodiment of the present disclosure.
  • the transition area A12 may be located on both sides of the second display area A2 in the first direction X.
  • the remaining description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it is not repeated here.
  • the first display area may not be distinguished between the transition area and the sub-display area, and the plurality of second pixel circuits may be arranged in the entire first display area. This embodiment is not limited to this.
  • This embodiment also provides a display substrate, including: a substrate, a driving circuit layer and a light-emitting structure layer.
  • the substrate includes a first display area and a second display area, and the first display area is located on at least one side of the second display area.
  • the driving circuit layer is located in the first display area, including a plurality of first pixel circuits and a plurality of second pixel circuits.
  • the light-emitting structure layer is located on the side of the driving circuit layer away from the substrate, including a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area.
  • At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements
  • at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements.
  • the area of at least one first pixel circuit is different from the area of at least one second pixel circuit.
  • the driving circuit layer further includes: a plurality of invalid pixel circuits; an area of at least one invalid pixel circuit among the plurality of invalid pixel circuits is smaller than an area of the at least one first pixel circuit.
  • the plurality of second pixel circuits are arranged at intervals between the plurality of first pixel circuits in the first direction.
  • the length of the at least one first pixel circuit in the first direction is greater than the length of the at least one second pixel circuit in the first direction
  • the length of the at least one first pixel circuit in the second direction is less than the length of the at least one second pixel circuit in the second direction
  • the first direction intersects the second direction.
  • the driving circuit layer further includes: a plurality of invalid pixel circuits, the plurality of invalid pixel circuits being arranged between the plurality of first pixel circuits at intervals in the first direction, and at least one of the plurality of invalid pixel circuits being adjacent to the at least one second pixel circuit in the second direction.
  • the length of the at least one invalid pixel circuit in the first direction is the same as the length of the at least one second pixel circuit in the first direction, and the length of the at least one invalid pixel circuit in the second direction is less than the length of the at least one first pixel circuit in the second direction.
  • FIG29 is a schematic diagram of a display device of at least one embodiment of the present disclosure.
  • the present embodiment provides a display device, including: a display substrate 91.
  • the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function.
  • the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA, Personal Digital Assistant), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large area wall, an information query device (such as e-government, a bank, a medical device, etc.)
  • the display device may be any product in the following categories: business query equipment for departments such as hospitals and power, monitors, etc.
  • the display device may be any product in the following categories: a micro display, a VR device or an AR device including a micro display, etc.
  • the display device may further include: at least one sensor 92 located on a light-emitting side (non-display side) away from the display substrate 91.
  • the orthographic projection of the sensor 92 on the display substrate 91 overlaps with the second display area A2.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne un substrat d'affichage, comprenant : un substrat, et une couche de circuit d'attaque et une couche de structure électroluminescente qui sont disposées de manière séquentielle sur le substrat, le substrat comprenant une première zone d'affichage et une seconde zone d'affichage, et la première zone d'affichage étant située sur au moins un côté de la seconde zone d'affichage ; la couche de circuit d'attaque est située dans la première zone d'affichage, et comprend une pluralité de premiers circuits de pixels et une pluralité de seconds circuits de pixels ; et la couche de structure électroluminescente comprend une pluralité de premiers éléments électroluminescents situés dans la première zone d'affichage, et une pluralité de seconds éléments électroluminescents situés dans la seconde zone d'affichage. Au moins un premier circuit de pixel est électriquement connecté à au moins un premier élément électroluminescent, et au moins un second circuit de pixel est électriquement connecté à au moins un second élément électroluminescent. La taille du ou des premiers circuits de pixel est différente de la taille du ou des seconds circuits de pixel.
PCT/CN2024/099767 2023-07-25 2024-06-18 Substrat d'affichage et appareil d'affichage Pending WO2025020775A1 (fr)

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CN202310923033.2A CN116741786A (zh) 2023-07-25 2023-07-25 显示基板及显示装置
CN202310923033.2 2023-07-25

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WO2025020775A1 true WO2025020775A1 (fr) 2025-01-30

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CN116741786A (zh) * 2023-07-25 2023-09-12 京东方科技集团股份有限公司 显示基板及显示装置

Citations (5)

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Publication number Priority date Publication date Assignee Title
CN111180494A (zh) * 2020-01-03 2020-05-19 武汉天马微电子有限公司 一种显示面板及显示装置
CN115241236A (zh) * 2022-06-20 2022-10-25 京东方科技集团股份有限公司 显示基板及显示装置
CN115513270A (zh) * 2022-10-19 2022-12-23 京东方科技集团股份有限公司 显示基板及显示装置
US20230232672A1 (en) * 2018-01-12 2023-07-20 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, method for manufacturing the same and display device
CN116741786A (zh) * 2023-07-25 2023-09-12 京东方科技集团股份有限公司 显示基板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230232672A1 (en) * 2018-01-12 2023-07-20 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, method for manufacturing the same and display device
CN111180494A (zh) * 2020-01-03 2020-05-19 武汉天马微电子有限公司 一种显示面板及显示装置
CN115241236A (zh) * 2022-06-20 2022-10-25 京东方科技集团股份有限公司 显示基板及显示装置
CN115513270A (zh) * 2022-10-19 2022-12-23 京东方科技集团股份有限公司 显示基板及显示装置
CN116741786A (zh) * 2023-07-25 2023-09-12 京东方科技集团股份有限公司 显示基板及显示装置

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