WO2025073455A1 - Procédés de codage et de décodage de bloc d'image avec retournement ou rotation et appareils correspondants - Google Patents

Procédés de codage et de décodage de bloc d'image avec retournement ou rotation et appareils correspondants Download PDF

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Publication number
WO2025073455A1
WO2025073455A1 PCT/EP2024/075854 EP2024075854W WO2025073455A1 WO 2025073455 A1 WO2025073455 A1 WO 2025073455A1 EP 2024075854 W EP2024075854 W EP 2024075854W WO 2025073455 A1 WO2025073455 A1 WO 2025073455A1
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Prior art keywords
block
ibc
flipping
flag
vector
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Milos RADOSAVLJEVIC
Fabrice Le Leannec
Ya CHEN
Gagan Bihari RATH
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InterDigital CE Patent Holdings SAS
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InterDigital CE Patent Holdings SAS
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/103—Selection of coding mode or of prediction mode
    • H04N19/11—Selection of coding mode or of prediction mode among a plurality of spatial predictive coding modes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/136—Incoming video signal characteristics or properties
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/593—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques

Definitions

  • At least one of the present examples generally relates to a method and an apparatus for encoding (decoding respectively) a vector, e.g. a block vector, a block vector difference, a motion vector or a motion vector difference.
  • a vector e.g. a block vector, a block vector difference, a motion vector or a motion vector difference.
  • At least another one of the present examples generally relates to a method and an apparatus for encoding (decoding respectively) an image block, wherein image block is flipped or rotated.
  • image and video coding schemes usually employ prediction and transform to leverage spatial and temporal redundancy in the video content.
  • intra or inter prediction is used to exploit the intra or inter picture correlation, then the differences between the original block and the predicted block, often denoted as prediction errors or prediction residuals, are transformed, quantized, and entropy coded.
  • the compressed data are decoded by inverse processes corresponding to the entropy coding, quantization, transform, and prediction.
  • a method for encoding that makes it possible to indicate the case where components of a vector of an image block are equal.
  • a flag may be signaled to the decoder to indicate such a case where components are equal, e.g. to indicate the case where block vector components are equal or the case where block vector difference components are equal.
  • absolute values may be considered.
  • Corresponding decoding method is also disclosed.
  • a decoding method is disclosed wherein signs of block vector difference components are derived from a block vector predictor.
  • the block vector predictor is selected, e.g. based on a decoded index, from a list of block vector predictors.
  • block vector difference components are of equal amplitude and an absolute value of only one of the block vector difference components is decoded. This specific mode may be signaled by a syntax element, e.g. a flag, that indicates that the signs of block vector difference components are obtained from a block vector predictor.
  • a decoding method wherein samples of a reconstructed block may be flipped diagonally or rotated.
  • the use of diagonal flipping may be signaled by a syntax element and the direction of flipping by another syntax element.
  • the use of rotation may be signaled by a syntax element and the rotation angle by another syntax element.
  • Corresponding encoding method is also disclosed.
  • FIG. 1 illustrates a block diagram of a system within which aspects of the present embodiments may be implemented
  • FIG. 2 illustrates a block diagram of an embodiment of a video encoder
  • FIG. 3 illustrates a block diagram of an embodiment of a video decoder
  • FIG. 4 depicts a current block predicted from a reference block identified by a block vector
  • FIG. 5 represents a reference region of Intra Block Copy (IBC) mode
  • FIG. 7 illustrates examples of locations of Block Vector Predictor (BVP) candidates that may be used for the replacement of zero vector in IBC Merge/ AMVP (Advanced Motion Vector Prediction) list(s);
  • BVP Block Vector Predictor
  • FIG. 8 illustrates a clustering of BVP candidates based on L2 distance and Template Matching (TM) cost
  • FIG. 9 illustrates an intra template matching (IntraTMP) search area
  • FIG. 10A illustrates the use of IntraTMP (Intra Template Matching prediction) block vector for an IBC block ;
  • FIG. 10B illustrates BV predictive coding
  • FIG. 11 A depicts a flowchart of a decoding method according to an example ;
  • FIG. 1 IB depicts a flowchart of an encoding method according to an example ;
  • FIG. 12 depicts a flowchart of an encoding method according to an example .
  • FIG. 13 depicts a flowchart of a decoding method according to an example
  • FIG. 14 depicts a flowchart of an encoding method according to an example .
  • FIG. 15 depicts a flowchart of a decoding method according to an example .
  • FIG. 16 depicts a flowchart of an encoding method according to an example .
  • FIG. 17 depicts a flowchart of a decoding method according to an example .
  • FIG. 18 depicts a flowchart of an encoding method according to an example .
  • FIG. 19 depicts a flowchart of a decoding method according to an example .
  • FIG. 20A depicts a flowchart of a decoding method according to an example ;
  • FIG. 20B depicts a flowchart of an encoding method according to an example ;
  • FIGs 21A and 21B depict a picture part wherein block vector predictor located on the diagonal relative to a current block are represented
  • FIG.s 22 A and 22B depict flowcharts of a decoding method for a square block and a non-square block respectively ;
  • FIG.s 23 A and 23B depict flowcharts of an encoding method for a square block and a nonsquare block respectively ;
  • FIG.24A depicts an original image block along with the image block obtained after an horizontal flipping, a vertical flipping and a rotation by 90 degrees of the original image block ;
  • FIG.24B depicts the image block obtained after a rotation by 45 degrees, a rotation by -45 degrees, a diagonal flipping in a primary diagonal direction and a diagonal flipping in a secondary diagonal direction of the original image block ;
  • FIG. 25A illustrates the principles of diagonal flipping in a primary diagonal direction
  • FIG. 25B illustrates the principles of diagonal flipping in a primary diagonal direction.
  • FIGs. 1, 2 and 3 below provide some embodiments, but other embodiments are contemplated and the discussion of FIGs. 1, 2 and 3 does not limit the breadth of the implementations.
  • At least one of the aspects generally relates to video encoding and decoding, and at least one other aspect generally relates to transmitting a bitstream generated or encoded.
  • These and other aspects can be implemented as a method, an apparatus, a computer readable storage medium having stored thereon instructions for encoding or decoding video data according to any of the methods described, and/or a computer readable storage medium having stored thereon a bitstream generated according to any of the methods described.
  • the terms “reconstructed” and “decoded” may be used interchangeably, the terms “encoded” or “coded” may be used interchangeably, the terms “pixel” and “sample” may be used interchangeably and the terms “image,” “picture” and “frame” may be used interchangeably.
  • the term “reconstructed” is used at the encoder side while “decoded” is used at the decoder side.
  • each of the methods comprises one or more steps or actions for achieving the described method. Unless a specific order of steps or actions is required for proper operation of the method, the order and/or use of specific steps and/or actions may be modified or combined. Additionally, terms such as “first”, “second”, etc. may be used in various embodiments to modify an element, component, step, operation, etc., such as, for example, a “first decoding” and a “second decoding”. Use of such terms does not imply an ordering to the modified operations unless specifically required. So, in this example, the first decoding need not be performed before the second decoding, and may occur, for example, before, during, or in an overlapping time period with the second decoding.
  • satisfying, failing to satisfy a condition and configuring condition parameter(s) are described throughout embodiments described herein as relative to a threshold (e.g. greater, or lower than), a (e.g. threshold) value, configuring the (e.g. threshold) value, etc.).
  • a threshold e.g. greater, or lower than
  • a condition e.g. performance criteria
  • Embodiments described herein are not limited to thresholdbased conditions. Any kind of other condition and parameter(s) (such as e.g. belonging or not belonging to a range of values) may be applicable to embodiments described herein.
  • the present aspects are not limited to ECM, VVC or HEVC, and can be applied, for example, to other standards and recommendations, whether pre-existing or future-developed, and extensions of any such standards and recommendations (including VVC and HEVC). Unless indicated otherwise, or technically precluded, the aspects described in this application can be used individually or in combination.
  • FIG. 1 illustrates a block diagram of an example of a system in which various aspects and embodiments can be implemented.
  • System 100 may be embodied as a device including the various components described below and is configured to perform one or more of the aspects described in this application. Examples of such devices, include, but are not limited to, various electronic devices such as personal computers, laptop computers, smartphones, tablet computers, digital multimedia set top boxes, digital television receivers, personal video recording systems, connected home appliances, and servers.
  • Elements of system 100 singly or in combination, may be embodied in a single integrated circuit, multiple ICs, and/or discrete components.
  • the processing and encoder/decoder elements of system 100 are distributed across multiple ICs and/or discrete components.
  • system 100 is communicatively coupled to other systems, or to other electronic devices, via, for example, a communications bus or through dedicated input and/or output ports.
  • system 100 is configured to implement one or more of the aspects described in this application.
  • the system 100 includes at least one processor 110 configured to execute instructions loaded therein for implementing, for example, the various aspects described in this application.
  • Processor 110 may include embedded memory, input output interface, and various other circuitries as known in the art.
  • the system 100 includes at least one memory 120 (e.g. a volatile memory device, and/or a non-volatile memory device).
  • System 100 includes a storage device 140, which may include non-volatile memory and/or volatile memory, including, but not limited to, EEPROM, ROM, PROM, RAM, DRAM, SRAM, flash, magnetic disk drive, and/or optical disk drive.
  • the storage device 140 may include an internal storage device, an attached storage device, and/or a network accessible storage device, as non-limiting examples.
  • System 100 includes an encoder/decoder module 130 configured, for example, to process data to provide an encoded video or decoded video, and the encoder/decoder module 130 may include its own processor and memory.
  • the encoder/decoder module 130 represents module(s) that may be included in a device to perform the encoding and/or decoding functions. As is known, a device may include one or both of the encoding and decoding modules. Additionally, encoder/decoder module 130 may be implemented as a separate element of system 100 or may be incorporated within processor 110 as a combination of hardware and software as known to those skilled in the art.
  • Program code to be loaded onto processor 110 or encoder/decoder 130 to perform the various aspects described in this application may be stored in storage device 140 and subsequently loaded onto memory 120 for execution by processor 110.
  • one or more of processor 110, memory 120, storage device 140, and encoder/decoder module 130 may store one or more of various items during the performance of the processes described in this application. Such stored items may include, but are not limited to, the input video, the decoded video or portions of the decoded video, the bitstream, matrices, variables, and intermediate or final results from the processing of equations, formulas, operations, and operational logic.
  • memory inside of the processor 110 and/or the encoder/decoder module 130 is used to store instructions and to provide working memory for processing that is needed during encoding or decoding.
  • a memory external to the processing device (for example, the processing device may be either the processor 110 or the encoder/decoder module 130) is used for one or more of these functions.
  • the external memory may be the memory 120 and/or the storage device 140, for example, a dynamic volatile memory and/or a non-volatile flash memory.
  • an external non-volatile flash memory is used to store the operating system of a television.
  • a fast external dynamic volatile memory such as a RAM is used as working memory for video coding and decoding operations, such as for MPEG-2, (MPEG refers to the Moving Picture Experts Group, MPEG-2 is also referred to as ISO/IEC 13818, and 13818-1 is also known as H.222, and 13818-2 is also known as H.262), HEVC (HEVC refers to High Efficiency Video Coding, also known as H.265 and MPEG-H Part 2), or VVC (Versatile Video Coding, a new standard being developed by JVET, the Joint Video Experts Team).
  • MPEG refers to the Moving Picture Experts Group
  • MPEG-2 is also referred to as ISO/IEC 13818
  • 13818-1 is also known as H.222
  • 13818-2 is also known as H.262
  • HEVC High Efficiency Video Coding
  • VVC Very Video Coding
  • the input to the elements of system 100 may be provided through various input devices as indicated in block 105.
  • Such input devices include, but are not limited to, (i) a radio frequency (RF) portion that receives an RF signal transmitted, for example, over the air by a broadcaster, (ii) a Component (COMP) input terminal (or a set of COMP input terminals), (iii) a Universal Serial Bus (USB) input terminal, and/or (iv) a High Definition Multimedia Interface (HDMI) input terminal.
  • RF radio frequency
  • COMP Component
  • USB Universal Serial Bus
  • HDMI High Definition Multimedia Interface
  • the input devices of block 105 have associated respective input processing elements as known in the art.
  • the RF portion may be associated with elements suitable for (i) selecting a desired frequency (also referred to as selecting a signal, or band-limiting a signal to a band of frequencies), (ii) down converting the selected signal, (iii) band-limiting again to a narrower band of frequencies to select (for example) a signal frequency band which may be referred to as a channel in certain embodiments, (iv) demodulating the down converted and band-limited signal, (v) performing error correction, and (vi) demultiplexing to select the desired stream of data packets.
  • the RF portion of various embodiments includes one or more elements to perform these functions, for example, frequency selectors, signal selectors, band-limiters, channel selectors, filters, downconverters, demodulators, error correctors, and demultiplexers.
  • the RF portion may include a tuner that performs various of these functions, including, for example, down converting the received signal to a lower frequency (for example, an intermediate frequency or a near-baseband frequency) or to baseband.
  • the RF portion and its associated input processing element receives an RF signal transmitted over a wired (for example, cable) medium, and performs frequency selection by filtering, down converting, and filtering again to a desired frequency band.
  • Adding elements may include inserting elements in between existing elements, for example, inserting amplifiers and an analog-to-digital converter.
  • the RF portion includes an antenna.
  • the USB and/or HDMI terminals may include respective interface processors for connecting system 100 to other electronic devices across USB and/or HDMI connections. It is to be understood that various aspects of input processing, for example, Reed-Solomon error correction, may be implemented, for example, within a separate input processing IC or within processor 110 as necessary. Similarly, aspects of USB or HDMI interface processing may be implemented within separate interface ICs or within processor 110 as necessary.
  • the demodulated, error corrected, and demultiplexed stream is provided to various processing elements, including, for example, processor 110, and encoder/decoder 130 operating in combination with the memory and storage elements to process the datastream as necessary for presentation on an output device.
  • connection arrangement 115 for example, an internal bus as known in the art, including the I2C bus, wiring, and printed circuit boards.
  • the system 100 includes communication interface 150 that enables communication with other devices via communication channel 190.
  • the communication interface 150 may include, but is not limited to, a transceiver configured to transmit and to receive data over communication channel 190.
  • the communication interface 150 may include, but is not limited to, a modem or network card and the communication channel 190 may be implemented, for example, within a wired and/or a wireless medium.
  • Wi-Fi Wireless Fidelity
  • IEEE 802.11 IEEE refers to the Institute of Electrical and Electronics Engineers
  • the Wi-Fi signal of these embodiments is received over the communications channel 190 and the communications interface 150 which are adapted for Wi-Fi communications.
  • the communications channel 190 of these embodiments is typically connected to an access point or router that provides access to outside networks including the Internet for allowing streaming applications and other over-the-top communications.
  • Other embodiments provide streamed data to the system 100 using a set-top box that delivers the data over the HDMI connection of the input block 105.
  • Still other embodiments provide streamed data to the system 100 using the RF connection of the input block 105.
  • various embodiments provide data in a non-streaming manner. Additionally, various embodiments use wireless networks other than Wi-Fi, for example a cellular network or a Bluetooth network.
  • the system 100 may provide an output signal to various output devices, including a display 165, speakers 175, and other peripheral devices 185.
  • the display 165 of various embodiments includes one or more of, for example, a touchscreen display, an organic light-emitting diode (OLED) display, a curved display, and/or a foldable display.
  • the display 165 can be for a television, a tablet, a laptop, a cell phone (mobile phone), or other device.
  • the display 165 can also be integrated with other components (for example, as in a smart phone), or separate (for example, an external monitor for a laptop).
  • the other peripheral devices 185 include, in various examples of embodiments, one or more of a stand-alone digital video disc (or digital versatile disc) (DVR, for both terms), a disk player, a stereo system, and/or a lighting system.
  • DVR digital video disc
  • Various embodiments use one or more peripheral devices 185 that provide a function based on the output of the system 100. For example, a disk player performs the function of playing the output of the system 100.
  • control signals are communicated between the system 100 and the display 165, speakers 175, or other peripheral devices 185 using signaling such as AV. Link, CEC, or other communications protocols that enable device-to-device control with or without user intervention.
  • the output devices may be communicatively coupled to system 100 via dedicated connections through respective interfaces 160, 170, and 180. Alternatively, the output devices may be connected to system 100 using the communications channel 190 via the communications interface 150.
  • the display 165 and speakers 175 may be integrated in a single unit with the other components of system 100 in an electronic device, for example, a television.
  • the display interface 160 includes a display driver, for example, a timing controller (T Con) chip.
  • the display 165 and speaker 175 may alternatively be separate from one or more of the other components, for example, if the RF portion of input 105 is part of a separate set-top box.
  • the output signal may be provided via dedicated output connections, including, for example, HDMI ports, USB ports, or COMP outputs.
  • the embodiments can be carried out by computer software implemented by the processor 110 or by hardware, or by a combination of hardware and software. As a non-limiting example, the embodiments can be implemented by one or more integrated circuits.
  • the memory 120 can be of any type appropriate to the technical environment and can be implemented using any appropriate data storage technology, such as optical memory devices, magnetic memory devices, semiconductor-based memory devices, fixed memory, and removable memory, as non-limiting examples.
  • the processor 110 can be of any type appropriate to the technical environment, and can encompass one or more of microprocessors, general purpose computers, special purpose computers, and processors based on a multi-core architecture, as non-limiting examples.
  • FIG. 2 illustrates an example video encoder 200, such as a VVC (Versatile Video Coding) encoder.
  • FIG. 2 may also illustrate an encoder in which improvements are made to the VVC standard or an encoder employing technologies similar to VVC.
  • VVC Very Video Coding
  • the video sequence may go through pre-encoding processing (201), for example, applying a color transform to the input color picture (e.g. conversion from RGB 4:4:4 to YCbCr 4:2:0), or performing a remapping of the input picture components in order to get a signal distribution more resilient to compression (for instance using a histogram equalization of one of the color components).
  • Metadata can be associated with the preprocessing and attached to the bitstream.
  • a picture is encoded by the encoder elements as described below.
  • the picture to be encoded is partitioned (202) and processed in units of, for example, CUs (Coding Units).
  • Each unit is encoded using, for example, either an intra or inter mode.
  • intra prediction e.g. using an intra-prediction tool such as Decoder Side Intra Mode Derivation (DIMD).
  • inter mode motion estimation (275) and compensation (270) are performed.
  • the encoder decides (205) which one of the intra mode or inter mode to use for encoding the unit, and indicates the intra/inter decision by, for example, a prediction mode flag.
  • Prediction residuals are calculated, for example, by subtracting (210) the predicted block (a.k.a. prediction block) from the original image block.
  • the prediction residuals are then transformed (225) into transform coefficients c (a.k.a prediction residual transform coefficients) which are quantized (230) into quantization indexes c q (a.k.a transform coefficient levels or quantized transform coefficients on the encoder side).
  • the quantization levels (a.k.a quantization indexes) c q . as well as motion vectors and other syntax elements such as the picture partitioning information, are entropy coded (245) to output a bitstream.
  • the encoder can skip the transform and apply quantization directly to the non-transformed residual signal.
  • the encoder can bypass both transform and quantization, i.e. the residual is coded directly without the application of the transform or quantization processes.
  • the encoder decodes an encoded block to provide a reference for further predictions.
  • the quantized transform coefficients are de-quantized (240) (a.k.a. scaled) and inverse transformed (250) to decode prediction residuals.
  • In-loop filters (265) are applied to the reconstructed picture to perform, for example, deblocking/SAO (Sample Adaptive Offset)/ALF (Adaptive Loop Filter) filtering to reduce encoding artifacts.
  • the filtered image is stored in a reference picture buffer (280).
  • In-loop filters (265) are thus used to enhance reconstructed images before storing them in the reference picture buffer (280).
  • Inloop filters form a whole family.
  • deblocking filters aim at reducing blocking artifacts occurring along block boundaries.
  • Deblocking filters are usually designed to improve subjective quality, that is, the noticeability of such coding errors by the human psycho visual system.
  • deblocking filters are predetermined based on coding information (such as prediction modes, motion vectors, transform coefficients) and on local variations across block boundaries.
  • ALF adaptive loop filters
  • ALF adaptive loop filters
  • Adaptive loop filters are usually applied at CTU-level, while deblocking filters are applied along block borders.
  • FIG. 3 illustrates a block diagram of an example video decoder 300.
  • a bitstream is decoded by the decoder elements as described below.
  • Video decoder 300 generally performs a decoding pass reciprocal to the encoding pass as described in FIG. 2.
  • the encoder 200 also generally performs video decoding as part of encoding video data.
  • the input of the decoder includes a video bitstream, which can be generated by video encoder 200.
  • the bitstream is first entropy decoded (330) to obtain quantization levels c q (a.k.a. transform coefficient levels or quantization levels on the decoder side), prediction modes, motion vectors, and other coded information.
  • the picture partition information indicates how the picture is partitioned.
  • the decoder may therefore divide (335) the picture according to the decoded picture partitioning information.
  • the quantization levels c q are dequantized (340) into reconstructed transform coefficients c r . De-quantization is also named scaling.
  • the reconstructed transform coefficients c r are inverse transformed (350) to obtain the prediction residuals.
  • an image block is reconstructed.
  • the predicted block can be obtained (370) from intra prediction (360) or motion-compensated prediction (i.e. inter prediction) (375).
  • Inloop filters (365) are applied to the reconstructed image.
  • the filtered image is stored at a reference picture buffer (380). Note that, for a given picture, the contents of the reference picture buffer 380 on the decoder 300 side is identical to the contents of the reference picture buffer 280 on the encoder 200 side for the same picture.
  • the decoded picture can further go through post-decoding processing (385), for example, an inverse color transform (e.g. conversion from YCbCr 4:2:0 to RGB 4:4:4) or an inverse remapping performing the inverse of the remapping process performed in the pre-encoding processing (201).
  • post-decoding processing can use metadata derived in the pre-encoding processing and signaled in the bitstream.
  • IBC Intra Block Copy
  • CU An IBC-coded coding unit (CU) may be treated as separate prediction mode other than intra or inter prediction modes (as in VVC) or may be considered as part of inter mode (e.g. as in HEVC).
  • IBC is an independent coding mode, having its own vector coding engine as compared with the motion vector coding schemes in inter mode.
  • IBC prediction is performed from reconstructed samples before in-loop filtering.
  • IBC is a predictive coding technology that explores the similarity, e.g. repeating patterns, within the same picture.
  • a current picture block (a.k.a CU) is predicted by an already reconstructed reference block within the same picture (reference samples are derived from inside the reconstructed part of current picture).
  • the offset from the current block to its reference block is referred as a block vector (BV) or displacement vector, i.e. a vector that indicates the displacement from the current block to a reference block.
  • BV block vector
  • the CU is represented with a BV as well as the residual signal of that CU, which is the approach similar to an inter mode in inter-frame motion estimation. Merge mode and skip mode may also be performed in IBC.
  • IBC mode is implemented as a block level coding mode
  • block matching may be performed at the encoder to find an optimal BV for each CU.
  • the luma block vector of an IBC- coded CU may be in integer precision (for example for simplicity reasons).
  • the chroma block vector may round to integer precision as well.
  • the IBC mode can switch between 1-pel and 4- pel motion vector precisions, for example when combined with Adaptive Motion Vector Resolution (AMVR).
  • AMVR Adaptive Motion Vector Resolution
  • the IBC mode may be applicable to certain CUs (e.g. the CUs with both width and height smaller than or equal to 64 luma samples).
  • Fractional vector resolution may be used, e.g. for natural content.
  • IBC is known as intra picture block compensation or current picture referencing (CPR).
  • all the reconstructed part of the current picture may be used as IBC reference region (a.k.a IBC search range) for the current block coded in IBC mode.
  • IBC reference region a.k.a IBC search range
  • some constraints may be imposed on the full-frame based IBC solution to make its implementation friendly.
  • FIG. 4 depicts an image part wherein a current CU (a.k.a current block) of width w and height h is predicted from a reference block selected in an IBC reference region and identified by a block vector.
  • IBC reference region in HEVC Screen Content Coding extension (HEVC-SCC) is shown in FIG. 4, where the white area is the not yet decoded (a.k.a reconstructed) region of the current decoded picture. The grey area is the already reconstructed part.
  • the solid line LI in this area forms the border of the available IBC reference region (a.k.a IBC search range).
  • the line L2, which is right next to the border may be excluded from the search range when the video format is 4:2:0.
  • the part of the reconstructed area that is not inside the border enclosed by line LI may be excluded from the IBC reference region for parallel processing consideration.
  • a more constrained reference region may be used, for example, to limit memory consumption and/or decoder complexity.
  • the IBC reference region (a.k.a IBC search range) may be limited to the current coding tree unit (CTU) only.
  • CTU current coding tree unit
  • some of the reference samples from the left CTU can be used for IBC mode.
  • the largest block size in IBC mode may be limited to 64x64.
  • the IBC may allow the IBC reference region to include only the region of current CTU and some region(s) of the left CTU.
  • FIG. 5 represents a reference region of IBC mode, where each block represents 64x64 luma sample unit.
  • each cross identifies a block from the left CTU that is excluded from the available IBC reference region. The grey blocks without a cross belong to the IBC reference region.
  • current block (a.k.a current CU) falls into the top-left block (e.g. 64x64 block) of the current CTU, then in addition to the already reconstructed samples in the current CTU, it can also refer to the reference samples in the bottom-right blocks (e.g. 64x64 blocks) of the left CTU, using IBC mode.
  • the current block can also refer to the reference samples in the bottom-left 64x64 block of the left CTU and the reference samples in the top-right block (e.g. 64x64 block) of the left CTU, using IBC mode.
  • the current block can also refer to the reference samples in the bottom-left block (e.g. 64x64 block) and bottom-right block (e.g. 64x64 block) of the left CTU, using IBC mode; otherwise, the current block can also refer to reference samples in bottom-right block (e.g. 64x64 block) of the left CTU.
  • the current block can also refer to the reference samples in the top-right block (e.g. 64x64 block) and bottom-right block (e.g. 64x64 block) of the left CTU, using IBC mode. Otherwise, the current block can also refer to the reference samples in the bottom-right block (e.g. 64x64 block) of the left CTU, using IBC mode. If current block falls into the bottom-right block (e.g. 64x64 block) of the current CTU, it can only refer to the already reconstructed samples in the current CTU, using IBC mode.
  • One or more examples may allow the IBC mode to be implemented using local on-chip memory (or memories) for hardware implementations.
  • the reference region for IBC may be extended to two CTU rows above the CTU being processed by the encoder and/or the decoder.
  • FIG. 6 illustrates examples of the reference area(s) for encoding and/or decoding CTU (m,n).
  • the reference area(s) may include CTUs with index (m-2,n-2)... (W,n- 2),(0,n-l)... (W,n-l),(0,n)... (m,n), where W denotes the maximum horizontal index within the current tile, slice or picture.
  • the per-sample block vector search (or referred to as the local search) range may be limited to [-(C « 1), C » 2] horizontally and [-C, C » 2] vertically e.g. to adapt to the reference area extension, where C denotes the CTU size and » is a right shift operator and « is a left shift operator.
  • reference samples are samples before application of in-loop filtering.
  • IBC mode may be signaled at a CU level, (e.g. with a flag). IBC mode may be signaled as IBC advanced motion vector prediction (AMVP) mode or IBC skip/merge mode in one or more examples herein. In examples, IBC mode may be signaled as IBC skip/merge mode, where a merge candidate index may be used to indicate which of the block vectors in a list derived from neighboring candidate IBC coded blocks is used to predict the current block.
  • a merge list may include (e.g. consist of) spatial, history-based motion vector predictor (HMVP), and pairwise candidates.
  • HMVP history-based motion vector predictor
  • a simplified merge candidate list with 2 spatial neighboring blocks’ BV and 5 HMVPs may be used. Up to 6 candidates may be used in the list. The first two entries of the same predictor list may also be used for non-merge BV prediction mode.
  • IBC mode may be signaled as IBC AMVP mode, where a IBC block vector difference (BVD) may be encoded (decoded respectively) in a similar or same way as a motion vector difference (MVD).
  • the block vector prediction method may use multiple (e.g. two) candidates as predictors, which are selected from the list based on a minimum cost (e.g. if IBC coded). In an example, the block vector prediction method may use two candidates as predictors, one from left neighbor and one from above neighbor (e.g. if IBC coded). A default block vector may be used as a predictor, for example, if one or more of the candidates (e.g. neighbor(s)) are not available. An indication (e.g. a flag) may be signaled to indicate a block vector predictor index.
  • An indication e.g. a flag
  • IBC merge/ AMVP list construction may be modified, as one or more of the following.
  • An IBC merge/AMVP candidate may be inserted into the IBC merge/AMVP candidate list, if and/or only if the IBC merge/AMVP candidate is valid.
  • One or more of aboveright, bottom-left, and/or above-left spatial candidates and/or one pairwise average candidate may be added into the IBC merge/AMVP candidate list.
  • Template based adaptive reordering e.g. adaptive re-ordering of candidates based on template (ARMC-TM)
  • the HMVP table size for IBC may be increased to 25 entries.
  • IBC merge candidates e.g. up to 20 IBC merge candidates
  • the first candidates e.g. the first 6 candidates
  • the zero vectors candidates may be replaced with a set of block vector predictor (BVP) candidates (e.g. the ones used to pad the IBC Merge/ AMVP list for example in the case where the list is not complete) located in the IBC reference region.
  • BVP block vector predictor
  • a zero vector may be invalid as a block vector in IBC merge mode (e.g. consequently it is discarded as BVP in the IBC candidate list).
  • FIG. 7 illustrates an example showing locations of BVP candidates that may be used for the replacement of zero vector in the IBC Merge/ AMVP list(s).
  • three candidates are located on the nearest comers of the reference region delimited by a dotted line, and three additional candidates are determined in the middle of the three sub-regions (A, B, and C), whose coordinates may be determined by the width, and the height of the current block and AX and AY parameters.
  • a clustering of the BVP candidates may be applied when both BVP candidate components (horizontal and vertical projections of the vector, BVPx and BVPy) are non-zero, e.g. during the IBC AMVP list construction.
  • FIG. 8 illustrates the clustering based on L2 distance and TM cost. In examples, clustering may be applied if there are more than 2 valid BV candidates and up to 6 candidates.
  • the clustering radius may be defined as
  • the clustering method may be applied in the candidate list order, and the candidates assigned to a group may be removed from the list for the subsequent clusters.
  • a group e.g. each group
  • the BVP with a lowest TM cost is selected as the representative candidate of that group.
  • the representative candidates of the two first groups may be chosen as the candidates for the IBC AMVP list.
  • the original block may be flipped in a horizontal or vertical direction before searching a block vector for the current block.
  • the search for the best matching reference block may be constrained to the same row or column as the current block, thus requiring the BV to have one null component.
  • a first flag e.g. RRIBC flag
  • a second flag e.g. a directional flag
  • a syntax flag may be firstly signaled for an IBC AMVP coded block that indicates whether the reconstruction is flipped, and if/when it is flipped, another flag is further signaled specifying the flip type (e.g. the direction of flipping).
  • the flip type is inherited from neighboring blocks, without syntax signaling.
  • the current block and the reference block are normally aligned horizontally or vertically. Therefore, when a horizontal flip is applied, the vertical component of the BV is not signaled and inferred to be equal to 0. Similarly, the horizontal component of the BV is not signaled and inferred to be equal to 0 when a vertical flip is applied.
  • the use of RRIBC mode is signaled, followed by the direction of the flipping (horizontal or vertical).
  • the direction of the zero component e.g. horizontal or vertical component being zero
  • the AMVP BVPO may be set to the nearest valid location to the current block (-cbWidth or - cbHeight), so the non-zero BVD is always negative, pointing to the left for a BV with a zero vertical component or to the above for a BV with a zero horizontal component.
  • the AMVP BVP1 may be set to the farthest position from the current block in the valid reference region, that is the left boundary or the top boundary of the IBC search region. Consequently, if the BVP1 is selected, the BVD is always positive, pointing to the right for BV with a zero vertical component or to the bottom for BV with a zero horizontal component.
  • the optimal IBC AMVP index may be signaled, which allows obtaining (e.g. deriving) the sign of the non-zero BVD component at the decoder side.
  • the absolute magnitude of non-zero BVD component may be further signaled.
  • BVs with one null component may be signaled to the decoder by a first flag (e.g bvOneNullComp flag).
  • a first flag e.g bvOneNullComp flag
  • BVP candidates may be determined in the same way as in RRIBC mode, which are adjusted to the boundaries of the valid IBC search region according to the horizontal or vertical direction indicated by a second flag (e.g. bvNullCompDir flag) which indicates the direction of the zero component.
  • a third flag e.g. bvUseFlip flag
  • direction of the flipping horizontal or vertical
  • bvNullCompDir flag e.g. bvUseFlip flag
  • IBC may be used with template matching.
  • template matching (TM) based motion search and/or refinement may be applied to IBC, e.g. for both IBC merge mode and IBC AMVP mode.
  • An IBC-TM merge mode may be used.
  • An IBC-TM merge mode may involve a merge candidate list for BV prediction, different from the one used by a regular IBC merge mode.
  • the candidates may be selected according to a pruning method with motion distance(s) between the candidates (e.g. as in the regular TM merge mode).
  • the zero motion candidates may have been replaced by block vectors, for example, at (-W, 0), (0, -H), (-W, -H).
  • selected candidates may be refined with the template matching, e.g. prior to RDO (Rate Distortion Optimization) or decoding process.
  • the IBC-TM merge mode may be in competition with regular IBC merge mode.
  • a TM-merge indication (e.g. the TM-merge flag) may be signaled to indicate the template matching merge IBC mode.
  • one or more (e.g. up to 3) candidates may be selected from the IBC-TM merge list. Those candidates (e.g. each of those candidates) may be refined (e.g. according to the usual template matching method) and may be sorted, for example, according to their resulting TM costs. For example, one or more (e.g. only 2) first candidate(s) may be considered in the block vector estimation process.
  • TM refinement for example, for both IBC-TM merge and AMVP modes is quite simple since IBC block vectors may be constrained (i) to be integer and (ii) within a reference region. In IBC-TM merge mode, some (e.g. all) refinements may be performed at integer precision, and in IBC-TM AMVP mode, they may be performed either at integer or 4-pel precision depending on the AMVR value. Such a refinement accesses only to samples without interpolation. In both cases, the refined block vectors and the used template in each refinement step may respect the constraint of the IBC reference region.
  • the prediction signal may be generated by matching a L-shaped causal neighbor of the current block with another block in a (e.g. predefined search area), as shown by example in FIG. 9.
  • the search area may include several regions (e.g. four regions).
  • a first region R1 may indicate the current CTU
  • a second region R2 may indicate the top-left CTU
  • a third region R3 may indicate the above CTU
  • a fourth region R4 may indicate the left CTU.
  • Sum of absolute differences (SAD) may be used as a cost function.
  • the decoder may search for the template that has the least SAD with respect to the current one and use its corresponding block as a prediction block.
  • the dimensions of e.g.
  • SearchRange w, SearchRange h may be set proportional to the block dimension (BlkW, BlkH), for example, to have a fixed number of SAD comparisons per pixel.
  • the intra template matching tool may be enabled for CUs with a size less than or equal to 64 in width and height.
  • the maximum CU size for intra template matching may be configurable.
  • the Intra template matching prediction mode may be signaled at a CU level through a (e.g, dedicated) flag.
  • IntraTMP does not require encoding of a BV in order to create the prediction block at the decoder side.
  • the BV derived from the IntraTMP may be used for IBC.
  • the stored IntraTMP BV of the neighbouring blocks along with IBC BV may be used as spatial BV candidates in IBC candidate list construction.
  • a current IBC block can use both IBC BV and IntraTMP BV of neighbouring blocks as BV candidate for IBC BV candidate list as depicted on FIG. 10A.
  • IntraTMP block vectors are added to IBC block vector candidate list as spatial candidates.
  • IBC mode may interact with other coding tools, such as pairwise merge candidate, historybased motion vector predictor (HMVP), combined intra/inter prediction mode (CIIP), IBC merge mode with block vector differences (IBC-MBVD) which is an extension of the merge mode with motion vector difference (MMVD) to the IBC blocks, IBC-LIC (intra block copy with local illumination compensation), and geometric partitioning mode (GPM).
  • HMVP historybased motion vector predictor
  • CIIP combined intra/inter prediction mode
  • IBC-MBVD IBC merge mode with block vector differences
  • MMVD motion vector difference
  • IBC-LIC intra block copy with local illumination compensation
  • GPM geometric partitioning mode
  • IBC may be used with pairwise merge candidate and HMVP.
  • a new pairwise IBC merge candidate may be generated, for example, by averaging (e.g. two) IBC merge candidates.
  • IBC motion may be inserted into a history buffer for future referencing, e.g. for HMVP.
  • IBC may not be used in combination with an affine motion inter tool.
  • IBC may be used in combination with combined inter-intra prediction (CIIP), MMVD, and/or geometric partitioning mode (GPM).
  • IBC may not be allowed for chroma coding blocks, e.g. if/when a DUAL TREE partition is used.
  • IBC may be used with the inter prediction enhancement tool called LIC (Local Illumination Compensation).
  • IBC-LIC can be applied to IBC AMVP mode and IBC merge mode.
  • IBC AMVP mode an IBC-LIC flag may be signaled to indicate the use of IBC-LIC.
  • IBC merge mode the IBC- LIC flag is inferred from the merge candidate.
  • IBC-LIC flag can be inherited from an IBC HMVP candidate.
  • IBC-LIC may be applied to the CU whose block size is larger than or equal to 32 and smaller than or equal to 256.
  • the current picture may not be included as a reference picture in the reference picture list 0 for IBC prediction, for example.
  • the derivation process of block vectors for IBC mode may exclude (e.g. all) neighboring blocks in inter mode and vice versa.
  • IBC may share the (e.g. same) process as in (e.g. regular) MV merge, including with pairwise merge candidate and history-based motion predictor, but may disallow temporal motion vector prediction (TMVP) and zero vector, e.g. because they are invalid for IBC mode.
  • TMVP temporal motion vector prediction
  • a separate HMVP buffer e.g. five (5) candidates each
  • Block vector constraints may be implemented, e.g. in the form of a bitstream conformance constraint, e.g. so that the encoder ensures that invalid vectors are not present in the bitstream.
  • Merge mode may not be used, for example, if the merge candidate is invalid (e.g. out of range or zero (0)).
  • a bitstream conformance constraint may be expressed, for example, in terms of a virtual buffer.
  • IBC may be handled as inter mode, for example, for deblocking.
  • AMVR may not use quarter- pel, for example, if the current block is coded using IBC prediction mode.
  • AMVR may be signaled (e.g. only) to indicate whether a vector is integer-pel or 4 integer-pel, for example, if the current block is coded using IBC prediction mode.
  • the number of IBC merge candidates may be signaled in the slice header, for example, separately from the numbers of regular, subblock, and/or geometric merge candidates.
  • Bi-predictive IBC may be implemented, e.g. to enhance the coding performance of IBC for natural and screen content.
  • IBC may generate prediction samples with only one BV, i.e. uni- predictive IBC, but the prediction accuracy of IBC may still be improved.
  • IBC with several (e.g. two, i.e. bi-predictive IBC) BVs may be used besides uni -predictive IBC.
  • a first method may include an IBC BVP-merge mode.
  • a second method may include a Bi-predictive IBC merge mode.
  • Method 1 may derive the two (e.g. required) BVs from IBC block vector prediction mode (also referred to as IBC AMVP herein) and IBC merge mode (e.g. similar to the MV derivation of AMVP-merge mode that combines an AMVP motion vector predictor for a reference list and an inter merge candidate for the other reference list) to form a bi-predicted inter CU.
  • IBC block vector prediction mode also referred to as IBC AMVP herein
  • IBC merge mode e.g. similar to the MV derivation of AMVP-merge mode that combines an AMVP motion vector predictor for a reference list and an inter merge candidate for the other reference list
  • Two different indices for the IBC BVP mode and the IBC merge candidate may be signaled from the encoder to the decoder, respectively, taken from IBC AMVP candidate list and IBC merge candidate list.
  • Method 2 may derive the two (e.g. required) BVs from the IBC merge candidate list, for example, by utilizing two different IBC merge indices.
  • the two indices may be signaled from the encoder to the decoder.
  • the target of the bi-predictive IBC merge mode may be, for example, IBC-regular merge, IBC merge mode with block vector difference (IBC-MBVD), and IBC geometric partitioning mode (IBC-GPM), which may be enabled for screen content (e.g. by default).
  • IBC-MBVD may be enabled in natural and screen content
  • bi-predictive IBC-GPM may be enabled (e.g. only) in screen content.
  • the methods may be implemented based on one or more of the following.
  • the methods may reuse the IBC merge candidate list construction scheme for uni- predictive IBC merge mode.
  • the methods may use BV refinement.
  • the methods may enable the IBC with template matching.
  • the methods may use compensation.
  • the methods may generate final IBC prediction samples with a simple (1:1) average of bi-predictive IBC samples.
  • the methods may store the two BVs in BV storage, e.g. if/when the bi-predictive IBC is enabled.
  • the methods may use signaling.
  • a control flag of bi-predictive IBC may be signaled at a slice level in I slice (e.g. not signaled in B and P slices).
  • Reconstructed-Reordered IBC may be disabled, for example, if/when the bi-predictive IBC is enabled.
  • the methods may be enabled in chroma component blocks of the single tree.
  • the IBC coding mode may be used for the coding of camera- captured content.
  • the method may be adapted to make it perform well in terms of compression efficiency.
  • IBC merge modes may be disabled for natural content, i.e. camera-captured content.
  • a flag may be implemented to disable the associated CU level signaling. So, only IBC AMVP modes is activated when it is indicated explicitly by the flag.
  • RRIBC, TM-IBC and IBC-CIIP may be disabled for natural content.
  • corresponding flags may be implemented to activate/deactivate associated CU signaling.
  • IBC may be applied to intra slices for natural content. This may be indicated by high-level syntax to remove CU level signaling of IBC flag. For screen contents, IBC may be applied to all slices.
  • Encoder optimizations may be implemented in order to reduce computation workload for some cases.
  • IBC block vector search may be optimized for natural content, and the RDO process may be skipped for an IBC AMVP mode if its cost is worse than the lowest cost of all intra modes.
  • IBC AMVP modes may not be evaluated when the best intra mode has less than 3 nonzero coefficients.
  • some partitioning depth in an inter slice may be skipped depending on the distance between the current picture and its nearest reference picture.
  • the true distance may be used instead of setting to 0. It also applies fraction-pel extension on IBC.
  • the representation of IBC block vectors may be extended to fractional-pel resolution.
  • An interpolation filter may thus be required to derive the prediction samples located at a noninteger phase in the reconstructed area of the current frame.
  • the option of block vector resolutions may be extended to include quarter-pel resolution in additional to full-pel and 4-pel. Similar to inter AMVR syntax, the first bin of AMVR syntax may signaled to indicate whether BV is in quarter-pel resolution, while the second bin may be signaled to switch between full-pel and 4-pel resolutions.
  • the interpolation filters applied to the luma and chroma components of IBC blocks are the VVC style 8-tap luma filter and the same chroma filter as used in motion compensation, respectively.
  • An exception is that a 2-tap bilinear interpolation filter is applied to generate template prediction blocks, when needed in IBC-related coding tools.
  • Reference sample padding may be needed when some of them are not available or located outside valid IBC reference area in the current frame. When needed, it may be performed in horizontal direction first and then vertical direction.
  • BV may be explicitly encoded as illustrated on FIG. 10B, e.g. if/ when IBC AMVP mode is used.
  • the BV coding may use the similar processes specified for inter prediction but may use rules for predictor candidate list construction different from the ones used in the inter prediction.
  • the (e.g. optimal) IBC predictor may be selected during competing scheme with other candidates.
  • Once an encoder chooses a final predictor, its index may be signaled.
  • a block vector predictor (BVP) may be chosen by the encoder and a block vector difference (BVD) relative to the selected BVP may be signaled in addition.
  • BVP block vector predictor
  • BVD block vector difference
  • the absolute magnitude of non-zero BVD components here component referring to the x and y projection of the vector in 2-dimensional vector space, may be handled separately.
  • BV is equal to the sum of the BVP used for a given CU and its associated BVD.
  • specific coding scheme may apply. For both vector components, it is first checked if the absolute value of a component is greater than zero. It is indicated in the bitstream with the greater than zero flags, e.g. GrOx flag and GrOy_flag.
  • GrOx_flag
  • > 0 and GrOy_flag
  • j represents absolute value.
  • Gr0x_flag and Gr0y_flag are encoded into the bitstream, e.g. signaled to the decoder. For example, they can be encoded using Context Adaptive Binary Arithmetic Coding (CABAC) in a regular mode by using context modeling. After, if the component is greater than zero which is indicated by the corresponding greater than zero flag, the remaining absolute value is given with:
  • CABAC Context Adaptive Binary Arithmetic Coding
  • AbsRemY
  • the remaining absolute values AbsRemX and AbsRemY may be coded using first order Exponential-Golomb code. For example, it may first encode prefix bins followed by encoding suffix bins. First 5 prefix bins may be context coded (regular mode) after which remaining bins (if exist) may be coded with equal probability (EP) mode (bypass mode). Suffix bins may be coded with equal probability mode (EP mode).
  • sign may be encoded for those vector components with the amplitude greater than zero.
  • sign may be encoded by using the bypass mode.
  • the encoder side pseudo code for BVD encoding may be as follows.
  • GrOx_flag
  • GrOy_flag
  • Decoder side reassembles the same order of operations, however instead of encoding and writing the bins it reads and decode bins as follows.
  • decoder can reassemble final block vector.
  • Exponential-Golomb codes of k-th order (EGk) codes represent a symbol as two parts, where the first part is a prefix, and the second part is a suffix.
  • EGk code the code word size increases exponentially.
  • the number of the codes in the suffix part may double. Every code word comprises a unary code to represent the prefix part, followed by fixed length code for suffix part.
  • the index function p(L) may be coded using p(L) + 1 bits with unary code.
  • Index function maps from integers L to an index which is also an integer. In that sense integers are partitioned into the sets (called index sets) according to the index they map onto, and which is defined with index function p L). Note that the index of the set (and not the prefix value itself) is coded with unary code which represents the first part of the EGk code word.
  • Integers may then be encoded as their index, plus suffix part that represents their rank in the index set.
  • the index set may thus be ordered, e.g. natural ordering may be used in EGk code.
  • the rank e.g. suffix
  • the rank e.g. suffix
  • the rank (e.g. suffix) may be coded as fixed length representation of a length p(L) + k, where k is the order of the Exponential-Golomb code.
  • a fixed length part can be observed as a binary representation using the p(L) + k least significant bits.
  • suffix value itself may be coded with fix length binary representation. It represents the second part of the EGk codeword which is concatenated to the first part of the EGk codeword.
  • Example of partitioning into index sets with its prefix value and suffix values is given in Table 1.
  • any part of the syntax related to that component e.g. BVDy (and BVy) may be set to 0 without any further decoding.
  • BVDx any syntax element related to the BVDx component, e.g. signX, AbsRemX and GrOX flag.
  • BVDx component may not be encoded, e.g. encoding syntax elements related to the BVDx component may be omitted. It also implies that BVx is equal to 0 by the design of this mode. BVDx (and BVx) may be set to 0 by the decoder.
  • the previous example may be extended to any BV having one null component, regardless of whether it uses the RRIBC mode. If oneNullComp flag indicates that one component is zero, another flag, e.g. bvNullCompDir, indicates the direction of the zero component, and if flipping may be used, another flag, e.g. bvUseFlip, indicates if flipping is done in the direction of nonzero component. Since the zero-component of a block vector may be deducted from the oneNullComp and bvNullCompDir flags, it may not be needed to encode (decode respectively) the syntax elements related to this vector component. In the case where both vector components of BV are of equal amplitude, both components are encoded (decoded respectively) by previously described processes, which may lead to redundant bits.
  • a dedicated flag may be signaled to the decoder to indicate such a case where components are equal, e.g. values of BV (or of BVD) components are equal, i.e. the case where BVx is the same as BVy (or the case where BVDx is the same as BVDy).
  • BV or of BVD
  • values may be compared and this case may be signaled.
  • a specific mode may be designed to allow derivation of sign of BVD components on the decoder side, hence leading to additional bit savings by omitting the sign signaling.
  • a mode is signaled (e.g. encoded) through a dedicated syntax element (e.g. flag).
  • flipping e.g. a diagonal flipping
  • rotation of a block may be applied in order to improve the prediction process.
  • block vector encompasses both intra (IBC) block vector and inter motion vector.
  • IBC intra
  • a block vector is a displacement vector that applies to both intra and inter cases.
  • FIG. 11A depicts a flowchart of a decoding method according to an example.
  • a syntax element indicating whether two components of a vector (e.g. of BV or BVD or more generally a displacement vector) of an image block are equal is decoded.
  • a syntax element indicating whether absolute values of two components of a vector (e.g. of BV or BVD or more generally a displacement vector) of an image block are equal is decoded.
  • a first block vector component, e.g. BVx is decoded.
  • Decoding BVDx may comprise decoding GrOx flag, AbsRemX and signX as described before.
  • a second block vector component e.g. BVy
  • BVy a second block vector component
  • the image block is reconstructed based on the first block vector component and second block vector component. Reconstructing the image block comprises obtaining a prediction block by using the first block vector component and second block vector component and adding the prediction block to a decoded residual block.
  • FIG. 11B depicts a flowchart of an encoding method according to an example.
  • a syntax element is encoded indicating whether the two components of the vector of the image block are equal.
  • a syntax element is encoded indicating whether the absolute values of the two components of the vector of the image block are equal.
  • a first block vector component e.g. BVx
  • BV may be obtained by using standard encoder search procedure.
  • Encoding BVDx may comprise encoding GrOx flag, AbsRemX and signX as described before.
  • a second block vector component is encoded responsive to the determining.
  • Various embodiments are disclosed with reference to FIGs 12, 14, 16 and 18.
  • the image block is encoded based on the first block vector component and the second block vector component.
  • Encoding the image block comprises obtaining a prediction block by using the first block vector component and second block vector component and subtracting the prediction block from the image block to a obtain a residual block that is encoded.
  • FIG. 12 depicts a flowchart of an encoding method according to an example.
  • a BV of the current CU is obtained (e.g. found) by using standard encoder search procedure.
  • the components of a block vector BV are compared to check whether BV components are equal (including sign), e.g. whether BVx is the same as (i.e. is equal to) BVy.
  • a (e.g. dedicated) syntax element e.g. a flag
  • the signaled flag is set to 1 to indicate that the BVx and BVy are the same, i.e. equal.
  • the (e.g. dedicated) syntax element e.g.
  • both components BVx and BVy are encoded.
  • the values of the syntax elements are only examples. Other values may be used.
  • the flag may be signaled at CU level for each BV. Herein, the flag is referred as “bvEqualComp”.
  • a BV of a current CU is obtained (e.g. found), e.g. by using standard encoder search procedure.
  • a BV is obtained from a reference block and a BVD is obtained by subtracting the BVP from the obtained BV.
  • the flag bvEqualComp is initialized, for example to 0.
  • the vector components are then compared at SI 202, e.g. the BVx and BVy components of the vector are compared. In the case where BVx and BVy are the same, bvEqualComp is set to 1 indicating that both components are equal and thus that only BVx related syntax is present (e.g. signaled/encoded) in the bitstream.
  • bvEqualComp may be encoded (signaled) first at SI 204.
  • BVx component may be encoded at S1206.
  • encoding BVx comprises encoding BVDx component in a standard way of encoding block vector difference, as described previously. For example, it may comprise encoding Gr0x_flag, AbsRemX and signX as described before.
  • BVx and BVy components may be encoded (e.g. present in the bitstream) at SI 208 as described before.
  • encoding BVx and BVy components comprises encoding BVDx and BVDy components which may comprise, for example, encoding Gr0x_flag, AbsRemX, signX, Gr0y_flag, AbsRemY, signY as described before.
  • FIG. 13 depicts a flowchart of a decoding method according to an example.
  • the decoding method may use a sequence of operations similar to the encoding side sequence of operations in order to reassemble the block vector BV.
  • a syntax element e.g. bvEqualComp
  • BVx block vector components
  • BVy block vector components
  • BVx a first component
  • BVDx is decoded (e.g. Gr0x_flag, AbsRemX and signX are decoded as described before), and BVx is obtained (e.g. derived) therefrom, e.g.
  • BVDx may be decoded from the bitstream at SI 308, e.g. by decoding its associated syntax elements (e.g. Gr0y_flag, AbsRemY and signY) and deriving BVDy therefrom in a way as described before.
  • the component BVy may then be obtained (e.g. derived) therefrom.
  • a current block may then be reconstructed by using the block vector BV.
  • the sequence of operation may change (on both encoder and decoder side) without affecting the general idea of the whole process.
  • syntax elements related to the BVx component may be encoded (decoded) first. Then syntax element bvEqualComp may be encoded (decoded). If the information indicates that the components are the same, BVy is derived from BVx, otherwise, syntax elements related to the BVy component may be encoded (decoded).
  • absolute values of the vector components may be compared, e.g.
  • sign of a second vector component e.g. BVy component
  • sign of the second vector component is encoded (decoded) in (from) the bitstream.
  • FIG. 14 depicts a flowchart of an encoding method according to an example.
  • a BV of the current CU is obtained (e.g. found), e.g. by using standard encoder search procedure.
  • a (e.g. dedicated) syntax element e.g. a flag
  • the signaled flag is set to 1 to indicate that
  • the sign of the other component e.g. BVy, is encoded.
  • the (e.g. dedicated) syntax element e.g. the flag
  • both components BVx and BVy are encoded.
  • sign S of a BVy component cannot be deducted regardless of bvEqualComp value. Instead, sign S of BVy component is encoded at S1407 in the bitstream. If bvEqualComp is equal to 1 the absolute value
  • a BV of the current CU is obtained (e.g. found), e.g. by using standard encoder search procedure.
  • a BV is obtained from the reference block and the BVD is obtained by subtracting the BVP from the obtained BV.
  • the flag bvEqualComp is initialized, for example to 0.
  • the absolute values of block vector components are then compared at S1402, e.g. the
  • bvEqualComp is set to 1 indicating that both components are equal and thus that BVx related syntax elements are present (e.g. signaled/encoded) in the bitstream and sign of BVy component is present (e.g. signaled/encoded) in the bitstream.
  • bvEqualComp may be encoded (signaled) first at S1404.
  • BVDx related syntax elements may be encoded at SI 406.
  • BVDx component is obtained, e.g. by subtracting BVPx from the BVx.
  • BVDx is encoded in a standard way of encoding block vector difference, as described previously. For example, it may include encoding GrOx flag, AbsRemX and signX in a way as described before.
  • SI 407 only the sign of the BVy component is signaled (e.g. encoded).
  • the sign S of BVy component may be different from the sign of BVDy component (sign of BVDy here denoted as signY).
  • syntax elements related to the BVx and BVy may be encoded at S1408 in a standard way described before.
  • FIG. 15 depicts a flowchart of a decoding method according to an example.
  • the decoding method may use a sequence of operations similar to the encoding side sequence of operations in order to reassemble the block vector BV.
  • a syntax element e.g. bvEqualComp
  • BVDx indicates whether absolute values of block vector components, e.g.
  • a first component e.g. the component BVDx
  • Gr0x_flag, AbsRemX and signX are decoded as described before and BVDx derived therefrom
  • BVx is obtained (e.g. derived) therefrom, e.g.
  • BVDx is obtained (e.g. derived) from
  • BVy (S)
  • BVDy may be decoded from the bitstream at S 1510, e.g. by decoding its associated syntax elements (e.g. GrOy flag, AbsRemY and signY) and deriving BVDy therefrom in a way as described before. The component BVy may then be obtained (e.g. derived) therefrom.
  • a current block may then be reconstructed by using the block vector BV.
  • block vector difference BVD components may be compared, e.g. BVDx and BVDy or their absolute values
  • FIG. 16 depicts a flowchart of an encoding method according to an example.
  • a BV of the current CU is obtained (e.g. found) by using standard encoder search procedure.
  • BVDx and BVDy components are obtained, e.g. by subtracting BVP from the BV.
  • the flag bvEqualComp may be initialized, for example to 0.
  • the vector components e.g. the block vector difference components
  • bvEqualComp may be set to 1 indicating that both components are equal and thus that only BVDx is present (e.g. signaled/encoded) in the bitstream.
  • bvEqualComp is encoded at S1604.
  • BVDx is encoded at SI 606 in a standard way of encoding block vector difference, as described previously.
  • bvEqualComp is set to 0 indicating that components are not equal and thus that both BVDx and BVDy are present (e.g. signaled/encoded) in the bitstream.
  • bvEqualComp is encoded at SI 606.
  • BVDx and BVDy related syntax may be encoded at S1208 in a way described before.
  • FIG. 17 depicts a flowchart of a decoding method according to an example.
  • the decoding method may use a sequence of operations similar to the encoding side sequence of operations in order to reassemble the block vector BV.
  • a syntax element e.g. bvEqualComp
  • BVDx a first component
  • BVx is obtained, e.g. by adding BVDx and BVPx components.
  • BVy component may be obtained (e.g. reassembled) from BVDy, e.g. by adding BVDy and BVPy at S1708.
  • BVDy may be decoded from the bitstream at S1710, e.g. by decoding its associated syntax elements (e.g. GrOy_flag, AbsRemY and signY) and deriving BVDy therefrom in a way as described before.
  • the component BVy may then be obtained (e.g. derived) therefrom.
  • a current block may then be reconstructed by using the block vector BV.
  • the absolute values of the vector components are compared, e.g.
  • sign of a BVDy component cannot be deducted regardless of bvEqualComp value.
  • sign of BVDy component is encoded (decoded respectively) in (from) the bitstream.
  • FIG. 18 depicts a flowchart of an encoding method according to an example.
  • a BV of the current CU is obtained (e.g. found) by using standard encoder search procedure.
  • BVDx and BVDy components are obtained, e.g. by subtracting BVP from the BV.
  • the flag bvEqualComp may be initialized, for example to 0.
  • the absolute values of vector components are then compared at S1602, e.g.
  • bvEqualComp may be set to 1 indicating that both components are equal and thus that BVDx is present (e.g. signaled/encoded) in the bitstream and only the sign of the BVDy component is signaled (e.g. encoded) in the bitstream.
  • bvEqualComp is encoded at SI 604.
  • BVDx is encoded at SI 806 in a standard way of encoding block vector difference, as described previously. Then, only the sign of the BVDy component is signaled (e.g. encoded) in the bitstream at SI 807.
  • bvEqualComp is set to 0 indicating that components are not equal and thus that both BVDx and BVDy are present (e.g. signaled/encoded) in the bitstream.
  • bvEqualComp is encoded at SI 806.
  • BVDx and BVDy related syntax may be encoded at SI 808 in a way described before.
  • FIG. 19 depicts a flowchart of a decoding method according to an example.
  • the decoding method may use a sequence of operations similar to the encoding side sequence of operations in order to reassemble the block vector BV.
  • a syntax element e.g. bvEqualComp
  • indicates whether absolute values of BVD components are equal, i.e. whether
  • a first component e.g. BVDx
  • Gr0x_flag, AbsRemX and signX are decoded as described before
  • BVx is obtained, e.g. by adding BVDx and BVPx components.
  • BVDy is obtained (e.g. derived) from
  • BVDy (signY)
  • BVy component may be obtained (e.g. reassembled) from BVDy, e.g. by adding BVDy and BVPy at S 1910.
  • BVDy may be decoded from the bitstream at S1912, e.g. by decoding its associated syntax elements (e.g. GrOy flag, AbsRemY and signY) and deriving BVDy therefrom in a way as described before.
  • the component BVy may then be obtained (e.g. derived) therefrom.
  • a current block may then be reconstructed by using the block vector BV.
  • horizontal and vertical components may be swapped.
  • bvEqualComp is encoded (decoded respectively) after RRIBC flag or after oneNullComp flag.
  • RRIBC e.g. RRIBC flag is set to 1
  • bvEqualComp is not encoded (decoded respectively) and it may be assumed to be 0. Otherwise (RRIBC flag is 0), bvEqualComp is encoded (decoded respectively).
  • oneNullComp is equal to 1
  • bvEqualComp is not encoded (decoded respectively) and it may be assumed to be 0.
  • bvEqualComp is encoded (decoded respectively).
  • bvEqualComp is encoded (decoded respectively) before RRIBC flag or before oneNullComp flag.
  • RRIBC flag is not encoded (decoded respectively) and it may be assumed to be 0. Otherwise (bvEqualComp is 0), RRIBC flag is encoded (decoded respectively).
  • bvEqualComp is equal to 1
  • oneNullComp flag is not encoded (decoded respectively) and it may be assumed to be 0.
  • bvEqualComp is 0
  • oneNullComp is encoded (decoded respectively).
  • bvEqualComp flag is encoded in the bitstream and is equal to 1
  • another flag here noted as bvUseDiagFlip may be encoded.
  • This another flag bvUseDiagFlip indicates if diagonal flipping is performed (e.g. applied), e.g. is applied on the encoder side and thus is to be applied on the decoder side. For example, at the decoder side, when diagonal flipping is applied, the samples in a reconstructed block are flipped diagonally. At the encoder side, the original block may be flipped diagonally before block vector search.
  • original block may be flipped in a diagonal direction before vector search. After the optimal block vector is found, residual block may be obtained and flipped diagonally in a same direction to go back to the initial state (to recover initial block size). Residual is then encoded.
  • residual block is decoded.
  • Prediction block is obtained in a way that first width and height of the block are swapped. Then, prediction samples are taken with respect to the block vector of the current block and new prediction block size. Then, prediction is flipped in a diagonal direction to recover initial block size. Residual block and flipped prediction block are used to obtain reconstructed block.
  • another flag may be used instead of bvUseDiagFlip, e.g. to indicate a rotation of the block.
  • This another flag e.g. bvUseRot, indicates if rotation is performed (e.g. applied), e.g. is applied on the encoder side and thus is to be applied on the decoder side.
  • the encoder and decoder processes may be the same as with diagonal flipping, only that rotation is performed instead of flipping.
  • FIG. 24A and 24B illustrate pixel rearrangement approaches (including horizontal and vertical flipping). For example, two diagonal flipping and three rotation angles (e.g. -45°, 45° or 90°) may be supported.
  • the direction of diagonal flipping is relative to a primary diagonal, e.g. a diagonal that goes from the upper left comer to the lower right comer as illustrated on FIGs 24B and 25A.
  • the direction of diagonal flipping is relative to a secondary diagonal, e.g. a diagonal that goes from the lower left comer to the upper right comer as illustrated on FIGs 24B and 25B.
  • the used flipping direction may be signaled (e.g. encoded) in the bitstream.
  • the used flipping direction may be predefined. In the latter case, there is no need to signal this flipping direction in the bitstream.
  • the used rotation angle may be signaled (e.g. encoded) in the bitstream.
  • the used rotation angle may be predefined. In the latter case, there is no need to signal this rotation angle in the bitstream.
  • vertical and/or horizontal flipping may be supported along with the syntax element bvEqualComp.
  • the use of the flipping may be decided by the encoder and signaled to the decoder.
  • a coding mode (e.g. a specific coding mode) which allows sign derivation of the BVDx and BVDy component at the decoder side from a BVP.
  • This specific mode may be tested as an additional mode by the encoder during RDO.
  • a (e.g dedicated) syntax element (e.g. flag) may be set to 1 indicating the usage of this specific coding mode.
  • the encoder thus signals the usage of this mode by encoding the syntax element set to 1. Otherwise (if/when the mode is not used), the syntax element set to 0 may be encoded.
  • the values of the syntax elements are only examples.
  • the decoder may know whether or not this specific coding mode is used for a current block by decoding the syntax element (e.g. flag).
  • the flag may be signaled at CU level for each BV. Herein, the flag is referred as “bvDerivedSigns”.
  • FIG. 20A is a flowchart of a decoding method according to an example. The method applies for example in the case where the syntax element mentioned above (e.g. bvDerivedSigns) indicates the use of this specific coding mode for a current block, e.g. because this mode is selected during RDO search.
  • the syntax element mentioned above e.g. bvDerivedSigns
  • a block vector predictor (BVP) is obtained for an image block.
  • the BVP may be obtained for example from a list of candidate BVPs located as defined on FIGs 21 A and 21B.
  • an index is decoded that identifies the BVP in the list of candidate BVPs.
  • the list of candidate BVPs comprises a subset of the BVPs defined on FIGs 21A and 21B.
  • an absolute value of a first block vector difference component e.g.
  • a sign of the first block vector difference component and a sign of a second block vector difference component are obtained based on the block vector predictor obtained at S2002.
  • and a second block vector difference component is obtained from the absolute value of the first block vector difference component and the sign of the second block vector difference component, e.g. BVDy (signY)
  • the image block is reconstructed based on the first block vector component and second block vector component.
  • FIG. 20B is a flowchart of an encoding method according to an example. The method applies for example in the case where sign derivation of the BVDx and BVDy components is used, e.g. because this mode is to be tested in RDO search or is selected during RDO search.
  • a block vector predictor (BVP) and a BV are selected, e.g. by RDO, so that
  • the BVP may be selected for example from a list of candidate BVPs located as defined on FIGs 21 A and 21 B and block vectors are only diagonal, e.g. located at the one of the diagonals illustrated on FIGs 21 A and 21B. Therefore, both BV and BVP are located at the one of the diagonals illustrated on FIGs 21 A and 21B in order to verify the above condition
  • the list of candidate BVPs comprises a subset of the BVPs defined on FIGs 21A and 21B.
  • an index may be encoded identifying the selected BVP.
  • BVDx an absolute value of a first block vector difference component (e.g.
  • BVDx is obtained by subtracting BVPx from BVx, where BVPx is the first component of the selected BVP.
  • BVPx is the first component of the selected BVP.
  • No sign is encoded neither for BVDx nor for BVDy.
  • no amplitude is encoded for BVDy as by definition of the coding mode
  • the image block is encoded based on the first block vector component BVx and the second block vector component BVy.
  • Two modes may be tested by the encoder during the RDO search for the optimal BV.
  • bvDerivedSigns flag is set to 1.
  • a specific BVP derivation process may apply which may allow decoder to derive the signs of BVDx and BVDy components from a BVP without previously signaling (e.g. encoding) them.
  • block vector predictors may be defined. They are located on the direction of the three diagonals, e.g. diagonal Do, diagonal Di and diagonal D2, as illustrated on the FIGs 21A and 21B, where BVPs positions are marked with a “x” mark and where the coordinates of each BVP are given with respect to the top left sample of the current block PO with coordinates (0, 0).
  • the definition of a diagonal is given by the following.
  • diagonal represents a line segment in a reconstructed reference region (e.g. grey region on FIG.21B enclosed by dashed line) where each point on the line segment may represent a block vector for which both vector components are of the equal amplitude, e.g.
  • is equal to
  • is equal to
  • a position of a vector e.g. of a BV or of a BVP
  • is considered as valid in the case where a reference block obtained from that vector is completely within the reconstructed region. Therefore, with reference to FIG. 21B, the valid positions with respect to the current block are identified by thick line segments on Do, Di and D2.
  • the BVPs are selected to be located on the diagonals in a way that first BVP is located on a nearest valid position to the current block, and a second BVP is located on a farthest valid position from the current block, both lying on the diagonal relative to the current block position.
  • the BVPs are located at both ends of the thick line segments while the BV may be selected, on the encoder side, at any location between both ends of the thick line segments.
  • the valid positions on Do are between BVPo and BVPi.
  • the vector positions on Do between BVPo and PO are not valid since a reference block derived from that vector would overlap the current block (e.g. will fall within not yet reconstructed region).
  • valid locations are selected with the respect of the current block size and the borders of the reference region (e.g. when IBC mode is used and when encoding intra block vectors) as illustrated on FIG. 2 IB.
  • valid locations are selected only based on the reference region (e.g. in inter mode and when encoding motion vectors).
  • reconstructed region is the whole reference frame and the reference region may be extended to also include the bottom right part relative to the current block PO.
  • another diagonal e.g. denoted as D3, may be used in the process.
  • D3 is a line segment that connects PO and bottom right part of the reference region in a way as described before (line segment where both vector components are of the equal amplitude, e.g.
  • two new predictors may be added (e.g. in total 8 block vector predictors may be used).
  • a segment between PO and closer BVPs on each diagonal are now valid segments.
  • BVPO is of coordinates (-1,-1)
  • BVP2 is of coordinates (1,-1)
  • BVP4 is of coordinates (-1,1).
  • Location PO e.g. zero vector
  • Location PO e.g. zero vector
  • a BVP selected from valid locations is considered to be valid and can be used in the BV search process.
  • Valid BVP locations marked by “x” are selected with respect to the block width w and block height h, and with respect to the size of the reference region here defined by distances of the borders of the reference region i,j, m, and n relative to the current block. Same rules are applied at the decoder and encoder, hence both select the same set of BVPs.
  • a list of candidates BVPs (e.g. an AMVP list) is constructed (e.g. created) as follows. First predictor(s), e.g. BVPO and BVP1, from diagonal Do may be added to the list, if available. Then, predictor(s), e.g.BVP2 and BVP3, from Di may be added and at the end predictor(s), e.g. BVP4 and BVP5,from D2 may be added, if available.
  • available predictors may be reordered based on their template matching costs.
  • reordering may be done only in the case where there are more than two candidates in the list of candidates. In this latter case, up to two predictors with smallest template costs may be used in RDO.
  • An index e.g. optimal AMVP index
  • is signaled e.g. encoded
  • this mode is constrained to block vectors with vector components of equal amplitude, e.g. equal absolute values of BVx and BVy component (
  • This mode also implies, given the previous constraint and list (AMVP list) derivation (BVPs locations), that
  • the signs of the BVD components may be obtained (e.g. derived) at the decoder.
  • the same list of candidates is constructed with optionally the same template matching reordering.
  • the index is decoded to select a BVP in the constructed list of candidates. Since this mode is supported when bvDerivedSigns is 1, the absolute value of BVDx component is signaled to the decoder (e.g. encoded in the bitstream).
  • the absolute value of the BVDy is not signaled but it is obtained (e.g. derived) at the decoder side, e.g.
  • is set to be equal to
  • BVD if BVPo is selected as a final predictor, BVD if not zero may only point from the bottom to the top left diagonal, leading to the negative sign for BVDx and negative sign for BVDy component.
  • BVPs is selected as a final predictor, BVD if not zero may only point from the bottom to the top right diagonal, leading to the positive sign for BVDx component and negative sign for BVDy component.
  • bvDerivedSigns flag is set to 0.
  • the signs may not be obtained (e.g. derived) as in the previous mode (i.e. if/when bvDerivedSigns flag is set to 1).
  • standard list of candidates e.g. IBC AMVP list.
  • the list may be created in the same way at the encoder and at the decoder side.
  • the list may include BVPs that are used in the previous mode, e.g. ⁇ BVPO, BVP1, BVP2, BVP3, BVP4, BVP5 ⁇ illustrated on the FIG. 21.
  • BVPs that are used in the previous mode may be pruned (discarded) from the standard list of candidates (standard AMVP list) .
  • a BV is obtained from the reference block and the BVD is obtained by subtracting the BVP from the obtained BV.
  • BVD then may be encoded (decoded) in the standard way.
  • additional constraint may be imposed when searching for the optimal BV in this mode (e.g. bvDerivedSigns flag is set to 0).
  • may be skipped during the search process, e.g. during the RDO optimization.
  • is equal to
  • such vector may not be allowed to be used in this mode, i.e. if/when bvDerivedSigns flag is set to 0. Indeed, such block vectors with equal absolute component values may be more efficiently encoded with the first mode indicated by the bvDerivedSigns flag set to 1.
  • further processing may include signaling of bvEqualComp flag.
  • bvEqualComp may be obtained (e.g. derived) and encoded (decoded) by using one of the methods described in the previous embodiments disclosed with reference to FIGs 12-19. The use of bvEqualComp is as described in the previous embodiments.
  • both encoder and decoder Based on the mode index, e.g. based on the bvDerivedSigns flag, both encoder and decoder know which list of candidates (AMVP list) should be constructed.
  • the mode index e.g. the value of bvDerivedSigns, may be decided by the encoder during the RDO process and signaled to the decoder.
  • bvDerivedSigns is encoded (decoded) after RRIBC flag or after oneNullComp flag.
  • RRIBC flag is set to 1
  • bvDerivedSigns is not encoded (decoded) and standard way of finding optimal BV is used without any modification (e.g. as in prior art).
  • RRIBC flag is 0
  • bvDerivedSigns is encoded (decoded).
  • oneNullComp is equal to 1
  • bvDerivedSigns is not encoded (decoded) and standard way of finding optimal BV is used without any modification (e.g. as in prior art).
  • oneNullComp is 0
  • bvDerivedSigns is encoded (decoded).
  • bvDerivedSigns is encoded (decoded) before RRIBC flag or before oneNullComp flag.
  • RRIBC flag is not encoded (decoded) and it may be assumed to be 0. Otherwise (bvDerivedSigns is 0), RRIBC flag is encoded (decoded).
  • oneNullComp flag is not encoded (decoded) and it may be assumed to be 0. Otherwise (bvDerivedSigns is 0), oneNullComp flag is encoded (decoded).
  • the encoding of the RRIBC flag or oneNullComp flag may be further conditioned based on the bvEqualComp flag (if used) as described previously.
  • bvDerivedSigns flag is encoded in the bitstream and is equal to 1
  • another flag here noted as bvUseDiagFlip may be encoded. It indicates if diagonal flipping is performed (e.g. applied), e.g. is applied on the encoder side and thus is to be applied on the decoder side. For example, at the decoder side, when diagonal flipping is applied, the samples in a reconstructed block are flipped diagonally. At the encoder side, the original block may be flipped diagonally before block vector search. For non-square blocks additional steps may be applied, for example to maintain the block size, in case where the diagonal flipping is performed.
  • original block may be flipped diagonally before vector search. After an optimal block vector is found, prediction block is obtained, and residual block is obtained therefrom. Then residual block is flipped diagonally in a same direction to go back to the initial state (to recover initial block size). Residual block is then encoded.
  • residual block is decoded.
  • Prediction block is obtained in way that first width and height of the block are swapped.
  • prediction samples are taken with respect to the block vector of the current block and new prediction block size.
  • prediction block is flipped in a diagonal direction to recover initial block size. Residual block and flipped prediction block are used to obtain reconstructed block.
  • another flag may be used instead of bvUseDiagFlip, e.g. to indicate a rotation of the block.
  • This another flag e.g. bvUseRot, indicates if rotation is performed (e.g. applied), e.g. is applied on the encoder side and thus is to be applied on the decoder side.
  • the encoder and decoder processes may be the same as with diagonal flipping, only that instead of flipping, rotation is performed.
  • FIG. 24A, 24B, 25 A and 25B illustrate pixel rearrangement approaches (including horizontal and vertical flipping). For example, two diagonal flipping and three rotation angles (e.g. -45°, 45° or 90°) may be supported.
  • the used flipping direction or rotation angle may be deducted from the position of the BVP candidate within the mode signaled by bvDerivedSigns equal to 1. For example, if BVP is on the diagonal Do, flipping is from the bottom right to the top left, which corresponds to the diagonal flipping in the primary diagonal direction. If, for example, BVP is on the diagonal Di, flipping is from the bottom left to the top right which corresponds to the diagonal flipping in the secondary diagonal direction, and for example, if BVP is on the diagonal D2, flipping is from the top right to the bottom left direction which corresponds to the diagonal flipping in the primary diagonal direction.
  • the used flipping (or rotation) direction may be signaled (e.g. encoded) in the bitstream.
  • the used flipping direction (or the used rotation angle) may be predefined in which case there is no need to signal this flipping direction (rotation angle respectively) in the bitstream.
  • vertical and/or horizontal flipping may be supported along with the syntax element bvDerivedSigns.
  • the use of the flipping and/or rotation may be decided by the encoder and signaled to the decoder.
  • FIG 22A discloses a decoding method comprising diagonal flipping and/or rotation in a case of a square block
  • FIG. 22B discloses a decoding method comprising diagonal flipping and/or rotation in a case of a non-square block, e.g. of a rectangular block.
  • the decoding method and encoding method are disclosed for diagonal flipping.
  • the encoder and decoder methods may be the same for rotation as with diagonal flipping, only that rotation is performed instead of flipping and rotation angle replaces diagonal direction.
  • a syntax element e.g. a flag
  • the flag may be UseDiagFlip.
  • an image block is reconstructed.
  • the image block e.g. the reconstructed image block
  • a diagonal direction e.g. the same diagonal direction as used on the encoder side
  • the rotation angle used at S2206 is the opposite of the rotation angle used on the encoder side.
  • the syntax element indicates diagonal flipping is to be applied (e.g. UseDiagFlip is equal to 1)
  • the samples of the image block are flipped. Otherwise (e.g. UseDiagFlip is equal to 0) no diagonal flipping applies.
  • the direction of diagonal flipping is relative to the primary diagonal, e.g. a diagonal of a block that goes from the upper left comer to the lower right comer.
  • the direction of diagonal flipping is relative to the secondary diagonal, e.g. a diagonal of a block that goes from the lower left comer to the upper right comer.
  • the flipping direction may be signaled in the bitstream or defined a priori.
  • the decoding method comprise additional steps.
  • a syntax element e.g. a flag
  • the flag may be UseDiagFlip.
  • a residual block is obtained, e.g. decoded.
  • the following steps apply responsive to the syntax element indicating diagonal flipping is to be applied. Said otherwise, in the case where the syntax element indicates diagonal flipping is to be applied (e.g. UseDiagFlip is equal to 1), the steps S2214 to S2218 apply. Otherwise (e.g. UseDiagFlip is equal to 0) no diagonal flipping applies and thus regular block reconstruction applies.
  • a prediction block is obtained with swapped height and width with respect to the residual block, i.e. the prediction block has a width h and a height w.
  • the prediction samples of the prediction block are taken from the reconstructed image with respect to the block vector of the image block and new prediction block size, i.e. hxw.
  • the prediction block is flipped in a diagonal direction, e.g. the same as the one used on the encoder side, to recover initial block size, i.e. wxh. In case of rotation, the prediction block is rotated by a rotation angle which is the opposite of the rotation angle used at S2308 at the encoder side.
  • a reconstructed block is obtained based on the residual block and the flipped prediction block, e.g. by adding the residual block and the flipped prediction block.
  • FIG 23A discloses an encoding method comprising diagonal flipping and/or rotation in a case of a square block
  • FIG. 23B discloses an encoding method comprising diagonal flipping and/or rotation in a case of a non-square block, e.g. in case of a rectangular block.
  • different steps may thus apply.
  • an image block (e.g. original image block) is flipped in a diagonal direction to obtain a flipped image block, e.g. samples of the image block are flipped in the diagonal direction.
  • a syntax element e.g. a flag
  • a flag e.g. UseDiagFlip
  • the flag indicates thus to a decoder that the samples of the encoded block were flipped and thus that flipping has to be applied on the decoder side.
  • the flipped image block is encoded. Encoding the flipped image block may comprise obtaining a prediction block, subtracting the prediction block from the flipped image block to obtain a residual block. The residual block may then be transformed, quantized and entropy coded.
  • the encoding method comprise of additional steps.
  • an image block e.g. an original image block or source image block
  • a diagonal direction e.g. before vector search
  • a syntax element indicating diagonal flipping is to be applied on the image block is encoded.
  • a prediction block of the flipped image block is obtained, wherein the prediction block has a width h and a height w.
  • an optimal block vector is selected by a vector search process and the prediction is derived therefrom.
  • a residual block is obtained based on the prediction block and the (e.g. flipped original) image block, e.g. by subtracting the prediction block from the (e.g. flipped original) image block.
  • the residual block is flipped back (in a same diagonal direction as the one used at S2308) to come back to initial block size, i.e. to obtain a residual block of size of width w and height h.
  • the residual block is rotated by an angle which is the opposite of the rotation angle used at S2308.
  • the flipped residual block is further encoded at S2318.
  • another flag may be used instead of bvUseDiagFlip, e.g. to indicate a rotation of the block.
  • This another flag e.g. bvUseRot, indicates if rotation is performed (e.g. applied), e.g. is applied on the encoder side and thus is to be applied on the decoder side.
  • FIGs 24A and 24B illustrate pixel rearrangement approaches (including horizontal and vertical flipping). For example, two diagonal flipping and three rotation angles (e.g. -45°, 45° or 90°) may be supported.
  • the direction of diagonal flipping is relative to a primary diagonal, e.g. a diagonal that goes from the upper left comer to the lower right comer as illustrated on FIGs 24B and 25A.
  • the direction of diagonal flipping is relative to a secondary diagonal, e.g. a diagonal that goes from the lower left comer to the upper right comer as illustrated on FIGs 24B and 25B.
  • the used flipping direction may be signaled (e.g. encoded) in the bitstream.
  • the used flipping direction may be predefined. In the latter case, there is no need to signal this flipping direction in the bitstream.
  • the used rotation angle may be signaled (e.g. encoded) in the bitstream.
  • the used rotation angle may be predefined. In the latter case, there is no need to signal this rotation angle in the bitstream.
  • the present aspects are not limited to ECM, VVC or HEVC, and can be applied, for example, to other standards and recommendations, and extensions of any such standards and recommendations. Unless indicated otherwise, or technically precluded, the aspects described in this application can be used individually or in combination.
  • syntax elements as used herein such as terms in equations and algorithms, signal (e.g. flag) labels/names, etc., such as bvEqualComp, bvDerivedSigns, bvUseDiagFlip, bvUseRot, UseDiagFlip and so on, are descriptive terms. As such, they do not preclude the use of other syntax element names.
  • Decoding can encompass all or part of the processes performed, for example, on a received encoded sequence in order to produce a final output suitable for display.
  • processes include one or more of the processes typically performed by a decoder, for example, entropy decoding, inverse quantization, inverse transformation, and differential decoding.
  • processes also, or alternatively, include processes performed by a decoder of various implementations described in this application, for example, decode a block vector or a block vector difference.
  • decoding refers only to entropy decoding
  • decoding refers only to differential decoding
  • decoding refers to a combination of entropy decoding and differential decoding
  • decoding refers to the whole reconstructing picture process including entropy decoding.
  • encoding can encompass all or part of the processes performed, for example, on an input video sequence in order to produce an encoded bitstream.
  • processes include one or more of the processes typically performed by an encoder, for example, partitioning, differential encoding, transformation, quantization, and entropy encoding.
  • processes also, or alternatively, include processes performed by an encoder of various implementations described in this application, for example, encode a block vector or a block vector difference.
  • encoding refers only to entropy encoding
  • encoding refers only to differential encoding
  • encoding refers to a combination of differential encoding and entropy encoding.
  • This disclosure has described various pieces of information, such as for example syntax, that can be transmitted or stored, for example.
  • This information can be packaged or arranged in a variety of manners, including for example manners common in video standards such as putting the information into an SPS, a PPS, a NAL unit, a header (for example, a NAL unit header, or a slice header), or an SEI message.
  • Other manners are also available, including for example manners common for system level or application level standards such as putting the information into one or more of the following: a. SDP (session description protocol), a format for describing multimedia communication sessions for the purposes of session announcement and session invitation, for example as described in RFCs and used in conjunction with RTP (Real-time Transport Protocol) transmission.
  • SDP session description protocol
  • RTP Real-time Transport Protocol
  • DASH MPD Media Presentation Description
  • a Descriptor is associated with a Representation or collection of Representations to provide additional characteristic to the content Representation.
  • RTP header extensions for example as used during RTP streaming.
  • ISO Base Media File Format for example as used in OMAF and using boxes which are object-oriented building blocks defined by a unique type identifier and length also known as 'atoms' in some specifications.
  • HLS HTTP live Streaming
  • a manifest can be associated, for example, to a version or collection of versions of a content to provide characteristics of the version or collection of versions.
  • Some embodiments may refer to rate distortion optimization.
  • the rate distortion optimization is usually formulated as minimizing a rate distortion function, which is a weighted sum of the rate and of the distortion.
  • the approaches may be based on an extensive testing of all encoding options, including all considered modes or coding parameters values, with a complete evaluation of their coding cost and related distortion of the reconstructed signal after coding and decoding.
  • Faster approaches may also be used, to save encoding complexity, in particular with computation of an approximated distortion based on the prediction or the prediction residual signal, not the reconstructed one.
  • the implementations and aspects described herein can be implemented in, for example, a method or a process, an apparatus, a software program, a data stream, or a signal. Even if only discussed in the context of a single form of implementation (for example, discussed only as a method), the implementation of features discussed can also be implemented in other forms (for example, an apparatus or program).
  • An apparatus can be implemented in, for example, appropriate hardware, software, and firmware.
  • the methods can be implemented in, for example, a processor, which refers to processing devices in general, including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device. Processors also include communication devices, such as, for example, computers, cell phones, portable/personal digital assistants ("PDAs”), and other devices that facilitate communication of information between end-users.
  • PDAs portable/personal digital assistants
  • references to “one embodiment” or “an embodiment” or “one implementation” or “an implementation”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment.
  • the appearances of the phrase “in one embodiment” or “in an embodiment” or “in one implementation” or “in an implementation”, as well any other variations, appearing in various places throughout this application are not necessarily all referring to the same embodiment.
  • Determining the information can include one or more of, for example, estimating the information, calculating the information, predicting the information, or retrieving the information from memory.
  • Accessing the information can include one or more of, for example, receiving the information, retrieving the information (for example, from memory), storing the information, moving the information, copying the information, calculating the information, determining the information, predicting the information, or estimating the information.
  • this application may refer to “receiving” various pieces of information.
  • Receiving is, as with “accessing”, intended to be a broad term.
  • Receiving the information can include one or more of, for example, accessing the information, or retrieving the information (for example, from memory).
  • “receiving” is typically involved, in one way or another, during operations such as, for example, storing the information, processing the information, transmitting the information, moving the information, copying the information, erasing the information, calculating the information, determining the information, predicting the information, or estimating the information.
  • the word “signal” refers to, among other things, indicating something to a corresponding decoder.
  • the encoder signals whether suffix part of BVD is present or not in the bitstream and thus whether it has to be decoded or predicted.
  • the same parameter is used at both the encoder side and the decoder side.
  • an encoder can transmit (explicit signaling) a particular parameter to the decoder so that the decoder can use the same particular parameter.
  • signaling can be used without transmitting (implicit signaling) to simply allow the decoder to know and select the particular parameter.
  • signaling can be accomplished in a variety of ways. For example, one or more syntax elements, flags, and so forth are used to signal information to a corresponding decoder in various embodiments. While the preceding relates to the verb form of the word “signal”, the word “signal” can also be used herein as a noun.
  • implementations can produce a variety of signals formatted to carry information that can be, for example, stored or transmitted.
  • the information can include, for example, instructions for performing a method, or data produced by one of the described implementations.
  • a signal can be formatted to carry the bitstream of a described embodiment.
  • Such a signal can be formatted, for example, as an electromagnetic wave (for example, using a radio frequency portion of spectrum) or as a baseband signal.
  • the formatting can include, for example, encoding a data stream and modulating a carrier with the encoded data stream.
  • the information that the signal carries can be, for example, analog or digital information.
  • the signal can be transmitted over a variety of different wired or wireless links, as is known.
  • the signal can be stored on a processor-readable medium.
  • features described herein may be implemented in a bitstream or signal that includes information generated as described herein. The information may allow a decoder to decode a bitstream and/or an encoder to encode a bitstream, according to any of the embodiments described.
  • features described herein may be implemented by creating and/or transmitting and/or receiving and/or decoding a bitstream or signal.
  • features described herein may be implemented by a method, process, apparatus, medium storing instructions, medium storing data, or signal.
  • features described herein may be implemented by a TV, set-top box, cell phone, tablet, or other electronic device that performs decoding (encoding respectively).
  • the TV, set-top box, cell phone, tablet, or other electronic device may display (e.g. using a monitor, screen, or other type of display) a resulting image (e.g., an image from residual reconstruction of the video bitstream).
  • the TV, set-top box, cell phone, tablet, or other electronic device may receive a signal including an encoded image and perform decoding.
  • a decoding method comprises: decoding a syntax element indicating whether two components of a vector of an image block are equal ; decoding a first block vector component ; obtaining a second block vector component responsive to the syntax element ; and reconstructing the image block by using the first block vector component and second block vector component.
  • the syntax element indicates whether the first and the second block vector components are equal and obtaining the second block vector component responsive to the syntax element comprises : obtaining the second block vector component from the first block vector component in a case where said syntax element indicates the first and the second block vector components are equal ; and decoding the second block vector component otherwise.
  • the syntax element indicates whether absolute values of the first and the second block vector components are equal and obtaining the second block vector component responsive to the syntax element comprises : decoding a sign of the second block vector component ; obtaining the second block vector component from the absolute value of the first block vector component and the sign of the second block vector component in a case where said syntax element indicates the absolute values of the first and the second block vector components are equal ; and decoding the second block vector component otherwise.
  • the syntax element indicates whether first and second block vector difference components are equal and obtaining the second block vector component responsive to the syntax element comprises : obtaining a second block vector difference component from a decoded first block vector difference component in a case where said syntax element indicates the first and second block vector difference components are equal and obtaining the second block vector component from the second block vector difference component; and decoding the second block vector component otherwise.
  • decoding another syntax element indicating whether diagonal flipping or rotation is performed on the reconstructed image block.
  • the syntax element is decoded after decoding a flag indicating whether reconstruction-reordered intra block copy applies, the syntax element is decoded only in a case where the flag indicates reconstruction-reordered intra block copy does not apply.
  • the syntax element in a case where the syntax element is decoded after decoding a flag indicating whether a block vector has one null component, the syntax element is decoded only in a case where the flag indicates the block vector has not a null component.
  • the flag is decoded only in a case where the syntax element indicates that the two components of the vector of the image block are not equal.
  • the flag is decoded only in a case where the syntax indicates that the two components of the vector of the image block are not equal.
  • An encoding method comprises : determining whether two components of a vector of an image block are equal ; encoding a syntax element indicating whether the two components of the vector of the image block are equal ; encoding a first block vector component ; encoding a second block vector component responsive to the determining; and encoding the image block based on the first block vector component and second block vector component.
  • a decoding method comprises : obtaining a block vector predictor for an image block ; decoding an absolute value of a first block vector difference component ; obtaining a sign of the first block vector difference component and a sign of a second block vector difference component based on the block vector predictor ; obtaining a first block vector difference component from the absolute value of the first block vector difference component and the sign of the first block vector difference component and a second block vector difference component from the absolute value of the first block vector difference component and the sign of the second block vector difference component ; obtaining a first block vector component by adding a first block vector difference component and a first block vector predictor component and obtaining a second block vector component by adding a second block vector difference component and a second block vector predictor component; and reconstructing the image block based on the first block vector component and the second block vector component.
  • constructing the list of block vector predictor candidates comprises adding block vector predictors located on at least one diagonal relative to a position of the image block so that one block vector predictor is located on a nearest position to the image block and another block vector predictor is located on a farthest position from the image block.
  • constructing the list of block vector predictor candidates comprises reducing the list of block vector predictor candidates by selecting at least two block vector predictors associated with lowest template matching costs .
  • decoding another syntax element indicating whether diagonal flipping or rotation is performed on the reconstructed image block is performed on the reconstructed image block.
  • a direction of flipping may be derived from the block vector predictor obtained for the image block.
  • the syntax element in a case where a syntax element indicating signs of block vector difference components are obtained based on the block vector predictor is decoded after decoding a flag indicating whether reconstruction-reordered intra block copy applies, the syntax element is decoded only in a case where the flag indicates reconstruction-reordered intra block copy does not apply.
  • the syntax element in a case where a syntax element indicating signs of block vector difference components are obtained based on the block vector predictor is decoded after a flag indicating whether a block vector has one null component, the syntax element is decoded only in a case where the flag indicates the block vector has not a null component.
  • a syntax element indicating signs of block vector difference components are obtained based on the block vector predictor is decoded before decoding a flag indicating whether reconstruction-reordered intra block copy applies
  • said flag is decoded only in a case where the syntax element indicates that the signs of block vector differences are not obtained based on the block vector predictor.
  • a syntax element indicating signs of block vector difference components are obtained based on the block vector predictor is decoded before decoding a flag indicating whether a block vector has one null component
  • said flag is decoded only in a case where the syntax element indicates that the signs of block vector differences are not obtained based on the block vector predictor.
  • An encoding method comprises : obtaining a block vector predictor and a block vector for an image block so that absolute values of block vector components are equal and absolute values of block vector predictor components are equal ; encoding an absolute value of a first block vector difference component ; and encoding the image block based on the block vector components.
  • a decoding method comprises : decoding a syntax element indicating whether diagonal flipping is to be applied ; reconstructing an image block, the image block being square; and flipping the image block in a diagonal direction responsive to the syntax element indicating flipping is to be applied.
  • a decoding method comprises : decoding a syntax element indicating whether diagonal flipping is to be applied ; obtaining a residual block, the residual block being not square ; and responsive to the syntax element indicating flipping is to be applied : obtaining a prediction block of height equal to a width of the residual block and of width equal to a height of the residual block ; flipping the prediction block in a diagonal direction ; obtaining a reconstructed block based on the flipped prediction block and the residual block.
  • the diagonal direction goes from an upper left comer to a lower right comer of the image block.
  • the diagonal direction goes from goes from a lower left comer to an upper right comer of the image block.
  • the diagonal direction is indicated by another syntax element.
  • An encoding method comprises : flipping an image block in a diagonal direction to obtain a flipped image block, the image block being square; encoding a syntax element indicating diagonal flipping is to be applied on the image block ; and encoding the flipped image block.
  • An encoding method comprises : flipping an image block in a diagonal direction to obtain a flipped image block, the image block being not square ; encoding a syntax element indicating diagonal flipping is to be applied on the image block; obtaining a prediction block of the flipped image block ; obtaining a residual block based on the prediction block and the flipped image block ; flipping the residual block in the diagonal direction and encoding the flipped residual block.
  • a decoding method comprises : decoding a syntax element indicating whether rotation is to be applied ; reconstructing an image block, the image block being square; and rotating the image block according to a rotation angle responsive to the syntax element indicating rotation is to be applied.
  • a decoding method comprises : decoding a syntax element indicating whether rotation is to be applied ; obtaining a residual block, the residual block being not square ; and responsive to the syntax element indicating rotation is to be applied : obtaining a prediction block of height equal to a width of the residual block and of width equal to a height of the residual block ; rotating the prediction block according to a rotation angle ; obtaining a reconstructed block based on the rotated prediction block and the residual block.
  • the rotation angle is indicated by another syntax element.
  • An encoding method comprises : rotating an image block according to a rotation angle to obtain a rotated image block, the image block being square; encoding a syntax element indicating rotation is to be applied on the image block ; and encoding the rotated image block.
  • An encoding method comprises : rotating an image block according to a first rotation angle to obtain a rotated image block, the image block being not square ; encoding a syntax element indicating rotated is to be applied on the image block; obtaining a prediction block of the rotated image block ; obtaining a residual block based on the prediction block and the rotated image block ; rotating the residual block according to a rotation angle opposite to the first rotation angle and encoding the rotated residual block.
  • a decoding apparatus comprises one or more processors and at least one memory coupled to said one or more processors, wherein said one or more processors are configured to perform the decoding method to any one of the examples disclosed.
  • An encoding apparatus comprises one or more processors and at least one memory coupled to said one or more processors, wherein said one or more processors are configured to perform the encoding method according to any one of the examples disclosed.
  • a computer program comprises program code instructions for implementing the decoding method according to any one of the examples disclosed when executed by a processor.
  • a computer readable storage medium that has stored thereon instructions for implementing the decoding method according to any one of the examples disclosed.
  • a computer program comprises program code instructions for implementing the encoding method according to any one of the examples disclosed when executed by a processor.
  • a computer readable storage medium that has stored thereon instructions for implementing the encoding method according to any one of the examples disclosed.

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Abstract

L'invention divulgue un procédé de décodage. Un élément de syntaxe indiquant si un retournement diagonal doit être appliqué est décodé (S2202). Un bloc d'image carré est reconstruit (S2204). Le bloc d'image est retourné (S2206) dans une direction diagonale en réponse à l'indication d'un élément de syntaxe, selon laquelle un retournement doit être appliqué. L'invention divulgue également un procédé similaire pour des blocs non carrés.
PCT/EP2024/075854 2023-10-02 2024-09-17 Procédés de codage et de décodage de bloc d'image avec retournement ou rotation et appareils correspondants Pending WO2025073455A1 (fr)

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