WO2025123742A1 - Mosfet au carbure de silicium à grille multiple et son procédé de préparation, et puce - Google Patents

Mosfet au carbure de silicium à grille multiple et son procédé de préparation, et puce Download PDF

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Publication number
WO2025123742A1
WO2025123742A1 PCT/CN2024/112951 CN2024112951W WO2025123742A1 WO 2025123742 A1 WO2025123742 A1 WO 2025123742A1 CN 2024112951 W CN2024112951 W CN 2024112951W WO 2025123742 A1 WO2025123742 A1 WO 2025123742A1
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Prior art keywords
comb
silicon carbide
tooth
region
gate
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Chinese (zh)
Inventor
黄兴
谢思思
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Pn Junction Semiconductor Zhejiang Co Ltd
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Pn Junction Semiconductor Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

Definitions

  • the invention relates to a semiconductor method, and in particular to a multi-faceted gate silicon carbide MOSFET transistor and a preparation method and chip thereof.
  • Silicon carbide power devices are increasingly being used in new energy fields, such as charging piles, electric vehicles, photovoltaic inverters, energy storage, etc.
  • the existing silicon carbide MOSFET transistor structure mainly includes a planar gate structure and a trench gate structure.
  • the embodiments of the present invention provide a multi-faceted gate silicon carbide MOSFET transistor and a preparation method and chip thereof, which are compatible with the existing planar gate silicon carbide MOSFET process, are conducive to maintaining a high yield and reliability at the application end during large-scale mass production, and also have a high channel mobility.
  • a multi-faceted gate silicon carbide MOSFET transistor comprising:
  • a well region located in the silicon carbide drift region, a source region located in the well region, the semiconductor substrate, the silicon carbide drift region and the source region are of a first doping type, and the well region is of a second doping type;
  • a source electrode located on the surface of the source region
  • a gate structure located on the surface of the source region, the well region and the silicon carbide drift region, wherein a portion of the well region in contact with the gate structure serves as a channel region;
  • the gate structure includes a comb-tooth-shaped first gate structure, which is located in the source region, the corresponding well region and the silicon carbide drift region.
  • the comb-tooth length direction of the comb-tooth-shaped first gate structure is consistent with the current direction of the channel region, and the channel mobility of the channel corresponding to the comb-tooth side wall surface of the comb-tooth-shaped first gate structure is greater than the channel mobility of the channel corresponding to the comb-tooth top surface and the comb-tooth bottom surface of the comb-tooth-shaped first gate structure.
  • the side wall surface of the comb teeth is perpendicular to the substrate plane, or the side wall surface of the comb teeth is inclined to the substrate plane to form an angle.
  • the comb tooth side wall surface is silicon carbide m-face, a-face or Bevel.
  • the cross-section of the comb teeth is an inverted triangle or an inverted trapezoid.
  • the number of the comb teeth is one or more.
  • the depth of the comb teeth ranges from 0.1 micrometers to 1.5 micrometers, and the depth of the comb teeth is less than the depth of the well region.
  • it further includes a JFET current enhancement layer located in the silicon carbide drift region and adjacent to the well region, wherein the JFET current enhancement layer has a first doping type and a doping concentration greater than that of the silicon carbide drift region.
  • it also includes a lightly doped channel of the first doping type located in the channel region.
  • the embodiment of the present invention further provides a method for preparing a multi-faceted gate silicon carbide MOSFET transistor, comprising:
  • a gate structure is formed on the surface of the comb-tooth-shaped groove, and a portion of the well region contacted by the gate structure is used as a channel region.
  • the gate structure includes a comb-tooth-shaped first gate structure located in the comb-tooth-shaped groove, the comb-tooth length direction of the comb-tooth-shaped first gate structure is consistent with the current direction of the channel region, and the channel mobility of the channel region corresponding to the comb-tooth sidewall surface of the comb-tooth-shaped first gate structure is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface and the comb-tooth bottom surface of the comb-tooth-shaped first gate structure;
  • a source electrode is formed on the surface of the source region.
  • An embodiment of the present invention also provides a chip having the polyhedral gate silicon carbide MOSFET transistor.
  • Comb-tooth-shaped grooves are formed in the source region, the corresponding well region and the silicon carbide drift region of the multi-faceted gate silicon carbide MOSFET transistor, and a comb-tooth-shaped first gate structure is formed accordingly.
  • the comb-tooth-shaped first gate structure has three surfaces, namely, a comb-tooth side wall surface, a comb-tooth top surface and a comb-tooth bottom surface, which are in contact with the channel region, thereby increasing the width of the channel region.
  • the comb-tooth side wall surface is perpendicular to the existing substrate plane or forms a certain inclination angle.
  • the channel mobility of the channel region corresponding to the comb-tooth side wall surface is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface and the comb-tooth bottom surface of the comb-tooth-shaped first gate structure, thereby improving the overall comprehensive mobility.
  • the multi-faceted gate silicon carbide MOSFET transistor is compatible with the process of existing planar gate silicon carbide MOSFET transistors and has low cost.
  • FIG1 is a schematic cross-sectional structure diagram of a polyhedral gate silicon carbide MOSFET transistor along the AA′ plane according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a cross-sectional structure along the BB′ plane of a multi-faceted gate silicon carbide MOSFET transistor according to an embodiment of the present invention
  • FIG. 3 is a three-dimensional structural diagram of a polyhedral gate silicon carbide MOSFET transistor according to an embodiment of the present invention (gate structure removed);
  • FIG. 4 is a schematic diagram of a cross-sectional structure along the CC′ plane of a polyhedral gate silicon carbide MOSFET transistor according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a cross-sectional structure along the DD′ plane of a multi-faceted gate silicon carbide MOSFET transistor according to an embodiment of the present invention
  • FIG. 6 is a schematic cross-sectional structure diagram of a multi-faceted gate silicon carbide MOSFET transistor along the EE′ plane according to an embodiment of the present invention
  • FIG. 7 is a schematic cross-sectional structure diagram of a multi-faceted gate silicon carbide MOSFET transistor along the FF′ plane according to another embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional structure diagram of a polyhedral gate silicon carbide MOSFET transistor along the GG′ plane according to another embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional structure diagram of a polyhedral gate silicon carbide MOSFET transistor along the HH′ plane according to another embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional view of a multi-faceted gate silicon carbide MOSFET transistor according to another embodiment of the present invention.
  • FIG. 11 is a schematic diagram of a cross-sectional structure along plane II′ of a multi-faceted gate silicon carbide MOSFET transistor according to another embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a cross-sectional structure along the JJ′ plane of a polyhedral gate silicon carbide MOSFET transistor according to another embodiment of the present invention.
  • FIG. 13 is a diagram of a multi-faceted gate silicon carbide MOSFET transistor along the KK′ plane according to another embodiment of the present invention. Schematic diagram of the cross-section structure.
  • Figures 1 to 6 are schematic diagrams of the structure of a multi-faceted gate silicon carbide MOSFET transistor according to an embodiment of the present invention
  • Figure 1 is a schematic diagram of the cross-sectional structure of the multi-faceted gate silicon carbide MOSFET transistor along the AA′ plane according to an embodiment of the present invention
  • Figure 2 is a schematic diagram of the cross-sectional structure of the multi-faceted gate silicon carbide MOSFET transistor along the BB′ plane according to an embodiment of the present invention
  • Figure 3 is a three-dimensional structural diagram of the multi-faceted gate silicon carbide MOSFET transistor according to an embodiment of the present invention (without the gate structure)
  • Figure 4 is a schematic diagram of the cross-sectional structure of the multi-faceted gate silicon carbide MOSFET transistor along the CC′ plane according to an embodiment of the present invention
  • Figure 5 is a schematic diagram of the cross-sectional structure of the multi-faceted gate silicon carbide MOSFET transistor along the DD′ plane according to an embodiment of the present invention
  • Figure 6 is a schematic diagram
  • a well region 40 located in the silicon carbide drift region 20, a source region 50 located in the well region 40, the semiconductor substrate 10, the silicon carbide drift region 20 and the source region 50 are of a first doping type, and the well region 40 is of a second doping type;
  • a gate structure 60 located on the surface of the source region 50, the well region 40 and the silicon carbide drift region 20, wherein a portion of the well region contacted by the gate structure 60 serves as a channel region 55;
  • the gate structure 60 includes a comb-tooth-shaped first gate structure 65, which is located in the source region 50, the corresponding well region 40 and the silicon carbide drift region 20, and the comb-tooth length direction of the comb-tooth-shaped first gate structure 65 is consistent with the current direction of the channel region, and the channel mobility of the channel region corresponding to the comb-tooth side wall surface 61 of the comb-tooth-shaped first gate structure 65 is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface 63 and the comb-tooth bottom surface 62 of the comb-tooth-shaped first gate structure, wherein the comb-tooth length direction is the direction aa′.
  • the channel plane of existing planar gate SiC MOSFET transistors is perpendicular to the c-axis of 4H-SiC, and the channel mobility of this plane is low (generally less than 30cm 2 /V ⁇ s), which will bring additional conduction loss.
  • the channel of SiC MOSFET transistors with trench gate structure is parallel to the c-axis, so its mobility is higher, up to 120cm 2 /V ⁇ s.
  • Due to the large trench depth of the trench gate structure it is very difficult to etch SiC materials. It is generally difficult to etch a trench with a depth of more than 1.5um, which makes the yield of this process step a great challenge in large-scale device production.
  • a comb-tooth-shaped groove 21 is formed in the source region 50, the corresponding well region 40 and the silicon carbide drift region 20, and a comb-tooth-shaped first gate structure 65 is formed accordingly.
  • the comb-tooth-shaped first gate structure has three surfaces, namely, a comb-tooth side wall surface 61, a comb-tooth top surface 63 and a comb-tooth bottom surface 62, which are in contact with the channel region.
  • the comb-tooth top surface 63 and the comb-tooth bottom surface 62 are parallel to the existing substrate plane, and the comb-tooth side wall surface 61 is perpendicular to the existing substrate plane or forms a certain inclination angle.
  • the channel mobility of the channel region corresponding to the comb-tooth side wall surface 61 is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface 63 and the comb-tooth bottom surface 62 of the comb-tooth-shaped first gate structure.
  • the planes where the comb tooth top surface 63 and comb tooth bottom surface 62 of the multi-faceted gate silicon carbide MOSFET transistor are located are perpendicular to the c-axis of 4H-SiC, and the plane where the comb tooth side wall surface 61 is located is parallel to the c-axis of 4H-SiC.
  • the channel mobility of SiC on the substrate plane is low ( ⁇ 25 cm2 /V ⁇ s)
  • the channel mobility of the a-face and m-face in the vertical direction parallel to the c-axis of 4H-SiC is higher. (50-120 cm 2 /V ⁇ s)
  • the comprehensive mobility obtained by the multi-faceted channels of the multi-faceted gate silicon carbide MOSFET transistor of the embodiment of the present invention is higher than that of the traditional planar gate structure.
  • the embodiment of the present invention can improve the channel resistance by adjusting the ratio of the comb tooth side wall surface 61 to the comb tooth top surface 63 and the comb tooth bottom surface 62 by adjusting the depth-to-width ratio of the groove, and at the same time improve the comprehensive channel mobility of the multi-faceted gate silicon carbide MOSFET transistor of the present invention by adjusting the corresponding crystal plane of the comb tooth side wall surface 61.
  • the height of the comb teeth of the comb-toothed first gate structure 65 is less than the depth of the well region 40 but greater than the depth of the source region 50.
  • the height of the comb teeth is 0.2 microns
  • the depth of the well region is 0.8 microns
  • the depth of the source region is 0.3 microns or 0.15 microns.
  • the height of the comb teeth ranges from 0.1 micrometers to 1.5 micrometers, preferably from 0.1 micrometers to 0.5 micrometers.
  • the depth of the well region of the present invention is deeper than the bottom of the comb-tooth trench.
  • the deeper PN junction formed by the bottom of the well region and the silicon carbide drift region can effectively protect the gate oxide, reduce the high electric field formed by the gate oxide under the high voltage bias of the drain, and improve the life of the gate oxide.
  • the trench etching depth of the traditional trench gate needs to be strictly controlled, generally around 1 to 1.5um, and the depth of the channel etching needs to be deeper than the channel current at the exit of the well region, but shallower than the deep PN junction used for avalanche clamping.
  • the process difficulties faced here include: the trench gate etching process is relatively difficult, and the deep junction for clamping protection is difficult to process.
  • the process difficulty is also very high. Since the groove depth of the present invention can be controlled within 0.5 microns, as long as the aspect ratio of the groove structure is controlled to ensure sufficient side gate width, the present invention can even work at a depth of only 0.1 microns.
  • the requirements for the silicon carbide etching process are relatively low, and the process difficulty of forming a high-quality gate oxide layer in a shallow groove is also relatively low, which greatly reduces the process difficulty, is conducive to forming a high-quality gate structure, and ensures that the product has a high yield in mass production.
  • the channel current direction of the traditional trench gate MOSFET structure is perpendicular to the substrate plane and parallel to the electric field direction of the drift region, resulting in the channel region being affected by the drain induced barrier lowering (DIBL) effect when turned off, resulting in a higher channel leakage current under drain high voltage bias.
  • DIBL drain induced barrier lowering
  • the channel current direction of the present invention is still parallel to the substrate plane and perpendicular to the electric field of the drift region, resulting in the channel being less susceptible to the DIBL effect, which can greatly reduce the leakage current under high-voltage applications.
  • the height of the comb teeth of the comb-shaped first gate structure 65 is less than the depth of the well region 40 and less than the depth of the source region 50. Since it is not critical whether the trench depth is deeper than the source region, the present invention has a higher process margin for the trench etching depth.
  • the number of the comb teeth is one or more, and a suitable number of comb teeth can be reasonably set according to the width of the channel.
  • the gate structure 60 includes a comb-teeth-shaped first gate structure 65 located in the source region, the corresponding well region and the silicon carbide drift region and a second gate structure located on the surface of the comb-teeth-shaped first gate structure.
  • a cell structure includes two polyhedral gate silicon carbide MOSFET transistors, wherein after carriers come out of the channel, they need to pass through the JFET region formed by two adjacent well regions to reach the silicon carbide drift region.
  • a cell structure may also include only one polyhedral gate silicon carbide MOSFET transistor, for example, as shown in FIG. 3 .
  • the semiconductor substrate is a heavily doped silicon carbide substrate.
  • the semiconductor substrate may also be other suitable substrates, such as a silicon substrate, a diamond substrate, Aluminum nitride substrate, gallium nitride substrate, etc.
  • the polyhedral gate silicon carbide MOSFET transistor is an N-type channel MOSFET transistor, the first doping type is N-type, the second doping type is P-type, wherein the semiconductor substrate 10 is an N-type heavily doped substrate, the silicon carbide drift region 20 is an N-type lightly doped drift region, the well region 40 is a P-type lightly doped well region, and the source region 50 is an N-type heavily doped source region.
  • the polyhedral gate silicon carbide MOSFET transistor may also be a P-type channel MOSFET transistor, the first doping type is P-type, the second doping type is N-type, wherein the semiconductor substrate 10 is a P-type heavily doped substrate, the silicon carbide drift region 20 is a P-type lightly doped drift region, the well region 40 is an N-type lightly doped well region, and the source region 50 is a P-type heavily doped source region.
  • the silicon carbide MOSFET can further introduce a first doping type doping higher than that of the drift region into the JFET region to form a JFET current enhancement layer 25 .
  • the depth of the N-type doping of the JFET current enhancement layer 25 is greater than the depth of the well region, which is beneficial to the lateral diffusion of the current in the drift region.
  • the channel region of the multi-faceted gate silicon carbide MOSFET transistor can also be a lightly doped channel 45 of the first doping type. Due to the comb-shaped first gate structure, the silicon carbide channel body forms a three-sided ring gate structure, so that the gate control capability is enhanced, so that the lightly doped first doping type channel doping can still allow the device to operate in the enhancement mode (that is, if the device is an N-channel enhancement MOSFET, its threshold voltage Vth>0).
  • the threshold voltage can be adjusted by selecting gate materials with different work functions and adjusting the concentration of N-type doping in the channel.
  • FIG. 12 and FIG. 13 are schematic diagrams of structures of polyhedral gate silicon carbide MOSFET transistors according to two other embodiments of the present invention, wherein the plane where the comb-tooth sidewall surface 61 is located is The inclined surface is inclined at an angle of 54.7° with the substrate plane.
  • the channel mobility corresponding to the inclined surface is higher, so the comprehensive mobility of the multi-faceted gate silicon carbide MOSFET transistor is higher.
  • the cross-sectional shape of the comb teeth is an inverted triangle, and the two side walls of the inverted triangle are The comb teeth have an inclined surface and no bottom surface.
  • the cross-sectional shape of the comb teeth is an inverted trapezoid, and the two side walls of the inverted trapezoid are
  • the comb teeth have an inclined surface, and the comb teeth have a bottom surface 62.
  • An embodiment of the present invention further provides a chip having the above-mentioned multi-faceted gate silicon carbide MOSFET transistor.
  • the embodiment of the present invention further provides a method for preparing a multi-faceted gate silicon carbide MOSFET transistor, comprising:
  • the well region is located in the silicon carbide drift region, the source region is located in the well region, the source region is of a first doping type, and the well region is of a second doping type;
  • a gate structure is formed on the surface of the comb-tooth-shaped groove, and a portion of the well region contacted by the gate structure is used as a channel region.
  • the gate structure includes a comb-tooth-shaped first gate structure located in the comb-tooth-shaped groove, the comb-tooth length direction of the comb-tooth-shaped first gate structure is consistent with the current direction of the channel region, and the channel mobility of the channel region corresponding to the comb-tooth sidewall surface of the comb-tooth-shaped first gate structure is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface and the comb-tooth bottom surface of the comb-tooth-shaped first gate structure;
  • a drain electrode is formed on the second surface of the semiconductor substrate.
  • the multi-faceted gate silicon carbide MOSFET transistor of the embodiment of the present invention is compatible with the traditional planar gate process. It only requires etching comb-shaped grooves in the gate layout direction inside the silicon carbide before forming the gate structure, and filling to form the gate structure, so the process cost is relatively low.
  • the etching process for forming the comb-shaped grooves can be prepared by using the existing silicon carbide etching process, which will not be described in detail here.

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Abstract

La présente invention concerne la technologie des semi-conducteurs, et en particulier un MOSFET au carbure de silicium à grille multiple et son procédé de préparation, et une puce. Une première structure de grille en forme de dent de peigne est formée dans une région de source, une région de puits correspondante et une région de dérive de carbure de silicium du MOSFET au carbure de silicium à grille multiple. La première structure de grille en forme de dent de peigne possède trois faces, c'est-à-dire une face de paroi latérale de dent de peigne, une face supérieure de dent de peigne et une face inférieure de dent de peigne, et les trois faces sont en contact avec une région de canal, de sorte que la largeur de la région de canal est augmentée. La face de paroi latérale de dent de peigne est perpendiculaire à un plan de substrat existant ou forme un certain angle d'inclinaison avec celle-ci, de sorte que la mobilité de canal de la région de canal correspondant à la face de paroi latérale de dent de peigne est supérieure à la mobilité de canal de la région de canal correspondant à la face supérieure de dent de peigne et à la face inférieure de dent de peigne de la première structure de grille en forme de dent de peigne, ce qui permet d'améliorer la mobilité globale d'un dispositif.
PCT/CN2024/112951 2023-12-15 2024-08-19 Mosfet au carbure de silicium à grille multiple et son procédé de préparation, et puce Pending WO2025123742A1 (fr)

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CN118471907B (zh) * 2024-07-02 2024-09-27 合肥晶合集成电路股份有限公司 半导体器件及其制备方法
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