WO2025148564A1 - Procédé et appareil de traitement de données de remplissage, et dispositif, support de stockage et programme - Google Patents

Procédé et appareil de traitement de données de remplissage, et dispositif, support de stockage et programme

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Publication number
WO2025148564A1
WO2025148564A1 PCT/CN2024/136263 CN2024136263W WO2025148564A1 WO 2025148564 A1 WO2025148564 A1 WO 2025148564A1 CN 2024136263 W CN2024136263 W CN 2024136263W WO 2025148564 A1 WO2025148564 A1 WO 2025148564A1
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WO
WIPO (PCT)
Prior art keywords
cache
data
refill
memory access
access instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/136263
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English (en)
Chinese (zh)
Inventor
陈熙
王凯帆
陈键
唐丹
包云岗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Institute of Open Source Chip
Original Assignee
Beijing Institute of Open Source Chip
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Filing date
Publication date
Application filed by Beijing Institute of Open Source Chip filed Critical Beijing Institute of Open Source Chip
Publication of WO2025148564A1 publication Critical patent/WO2025148564A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of computer technology, and in particular to a method, device, electronic device, computer-readable storage medium and computer program for processing refill data.
  • Modern processors generally have three levels of cache: L1 cache, L2 cache and L3 cache.
  • L1 cache When the processor's memory access instruction misses the L1 cache, L2 cache needs to refill the data requested by the memory access instruction into the L1 cache to ensure normal data access.
  • L3 cache when the memory access instruction misses the L2 cache, L3 cache needs to refill the requested data into the L2 cache.
  • the upper-level cache first selects a data block (data is used to represent the location where data is stored) and releases the old data in it, and then writes the refill data into the data block when the lower-level cache sends the refill data to realize data refill.
  • Embodiments of the present application provide a method, device, electronic device, computer-readable storage medium, and computer program for processing refill data to solve problems in related technologies.
  • an embodiment of the present application provides a method for processing refill data, the method comprising:
  • the memory access instruction is suspended, and a fetch request is sent to a second cache through the first cache;
  • the second cache is a lower-level cache of the first cache;
  • the target data block is determined from the first cache, the old data stored in the target data block is released, and the refill data is written into the target data block.
  • an embodiment of the present application provides a device for processing refill data, the device comprising:
  • An acquisition module configured to acquire a hit result of a memory access instruction in the first cache when a memory access instruction of the processor is acquired through the first cache;
  • a miss module configured to suspend the memory access instruction if the hit result is a miss, and send a fetch request to a second cache through the first cache;
  • the second cache is a lower-level cache of the first cache;
  • a write module is used to determine a target data block from the first cache, release old data stored in the target data block, and write the refill data into the target data block when receiving the refill data sent by the second cache in response to the acquisition request through the first cache.
  • an embodiment of the present application further provides an electronic device, including a processor
  • a memory for storing instructions executable by the processor
  • the processor is configured to execute the instructions to implement the method of the first aspect.
  • an embodiment of the present application further provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method of the first aspect.
  • an embodiment of the present application provides a computer program, comprising a computer-readable code, which, when executed on a computing processing device, causes the computing processing device to execute the method of the first aspect.
  • the data block when a memory access instruction misses in the first cache, the data block is not selected for release first, but the subordinate second cache is notified to obtain the refill data required for the memory access request, and when the second cache obtains the refill data and sends the refill data to the first cache, the target data block is determined from the first cache, and the old data stored in the target data block is released, and the refill data is written into the target data block.
  • the data block storing the old data operates normally, is not vacant or occupied, and the old data can also be accessed normally.
  • the present application releases the old data stored in the selected target data block, which also ensures the normal implementation of the old data reading process of the memory access instruction during this period.
  • FIG1 is an architecture diagram of an implementation scenario provided by an embodiment of the present application.
  • FIG2 is a flowchart of a method for processing refill data provided by an embodiment of the present application.
  • FIG3 is a schematic diagram of the architecture of a first cache provided by an embodiment of the present invention.
  • FIG4 is a flowchart of specific steps of a method for processing refill data provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of another architecture of a first cache provided by an embodiment of the present invention.
  • FIG6 is a block diagram of a device for processing refill data provided by an embodiment of the present application.
  • FIG8 schematically shows a storage unit for holding or carrying a program code for implementing the method according to the present application
  • FIG. 9 is a block diagram of an electronic device provided in an embodiment of the present application.
  • first, second, etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first”, “second”, etc. are generally a class, and the number of objects is not limited.
  • the first object can be one or more.
  • the term “and/or” in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and/or B can be represented: A exists alone, A and B exist at the same time, and B exists alone.
  • the character "/" generally indicates that the front and back associated objects are a kind of "or” relationship.
  • the term “multiple” refers to two or more, and other quantifiers are similar.
  • FIG. 1 is an implementation scenario architecture diagram provided by an embodiment of the present application.
  • the common architecture is the three-level cache structure of Figure 1, including: Level 1 cache L1, Level 2 cache L2 and Level 3 cache L3.
  • Level 1 cache L1 is the cache closest to the processor, with the smallest capacity and the fastest speed;
  • Level 2 cache L2 has a larger capacity, but is slower than Level 1 cache L1.
  • Level 2 cache L2 is the buffer of Level 1 cache L1.
  • the function of Level 2 cache L2 is to store data that is needed for processor processing but cannot be stored by Level 1 cache L1;
  • Level 3 cache L3 has the largest capacity and is also the slowest level.
  • Level 3 cache L3 and memory can be regarded as buffers of Level 2 cache L2.
  • the processor When the processor is running, the processor will first go to the first-level cache L1 to find the required data according to the memory access instruction, then go to the second-level cache L2, and then go to the third-level cache L3. If the third-level cache does not find the data it needs, it will get the data from the memory. The longer the search path, the longer it takes, so if you need to get certain data very frequently, make sure that the data is in the first-level cache L1, so that the speed will be very fast.
  • the memory access instruction is an instruction to get data from a specified address in the memory, or to store data at a specified address in the memory.
  • the memory access instruction will continue to be searched whether it hits in the second-level cache L2. If it hits in the second-level cache L2, the second-level cache L2 will refill the data requested to be read by the memory access instruction into the first-level cache L1; if it does not hit in the second-level cache L2, the memory access instruction will continue to be searched whether it hits in the third-level cache L3. If it hits in the third-level cache L3, the third-level cache L3 will refill the data requested to be read by the memory access instruction into the second-level cache L2, and then the second-level cache L2 will refill the data into the first-level cache L1.
  • the related technology is that when the first cache notifies the lower-level second cache to refill data, it selects a data block in the first cache to release the old data therein, and when the lower-level cache sends the refill data, the refill data is written into the data block to achieve data refill. This will cause the vacant data block to be continuously occupied during the waiting process for the refill data. In addition, if there is a need to access the old data during this process, it cannot be successfully accessed because the old data has been released.
  • the embodiment of the present application may not select a data block for release when the memory access instruction does not hit the first cache, but instead notify the subordinate second cache to obtain the refill data required for the memory access request, wait for the second cache to obtain the refill data and send the refill data to the first cache, and then determine the target data block from the first cache, release the old data stored in the target data block, and write the refill data to the target data block.
  • the data block storing the old data operates normally and is not vacant or occupied, and the old data can also be accessed normally.
  • the present application releases the old data stored in the selected target data block and writes the refill data to the target data block, which also ensures the normal implementation of the old data reading process of the memory access instruction during this period.
  • FIG. 2 is a flowchart of a method for processing refill data provided by an embodiment of the present application. As shown in FIG. 2 , the method may include:
  • Step 101 when a memory access instruction of a processor is obtained through a first cache, a hit result of the memory access instruction in the first cache is obtained.
  • the process of determining whether the data exists can be understood as determining the hit result of the memory access instruction in the first cache.
  • the hit result includes a hit or a miss.
  • a hit represents that the first cache contains the data requested to be read by the memory access instruction; a miss represents that the first cache does not contain the data requested to be read by the memory access instruction.
  • FIG. 3 shows a schematic diagram of the architecture of the first cache.
  • the first cache can adopt a 5-level pipeline architecture, that is, it includes a pipeline queue with 5 sequentially arranged data bits, each data bit corresponds to a pipeline moment, and different data bits correspond to different pipeline moments.
  • the instruction is used to enter the pipeline from the initial data bit S1 of the pipeline queue, and change the data bit with the migration of time.
  • the embodiment of the present application can obtain the hit result of the memory access instruction in the first cache (obtain the hit result at the moment corresponding to the S3 data bit) after the memory access instruction enters the pipeline from the starting data bit (S1) of the pipeline queue, after a fixed number of data bits (for example, 2 data bits are separated). Since the hit result is obtained, and the hit result includes a hit or a miss. Therefore, the embodiment of the present application can subsequently perform corresponding instruction control operations according to the hit result.
  • the interval of a fixed number of data bits refers to the time required for the execution of the operation of waiting to determine the hit result of the memory access instruction in the first cache. Since the time length is fixed, and the data bits in the pipeline queue of the first cache represent the moment, the time length can be converted into a fixed number of data bits. Starting from the starting data bit (S1), a fixed number of data bits are spaced to represent the completion of the execution process of waiting to determine whether a hit is achieved after the memory access instruction enters the pipeline of the first cache, thereby obtaining the hit result of the memory access instruction in the first cache.
  • Step 102 If the hit result is a miss, the memory access instruction is suspended, and a fetch request is sent to a second cache through the first cache; the second cache is a lower-level cache of the first cache.
  • the hit result of the memory access instruction in the first cache is a hit, indicating that the first cache has the data requested to be read by the memory access instruction. If the first cache also has a superior third cache, the first cache can refill the data requested to be read by the memory access instruction into the third cache; if the first cache does not have a superior third cache, the processor can read data directly from the first cache through the memory access instruction.
  • the hit result of the memory access instruction in the first cache is a miss, indicating that the first cache does not store the data requested to be read by the memory access instruction.
  • the second cache is a lower-level cache of the first cache.
  • first-level cache L1, second-level cache L2 and third-level cache L3 assuming that the first cache is first-level cache L1, then the second-level cache can be second-level cache L2; assuming that the first cache is second-level cache L2, then the second-level cache can be third-level cache L3.
  • miss status register is a register used to record each unfinished transaction, and the recorded information includes the invalid address, keyword information, and unfinished execution instructions.
  • Step 103 When the first cache receives the refill data sent by the second cache in response to the acquisition request, determine the target data block from the first cache, release the old data stored in the target data block, and write the refill data into the target data block.
  • the process in which the second cache responds to the acquisition request to search and obtain the refill data and send it to the first cache usually takes a long time (it takes dozens to hundreds of data bits in the pipeline of the first cache).
  • the embodiment of the present application does not release or occupy the data block containing the old data, thereby improving the utilization rate of the cache resources while ensuring that the old data can be accessed normally.
  • the target data block is selected only when the refill data sent by the second cache is received through the first cache. If the target data block stores old data, the old data is released and the refill data is written into the target data block. In this way, during the period before the refill data arrives, the data block storing the old data in the first cache can operate normally and is not vacant or occupied, and the old data can also be accessed normally. After the first cache receives the refill data, the old data stored in the selected target data block is released, and the refill data is written into the target data block, which also ensures the normal implementation of the data reading process of the memory access instruction.
  • the data block when a memory access instruction does not hit in the first cache, the data block is not selected for release first, but the subordinate second cache is notified to obtain the refill data required for the memory access request, and waits for the second cache to obtain the refill data and send the refill data to the first cache, and then the target data block is determined from the first cache, and the old data stored in the target data block is released, and the refill data is written into the target data block.
  • the data block storing the old data operates normally and is not vacant or occupied, and the old data can also be accessed normally.
  • the present application releases the old data stored in the selected target data block, which also ensures the normal implementation of the old data reading process of the memory access instruction during this period.
  • FIG. 4 is a flowchart of specific steps of a method for processing refill data provided by an embodiment of the present application. As shown in FIG. 4 , the method may include:
  • Step 201 When a memory access instruction of a processor is obtained through a first cache, a hit result of the memory access instruction in the first cache is obtained.
  • This step may specifically refer to the above step 101, which will not be described in detail here.
  • Step 202 If the hit result is a miss, the memory access instruction is controlled to leave the pipeline queue and enter the missing state register for suspended waiting, and at the same time, a fetch request is sent to a second cache through the first cache; the second cache is a lower-level cache of the first cache.
  • the hit result of the memory access instruction in the first cache is a miss, indicating that the data requested to be read by the memory access instruction is not stored in the first cache.
  • the memory access instruction can be removed from the pipeline queue of the first cache and enter an allocated miss status register (MSHR) for waiting.
  • MSHR miss status register
  • the miss status register is a register used to record each unfinished transaction.
  • the memory access instruction is separated from the pipeline queue of the first cache because the data requested by the memory access instruction is not stored in the first cache, which causes the memory access instruction to currently fail to realize data reading. Therefore, the memory access instruction is first separated from the pipeline queue of the first cache and enters the missing status register to wait, so as to avoid interfering with the execution of other requests of the first cache. After waiting for the lower-level second cache to send the data requested by the memory access instruction to the first cache, the data requested by the memory access instruction has been obtained by the first cache. Then, the memory access instruction in the missing status register can enter the pipeline queue of the first cache again, so as to correctly read the data in the first cache.
  • Step 203 When the refill data sent by the second cache in response to the acquisition request is received through the first cache, the first cache directory is read starting from the starting data bit of the pipeline queue of the first cache, and after an interval of a first number of data bits, the target data block is determined from the first cache according to the first cache directory.
  • FIG5 is a first cache processing process connected to FIG3.
  • the memory access instruction can enter the pipeline from the starting data bit (S1 data bit) of the pipeline queue of the first cache, and read the first cache directory from the starting data bit (S1 data bit).
  • the first cache directory is a data that represents the directory of data stored in the first cache. By reading the first cache directory, a target data block can be determined from the first cache to release and store the refill data.
  • step 203 may specifically include sub-steps 2031-2032:
  • Sub-step 2031 According to the first cache directory, obtain the last access time of each data block in the first cache.
  • Sub-step 2032 taking the data block with the earliest last access time as the target data block.
  • the first cache directory records the last access time of each data block in the first cache.
  • the embodiment of the present application can obtain the last access time of each data block in the first cache based on the first cache directory, and use the data block with the earliest last access time as the target data block.
  • the data block with the earliest last access time indicates that the data stored in the data block is the least active. Therefore, by using the data block with the earliest last access time as the target data block, the impact on the more active data in other data blocks can be minimized.
  • Sub-step 2034 when it is determined that the storage status is: there is no free data block in the first cache that can store the refill data, determine a target data block from the first cache.
  • the storage status of the first cache can be first detected. If the storage status is that there are free data blocks in the first cache that can store the refill data, the free data blocks are directly used as the target data blocks. However, when a capacity conflict occurs in the first cache (there are no free data blocks in the first cache that can store the refill data), it is necessary to determine the target data block from the first cache through the method of the above embodiment, release the old data in the target data block to make it a free data block, and write the refill data into the free target data block.
  • Step 204 Write the refill data into the refill buffer area of the first cache.
  • Step 205 read the refill buffer area at the data bit after the starting data bit, and read the refill data after an interval of a second number of data bits, write the read refill data into the write buffer area of the first cache, and read the old data in the target data block.
  • the operation of reading and refilling the buffer area is started at the next data bit (S2 data bit) of the starting data bit (S1 data bit) of the pipeline queue of the first cache. Since it takes a fixed time for the first cache to read the refill cache area from the beginning to read the refill data (corresponding to the pipeline, it takes a time corresponding to 1 data bit), the refill data can be read at the S3 data bit after an interval of the second number of data bits (an interval of 1 data bit).
  • Step 206 After a third number of data bits have been left, the old data obtained by reading is stored in the second cache, thereby completing the release of the target data block.
  • the first cache also synchronously starts the operation of reading the old data in the target data block in the S3 data bit of the pipeline queue of the first cache. Since it takes a fixed time for the first cache to read the target data block from the beginning to read the old data therein (corresponding to the pipeline, it takes a time corresponding to 2 data bits), after an interval of the third number of data bits (an interval of 2 data bits), the old data in the target data block can be read at the S5 data bit of the pipeline queue of the first cache. At this time, the old data is read out from the target data block.
  • the S5 data bit of the pipeline queue of the first cache can also send the read old data to the second cache to complete the release of the target data block.
  • the first cache still needs to obtain data from the second cache and refill the first cache according to steps 201 to 207 to meet the read instruction's requirement to read the old data.
  • Step 207 When it is detected that the operation of reading the target data block is completed, write the refill data in the write buffer area into the target data block.
  • the function of the write buffer area is to determine whether to write the refill data into the target data block according to the judgment of the read operation performed on the target data block. Specifically, the embodiment of the present application sets a higher priority for the operation of reading the target data block, so the write buffer needs to wait until all the read operations on the target data block are completed before starting the operation of writing the refill data in the write buffer area into the target data block. That is, when the write buffer area determines that all the read operations performed on the target data block are completed, the write buffer area executes the operation of writing the refill data in the write buffer area into the target data block, thereby completing the operation of storing the refill data into the first cache storage unit.
  • the method may further include:
  • Step 208 When the first address carried in the read request received by the first cache matches the second address of the target refill data in the write buffer area, return the target refill data as a response to the read request.
  • the target refill data in the write buffer area can be directly returned as a response to the read request.
  • the first address carried by the read request received by the first cache matches the second address of the target refill data in the write buffer area, it is determined that the data requested to be read by the read request is the target refill data in the refill buffer area.
  • the missing status register can establish two tasks.
  • the first task is used to implement the first cache obtaining refill data from the second cache during the above embodiment;
  • the second task is used to implement the target data block, release the target data block, write the refill data to the target data block, and continue to refill the refill data to the superior cache during the above embodiment.
  • the method may further include:
  • Step 209 After writing the refill data into the target data block, extract the memory access instruction from the missing status register, write the refill data into the third cache, and wake up the operation of reading data from the third cache through the memory access instruction.
  • the third cache is an upper-level cache of the first cache; and the memory access instruction misses in the third cache.
  • the memory access instruction when the first cache does not have a third cache of the upper level, can directly obtain the refill data from the first cache and feed it back to the processor.
  • the first cache after writing the refill data into the target data block, the first cache also needs to extract the memory access instruction from the missing status register, write the refill data into the third cache, and wake up the operation of reading data from the third cache through the memory access instruction, that is, the memory access instruction is to first access the upper cache, if the access to the upper cache does not hit, then access the data of the lower cache for data access, so when the memory access instruction does not hit in the upper third cache, after the lower second cache writes the refill data into the first cache of the current level, the first cache also needs to refill the refill data into the upper third cache, and when the third cache has no upper cache, the operation of reading data from the third cache through the memory access instruction can be awakened, and the awakened memory access instruction can directly obtain the refill data from the third
  • step 209 may specifically include sub-steps 2091-2092:
  • Sub-step 2091 Control the memory access instruction to enter the pipeline queue of the first cache from the starting data bit, and at the same time generate a wake-up instruction through the first cache and send it to the third cache through the wake-up queue.
  • Sub-step 2092 after spacing out the second number of data bits in the pipeline queue, obtain refill data through the first cache, and issue the memory access instruction as a refill instruction from the refill queue to the third cache.
  • the wake-up instruction is used to wake up the operation of reading data from the third cache through the memory access instruction; and the refill instruction is used to write the refill data into the third cache for reading by the memory access instruction.
  • the hit result is a miss, indicating that the data requested to be read by the memory access instruction is not stored in the first cache. At this time, it is necessary to check whether the data is stored in the lower-level second cache. If the data is stored in the second cache, the second cache is allowed to refill the data into the first cache for reading by the memory access instruction.
  • the memory access instruction is controlled to re-enter the pipeline queue from the starting data bit, and at the same time, a wake-up instruction is generated through the first cache and issued by the wake-up queue to the upper third cache (the moment of entering the wake-up queue and issuing the wake-up instruction is the moment corresponding to the data bit S1); and after an interval of the second number of data bits (an interval of 2 data bits), the refill data is obtained through the first cache, and the memory access instruction is issued from the refill queue to the third cache as a refill instruction.
  • the actual sending time of the wake-up request is the moment corresponding to data bit S1. Since the refill request has to wait in the refill queue for the length of time represented by a data bit (ensuring that the refill request at the exit of the refill queue is issued in time to reduce the probability of congestion in the refill queue), the actual sending time of the refill request is the moment corresponding to data bit S4. It can be seen that the embodiment of the present application can ensure that for each refill request, a wake-up request is issued three data bits in advance.
  • the embodiment of the present application realizes the management of memory access instructions through the concise and clear multi-level pipeline queue architecture of the first cache. Based on the pipeline queue, it is designed to obtain the hit result of the memory access instruction and send a wake-up request at a fixed data bit, and to obtain the refill data at another fixed data bit and send the refill request through the refill queue; based on the pipeline queue architecture and the design of each processing time of the instruction in the pipeline, it can achieve accurate and stable control of the fixed advance amount of the wake-up request, ensuring the accuracy and coverage of the memory access instruction reading process.
  • the whole process does not need to read the status of the pipeline requests at each level, and the real-time calculation of the advance issuance time based on the status of the refill queue request, so the complexity is extremely low, reducing the cost and power consumption of the circuit.
  • the method may further include:
  • Step 210 If the hit result is a hit, read the data in the data block hit by the memory access instruction in the first cache and return it.
  • the hit result of the memory access instruction in the first cache is a hit, indicating that the first cache has the data requested to be read by the memory access instruction. If the first cache also has a third cache of an upper level, the first cache can refill the data requested to be read by the memory access instruction into the third cache; if the first cache does not have a third cache of an upper level, the processor can read data directly from the first cache through the memory access instruction.
  • the data block when a memory access instruction misses in the first cache, the data block is not selected for release first, but the subordinate second cache is notified to obtain the refill data required for the memory access request, and when the second cache obtains the refill data and sends the refill data to the first cache, the target data block is determined from the first cache, and the old data stored in the target data block is released, and the refill data is written into the target data block.
  • the data block storing the old data operates normally, is not vacant or occupied, and the old data can also be accessed normally.
  • the present application releases the old data stored in the selected target data block, which also ensures the normal implementation of the old data reading process of the memory access instruction during this period.
  • FIG6 is a block diagram of a device for processing refill data provided by an embodiment of the present application, the device comprising:
  • the acquisition module 301 is used to acquire a hit result of the memory access instruction in the first cache when the memory access instruction of the processor is acquired through the first cache;
  • the write module 303 is used to determine the target data block from the first cache, release the old data stored in the target data block, and write the refill data into the target data block when receiving the refill data sent by the second cache in response to the acquisition request through the first cache.
  • the writing module 303 includes:
  • the determination submodule is used to read the first cache directory starting from the start data bit of the pipeline queue of the first cache, and determine the target data block from the first cache according to the first cache directory after an interval of a first number of data bits.
  • the writing module 303 includes:
  • a first writing submodule used for writing the refill data into a refill buffer area of the first cache
  • a processing submodule configured to read the refill buffer area at a data bit following the start data bit, and read the refill data after a second number of data bits, write the read refill data into the write buffer area of the first cache, and read old data in the target data block;
  • the data block when a memory access instruction misses in the first cache, the data block is not selected for release first, but the subordinate second cache is notified to obtain the refill data required for the memory access request, and when the second cache obtains the refill data and sends the refill data to the first cache, the target data block is determined from the first cache, and the old data stored in the target data block is released, and the refill data is written into the target data block.
  • the data block storing the old data operates normally, is not vacant or occupied, and the old data can also be accessed normally.
  • the present application releases the old data stored in the selected target data block, which also ensures the normal implementation of the old data reading process of the memory access instruction during this period.
  • These computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards, or floppy disks. Such computer program products are generally portable or fixed storage units as described with reference to FIG. 8.
  • the storage unit can have storage segments, storage spaces, etc. arranged similarly to the memory 1020 in the computing processing device of FIG. 7.
  • the program code can be compressed, for example, in an appropriate form.
  • the storage unit includes computer readable code 1031', i.e., code that can be read by a processor such as 1010, which, when executed by a computing processing device, causes the computing processing device to perform the various steps in the method described above.
  • the electronic device includes: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the processing method of refilling data in the above-mentioned embodiment.
  • the processor may be a CPU (Central Processing Unit), a general processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof.
  • the processor may also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.
  • the communication bus may include a path for transmitting information between the memory and the communication interface.
  • the communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc.
  • the communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one line is used in FIG9 , but it does not mean that there is only one bus or one type of bus.
  • the memory can be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access) or other types of dynamic storage devices that can store information and instructions, or it can be EEPROM (Electrically Erasable Programmable Read Only), CD-ROM (Compact Disa Read Only), magnetic tape, floppy disk and optical data storage device, etc.
  • ROM Read Only Memory
  • RAM Random Access
  • EEPROM Electrically Erasable Programmable Read Only
  • CD-ROM Compact Disa Read Only
  • magnetic tape magnetic tape
  • floppy disk and optical data storage device etc.
  • references to "one embodiment,” “embodiment,” or “one or more embodiments” herein mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present application.
  • examples of the term “in one embodiment” herein do not necessarily all refer to the same embodiment.
  • any reference signs placed between brackets shall not be construed as limiting the claims.
  • the word “comprising” does not exclude the presence of elements or steps not listed in the claims.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the present application may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware.
  • the use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

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  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

La présente demande propose un procédé et un appareil de traitement de données de remplissage, ainsi qu'un dispositif électronique, un support de stockage lisible par ordinateur et un programme informatique. Le procédé comprend les étapes consistant à : lorsqu'une instruction d'accès à la mémoire d'un processeur est acquise au moyen d'une première mémoire cache, acquérir un résultat de coïncidence de l'instruction d'accès à la mémoire dans la première mémoire cache si le résultat de coïncidence est que l'instruction d'accès à la mémoire n'est pas une coïncidence, suspendre l'instruction d'accès à la mémoire et envoyer une demande d'acquisition à une deuxième mémoire cache au moyen de la première mémoire cache en même temps ; et lors de la réception, au moyen de la première mémoire cache, de données de remplissage envoyées par la deuxième mémoire cache en réponse à la demande d'acquisition, déterminer un bloc de données cible à partir de la première mémoire cache, libérer des anciennes données stockées dans le bloc de données cible, et écrire les données de remplissage dans le bloc de données cible. Dans la présente demande, après réception de données de remplissage, une première mémoire cache libère des anciennes données stockées dans un bloc de données cible sélectionné, ce qui permet d'assurer la mise en œuvre normale du processus de lecture des anciennes données par une instruction d'accès à la mémoire pendant cette période.
PCT/CN2024/136263 2024-01-12 2024-12-03 Procédé et appareil de traitement de données de remplissage, et dispositif, support de stockage et programme Pending WO2025148564A1 (fr)

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