WO2025155121A1 - Procédé et dispositif de codage et de décodage de données dans un système de communication ou de diffusion - Google Patents

Procédé et dispositif de codage et de décodage de données dans un système de communication ou de diffusion

Info

Publication number
WO2025155121A1
WO2025155121A1 PCT/KR2025/000983 KR2025000983W WO2025155121A1 WO 2025155121 A1 WO2025155121 A1 WO 2025155121A1 KR 2025000983 W KR2025000983 W KR 2025000983W WO 2025155121 A1 WO2025155121 A1 WO 2025155121A1
Authority
WO
WIPO (PCT)
Prior art keywords
matrix
basic
parity check
bits
ldpc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/KR2025/000983
Other languages
English (en)
Korean (ko)
Inventor
명세호
장민
이동훈
한동화
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020240026737A external-priority patent/KR20250113863A/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of WO2025155121A1 publication Critical patent/WO2025155121A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector

Definitions

  • the present disclosure relates to a method and device for encoding and decoding data in a communication or broadcasting system.
  • the maximum transmission speed in the 6G communication system which is expected to be realized around 2030, is tera (i.e., 1,000 giga) bps (bits per second), and the wireless delay time is 100 microseconds ( ⁇ sec).
  • the transmission speed in the 6G communication system is 50 times faster than that of the 5G communication system, and the wireless delay time is reduced to one-tenth.
  • terahertz e.g., from 95 gigahertz (GHz) to 3 terahertz (THz) band.
  • GHz gigahertz
  • mmWave millimeter wave
  • the terahertz band is expected to have more serious path loss and atmospheric absorption phenomena, and thus the importance of technologies that can guarantee signal reach, or coverage, is expected to increase.
  • RF Radio Frequency
  • antennas new waveforms that are better than OFDM (Orthogonal Frequency Division Multiplexing) in terms of coverage, beamforming, and multiple antenna transmission technologies such as massive Multiple-Input and Multiple-Output (MIMO), Full Dimensional MIMO (FD-MIMO), array antennas, and large scale antennas.
  • MIMO massive Multiple-Input and Multiple-Output
  • FD-MIMO Full Dimensional MIMO
  • array antennas and large scale antennas.
  • new technologies such as metamaterial-based lenses and antennas, high-dimensional spatial multiplexing technology using Orbital Angular Momentum (OAM), and Reconfigurable Intelligent Surfaces (RIS) are being discussed to improve the coverage of terahertz band signals.
  • OFDM Orthogonal Frequency Division Multiplexing
  • FD-MIMO Full Dimensional MIMO
  • RIS Reconfigurable Intelligent Surfaces
  • 6G communication systems are being developed with full duplex technology that utilizes the same frequency resources at the same time for uplink and downlink, network technology that comprehensively utilizes satellites and HAPS (High-Altitude Platform Stations), network structure innovation technology that supports mobile base stations and enables optimization and automation of network operation, dynamic spectrum sharing technology through collision avoidance based on spectrum usage prediction, AI-based communication technology that utilizes AI (Artificial Intelligence) from the design stage and internalizes end-to-end AI support functions to realize system optimization, and next-generation distributed computing technology that realizes services with complexity that exceeds the limits of terminal computing capabilities by utilizing ultra-high-performance communication and computing resources (Mobile Edge Computing (MEC), cloud, etc.).
  • AI Artificial Intelligence
  • MEC Mobile Edge Computing
  • 6G communication systems are expected to enable the next hyper-connected experience through the hyper-connectivity of 6G communication systems that include not only connections between things but also connections between people and things.
  • 6G communication systems are expected to enable the provision of services such as truly immersive eXtended Reality (XR), high-fidelity mobile holograms, and digital replicas.
  • services such as remote surgery, industrial automation, and emergency response through enhanced security and reliability will be provided through 6G communication systems, which will be applied in various fields such as industry, medicine, automobiles, and home appliances.
  • the present disclosure provides algebraic characteristics that a parity check matrix of an LDPC (Low Density Parity Check) code must satisfy in order to reduce decoding latency and lower encoding complexity.
  • LDPC Low Density Parity Check
  • an efficient encoding and decoding method and device using an LDPC code having the algebraic characteristics are provided.
  • the present disclosure provides algebraic characteristics that a parity check matrix of an LDPC code must satisfy in order to reduce the Block Error Rate (BLER) or block error probability.
  • BLER Block Error Rate
  • an efficient encoding and decoding method and device using an LDPC code having the algebraic characteristics are provided.
  • the present disclosure provides algebraic characteristics that a parity check matrix of an LDPC code must satisfy by appropriately combining the above algebraic characteristics to simultaneously reduce decoding latency, encoding complexity and BLER.
  • an efficient encoding and decoding method and device using an LDPC code having the combined algebraic characteristics are provided.
  • the present disclosure provides a method for variably applying puncturing of LDPC encoded bits to support a trade-off between encoding performance and decoding latency.
  • an efficient encoding and decoding method and device supporting the variable puncturing method are provided.
  • a data transmission method of a base station or a terminal may include a step of LDPC encoding data bits based on a basic matrix and/or a parity check matrix, a step of applying rate matching to the encoded bits, a step of modulating the rate-matched encoded bits, and a step of transmitting the modulated signal through a transmission device, wherein, depending on a setting of the system, the encoded bits are variably applied so that some of the data bits are not included or are included.
  • a data receiving method of a base station or a terminal may include the steps of receiving a modulated signal corresponding to at least a part of encoded bits through a receiving device, performing demodulation to determine values for decoding based on the received signal, performing LDPC decoding based on the determined values and a base matrix and/or a parity check matrix, appropriately applying rate dematching to the LDPC decoded result, and determining data bits from the rate dematched result, wherein the encoding bits are variably applied so that some of the data bits are not included or included depending on a setting of the system.
  • the method comprises the steps of: determining a number of input bits; determining a fundamental matrix based on the number of input bits; determining a lifting size (Z) based on at least one of the number of input bits or the fundamental matrix; determining a parity check matrix based on at least one of the fundamental matrix or the lifting size (Z); performing encoding based on the parity check matrix and the input bits to determine encoded bits; and transmitting at least a portion of the encoded bits to a receiver, wherein when a first setting is indicated, input bits of a first length among the input bits are not included in the encoded bits, and when a second setting is indicated, input bits of a second length among the input bits are not included in the encoded bits, and the second length is 0 or less than the first length.
  • a method performed by a receiver in a communication system comprising the steps of: receiving a signal corresponding to at least a portion of coding bits; determining a number of input bits based on the signal; determining a fundamental matrix based on the number of input bits; determining a lifting size (Z) based on at least one of the number of input bits or the fundamental matrix; determining a parity check matrix based on at least one of the fundamental matrix or the lifting size (Z); and performing decoding of the signal based on the parity check matrix, wherein when a first setting is indicated, an input bit of a first length among the input bits is not included in the coding bits, and when a second setting is indicated, an input bit of a second length among the input bits is not included in the coding bits, and the second length is 0 or less than the first length.
  • a transmitter comprises: a transmitting unit; and a control unit connected to the transmitting unit, wherein the control unit determines a number of input bits, determines a basic matrix based on the number of the input bits, determines a lifting size (Z) based on at least one of the number of input bits or the basic matrix, determines a parity check matrix based on at least one of the basic matrix or the lifting size (Z), performs encoding based on the parity check matrix and the input bits to determine encoded bits, and transmits at least a portion of the encoded bits to a receiver, wherein when a first setting is indicated, an input bit of a first length among the input bits is not included in the encoded bits, and when a second setting is indicated, an input bit of a second length among the input bits is not included in the encoded bits, and the second length is 0 or less than the first length.
  • a receiver comprises: a receiving unit; and a control unit connected to the transmitting unit, wherein the control unit receives a signal corresponding to at least a portion of coding bits, determines a number of input bits based on the signal, determines a basic matrix based on the number of input bits, determines a lifting size (Z) based on at least one of the number of input bits or the basic matrix, determines a parity check matrix based on at least one of the basic matrix or the lifting size (Z), and performs decoding of the signal based on the parity check matrix, wherein when a first setting is indicated, an input bit of a first length among the input bits is not included in the coding bits, and when a second setting is indicated, an input bit of a second length among the input bits is not included in the coding bits, and the second length is 0 or less than the first length.
  • the method comprises the steps of: determining a number of input bits; determining a basic matrix; determining a lifting size (Z) based on at least one of the number of input bits or the basic matrix; determining a parity check matrix based on at least one of the basic matrix or the lifting size (Z); performing encoding based on the parity check matrix and the input bits to determine encoded bits; and wherein the basic matrix is one of a plurality of basic matrices, the plurality of basic matrices have the same size, a first basic matrix and a second basic matrix included in the plurality of basic matrices have core matrices of different sizes, and the core matrix includes a submatrix corresponding to the input bits in the basic matrix and a matrix corresponding to some of the parity bits.
  • the method comprises the steps of: receiving a signal corresponding to an input bit; demodulating the signal to determine a value for decoding; checking the number of the input bits based on the signal; determining a basic matrix; determining a lifting size (Z) based on at least one of the number of input bits or the basic matrix; determining a parity check matrix based on at least one of the basic matrix or the lifting size (Z); and performing decoding based on the parity check matrix and the values, wherein the basic matrix is one of a plurality of basic matrices, the plurality of basic matrices have the same size, and a first basic matrix and a second basic matrix included in the plurality of basic matrices have core matrices of different sizes, and the core matrix includes a submatrix corresponding to the input bits in the basic matrix and a matrix corresponding to some of the parity bits.
  • a transmitter comprises: a transceiver; and a control unit connected to the transceiver, wherein the control unit determines a number of input bits, determines a basic matrix, determines a lifting size (Z) based on at least one of the number of input bits or the basic matrix, determines a parity check matrix based on at least one of the basic matrix or the lifting size (Z), and performs encoding based on the parity check matrix and the input bits to determine encoded bits, wherein the basic matrix is one of a plurality of basic matrices, the plurality of basic matrices have the same size, and a first basic matrix and a second basic matrix included in the plurality of basic matrices have core matrices of different sizes, and the core matrix includes a submatrix corresponding to the input bits in the basic matrix and a matrix corresponding to some of the parity bits.
  • a receiver comprises a transceiver; and a control unit connected to the transceiver, wherein the control unit receives a signal corresponding to an input bit, demodulates the signal to determine a value for decoding, verifies the number of the input bits based on the signal, determines a basic matrix, determines a lifting size (Z) based on at least one of the number of input bits or the basic matrix, determines a parity check matrix based on at least one of the basic matrix or the lifting size (Z), and performs decoding based on the parity check matrix and the values, wherein the basic matrix is one of a plurality of basic matrices, the plurality of basic matrices have the same size, and a first basic matrix and a second basic matrix included in the plurality of basic matrices have core matrices of different sizes, and the core matrix includes a submatrix corresponding to the input bits in the basic matrix and a matrix corresponding to
  • the present disclosure applies a method of variably applying puncturing of data bits when determining encoding bits.
  • the present disclosure can support an efficient LDPC encoding method and device by enabling a method of variably applying a method of maximizing encoding gain or minimizing decoding latency depending on a system situation.
  • Figure 1 is a diagram of a systematic LDPC codeword structure.
  • Figure 2 is a diagram illustrating a method for representing a graph of an LDPC code.
  • Figure 3a is an example diagram explaining the cycle characteristics of a QC-LDPC code.
  • Figure 3b is an example diagram explaining the cycle characteristics of a QC-LDPC code.
  • FIG. 4 is a transmission block structure diagram according to an embodiment of the present disclosure.
  • FIG. 5 is an exemplary diagram of an LDPC encoding process according to an embodiment of the present disclosure.
  • FIG. 6 is an example diagram of an LDPC decoding process according to an embodiment of the present disclosure.
  • FIG. 7 is a block diagram of a transmitter according to an embodiment of the present disclosure.
  • FIG. 8 is a block diagram of a receiving device according to an embodiment of the present disclosure.
  • FIG. 9 is a structural diagram of an LDPC decoding unit according to an embodiment of the present disclosure.
  • Figure 10 is an example diagram of the structure of a parity check matrix of an LDPC code.
  • FIG. 11a is an example diagram of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
  • FIG. 11b is an example diagram of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
  • FIG. 12a is an example diagram for explaining cycle characteristics in a submatrix of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
  • FIG. 12b is an example diagram for explaining cycle characteristics in a submatrix of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
  • FIG. 12c is an example diagram for explaining cycle characteristics in a submatrix of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
  • a communication system is a term that generally includes the meaning of a broadcasting system, but in the present disclosure, if a broadcasting service is the main service among the communication systems, it can be more clearly named as a broadcasting system.
  • LDPC Low Density Parity Check
  • LDPC codes are generally defined by a parity-check matrix and can be represented using a bipartite graph, commonly referred to as a Tanner graph.
  • LDPC codes are a type of parity-check codes, and are called 'low-density' parity-check codes because they have the characteristic that the ratio of the number of 1s (i.e., density) in the parity-check matrix for very long cases is very low. Therefore, the techniques proposed in this disclosure based on LDPC codes for convenience can be easily extended to general parity-check matrix codes.
  • Figure 1 is a diagram illustrating a systematic LDPC code structure.
  • a device performing LDPC encoding receives an information word (102) composed of K ldpc bits or symbols and performs encoding to generate a codeword (100) composed of N ldpc bits or symbols.
  • an information word (102) including K ldpc bits is received and a codeword (100) composed of N ldpc bits is generated. That is, an information word having K ldpc input bits
  • the code word (100) is generated. That is, the information word and the code word are bit strings composed of a number of bits, and the information word bit and the code word bit mean each bit that constitutes the information word and the code word.
  • N parity N ldpc - K ldpc .
  • LDPC code is a type of linear block code and includes a process of determining a codeword that satisfies the condition in mathematical expression 1 below.
  • H is a parity check matrix
  • c is a codeword
  • c i is the i-th bit of the codeword
  • N ldpc is the LDPC codeword length.
  • the parity check matrix H consists of N ldpc columns, which is the same number of bits as the LDPC codeword.
  • Mathematical expression 1 is the i-th column of the parity check matrix ( ) and the i-th code word bit c i means that the sum of the products is '0', so the i-th column ( ) means that it is related to the i-th code word bit c i .
  • Figure 2 is a diagram illustrating a method for representing a graph of an LDPC code.
  • Fig. 2 is a diagram illustrating an example of a parity check matrix H 1 of an LDPC code consisting of 4 rows and 8 columns and its representation as a Tanner graph.
  • the parity check matrix H 1 has 8 columns, a codeword of length 8 is generated, and the code generated through H 1 means an LDPC code, and each column corresponds to 8 encoded bits.
  • the Tanner graph of an LDPC code that encodes and decodes based on a parity check matrix H 1 is composed of eight variable nodes, namely x 1 (202), x 2 (204), x 3 (206), x 4 (208), x 5 (210), x 6 (212), x 7 (214), x 8 (216), and four check nodes (218, 220, 222, 224).
  • the i-th column and the j-th row of the parity check matrix H 1 of the LDPC code correspond to the variable node x i and the j-th check node, respectively.
  • the value of 1, i.e., a non-zero value, at the point where the ith column and the jth row of the parity check matrix H 1 of the LDPC code intersect means that there is an edge connecting the variable node x i and the jth check node on the Tanner graph, as shown in Fig. 2.
  • the degree of a variable node and a check node refers to the number of segments connected to each node, which is equal to the number of non-zero elements (entries) in the column or row corresponding to the corresponding node in the parity check matrix of the LDPC code.
  • the degrees of variable nodes x 1 (202), x 2 (204), x 3 (206), x 4 (208), x 5 (210), x 6 (212), x 7 (214), x 8 (216) are 4, 3, 3, 2, 2, 2, 2, 2, respectively, and the degrees of check nodes (218, 220, 222, 224) are 6, 5, 5, 5, respectively.
  • the number of non-zero elements in each column of the parity check matrix H 1 of FIG. 2 corresponding to the variable nodes of FIG. 2 is identical to the degrees of the above-described variable nodes, which are 4, 3, 3, 3, 2, 2, 2, 2, in that order, and the number of non-zero elements in each row of the parity check matrix H 1 of FIG. 2 corresponding to the check nodes of FIG. 2 is identical to the degrees of the above-described check nodes, which are 6, 5, 5, 5, in that order.
  • the degree of each variable node is also called the column degree or column weight
  • the degree of a check node is also called the row degree or row weight.
  • LDPC encoded codeword bits can be decoded based on an iterative decoding algorithm based on a sum-product algorithm on a bipartite graph as listed in Fig. 2.
  • the sum-product algorithm is a type of message passing algorithm, and the message passing algorithm represents an algorithm that exchanges messages through edges on a bipartite graph and calculates and updates output messages from messages input to variable nodes or check nodes.
  • the value of the ith coding bit can be determined based on the message of the ith variable node. Both hard decision and soft decision are possible methods for determining the value of the ith coding bit. Therefore, the performance of the ith bit c i of the LDPC codeword corresponds to the performance of the ith variable node of the Tanner graph, which can be determined by the position and number of 1s in the ith column of the parity check matrix. In other words, the performance of the N ldpc codeword bits of the codeword can be affected by the position and number of 1s in the parity check matrix, which means that the performance of the LDPC code is greatly affected by the parity check matrix. Therefore, in order to design an LDPC code with excellent performance, a method for designing a good parity check matrix is required.
  • the parity check matrix used in communication and broadcasting systems is usually a quasi-cyclic LDPC code (or QC-LDPC code, hereinafter referred to as QC-LDPC code) that uses a quasi-cyclic parity check matrix for ease of implementation.
  • QC-LDPC code quasi-cyclic LDPC code
  • a parity check matrix that has a structure that is not a complete quasi-cyclic structure but is almost similar to a quasi-cyclic structure is used.
  • Such LDPC codes may not be strictly classified as QC-LDPC codes in terms of algebra, but are sometimes categorized as QC-LDPC codes for convenience.
  • a typical QC-LDPC code is characterized by having a parity check matrix composed of zero matrices or circulant permutation matrices in the form of small square matrices.
  • a permutation matrix means a matrix in which each row or column contains only one 1 and all the remaining elements are 0.
  • a circulant permutation matrix means a matrix in which each element of an identity matrix is circulatively shifted to the right or left.
  • the identity matrix itself is also included in a circulant permutation matrix because each element of the identity matrix is considered to be circulantly shifted 0 times. Therefore, a circulant permutation matrix basically includes an identity matrix, but for the convenience of explanation, an identity matrix and a circulant permutation matrix that is not an identity matrix can be expressed by distinguishing between them.
  • Circular permutation matrix of size means the entry of the i-th row and j-th column in the matrix P above.
  • the cyclic permutation matrix can also be defined as in [Mathematical Formula 2-2], in which case go It is a cyclic permutation matrix in the form of each element of the identity matrix of size shifted to the left by i times:
  • parity check matrix H of the simplest QC-LDPC code can be expressed in the following mathematical formula 3.
  • each index of the cyclic permutation matrix or 0-matrix in the above mathematical expression 3 has one of the values ⁇ -1, 0, 1, 2, ..., Z-1 ⁇ .
  • the identity matrix is or can be expressed as
  • the 0-matrix is or can be expressed as.
  • the parity check matrix H of the above mathematical expression 3 is a column block. Dog, row block Since it is a dog, the size of the above parity check matrix H is am.
  • the parity check matrix of the above mathematical expression 3 has the maximum rank (full rank, or complete coefficient)
  • the length of the information word bit of the QC-LDPC code corresponding to the parity check matrix is For convenience, it corresponds to the information word bit.
  • the ten blocks of a dog are called information word ten blocks and the number of information word bits is , corresponding to the remaining parity bits.
  • the ten blocks of the dog can be called parity ten blocks. In this case, the number of parity bits is For reference, if the parity check matrix of the above mathematical expression 3 does not have the maximum rank, the above information bits is larger, and the number of information bits is The larger the value, the more parity bits has a smaller value.
  • each cyclic permutation matrix and 0-matrix in the parity check matrix of the above mathematical expression 3 are replaced with 1 and 0, respectively.
  • a binary matrix of size H is called the mother matrix or base matrix or base graph of the parity check matrix H, and M(H) or It is expressed as . Also, by selecting the index of each cyclic permutation matrix or 0-matrix, it is obtained as in mathematical formula 4.
  • An integer matrix of size H is called the exponent matrix of the parity check matrix H. It is said.
  • each indices is called a circular shift value (or circular shift value). It can also be called a circular shift value matrix or shift value matrix. It is generally a matrix of exponential or shift value matrix and a circular permutation matrix or 0-matrix corresponding in size to the Given a value, a parity check matrix can be determined or identified.
  • a parity check matrix means a binary matrix H that satisfies the condition of Equation 1, but in some cases, an exponential matrix or a shift value matrix can be conveniently named a parity check matrix.
  • the exponential matrix may be conveniently expressed as a sequence of integers.
  • a parity check matrix can be expressed not only as an exponential matrix but also as various sequences that can express algebraically identical characteristics.
  • the parity check matrix is expressed as a sequence indicating the position of 1 in an exponential matrix or a parity check matrix, but since there are various sequence notations that can distinguish the positions of 1 or 0 included in a parity check matrix, it is not limited to the method expressed in this specification and can be expressed in the form of various sequences or matrices that exhibit the algebraically identical effect.
  • the sequence may be called in various ways, such as an LDPC sequence, an LDPC code sequence, an LDPC sequence, a parity check matrix sequence, or a (cyclic) shift value sequence, in order to distinguish it from other sequences.
  • a transceiver may perform LDPC encoding and decoding by directly generating a parity check matrix, but depending on the implementation characteristics, LDPC encoding and decoding may also be performed based on an exponential matrix, a shift value matrix, or a sequence that has the same effect algebraically as the parity check matrix. Therefore, although encoding and decoding using a parity check matrix is described for convenience in this disclosure, an actual transceiver may implement encoding and decoding through various methods that can obtain the same effect as the parity check matrix.
  • the algebraically identical effect means that two or more different representations can be explained or converted as being completely identical to each other logically or mathematically.
  • codes that can be defined by matrices such as LDPC codes
  • algebraic values that can be defined by matrices such as minimum distance, rank, and cycle characteristics on Tanner graphs, are identical, and it can also mean that the basic structure or operation in the encoding/decoding process is identical.
  • the two matrices can be viewed as algebraically identical matrices from a code perspective.
  • various transpose transformations that do not change the characteristics of the actual code can also provide algebraically identical effects.
  • silver This is an example of a block-by-block permutation that permutes the second and third row blocks.
  • silver In addition, here is an example of a block-by-block permutation where the first and third row blocks are permuted.
  • silver This is an example where cyclic permutation is applied only to the first and third column blocks.
  • cyclic permutation is applied only to the second and fourth row blocks.
  • transpose This is an example of applying block-wise transposition transformation.
  • silver Here is an example of reversing the signs of each index (or cyclic shift value) (for convenience only)
  • a 0-matrix of size When expressing as , using negative exponents (or shift values) can be confusing, so Is ) can also be expressed as a positive value, such as .
  • silver This is an example of applying an affine transformation with a constant term of 0 (it can also be applied to cases where the constant term is not 0 in general). For reference, the above examples are for convenience. go although we have described the case where there are no elements that are 0-matrix of size 0, when a 0-matrix is included, the part corresponding to the 0-matrix is always a 0-matrix regardless of the transformation.
  • each transformation is only an example, and various other transformations may exist.
  • each transformation can be applied independently, but can also be applied in an appropriate overlapping and combined manner.
  • the characteristic of each transformation or combination of transformations can be converted into the original matrix through an appropriate invertible transform process.
  • QC-LDPC codes can correspond to one or more cyclic permutation matrices in one row block and one column block in the parity check matrix, and for reference, multiple cyclic permutation matrices are duplicated in one row block and one column block.
  • a matrix of the size of is called a circulant matrix (or circulant matrix or circular matrix).
  • each element (entry) of a circulant matrix has not only binary numbers but also arbitrary numbers as elements, but in this disclosure, for convenience, a binary code is described, so the circulant matrix means a binary circulant matrix.
  • the algebraic structure and features proposed in this disclosure can be extended in a similar manner to the case of non-binary codes, but details are omitted in this disclosure.
  • the basic matrix (or mother matrix or basic graph) for the parity check matrix and the index matrix (or cyclic shift value matrix) of the above mathematical expressions 5 and 6 means a binary matrix obtained by replacing each cyclic permutation matrix and 0-matrix with 1 and 0, respectively, similar to the definition used in the above mathematical expression 3, and the cyclic matrix included in one block (i.e., the sum of multiple cyclic permutation matrices) can also be replaced with 1.
  • the index of a 0-matrix of size (or a shift value) is represented as -1, and it can be expressed in various ways.
  • the matrix representation method of the above [Mathematical Formula 7] can be represented in various other ways, and as a specific example, the representation method of the parity check matrix of the LDPC code defined in 3GPP TS 38.212, which is a 3GPP 5G standard specification, can be used.
  • 3GPP TS 38.212 the sizes of the parity check matrices of the LDPC code corresponding to BG1 (Base Graph 1) and BG2 (Base Graph 2) are too large, so they are represented using a table.
  • the corresponding representation method is applied to the matrices of the above [Mathematical Formula 7], the result is as shown in the following [Table 1].
  • Is is a matrix of size
  • silver is a matrix of size.
  • the entries of the basic matrix (or basic graph) and parity check matrices not expressed in Table 1 below are 0 or A 0-matrix of size 0 corresponds.
  • Exponential matrix as above When expressed as a sequence, it can be conveniently named in various ways, such as shift sequence, shift value sequence, LDPC sequence, etc.
  • sequence expression method is a method of listing the positions of columns where the elements are not 0 for each row.
  • index matrix or shift value matrix
  • parity check matrix can also be defined exactly.
  • Equation 8 Another simple example of the relationship between the parity check matrix and the exponential matrix (or cyclic shift matrix), the fundamental matrix, etc. is given in Equation 8 below.
  • Equation 8 At least one It illustrates a case where a block of size contains a circulant matrix corresponding to two or more circulant permutation matrices.
  • [Mathematical Formula 8] is a weight matrix for the fundamental matrix, exponential matrix, or parity check matrix, and is a matrix expressing how many cyclic permutation matrices correspond to the i-th row, j-th column in the fundamental matrix and exponential matrix, or the i-th row block, j-th column block in the parity check matrix. For example, corresponds to the i-th row block and the j-th column block in the parity check matrix. It means a matrix that represents the number of circulant permutation matrices that constitute a circulant matrix of size as an element of the i-th row and j-th column.
  • a 0-matrix is a matrix that represents 0 as an element when a 0-matrix corresponds, and w as an element when w cyclic permutation matrices correspond.
  • a 0-matrix can be viewed as a cyclic matrix in a broad sense, but it is not a cyclic 'permutation' matrix.
  • Is is a matrix of size
  • silver is a matrix of size
  • the elements of the basic matrix (or basic graph) and parity check matrix not expressed in Table 2 below are 0 or A 0-matrix of size 0 corresponds.
  • the above expression is a method of listing the positions of columns where the elements are not 0 for each row.
  • the exponential matrix can be defined exactly from the above sequences, and if If we obtain information about the values, the parity check matrix can also be defined exactly.
  • an LDPC code Since the performance of an LDPC code is determined by the parity check matrix, it is necessary to design a parity check matrix for an LDPC code with excellent performance. In addition, an LDPC encoding or decoding method that can support various input lengths and code rates is required.
  • Lifting can be used not only for the efficient design of QC-LDPC codes, but can also mean a method for generating parity check matrices of various lengths or generating LDPC codewords using given base matrices and exponent matrices. That is, the lifting can be applied to efficiently design a very large parity check matrix by setting the Z value, which determines the size of a cyclic permutation matrix or a 0-matrix from a given small parent matrix, according to a specific rule, or can mean a method for generating parity check matrices of various lengths or generating LDPC codewords by applying an appropriate Z value to a given exponent matrix or its corresponding sequence.
  • S QC-LDPC codes to be designed by the lifting method are C 1 , ..., C S
  • the values corresponding to the sizes of the row blocks and column blocks of the parity check matrix of each QC-LDPC code are L k .
  • C 0 corresponds to the smallest LDPC code that has the parent matrix of the C 1
  • ..., C S codes as the parity check matrix
  • the value Z 0 corresponding to the size of the row blocks and column blocks is 1.
  • the parity check matrix of each code C k Is exponential matrix of size and each index are chosen as one of the values ⁇ -1, 0, 1, 2, ..., Z k - 1 ⁇ .
  • the parity check matrix of C s is If only storing is performed, all of the above QC-LDPC codes C 0 , C 1 , ..., C S can be represented using the following mathematical expressions 9 or 10 depending on the lifting method.
  • Figure 3b is a diagram explaining the cycle characteristics of a QC-LDPC code.
  • the exponential matrix in Fig. 3b is , and in this case, the length of the shortest cycle on the Tanner graph is 12. Since the cycle characteristics on the Tanner graph can change significantly even by changing only one index of the cyclic permutation matrix, the selection of the index matrix plays an important role in improving the performance of the LDPC code.
  • the lifting method can be viewed as one of the design methods that considers these cycle characteristics.
  • lifting can be thought of as using the exponential matrix of Equation 4 for LDPC encoding and decoding by changing the values of its elements for various Z values.
  • the exponential matrix of Equation 4 and the transformed exponential matrix according to the Z value can be generally applied.
  • D means a constant which is a positive integer defined in advance.
  • the reference value (or, and To distinguish the application of The reference value) is expressed as 0 for convenience, but the reference value is the lifting size Z value to be supported or It can be set differently depending on how the 0-matrix of size is expressed.
  • the reference value for applying the conversion formula f can be defined differently.
  • the expression of the index matrix or LDPC sequence is based on a method of not expressing the index corresponding to the 0-matrix by excluding it from the beginning, the rule for values whose index is less than 0 in mathematical expression 11 can be omitted. Since the conversion formula f is applied to a circulant permutation matrix or a circulant matrix, not a 0-matrix, in general, There are various ways to omit transformations for zero-matrix sizes.
  • the LDPC code defined in TS 38.212, the 3GPP 5G standard, is also a code designed in the same way, with two basic matrices. This is defined and 8 exponent matrices (or circular shift value matrices) for each fundamental matrix. ( ) is defined and can be used for LDPC encoding. That is, according to the standard, a total of two basic matrices and 16 exponent matrices, and an appropriate lifting size Based on this, the parity check matrix of various LDPC codes can be determined. However, in the TS 38.212 standard, The matrix corresponding to is called the parity check matrix, and the matrix corresponding to the normal parity check matrix is matrix- It was named La. is a matrix of integers with lifting size A parity check matrix in the strict sense can be constructed if given, but for convenience as explained above, can also be called a parity check matrix.
  • lifting sizes or block sizes are basically expressed in the manner as in [Table 3] above, but they can also be expressed in the manner as in [Table 4] below, and various other expression methods are also possible.
  • lifting sizes or block sizes Z can be used by dividing them into multiple sets (or groups) as in [Table 3] or [Table 4]. (Hereinafter, for convenience, they are called lifting size sets (or groups) or block size sets (or groups))
  • each column block that constitutes the parity check matrix of the LDPC code used for LDPC encoding and decoding can be composed of at least 7 columns.
  • the lifting size set (or block size group) may be changed as shown in [Table 6] below.
  • the lifting size sets defined in the above [Table 7-1] and [Table 7-2] all include the same number of Z values, but appropriate Z values can be further added or subtracted for each set as needed. For example, it is possible to define the lifting size sets of the above [Tables 3] to [Tables 6] based on the lifting size sets of the above [Table 7-2].
  • FIG. 4 is a transport block structure diagram according to one embodiment of the present disclosure.
  • a transport block composed of A bits is added with L bits of CRC bits (TB-CRC bits), and one transport block can become one code block.
  • the value B A + L is greater than a specific threshold value, it can be divided into multiple code blocks through an appropriate segmentation process.
  • the sizes of the code blocks K are all the same, and for this purpose, specific bits called null bits or filler bits can be added to each code block.
  • the null bits or filler bits usually correspond to a value of 0, but they are not necessarily limited to this, and can be composed of any specific bits determined in advance.
  • the operation of adding predetermined bits such as null bits or fillers in this way is usually called shortening because the size of actual pure information word bits is reduced, and if the values are 0, it can be called zero-padding.
  • one of the basic matrices of two different LDPC codes used for LDPC encoding or decoding can be determined based on the code rate indicated by the TBS size and MCS through a method such as the [basic matrix determination method] below.
  • LDPC encoding can be performed using LDPC basic matrix 2.
  • LDPC encoding can be performed using LDPC basic matrix 1.
  • basic matrix 1 defined in the 3GPP 5G standard and basic matrix 2 is as follows.
  • the above basic matrix 1 and basic matrix 2 The sizes of are 46 ⁇ 68 and 42 ⁇ 52, respectively, and the sizes of the parity check matrices determined from the above basic matrices are 46Z ⁇ 68Z and 42Z ⁇ 52Z.
  • the number of CRC bits (L TB ) to be added to the transport block can be determined as follows based on the above-determined TBS.
  • K cb 8448
  • K cb 3840.
  • Step 1 Number of code blocks can be decided.
  • the number of bits K included in each code block can be calculated as follows:
  • Step 3 Table 3 Among the values The minimum value that satisfies can be determined. For LDPC basic matrix 1, , and for LDPC basic matrix 2 Set to .
  • the value corresponds to a column or column block corresponding to an LDPC information bit in the basic matrix (or basic graph) or parity check matrix of the LDPC code, and is the maximum value of the LDPC information bit without shortening or zero padding. ) can be corresponded to. For example, even if the number of columns (or column blocks) corresponding to information word bits in the LDPC basic matrix 2 or the parity check matrix corresponding to the basic matrix 2 is 10, if If set to , then substantially the maximum LDPC encoding/decoding is performed on the information bits of the bits, and at least The information bits corresponding to the column of the dog are shortened or zero-padded.
  • shortening or zero-padding can mean that the transmitter and receiver assign a promised bit value, such as 0, or it can mean that the corresponding part is not used in the parity check matrix.
  • each number included in the parity check matrix or sequence of the LDPC code means a value corresponding to a cyclic permutation matrix.
  • FIGS. 5 and 6 A flowchart of an embodiment of an LDPC encoding and decoding process based on a designed base matrix or exponential matrix is shown in FIGS. 5 and 6.
  • Figure 5 is a diagram illustrating an embodiment of an LDPC encoding process.
  • step (540) the transmitter determines the lifting size (Z) value to be applied to LDPC encoding based on the CBS.
  • the transmitter determines a parity check matrix or sequence according to the TBS or CBS or lifting size (Z) value at step (550).
  • the transmitter may determine an LDPC index matrix or sequence that has an effect algebraically identical to the parity check matrix.
  • the transmitter performs LDPC encoding based on the parity check matrix or sequence in step (560).
  • the transmitter may perform LDPC encoding based on the exponential matrix or sequence in step (560).
  • the transmitter may perform LDPC encoding based on the lifting size and the exponential matrix or sequence in step (560).
  • the step (550) above may include a process of converting the determined LDPC index matrix or sequence based on the determined lifting size, depending on the case.
  • the LDPC index matrix or sequence or parity check matrix for LDPC encoding may be determined in various ways based on TBS or CBS, depending on the system.
  • the transmitter may first determine the base matrix through TBS, and then determine the LDPC index matrix or sequence parity check matrix based on the determined base matrix and CBS, and various other methods may also be applied.
  • additional operations may be included depending on the system between steps (520) and (540) or between steps (530) and (540).
  • the base matrix 2 ( ) means the number of columns to be actually used in the base matrix or the number of column blocks to be used in the parity check matrix depending on the TBS size. The process of determining the value may be included. (For reference, The column blocks of the parity check matrix corresponding to the columns of the basic matrix of the dog are shortened.)
  • the receiver determines in step (620) whether TBS is greater than, less than, or equal to max CBS.
  • the process of determining the exponent matrix or sequence of the LDPC code in steps (550) and (650) of FIGS. 5 and 6 has been described for the case where the exponent matrix or sequence is determined by one of the TBS or CBS or the lifting size (Z), but various other methods may exist.
  • additional operations may be included between steps (620) and (640) or between steps (630) and (640) of FIG. 6 depending on the system.
  • the basic matrix 2 ( ) means the number of columns to be actually used in the base matrix or the number of column blocks to be used in the parity check matrix depending on the TBS size.
  • a process for determining the value may be included. Note that the receiver Since the bits corresponding to the column blocks of the parity check matrix corresponding to the columns of the basic matrix of the dog can be known to have been shortened at the transmitter, the receiver may additionally perform appropriate operations on the shortened bits before performing LDPC decoding.
  • the first of the input bits or code block bits Beats is not included in the encoding bits. That is, the above It means that the bits are punctured at the transmitter and are not transmitted to the receiver. For reference, if a part of the information word bits are punctured, it means that the transmitter does not transmit a part of the information word (102) of Fig. 1, and therefore, the receiver can perform decoding by processing the information word bits that are not transmitted as erased. In other words, since the punctured bits are regarded as erased and have the same probability of being 0 and 1, the receiver can also perform decoding by inserting a corresponding value.
  • the information bits punctured in the above encoding process may not always be transmitted even in the case of retransmission.
  • the punctured information bits may not always be transmitted.
  • some of the information bits may be perforated, and in the case of a retransmission, all or some of the perforated information bits may be transmitted. All of the information bits are stored in a circular buffer, but in the case of a first transmission, a redundancy value (RV) may be appropriately set so that some of the information bits are perforated (e.g., the RV0 value is set to exclude the information bits to be perforated). Even if some of the information bits are perforated in the first transmission, since the bit values are stored in the circular buffer, in the case of a retransmission, some or all of the perforated information bits may be transmitted depending on the circular buffer rate matching operation and selection of an appropriate RV value.
  • RV redundancy value
  • [Table 9] For convenience, is called a coding bit, but the definition of a coding bit can be changed for convenience of explanation.
  • the bit string after punching out some of the information bits can be defined as the encoded bit, but in reality, the parity bit vector is used in the encoding process. Input bits or code block bits to generate Because this is used, it is based on the information bit before perforation.
  • bit string with rate matching applied based on the allocated resource amount can also be defined as a coded bit, a bit stream with interleaving applied to the rate-matched bit stream. This can be defined as a coding bit.
  • the coding bit string can be defined in various ways for convenience of explanation, but usually, the bit string related to actual transmission in the system is Ina, related to the encoding process This can be defined by the encoding bits.
  • decoding can be performed by adding an appropriate operation for the shortened information bits and the punctured bits or repeated bits corresponding to the transmitter operation.
  • the shortened information bits are 0, so the receiver performs decoding by excluding the column corresponding to the shortened bits from the parity check matrix, or performs decoding by setting a value preset in the system for the shortened bits.
  • the receiver can perform decoding by inserting a corresponding value, or, depending on the structure of the parity check matrix, decoding can be performed without using at least some of the rows corresponding to the punctured parity bits.
  • the LDPC decoder can perform decoding without using part or all of the corresponding part in the parity check matrix, which has the advantage of reducing the decoding complexity.
  • the transmitter first determines the size of the input bits (or code blocks) to which the LDPC encoding is to be applied, and then determines the lifting size (Z) to which the LDPC encoding is to be applied based on the size, determines an appropriate LDPC index matrix or sequence based on the lifting size, and then performs LDPC encoding based on the lifting size (Z) and the determined index matrix or LDPC sequence.
  • the LDPC index matrix or sequence may be applied to the LDPC encoding without transformation, and in some cases, the LDPC index matrix or sequence may be appropriately transformed according to the lifting size (Z) to perform LDPC encoding.
  • the lifting method applied to the sequence corresponding to the information bits in the index matrix and the lifting method applied to the sequence corresponding to the parity bits may be set differently, and in some cases, lifting may not be applied to a part or all of the sequence corresponding to the parity bits, so that a fixed value may be used without sequence transformation.
  • FIG. 7 is a block diagram of a transmitter according to an embodiment of the present disclosure.
  • the transmitter (700) may include a segmentation unit (710), a zero padding unit (720), an LDPC encoding unit (730), a rate matching unit (740), a modulation unit (750), etc., to process variable length input bits.
  • the rate matching unit (740) may include an interleaver (741) and a puncturing/repetition/zero removal unit (742), etc.
  • the components illustrated in FIG. 7 are components that perform encoding and modulation for variable-length input bits, and this is only an example, and in some cases, some of the components illustrated in FIG. 7 may be omitted or changed, and other components may be added.
  • the transmitting device (700) can determine necessary parameters (for example, at least one of input bit length, ModCod (modulation and code rate), parameters for zero padding (or shortening), code rate/code length of LDPC code, parameters for interleaving, parameters for repetition and puncturing, and modulation methods), and encode input bits based on the determined parameters and transmit them to the receiving device (800).
  • necessary parameters for example, at least one of input bit length, ModCod (modulation and code rate), parameters for zero padding (or shortening), code rate/code length of LDPC code, parameters for interleaving, parameters for repetition and puncturing, and modulation methods
  • the input bits can be segmented to have a length less than or equal to the preset value. Also, each segmented block can correspond to one LDPC coded block. However, when the number of input bits is less than or equal to the preset value, the input bits are not segmented and the input bits can correspond to one LDPC coded block.
  • the transmitter (700) may store various parameters used for encoding, interleaving, and modulation.
  • the parameter used for encoding may include at least one of information on a code rate of an LDPC code, a codeword length, and a parity check matrix.
  • the parameter used for interleaving may include information on an interleaving rule
  • the parameter used for modulation may include information on a modulation method.
  • the information on puncturing may include a puncturing length.
  • the information on repetition may include a repetition length.
  • the information on the parity check matrix may include an exponent value of a circulant matrix or values algebraically identical thereto when the parity matrix presented in the present disclosure is used.
  • each component constituting the transmitter device (700) can perform an operation using these parameters.
  • the transmitter (700) may further include a control unit (not shown) for controlling the operation of the transmitter (700).
  • FIG. 8 is a block diagram of a receiving device according to an embodiment of the present disclosure.
  • the receiving device (800) may include a demodulation unit (810), a rate dematching unit (820), an LDPC decoding unit (830), a zero removal unit (840), and a desegmentation unit (850), etc., to process variable length information.
  • the rate dematching unit (820) may include an LLR (log likelihood ratio) insertion unit (822), an LLR combiner (823), a deinterleaver (824), etc.
  • FIG. 8 are components that perform functions corresponding to the components illustrated in FIG. 8, but this is only an example, and some may be omitted or changed depending on the case, and other components may be added.
  • the parity check matrix in the present disclosure may be read using a memory, may be given in advance to the transmitter or receiver, or may be generated directly in the transmitter or receiver.
  • the transmitter may store or generate a sequence or exponential matrix corresponding to the parity check matrix, or a value algebraically identical thereto, and apply it to encoding.
  • the receiver may store or generate a sequence or exponential matrix corresponding to the parity check matrix, or a value algebraically identical thereto, and apply it to decoding.
  • the demodulator (810) demodulates a signal received from the transmitter (700).
  • the demodulator (810) is a component corresponding to the modulation unit (750) of the transmitter (700), and can demodulate a signal received from the transmitter (700) to generate values corresponding to bits transmitted by the transmitter (700).
  • the receiving device (800) determines parameters required for demodulation and decoding (for example, at least one of input bit length, ModCod (modulation and code rate), parameters for zero padding (or shortening), code rate/codeword length of an LDPC code, parameters for interleaving, parameters for repetition and puncturing, and modulation methods), and based on the determined parameters, the demodulation unit (810) can perform a decoding process of demodulating a signal received from the transmitting device (700) according to a mode to generate values corresponding to LDPC codeword bits.
  • parameters required for demodulation and decoding for example, at least one of input bit length, ModCod (modulation and code rate), parameters for zero padding (or shortening), code rate/codeword length of an LDPC code, parameters for interleaving, parameters for repetition and puncturing, and modulation methods
  • the value corresponding to the bits transmitted from the transmitting device (700) may be a LR (likelihood ratio) value or an LLR (log likelihood ratio) value.
  • the LR value refers to the ratio of the probability that the bit transmitted from the transmitter (700) is 0 and the probability that it is 1, and the LLR value can be expressed as the log value of the ratio of the probability that the bit transmitted from the transmitter (700) is 0 and the probability that it is 1.
  • the LR or LLR value may be determined based on the probability or the ratio of the probability or the Log value for the ratio of the probability and expressed as the bit value itself, or may be expressed as a representative value defined in advance according to the section to which the probability or the ratio of the probability or the Log value for the ratio of the probability belongs.
  • An example of a method for determining a representative value defined in advance according to the section to which the probability or the ratio of the probability or the Log value for the ratio of the probability belongs includes a method that considers quantization.
  • various other values corresponding to the probability or the ratio of the probability or the Log value for the ratio of the probability may be used.
  • the operation based on the LLR value is shown to explain the operation of the receiving method and device, but it is not necessary to be limited thereto.
  • the above-mentioned demodulator (810) includes a function of performing multiplexing (not shown) for LLR values.
  • the multiplexer (not shown) is a component corresponding to the bit demuxer (not shown) of the transmitter (700) and can perform an operation corresponding to the bit demuxer (not shown).
  • the receiving device (800) may store information on parameters that the transmitting device (700) used for demultiplexing and block interleaving. Accordingly, the multiplexer (not shown) may perform the demultiplexing and block interleaving operation performed in the bit demuxer (not shown) in reverse for the LLR value corresponding to the cell word (information representing the received symbol for the LDPC codeword as a vector value), thereby multiplexing the LLR value corresponding to the cell word on a bit-by-bit basis.
  • the rate dematching unit (820) can additionally insert LLR values into the LLR values output from the demodulator (810).
  • the rate dematching unit (820) can insert LLR values agreed upon in advance between the LLR values output from the demodulator (810).
  • the rate dematching unit (820) is a component corresponding to the rate matching unit (740) of the transmitting device (700), and can perform operations corresponding to the interleaver (741), zero removal, and puncturing/repetition/zero removal unit (742).
  • the receiving device (800) may store information about the parameters that the transmitting device (700) used to pad zero bits. Accordingly, the rate dematching unit (820) may determine the position where zero bits were padded in the LDPC codeword and insert an LLR value corresponding to the shortened zero bits at the corresponding position.
  • the LLR insertion unit (822) of the rate dematching unit (820) can insert LLR values corresponding to the punctured bits into the positions of the punctured bits in the LDPC codeword.
  • the LLR values corresponding to the punctured bits can be 0 or another value that is determined in advance.
  • parity bits with degree 1 are punctured, there is no effect on improving the performance of the LDPC decoding process, so some or all of the corresponding punctured positions may not be used in the LDPC decoding process without LLR insertion.
  • the LLR insertion unit (822) can insert a pre-determined LLR value into positions corresponding to some or all of the punctured bits with degree 1 regardless of the improvement in the decoding performance.
  • the transmitter (700) selects LDPC encoded bits, repeats them between LDPC information bits and LDPC parity bits, and transmits them to the receiver (800).
  • the LLR value for the LDPC encoded bits may be composed of an LLR value for the repeated LDPC encoded bits and an LLR value for the non-repeated LDPC encoded bits.
  • the LLR combiner (823) may combine the LLR values for the same LDPC encoded bits.
  • the receiving device (800) can store information about parameters used for repetition in the transmitting device (700). Accordingly, the LLR combiner (823) can determine an LLR value for the repeated LDPC encoded bits and combine it with an LLR value for the LDPC encoded bits that are the basis of the repetition.
  • the LLR combiner (823) can combine the LLR value corresponding to the retransmitted or IR (increment redundancy) bits with another LLR value.
  • the other LLR value can be an LLR value for some or all of the LDPC codeword bits that are the basis for generating the retransmitted or IR bits in the transmitter (700).
  • the transmitting device (700) can transmit some or all of the code bits to the receiving device (800).
  • the LLR combiner (823) can combine the LLR values for bits received via retransmission or IR with the LLR values for LDPC codeword bits received via the previous frame.
  • the receiving device (800) can store information about parameters used by the transmitting device (700) to generate retransmission or IR bits. Accordingly, the LLR combiner (823) can determine an LLR value for the number of retransmission or IR bits and combine it with an LLR value for LDPC encoded bits that are the basis for generating the retransmission bits.
  • the deinterleaver (824) can deinterleave the LLR value output from the LLR combiner (823).
  • the deinterleaver unit (824) is a component corresponding to the interleaver (741) of the transmitting device (700) and can perform an operation corresponding to the interleaver (741).
  • the receiving device (800) may store information on parameters that the transmitting device (700) used for interleaving. Accordingly, the deinterleaver (824) may reversely perform the interleaving operation performed by the interleaver (741) on the LLR values corresponding to the transmitted LDPC encoded bits, thereby deinterleaving the LLR values corresponding to the transmitted LDPC encoded bits.
  • the LDPC decoding unit (830) can perform LDPC decoding based on the LLR value output from the rate dematching unit (820).
  • the LDPC decoding unit (830) is a component corresponding to the LDPC encoding unit (730) of the transmitting device (700) and can perform an operation corresponding to the LDPC encoding unit (730).
  • the receiving device (800) may store information on parameters used by the transmitting device (700) to perform LDPC encoding according to the mode. Accordingly, the LDPC decoding unit (830) may perform LDPC decoding based on the LLR value output from the rate dematching unit (820) according to the mode.
  • the LDPC decoding unit (830) can perform LDPC decoding based on the LLR value output from the rate dematching unit (820) based on an iterative decoding method based on a sum-product algorithm, and output bits whose errors are corrected according to the LDPC decoding.
  • the LDPC decoding unit (830) performs LDPC decoding on the LDPC codeword based on a parity check matrix or an exponential matrix or sequence corresponding thereto.
  • the LDPC decoding can be performed using a parity check matrix defined differently according to a code rate (i.e., a code rate of the LDPC code).
  • the LDPC decoding unit (830) can perform LDPC decoding by passing the LLR value corresponding to the LDPC codeword bits through an iterative decoding algorithm to generate information bits.
  • the LLR value is a channel value corresponding to the LDPC codeword bits, and can be expressed in various ways.
  • the zero removal unit (840) can remove zero bits from the bits output from the LDPC decoding unit (830).
  • the zero removal unit (840) is a component corresponding to the zero padding unit (720) of the transmitter (700) and can perform an operation corresponding to the zero padding unit (720).
  • the receiving device (800) may store information about the parameters used to pad zero bits in the transmitting device (700). Accordingly, the zero removal unit (840) may remove zero bits that were padded in the zero padding unit (720) from the bits output from the LDPC decoding unit (830).
  • the receiving device (800) may store information about the parameters that the transmitting device (700) used for segmentation. Accordingly, the desegmentation unit (850) can restore the bits before segmentation by combining the bits output from the zero removal unit (840), i.e., the segments for the variable-length input bits.
  • FIG. 9 illustrates a structural diagram of an LDPC decoding unit according to an embodiment of the present disclosure.
  • the inspection node operator (908) receives data from the memory (902) and performs inspection node operations based on the address information of the input data and the number information of the input data received from the controller (906). Thereafter, the inspection node operator (908) stores the inspection node operation results in the memory (902) based on the address information of the output data and the number information of the output data received from the controller (906).
  • the inspection node operation has been described above based on FIG. 6.
  • Various broadcasting systems and communication systems use LDPC codes optimized for each system.
  • the present disclosure describes a system using an LDPC code defined based on a parity check matrix having the same structure as the LDPC code used in the 3GPP 5G system, but is not necessarily limited thereto.
  • a communication system including a 5G or 6G system may apply rate matching at a transmitter and rate dematching at a receiver in order to support various code rates and various code lengths.
  • rate matching at a transmitter and rate dematching at a receiver in order to support various code rates and various code lengths.
  • a system that performs encoding/decoding based on a fixed LDPC code such as some broadcasting systems, not only rate matching or rate dematching but also all or part of other operations may be omitted.
  • FIG. 10 shows the general structure of a parity check matrix of an LDPC code, which is an internal code applied to an FEC encoding unit (not shown) and an FEC decoding unit (not shown) to be described in the present disclosure.
  • a parity check matrix based on the following conditions may be considered for the parity check matrix corresponding to the above-described FIG. 10.
  • the submatrix A(1010) and the submatrix B(1020) may be referred to as the first submatrix and the second submatrix, respectively.
  • the cyclic permutation matrix below is determined based on the lifting size Z. It may mean a cyclic permutation matrix having a size of , and may be configured as in mathematical expression 5 or mathematical expression 6, for example.
  • a cyclic matrix may mean a matrix in which cyclic permutation matrices are overlapped.
  • Condition 1(a) In the parity check matrix for the QC-LDPC code of Fig. 10, the submatrix B(1020) is In the case where the circulant permutation matrices of the size do not include nested circulant matrices, the weight of all column blocks of the submatrix B(1020) is 2 or more, and at least one column block with an odd weight of 3 or more can be included in the submatrix B(1020).
  • the basic matrix corresponding to the submatrix B(1020) All columns of the matrix have a weight of 2 or greater, and the columns with an odd weight of 3 or greater are the basic matrix. may contain at least one or more of:
  • the submatrix B(1020) is In the case where the circulant permutation matrices of the size include at least one nested circulant matrix, the weights of all column blocks of the submatrix B(1020) are 2 or greater, and at least one column block whose weight is an odd number of 3 or greater is included in the submatrix B(1020).
  • the weight matrix corresponding to the submatrix B(1020) In the weight matrix the sum of all the elements in the column is 2 or greater, and the column whose sum of the elements in the column is an odd number of 3 or greater is At least one of the above is included.
  • the weight of the column block containing the circulant matrix which is a nested circulant matrix of sizes 2 or 3 or more, may be 2 or 3 or more.
  • E(1060) and the submatrix of the basic matrix and the weight matrix corresponding to E(1060) are identity matrices or matrices that are converted to identity matrices by applying appropriate column permutation or row permutation, etc. (That is, E(1060) is an identity matrix or a matrix having an equivalent algebraic property.) If the parity check matrix of the above Fig. 10 is defined as a quasi-cyclic parity check matrix, the submatrix E has multiple They can be classified into size identity matrices.
  • FIGS. 11a and 11b are examples of parity check matrices that satisfy at least one of Condition 1(a), Condition 1(b), or Condition 2.
  • the code rate of the LDPC code corresponding to the parity check matrices of FIGS. 10, 11a, and 11b is K/N, a codeword with a lower code rate can be generated as M 2 decreases.
  • LDPC encoding and decoding can be performed based on a parity check matrix that can support a lower code rate by further extending columns having degree 1 while including the above-described FIGS. 11a and 11b.
  • the number of columns constituting one column block of the parity check matrix is greater than or equal to the minimum value of the lifting size.
  • the number of columns constituting one column block of the parity check matrix can be at least 4 or more. Therefore, in a communication system in which the lifting sizes of Table 6 are practically applied to a parity check matrix of an LDPC code having a structure as in FIGS. 10, 11a, and 11b satisfying at least one of Condition 1(a), Condition 1(b), or Condition 2, this means that the number of columns with degree 3 in the submatrix B(1020) is at least 4 or more.
  • the core matrix in the parity check matrix or base matrix or weight matrix can also be defined in a form that satisfies at least one of Condition 1(a), Condition 1(b), or Condition 2 by adding one or two more rows as follows.
  • a parity check matrix [A(1010) B(1020)] including a partial matrix B satisfying only Condition 1(a) or Condition 1(b) is regarded as a core matrix (or kernel matrix or precoding matrix). That is, in the present invention, the first part of the basic matrix or the first part of the parity check matrix or the core matrix/part or the kernel matrix/part, etc. means a partial matrix from which columns corresponding to parity bits of degree 1 and rows directly related to the parity bits of degree 1 are excluded.
  • the core matrix consists of four rows, which can also be expressed as a weight matrix as in Equation 14.
  • Basic matrix 1 or base matrix 2 LDPC code defined by is one Since we define a single cyclic permutation matrix to correspond to a size block, the base matrix and the weight matrix are basically the same.
  • one An LDPC code designed so that at most one cyclic permutation matrix corresponds to a size block is a structure suitable for performing layered decoding in units of one row block during decoding.
  • the structure of the LDPC code means that it is a structure suitable for performing decoding through a Z-unit parallel processing processor.
  • Layered decoding means an operation of sequentially performing decoding layer by layer. Therefore, decoding may be performed sequentially in units of one row block, or decoding may be performed layer by layer by configuring a plurality of row blocks as one layer.
  • layered decoding is defined as an operation of sequentially performing decoding in units of one layer, but performing decoding sequentially only means performing decoding in units of one layer, and does not mean that decoding must be performed in the order of the indexes of the layers.
  • performing decoding sequentially may mean performing decoding sequentially according to a layered decoding order or pattern (or sequence). Additionally, depending on the structure of a parity check matrix, some layers may consist of one row block and other layers may consist of multiple row blocks.
  • This layered decoding method usually performs parallel processing on a basic unit of a single row block or a layer composed of multiple row blocks, so that it can be determined that one iteration of decoding is completed when decoding is performed the number of total row blocks. This means that if the number of parallel processing processors is sufficient, the decoding throughput through layered decoding is inversely proportional to the number of row blocks. However, if a parity check matrix with a small number of row blocks is used to support the same code length, the lifting size Z value increases further, so the number of parallel processing processors required to simultaneously perform decoding on one row block increases.
  • the above weight matrix It consists of 4 rows and 14 columns, and the weights of each column are 3, 3, 2, 3, 3, 2, 3, 3, 2, 2, 2. If it consists of 3 rows and 13 columns, And the weight distribution is similar to the weight matrix It consists of 2 rows and 12 columns. And the weight distribution is similar to the weight matrix It can be structured as follows:
  • each weight matrix , LDPC codes with the same code length can be generated using the same code length, and the lifting size corresponding to each parity check matrix can be , , If so, , There is a relationship between . Also, in the LDPC decoder, each If the number of parallel processing processors allowed, the approximate decryption information processing volume is Is 1.5 times of Is can be twice as much.
  • the base matrix or weight matrix should be determined by simultaneously considering the target information processing volume and target error correction capability of the system.
  • the present disclosure proposes an algebraic property that a core matrix part of a basic matrix or a weight matrix, which is closely related to a maximum decoding throughput or a peak data rate of a system, must satisfy.
  • the parity check matrix does not include a second part of the parity check matrix composed of submatrices C (1040), D (1050) and E (1060) of FIG. 10, the core matrix may be identical to the basic matrix or the weight matrix.
  • Parity check matrix One of the conditions that the core matrix must satisfy is that when two columns are selected from the weight matrix corresponding to the core matrix, there is only one non-zero element. ( ) should not contain non-zero elements in only one row. As a simple example, , , , , ..., etc.
  • the minimum distance of the parity check matrix corresponding to the weight matrix or the core matrix including this structure is Since it is below, there is a high possibility that the error floor phenomenon will easily occur. Therefore, , , , ..., in any two columns that have only one non-zero element, the non-zero elements must be located in different rows. This also means that for the elementary matrix, all non-zero elements located in columns with weight 1 are located in different rows.
  • the above can be defined as conditions 3(a) and 3(b) below.
  • Condition 3(b) If there are two or more columns with weight 1 among the columns of the basic matrix or weight matrix corresponding to the core matrix, the non-zero elements included in the columns with weight 1 are located in different rows.
  • the above conditions 3(a) and 3(b) are satisfied when the number of column blocks consisting of only one circulating permutation matrix or circulating matrices included in the core matrix is at most 1, or when the core matrix includes two or more circulating permutation matrixes or circulating matrices. It means that the size circulant permutation matrix or circulant matrix is necessarily included in different row blocks.
  • the above conditions 3(a) and (3b) are structures to prevent serious error floor phenomenon, but if a better error floor characteristic is to be obtained, the following condition 4 may be additionally added.
  • the above circulant permutation matrix, circulant matrix Can have any size.
  • Condition 4 The weight of the column corresponding to the information bit (or input bit or code block) in the parity check matrix corresponding to the core matrix is 3 or greater.
  • the above condition 4 is the basic matrix 2 of mathematical expression 14. It can be applied when trying to improve the error floor phenomenon, but the encoding gain can be reduced by ensuring that the weight of the column corresponding to the information bit is not 2, such as the corresponding parity check matrix.
  • the above condition 4 is that the submatrix A(1010) in the parity check matrix for the QC-LDPC code If the circulant permutation matrices of the size do not contain nested circulant matrices, the weight of all column blocks of the submatrix A(1010) is 3 or greater, and the fundamental matrix corresponding to the submatrix A(1010) It means that the weight of all columns is 3 or more.
  • the submatrix A(1010) If the circulant permutation matrices of the size include at least one nested circulant matrix, the weight of all column blocks of the submatrix A(1010) is 3 or more, and the weight matrix corresponding to the submatrix A(1010) It means that the sum of all the elements of the column is 3 or more.
  • the weight matrix corresponding to the core matrix does not include an element greater than or equal to 3.
  • the core matrix of the weight matrix includes an element greater than or equal to 3, it means that three or more cyclic permutation matrices correspond to the corresponding position. If there are three or more circulant permutation matrices that constitute a circulant matrix of size that overlap, Regardless of the value, the maximum length of the cycle is limited to 6. When the cycle length is short, the performance improvement effect by iterative decoding is reduced, so it is appropriate to use a parity check matrix corresponding to a weight matrix or core matrix including values of 3 or more as elements when the code length is short or the code rate is relatively high.
  • the core matrix of the weight matrix does not include elements of 3 or more. (Of course, it may be included in the part corresponding to the single parity check extension part.)
  • the above contents can be defined as the following condition 5.
  • the weight matrix corresponding to the core matrix consists of only 0 and 1, or only 0, 1, and 2.
  • the submatrix B(1020) of Fig. 10 corresponding to must have the maximum rank to enable efficient encoding, and the following restrictive structure is desirable to prevent serious degradation of cycle characteristics.
  • condition 6(a) shows the case where the weight matrix and the base matrix are the same
  • condition 6(b) shows the case where the weight matrix is has the same form as the fundamental matrix only if 0 is in the fundamental matrix or weight matrix shown in Conditions 6(a), 6(b), and 6(c). It means a 0-matrix of size 1. Identity matrix of size or cyclic permutation matrix (v > 0). Also, 2 is Circular matrix of size It means ( ).
  • an upper bound on the cycle length can be predicted from the basic matrix or weight matrix, but the cycle characteristics of the parity check matrix corresponding to the basic matrix or weight matrix are unknown.
  • the submatrix B(1020) or In each case, regardless of the values of v1 and v2, the base matrix or weight matrix is or Although they are identical, their cycle characteristics are very different. If at least one of v1 or v2 is 0, (or ) will generate a large number of 4-cycles, so basically v1, v2 , (or ) is set to an integer satisfying . Likewise, In the case where v1 0, a large number of 4-cycles are generated, so basically v1 is An integer satisfying v2 is is set to an integer satisfying .
  • the above is only a method to remove 4-cycles, and the values of v1 and v2 can be restricted in various ways to obtain longer cycles.
  • a submatrix of a core matrix composed only of columns corresponding to the punctured information bits has at least one row with a row weight of 1.
  • the probability that the punctured bits are 0 and 1 is determined to be the same. This usually means 1 when decoding is performed using LR values, and 0 when decoding is performed using LLR values, but it may be determined in a different form based on the values used in the decoding process.
  • LDPC decoding is performed based on a parity check matrix that does not satisfy Condition 7, the punctured information bits may not be decoded unless ML (maximum likelihood) decoding or pseudo ML decoding is used. Since the ML or pseudo ML decoding methods are not usually used due to their complexity, the parity check matrix may be determined to satisfy Condition 7 in order to ensure successful decoding.
  • the parity check matrix can be expressed based on the lifting size Z value and the base matrix and/or the weight matrix and/or the exponent matrix, so it can also be expressed as in the following condition 8.
  • a submatrix of a basic matrix composed of only a columns corresponding to a submatrix of a core matrix composed of only a*Z columns corresponding to the punctured a*Z (a: integer greater than or equal to 1) information bits has at least one row whose weight is 1.
  • a submatrix of a weight matrix composed of only a columns corresponding to the submatrix of the core matrix composed of only a*Z columns has at least one row whose weight is 1 and whose element is 1.
  • the parity check matrix may be determined to satisfy one of the above conditions or may be determined to satisfy a combination of at least two of the above conditions.
  • a method for improving the error floor performance of an LDPC code is proposed.
  • the error floor phenomenon of an LDPC code is greatly affected by the cycle characteristic of the Tanner graph.
  • the cycle characteristic of a QC LDPC code on the Tanner graph is determined by the relationship between the index or the cyclic shift value of the basic matrix and the cyclic permutation matrix, not only the position of the cyclic permutation matrix constituting the parity check matrix but also the cyclic shift value must be appropriately selected.
  • first parity bits in the first part of the parity check matrix composed of sub-matrices A (1010) and B (1020) in FIG. 10
  • the size of the above submatrix B(1020) is (or ), and the submatrix B(1020) is (or ) corresponds to a basic matrix or a weight matrix of the size of the submatrix B(1020).
  • the first column block of the submatrix B(1020) is composed of three cyclic permutation matrices.
  • the cyclic permutation matrix may include an identity matrix. That is, in the present disclosure, the cyclic permutation matrix is defined as a matrix in which each element of the identity matrix is cyclically shifted by i, and when the value of i is 0, the cyclic permutation matrix can be an identity matrix. This can be applied throughout the detailed description of the present disclosure.
  • the remaining column blocks of the submatrix B(1020) are composed of two cyclic permutation matrices or identity matrices.
  • the remaining column blocks are expressed only when the identity matrix is composed of a dual diagonal structure, but in general, it is not necessary to be limited thereto.
  • the partial matrix B(1020) can be determined based on at least one of the matrices included in Mathematical Expression 15 below.
  • the embodiment of the present disclosure is not limited thereto, and various matrices satisfying the above characteristics (the first column block is composed of three cyclic permutation matrices, and the remaining column blocks are composed of two cyclic permutation matrices or an identity matrix) can be considered.
  • the first column blocks are three different cyclic permutation matrices. , , It consists of . Also, in mathematical expression 15, for convenience, although it is shown only for the cases where the values are 3, 4, 5, and 6, the submatrix B(1020) can be defined similarly for integers greater than that. In addition, matrices that can be transformed into the submatrix B(1020) of the above form through an appropriate invertible transform process can be considered as algebraically identical matrices.
  • the submatrix B(1020) has a dual diagonal structure with the size of the remaining column blocks consisting of identity matrices except for the first column block, the exponents (or circular shift values) of the cyclic permutation matrix of the first column block were used for encoding convenience. , , At least two values among them are set to the same value. In this case, the values used in the encoding process are Size of The matrix is an identity matrix or a simple cyclic permutation matrix It becomes, Inverse matrix of is the identity matrix or It is simplified together, so that the encoding process becomes simpler.
  • the length on the Tanner graph is determined by the structure shown in the following mathematical expression 16.
  • cycle The dog is always present. In other words, if If the value of is fixed, the lifting size and index Length regardless of value There is always a cycle in the QC LDPC code. (For detailed information on the cycle characteristics of QC LDPC codes, see [Myung2005].)
  • the lifting size is due to the structure as shown in the following mathematical expression 17. and index Regardless of the value There are always shorter cycles.
  • Equations 16 and 17 may not have a significant effect on the performance of the LDPC code.
  • the BLER may increase due to the error floor phenomenon, which becomes a non-negligible problem as the target BLER of the system is lower.
  • the present invention uses the indices (or cyclic shift values) of the cyclic permutation matrices constituting the first column block of the submatrix B(1020) having a structure as in mathematical expression 15.
  • the method improves the cycle characteristics while maintaining the required It explains that the computational complexity associated with matrices has a property of increasing to a reasonable level.
  • the lifting size for the parity check matrix of the QC LDPC code cast ( is odd, When is an integer greater than or equal to 0, the indices (or circular shift values) of the cyclic permutation matrices that constitute the first column block of the submatrix B(1020) , , are distinct integers, satisfying at least some or all of the following conditions:
  • Index condition 1a At least one of the differences between the two indices (circular shift values) is a lifting magnitude.
  • the greatest common divisor with is 1 or greater than 1 is the smallest number among the divisors of (i.e., and are prime or greater than 1 ) has its least divisor as its greatest common divisor.
  • Index condition 1b Two of the differences between the two indices are the lifting magnitudes.
  • the common divisor with is 1 or greater than 1 It is the smallest number among the divisors of .
  • Index condition 2a At least one of the differences between the two exponents is ( )am.
  • the difference between the two indices is If and are coprime, the length of the cycle determined by the cyclic permutation matrix associated with the two indices is maximized.
  • the value of In the case where and are relatively prime the mathematical expression 17 The length of a cycle on a Tanner graph is determined by becomes. If and The greatest common divisor of The ramen cycle length is As a result, As the value increases, the length of the cycle also increases.
  • the value of The cycle length determined by the structure of mathematical expression 16 in the case where and are coprime becomes. If and The greatest common divisor of The ramen cycle length is As a result, it can be seen that the cycle length is not fixed regardless of the Z value, but increases as the Z value increases. Considering only the cycle characteristics, the difference between the exponents is It is desirable that they are coprime to each other, but depending on the situation, the exponents may be chosen so that the greatest common divisor D is small (for example, so that it is the least divisor of Z greater than 1) by other conditions. For example, if the difference between the exponents cannot satisfy the property of being coprime to Z, the greatest common divisor It is desirable to select an exponent that makes the number smaller.
  • the matrix is defined as follows.
  • the matrix is It is not easy to find, The density of weights of a matrix also often has a high density characteristic rather than a low density characteristic. That is, it has a low density characteristic.
  • the matrix There is a characteristic that it does not guarantee the low density characteristic of the matrix.
  • the high density characteristic of the matrix is what increases the encoding complexity. It is desirable that the density of the matrix be as low as possible. It is desirable for matrices to have a simple structure.
  • index conditions 2a and 2b are for efficient LDPC encoding. It is a condition for simplifying the matrix as much as possible. For example, in the above index condition 2a, In that case
  • index selection method For convenience, as a concrete example of the index selection method, in other words, An example of index selection when set to is shown below.
  • index selection example 3 Specific examples related to index selection example 3 are described below.
  • the reference value is set to 48, the same method can be used.
  • the values can be defined as 32, 48, 40, 28, 36, 44, 26, 30 in order according to each lifting size set index.
  • the corresponding parity check matrix defined according to each lifting size set index is The value has the characteristic that it is determined by the ith largest lifting size in each set.
  • index selection example 4 For convenience, as a specific example of the above index selection example 4, , in other words, An example of index selection when set to is shown below.
  • index selection example 5 In this case yes Any arbitrary It also satisfies index condition 1a and index condition 1b. That is, In the integer About, , , (or ) The submatrix B set as satisfies the index condition 1a and the index condition 1b.
  • index selection methods including the index selection examples 1 to 6 above, can be variably applied depending on the target BLER and/or lifting size of the system. For example, if the target BLER of the system is high, since the cycle characteristic does not significantly affect the decoding performance of the code, encoding can be performed using an existing method with the highest encoding efficiency even if the cycle characteristic is not improved. However, if the target BLER is low, the index selection methods proposed in the present disclosure can be applied. Here, the high and low of the target BLER can be relatively determined when there are multiple target BLERs applicable in the system.
  • the first target BLER is And the second target is BLER
  • the first target BLER is higher than the second target BLER
  • the first target BLER is higher than the second target BLER.
  • the second target BLER And the third target BLER work (or )
  • the first target BLER may be determined to be higher than the second target BLER and the third target BLER
  • the first target BLER and the second target BLER may be determined to be higher than the third target BLER.
  • the high and low of the BLER can be determined based on a specific BLER value, and then the index selection method proposed in the present disclosure can be variably applied based on this.
  • the J value is If the system target BLER is judged to be low, the J value is set to a relatively large value. can be set to a value ( ) Also, the method of selecting these indices or the decision on the J value can be determined by considering the lifting size together. Generally, the BLER and/or lifting size that serve as the reference are set to A, and a total of (A+1) different J values can be distinguished. For example, if there are a first reference value, a second reference value, etc., the J value is , , ... can be subdivided into, etc. In general, J can also be set to 0, in which case It refers to the existing method that enables the simplest encoding without improving the cycle characteristics.
  • the size of the submatrix B(1020) of the above mathematical expression 20 is (or ) and corresponds to the basic matrix or weight matrix of size.
  • the first column block of the submatrix B(1020) is 1 A cyclic permutation matrix and two cyclic permutation matrices superimposed It consists of a circular matrix
  • the second column block consists of two It consists of an identity matrix (or a cyclic permutation matrix).
  • the second column blocks are expressed only when they consist of an identity matrix, but in general, it is not necessary to be limited to that.
  • matrices that can be transformed into a submatrix B(1020) of the above form through an appropriate invertible transform process can be considered as algebraically identical matrices.
  • the lifting size for the parity check matrix of the QC LDPC code cast ( is odd, When B(1020) is an integer greater than or equal to 0, the indices (or circular shift values) of the cyclic permutation matrices constituting the first column block of the submatrix B(1020) are 0, , are distinct integers, satisfying at least some or all of the following conditions:
  • Index condition 3 is the lifting size
  • the greatest common divisor with is 1 or greater than 1 is the smallest number among the divisors of (i.e., Is and are prime or greater than 1 ) has its least divisor as its greatest common divisor.
  • FIG. 12a is an example diagram for explaining cycle characteristics in a submatrix of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
  • the above index condition 5 is in the matrix of mathematical expression 20. It is a condition for improving the characteristics of the cycle on the Tanner graph determined by . In the above structure, if the index condition 5 is satisfied, In the integer About the length Since all cycles below are removed, the length is Only ideal cycles exist. A simple example of the cycle characteristics by the index condition 5 is shown in Figs. 12b and 12c.
  • FIG. 12b is an example diagram for explaining cycle characteristics in a submatrix of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
  • FIG. 12c is an example diagram for explaining cycle characteristics in a submatrix of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
  • Fig. 12c In case of It shows the cycle characteristics induced by .
  • a parity check matrix or index matrix can be defined for each lifting size set. That is, in the case of Tables 3 to 9, a parity check matrix or index matrix, etc. can be defined for a total of eight set indices.
  • step, , in other words, ) must be satisfied.
  • the minimum lifting size in each lifting size set is It is explained only for the case where the minimum lifting size is a multiple of 2. In general, the minimum lifting size in each lifting size set is a multiple of 2, but Even if the index is not a multiple of , the index selection method described in the present disclosure can be applied.
  • index conditions 3 and 6 are established.
  • step, And does not necessarily have to be an odd number.
  • Example 8 of selecting an index is given a set of lifting sizes, and the minimum lifting size contained in each lifting size set is It means a method of selecting an index based on.
  • the number of rows of the core matrix in the first basic matrix related to the first target BLER is the number of rows of the core matrix in the second basic matrix related to the second target BLER.
  • the number of columns corresponding to the information word bits in the first basic matrix and the second basic matrix and the total size are respectively and , and the lifting size can also be used for encoding and decoding.
  • the first target BLER and the second target BLER which is lower than the first target BLER, may be determined according to different service scenarios or system settings in one communication system.
  • the first target BLER and the second target BLER which is lower than the first target BLER, may be determined according to the communication system used when different communication systems, such as a 5G communication system and a 6G communication system, are supported by one terminal and one base station.
  • LDPC encoding and decoding may be performed by selecting one of the first basic matrix and the second basic matrix according to a service scenario or system setting, and LDPC encoding and decoding may be performed by selecting one of the first basic matrix and the second basic matrix according to the communication system used among a plurality of different communication systems supported by one terminal or one base station.
  • LDPC encoding and decoding may be performed using one of the first basic matrix and the second basic matrix in consideration of backward compatibility with the existing system, decoding information processing amount, stable error floor performance, etc., and LDPC encoding and decoding may be performed using only the second basic matrix with better error floor characteristics without the first basic matrix.
  • the usage methods of the first basic matrix and the second basic matrix can be applied differently depending on the various implementation methods of the terminal or base station, and the possible application methods can be summarized as follows.
  • the conditions of the basic matrices or parity check matrices may include at least one of the following conditions.
  • the lifting size is If so, the size of the parity check matrix is It means that.
  • the size of the core matrix of the first basic matrix corresponding to the submatrices A(1010) and B(1020) in Fig. 10 is , the size of the core matrix of the second fundamental matrix is And Therefore, the core matrix of the second basic matrix is smaller than that of the first basic matrix. There are more rows and columns of dogs. Also, the lifting size is In this case, the size of the first part of the parity check matrix is and It means that.
  • the number of columns and rows corresponding to parity bits of order 1 in the second basic matrix is greater than that in the first basic matrix. It could mean fewer dogs.
  • the terminal or the base station can perform encoding or decoding based on a first basic matrix related to the first target BLER and a parity check matrix corresponding thereto.
  • the terminal or the base station can perform encoding or decoding based on a second basic matrix related to the second target BLER and a parity check matrix corresponding thereto.
  • the first target BLER is higher than the second target BLER.
  • a first basic matrix may be used in a first system
  • a second basic matrix may be used in a second system.
  • At least one of the target BLERs of the second system may be smaller than a smallest value of the target BLERs of the first system.
  • an average of the log10 values of the largest and smallest values of the target BLERs of the second system is smaller than an average of the log10 values of the largest and smallest values of the target BLERs of the first system.
  • the different first and second systems may be supported through a single integrated modem or processor, or may be supported through different modems or processors.
  • LDPC encoding or decoding based on the first basic matrix is performed
  • LDPC encoding or decoding based on the second basic matrix can be performed.
  • LDPC encoding or decoding may be performed by determining either the first basic matrix or the second basic matrix according to the setting of the CQI table or the MCS table in combination with the method of (3-1) above.
  • either the first basic matrix or the second basic matrix may be determined according to the version of the second system.
  • the first system may be a 5G system and the second system may be a 6G system.
  • the maximum value of the first target BLER is , the minimum value is It can be, and the minimum value of the second target BLER is For example, for smaller values, or It can be a value of one or less.
  • the base matrix to be used can be determined by directly specifying the target BLER, but the base matrix to be used can also be determined by utilizing various system settings or service scenarios corresponding to the target BLER.
  • the sizes of the first and second fundamental matrices are , It could be. Also , It can be. Also, the first basic matrix is the basic matrix used in 5G and the basic matrix used in the existing 5G system. and There can be at least one of them.
  • the second basic matrix may have additional constraints on the column weights of the core matrix.
  • the core matrix of the second basic matrix there are three columns with column weight 2, and the information bits corresponding to the columns with column weight 2 have a disadvantage of slow decoding convergence when performing BP decoding. Therefore, in a situation where high data throughput is required, it is desirable to exclude columns with degree 2 in the core matrix as much as possible. Accordingly, depending on the target BLER of the system, it may be desirable to limit the weights of the columns corresponding to the information bits in the core matrix to 3 or more, or to limit the number of columns with column weight 2 to 1 or less.
  • the number of columns with degree 4 in the core matrix of the second basic matrix may be set to be equal to or greater than the number of columns with degree 4 in the core matrix of the first basic matrix.
  • the first basic matrix is the basic matrix used in the 5G system. and If at least one of them is The size is the same and the size of the core matrix may also be the same. The size of the core matrix may be the same, but it does not satisfy this at the same time, and the second fundamental matrix is or For at least one of them, the overall size must be the same, but the sizes of the core matrices must be different.
  • At least one of the columns with a degree of 4 or more is arranged in a column corresponding to the punctured information bits. That is, if there are two columns with a degree of 4 or more in the core matrix of the second basic matrix, at least one of the columns corresponding to the punctured bits may have a degree of 4 or more. In addition, if the number of columns corresponding to the punctured information bits is two or more, both of the columns with a degree of 4 may correspond to the punctured information bits.
  • the first fundamental matrix When the core matrix of the second fundamental matrix is Rows of dogs If a column consists of three columns, and the number of columns with weights greater than or equal to 4 is three, all or some of the following conditions may be satisfied:
  • Equation 15 (e.g.: Back side )
  • At least the weight of the 0th column, 1st column, and 6th column is 4 or more
  • the above 0th column and 1st column may correspond to the punched information bits.
  • at least one of the above 0th column and 1st column has a weight is less than (eg: If so, at least one column weight is 4.)

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Error Detection And Correction (AREA)

Abstract

La présente invention concerne un procédé mis en œuvre par un émetteur dans un système de communication, le procédé comprenant les étapes consistant à : déterminer le nombre de bits d'entrée ; déterminer une matrice élémentaire ; déterminer une taille de levée (Z) sur la base du ou des éléments parmi le nombre de bits d'entrée et la matrice élémentaire ; déterminer une matrice de contrôle de parité sur la base du ou des éléments parmi la matrice élémentaire et la taille de levée (Z) ; et mettre en œuvre un codage sur la base de la matrice de contrôle de parité et des bits d'entrée de manière à déterminer un bit de codage, dans laquelle la matrice élémentaire est l'une de multiples matrices élémentaires, les multiples matrices ont la même taille, une première matrice élémentaire et une seconde matrice élémentaire incluses dans les multiples matrices élémentaires ont des matrices de cœur ayant des tailles différentes, et les matrices de cœur comprennent une matrice partielle correspondant à un bit d'entrée dans la matrice élémentaire et une matrice correspondant à une partie de bits de parité.
PCT/KR2025/000983 2024-01-18 2025-01-17 Procédé et dispositif de codage et de décodage de données dans un système de communication ou de diffusion Pending WO2025155121A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20240007949 2024-01-18
KR10-2024-0007949 2024-01-18
KR1020240026737A KR20250113863A (ko) 2024-01-18 2024-02-23 통신 또는 방송 시스템에서 데이터의 부호화 및 복호화 방법 및 장치
KR10-2024-0026737 2024-02-23

Publications (1)

Publication Number Publication Date
WO2025155121A1 true WO2025155121A1 (fr) 2025-07-24

Family

ID=96471495

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2025/000983 Pending WO2025155121A1 (fr) 2024-01-18 2025-01-17 Procédé et dispositif de codage et de décodage de données dans un système de communication ou de diffusion

Country Status (1)

Country Link
WO (1) WO2025155121A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190006568A (ko) * 2017-03-30 2019-01-18 엘지전자 주식회사 무선 통신 시스템에서 ldpc 부호의 패리티 검사 행렬을 기반으로 부호화를 수행하는 방법 및 이를 이용한 단말
KR102194617B1 (ko) * 2017-06-27 2020-12-24 후아웨이 테크놀러지 컴퍼니 리미티드 정보 처리 방법, 장치 및 통신 디바이스
KR20210030848A (ko) * 2019-09-10 2021-03-18 삼성전자주식회사 통신 또는 방송 시스템에서 데이터 복호화 방법 및 장치
KR20230107872A (ko) * 2020-10-15 2023-07-18 삼성전자주식회사 통신 또는 방송 시스템에서 데이터 복호화 방법 및 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190006568A (ko) * 2017-03-30 2019-01-18 엘지전자 주식회사 무선 통신 시스템에서 ldpc 부호의 패리티 검사 행렬을 기반으로 부호화를 수행하는 방법 및 이를 이용한 단말
KR102194617B1 (ko) * 2017-06-27 2020-12-24 후아웨이 테크놀러지 컴퍼니 리미티드 정보 처리 방법, 장치 및 통신 디바이스
KR20210030848A (ko) * 2019-09-10 2021-03-18 삼성전자주식회사 통신 또는 방송 시스템에서 데이터 복호화 방법 및 장치
KR20230107872A (ko) * 2020-10-15 2023-07-18 삼성전자주식회사 통신 또는 방송 시스템에서 데이터 복호화 방법 및 장치

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NTT DOCOMO: "Evaluation of LDPC codes for eMBB data channels", 3GPP DRAFT; R1-1700866_EVALUATION_LDPC_EMBB, vol. RAN WG1, 10 January 2017 (2017-01-10), Spokane, USA, pages 1 - 6, XP051203169 *

Similar Documents

Publication Publication Date Title
WO2017111559A1 (fr) Appareil et procédé de codage et de décodage de canal dans un système de diffusion ou de communication
WO2020231235A1 (fr) Procédé et appareil de décodage de données dans un système de communication ou de diffusion
WO2021006513A1 (fr) Dispositif et procédé d'émission et de réception d'un signal dans un système de communication
WO2018117651A1 (fr) Appareil et procédé de codage/décodage de canal dans un système de diffusion ou de communication
WO2021049888A1 (fr) Procédé et appareil de décodage de données dans un système de communication ou de diffusion
WO2013055046A2 (fr) Appareil et procédé d'envoi et de réception de données dans un système de communication/diffusion
WO2018212558A1 (fr) Procédé et appareil de codage/décodage dans un système de communication ou de diffusion utilisant une modulation d'ordre élevé
WO2018236114A1 (fr) Procédé et appareil pour l'adaptation de débit pour des systèmes de communication et de diffusion
WO2019031925A1 (fr) Procédé et appareil de codage/décodage de canal dans un système de communication ou de diffusion
EP3625887A1 (fr) Procédé et appareil pour l'adaptation de débit pour des systèmes de communication et de diffusion
EP3289696A1 (fr) Appareil et procédé d'utilisation de livre de codes dans un système de communication sans fil
WO2022186678A1 (fr) Appareil et procédé de transmission et de réception de données et de signaux de commande dans un système de communication
WO2011053101A2 (fr) Appareil et procédé de génération d'une matrice de contrôle de parité dans un système de communication utilisant des codes linéaires en blocs et appareil et procédé d'émission / réception les utilisant
WO2020145516A1 (fr) Procédé et dispositif pour effectuer un codage de canal à l'aide d'une matrice de contrôle de parité à faible densité dans un système de communication sans fil
WO2018034503A1 (fr) Procédé et appareil pour concevoir une séquence d'entrelacement dans un système de communication sans fil
WO2012099398A2 (fr) Appareil et procédé permettant de transmettre et de recevoir des données dans un système de communication/diffusion
WO2016175623A1 (fr) Appareil et procédé d'utilisation de livre de codes dans un système de communication sans fil
WO2018182371A1 (fr) Appareil et procédé de codage/décodage de canal dans un système de communication ou de diffusion
AU2022217677A9 (en) Method and apparatus for csi reporting in a wireless communication system
WO2018236173A1 (fr) Procédé et appareil de codage et de décodage de canal dans un système de communication ou de diffusion
WO2020067637A1 (fr) Dispositif et procédé de codage et de décodage à l'aide d'un code polaire dans un système de communication sans fil
EP3542481A1 (fr) Appareil et procédé de codage/décodage de canal dans un système de diffusion ou de communication
WO2018143717A1 (fr) Procédé et appareil permettant d'émettre et de recevoir un signal au moyen d'un codage polaire
EP3586445A1 (fr) Appareil et procédé de codage/décodage de canal dans un système de communication ou de diffusion
WO2018203661A1 (fr) Procédé et appareil de codage/décodage de canal dans un système de communication ou de diffusion

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 25742260

Country of ref document: EP

Kind code of ref document: A1