WO2025155366A1 - Dispositif mémoire tridimensionnel comprenant une structure de contact de source à jonction p-i-n et procédés pour le former - Google Patents

Dispositif mémoire tridimensionnel comprenant une structure de contact de source à jonction p-i-n et procédés pour le former

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Publication number
WO2025155366A1
WO2025155366A1 PCT/US2024/054889 US2024054889W WO2025155366A1 WO 2025155366 A1 WO2025155366 A1 WO 2025155366A1 US 2024054889 W US2024054889 W US 2024054889W WO 2025155366 A1 WO2025155366 A1 WO 2025155366A1
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WO
WIPO (PCT)
Prior art keywords
layer
memory
semiconductor
vertical
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/US2024/054889
Other languages
English (en)
Inventor
Masanori Tsutsumi
Satoshi Shimizu
Kota Funayama
Akio Nishida
Genta Mizuno
Hiroyuki Tanaka
Kento Sakane
Tatsuya Hinoue
Makoto Koto
Seiji Shimabukuro
Shota YATSUZUKA
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Technologies LLC
Original Assignee
SanDisk Technologies LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/413,859 external-priority patent/US20250234543A1/en
Priority claimed from US18/413,918 external-priority patent/US20250234544A1/en
Priority claimed from US18/413,990 external-priority patent/US20250232812A1/en
Priority claimed from US18/658,557 external-priority patent/US20250234545A1/en
Application filed by SanDisk Technologies LLC filed Critical SanDisk Technologies LLC
Publication of WO2025155366A1 publication Critical patent/WO2025155366A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Definitions

  • THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A P-I-N JUNCTION SOURCE CONTACT STRUCTURE AND METHODS FOR FORMING THE SAME
  • a semiconductor structure which comprises: an alternating stack of insulating layers and electrically conductive layers that alternate along a vertical direction; a memory opening vertically extending through the alternating stack; a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a vertical stack of memory elements; and a layer stack of an undoped semiconductor material layer and a source semiconductor layer, wherein the undoped semiconductor material layer contacts a bottom end of the vertical semiconductor channel.
  • a method of forming a semiconductor structure comprises: forming an alternating stack of insulating layers and spacer material layers over a carrier substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers; forming a memory opening through the alternating stack; forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises a vertical stack of memory elements and a vertical semiconductor channel; removing the carrier substrate; and forming a layer stack of an undoped semiconductor material layer and a source semiconductor layer, wherein the undoped semiconductor material layer is formed on a bottom end of the vertical semiconductor channel.
  • a semiconductor structure which comprises: an alternating stack of insulating layers and electrically conductive layer that alternate along a vertical direction, wherein a bottommost layer of the alternating stack comprises a bottommost electrically conductive layer; a memory opening vertically extending through the alternating stack; a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a vertical stack of memory elements; a semiconductor material layer underlying the alternating stack, contacting an outer sidewall of the memory film and not directly contacting the vertical semiconductor channel; and a source layer underlying and contacting a bottom surface of the semiconductor material layer and contacting a bottom surface of the vertical semiconductor channel.
  • a method of forming a semiconductor structure comprises forming a stopper film over a carrier substrate; forming an alternating stack of insulating layers and spacer material layers over the stopper film, wherein the spacer material layers are formed as or are subsequently replaced with electrically conductive layers; forming a memory opening through the alternating stack and through the stopper film; forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises a vertical semiconductor channel and a vertical stack of memory elements; removing the carrier substrate such that protruding end portions of the memory film and the vertical semiconductor channel protrude below the alternating stack and the stopper film; at least partially removing the protruding end portion of at least one of the memory film and the vertical semiconductor channel using the stopper film as stopper; and forming a source layer on an exposed remaining end surface of the vertical semiconductor channel.
  • a semiconductor structure comprises: a planar dielectric layer; an alternating stack of insulating layers and electrically conductive layers located over the planar dielectric layer; a memory opening vertically extending through the alternating stack and the planar dielectric layer; a memory opening fill structure located in the memory opening and comprising a semiconductor channel, a drain region electrically contacting an upper portion of the semiconductor channel, and a vertical stack of memory elements; and a source layer electrically contacting a lower portion of the semiconductor channel, wherein the source layer comprises a planar base portion and first, second and third step portions which protrude upwards toward the drain region from the planar base portion.
  • a semiconductor structure which comprises: an alternating stack of insulating layers and electrically conductive layers overlying an etch-stop dielectric layer; a memory opening vertically extending through the alternating stack and at least partly through the etch-stop dielectric layer; a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel, a dielectric core that is laterally surrounded by the vertical semiconductor channel, and a memory film that laterally surrounds the vertical semiconductor channel; a metal capping layer contacting an end portion of the vertical semiconductor channel and a bottom portion of the dielectric core; and a source layer contacting the metal capping layer and a bottom surface of the etch-stop dielectric layer.
  • a method of forming a semiconductor structure comprises: forming an alternating stack of insulating layers and spacer material layers over a carrier substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers; forming a memory opening through the alternating stack; forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises a memory film and a vertical semiconductor channel; removing the carrier substrate; removing an end portion of the memory film; converting an end portion of the vertical semiconductor channel to a metal capping layer; and forming a source layer on the metal capping layer.
  • FIG. l is a schematic vertical cross-sectional view of a first exemplary structure after formation of an alternating stack of insulating layers and sacrificial material layers over a carrier substrate according to a first embodiment of the present disclosure.
  • FIG. 2 is a schematic vertical cross-sectional view of the first exemplary structure after formation of stepped surfaces and a stepped dielectric material portion according to the first embodiment of the present disclosure.
  • FIG. 3 A is a schematic vertical cross-sectional view of the first exemplary structure after formation of memory openings and support openings according to the first embodiment of the present disclosure.
  • FIG. 5 is a vertical cross-sectional view of the first exemplary structure after formation of support pillar structures according to the first embodiment of the present disclosure.
  • FIGS. 7 A - 7F are sequential vertical cross-sectional views of a memory opening during formation of a memory opening fill structure according to an embodiment of the present disclosure.
  • FIG. 8B is a top-down view of the first exemplary structure of FIG. 8 A.
  • the vertical plane A - A is the cut plane of the vertical cross-sectional view of FIG. 8 A.
  • FIG. 9A is a vertical cross-sectional view of the first exemplary structure after formation of lateral isolation trenches according to the first embodiment of the present disclosure.
  • FIG. 9B is a top-down view of the first exemplary structure of FIG. 9A.
  • the vertical plane A - A is the cut plane of the vertical cross-sectional view of FIG. 9A.
  • FIG. 10 is a vertical cross-sectional view of the first exemplary structure after formation of laterally-extending cavities according to the first embodiment of the present disclosure.
  • FIG. 11 is a schematic vertical cross-sectional view of the first exemplary structure after formation of electrically conductive layers according to the first embodiment of the present disclosure.
  • FIG. 13 is a vertical cross-sectional view of the first exemplary structure after formation of a memory die according to the first embodiment of the present disclosure.
  • FIG. 14 is a vertical cross-sectional view of a logic die according to the first embodiment of the present disclosure.
  • FIG. 15 is a vertical cross-sectional view of the first exemplary structure after attaching the logic die to the memory die according to the first embodiment of the present disclosure.
  • FIG. 16A is a vertical cross-sectional view of the first exemplary structure after removal of the carrier substrate according to the first embodiment of the present disclosure.
  • FIG. 16B is a magnified view of region B of FIG. 16A.
  • FIG. 18 is a vertical cross-sectional view of the first exemplary structure after formation of the Schottky source structure according to the first embodiment of the present disclosure.
  • FIG. 19 is a vertical cross-sectional view of the first exemplary structure after formation of a backside dielectric layer and a source contact structure according to the first embodiment of the present disclosure.
  • FIG. 20 is a schematic vertical cross-sectional view of a second exemplary structure after formation of a planar dielectric layer, a stopper dielectric layer, a semiconductor material layer, and an alternating stack of insulating layers and sacrificial material layers over a carrier substrate according to a second embodiment of the present disclosure.
  • FIG. 21 is a schematic vertical cross-sectional view of the second exemplary structure after formation of memory opening fill structures and support pillar structures according to the second embodiment of the present disclosure.
  • FIG. 23 is a vertical cross-sectional view of the second exemplary structure after attaching the logic die to the memory die according to the second embodiment of the present disclosure.
  • FIG. 24A is a vertical cross-sectional view of the second exemplary structure after removal of the carrier substrate according to the second embodiment of the present disclosure.
  • FIG. 24B is a magnified view of region B of FIG. 24A.
  • FIGS. 25A - 25G are sequential vertical cross-sectional views of a region of the second exemplary structure during formation of a Schottky source structure according to the second embodiment of the present disclosure.
  • FIG. 26 is a vertical cross-sectional view of the second exemplary structure after formation of the Schottky source structure according to the second embodiment of the present disclosure.
  • FIG. 27 is a vertical cross-sectional view of the second exemplary structure after formation of a backside dielectric layer and a source contact structure according to the second embodiment of the present disclosure.
  • FIG. 28 is a schematic vertical cross-sectional view of a third exemplary structure after formation of a planar dielectric layer, a semiconductor material layer, and an alternating stack of insulating layers and sacrificial material layers over a carrier substrate according to a third embodiment of the present disclosure.
  • FIG. 29 is a schematic vertical cross-sectional view of the third exemplary structure after formation of memory opening fill structures and support pillar structures according to the third embodiment of the present disclosure.
  • FIG. 30 is a schematic vertical cross-sectional view of the third exemplary structure after formation of lateral isolation trenches according to the third embodiment of the present disclosure.
  • FIG. 31 is a vertical cross-sectional view of the third exemplary structure after attaching the logic die to the memory die according to the third embodiment of the present disclosure.
  • FIG. 32A is a vertical cross-sectional view of the third exemplary structure after removal of the carrier substrate according to the third embodiment of the present disclosure.
  • FIG. 32B is a magnified view of region B of FIG. 32A.
  • FIGS. 33 A - 33E are sequential vertical cross-sectional views of a region of the third exemplary structure during formation of a Schottky source structure according to the third embodiment of the present disclosure.
  • FIG. 34 is a vertical cross-sectional view of the third exemplary structure after formation of a backside dielectric layer and a source contact structure according to the third embodiment of the present disclosure.
  • FIG. 35 A is a vertical cross-sectional view of a fourth exemplary structure after formation of an array of openings through a planar dielectric layer according to a fourth embodiment of the present disclosure.
  • FIG. 35B is a top-down view of the fourth exemplary structure of FIG. 35 A.
  • the hinged vertical plane A - A’ is the cut plane of the vertical cross-sectional view of FIG. 35 A.
  • FIG. 36 is a vertical cross-sectional view of the fourth exemplary structure after formation of first sacrificial pedestals according to the fourth embodiment of the present disclosure.
  • FIG. 37A is a vertical cross-sectional view of the fourth exemplary structure after formation of second sacrificial pedestals according to the fourth embodiment of the present disclosure.
  • FIG. 37B is a top-down view of the fourth exemplary structure of FIG. 37A.
  • the hinged vertical plane A - A’ is the cut plane of the vertical cross-sectional view of FIG. 37A.
  • FIG. 38 is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of an alternating stack of insulating layers and sacrificial material layers over a carrier substrate according to a fourth embodiment of the present disclosure.
  • FIG. 39A is a schematic vertical cross-sectional view of the fourth exemplary structure after formation of memory openings and support openings according to the fourth embodiment of the present disclosure.
  • FIG. 39B is a top-down view of the fourth exemplary structure of FIG. 39A.
  • the hinged vertical plane A - A’ is the cut plane of the vertical cross-sectional view of FIG. 39A.
  • FIG. 40 is a schematic vertical cross-sectional view of the fourth exemplary structure after removal of second sacrificial pedestals according to the fourth embodiment of the present disclosure.
  • FIG. 41 A is a schematic vertical cross-sectional view of the fourth exemplary structure after formation of memory opening fill structures and support opening fill structures according to the fourth embodiment of the present disclosure.
  • FIG. 4 IB is a magnified view of a region of the fourth exemplary structure of FIG. 41 A.
  • FIG. 42 is a schematic vertical cross-sectional view of the fourth exemplary structure after formation of lateral isolation trenches according to the fourth embodiment of the present disclosure.
  • FIG. 43 is a vertical cross-sectional view of the fourth exemplary structure after attaching the logic die to the memory die according to the fourth embodiment of the present disclosure.
  • FIG. 44A is a vertical cross-sectional view of the fourth exemplary structure after removal of the carrier substrate according to the fourth embodiment of the present disclosure.
  • FIG. 44B is a magnified view of region B of FIG. 44A.
  • FIGS. 45A - 45C are sequential vertical cross-sectional views of a region of the fourth exemplary structure during formation of a Schottky source structure according to the fourth embodiment of the present disclosure.
  • FIG. 46 is a vertical cross-sectional view of the fourth exemplary structure after formation of a backside dielectric layer and a source contact structure according to the fourth embodiment of the present disclosure.
  • FIG. 47 is a vertical cross-sectional view of a fifth exemplary structure after formation of an array of first openings through a first planar dielectric layer according to a fifth embodiment of the present disclosure.
  • FIG. 48B is a top-down view of the fifth exemplary structure of FIG. 48 A.
  • the hinged vertical plane A - A’ is the cut plane of the vertical cross-sectional view of FIG. 48 A.
  • FIG. 49 is a vertical cross-sectional view of a fifth exemplary structure after formation of an array of second openings through a second planar dielectric layer according to the fifth embodiment of the present disclosure.
  • FIG. 50A is a vertical cross-sectional view of the fifth exemplary structure after formation of second sacrificial pedestals according to the fifth embodiment of the present disclosure.
  • FIG. 50B is a top-down view of the fifth exemplary structure of FIG. 50 A.
  • the hinged vertical plane A - A’ is the cut plane of the vertical cross-sectional view of FIG. 50A.
  • FIG. 51 A is a schematic vertical cross-sectional view of the fifth exemplary structure after formation of an alternating stack of insulating layers and sacrificial material layers and formation of memory openings and support openings according to the fifth embodiment of the present disclosure.
  • FIG. 5 IB is a top-down view of the fifth exemplary structure of FIG. 51 A.
  • the hinged vertical plane A - A’ is the cut plane of the vertical cross-sectional view of FIG. 51 A.
  • FIG. 52 is a vertical cross-sectional view of the fifth exemplary structure after attaching the logic die to the memory die according to the fifth embodiment of the present disclosure.
  • FIG. 53 is a vertical cross-sectional view of the fifth exemplary structure after formation of a backside dielectric layer and a source contact structure according to the fifth embodiment of the present disclosure.
  • FIG. 54 is a schematic vertical cross-sectional view of a sixth exemplary structure after formation of memory opening fill structures and support opening fill structures according to a sixth embodiment of the present disclosure.
  • FIGS. 55A - 55G are sequential vertical cross-sectional views of a region of the sixth exemplary structure during formation of a Schottky source structure according to the sixth embodiment of the present disclosure.
  • FIG. 56 is a vertical cross-sectional view of the sixth exemplary structure after formation of the Schottky source structure according to the sixth embodiment of the present disclosure.
  • FIG. 57 is a vertical cross-sectional view of the sixth exemplary structure after formation of a backside dielectric layer and a source contact structure according to the sixth embodiment of the present disclosure.
  • FIG. 58A is a vertical cross-sectional view of a seventh exemplary structure after formation of the sacrificial material strips over a carrier substrate according to the seventh embodiment of the present disclosure.
  • FIG. 58B is a top-down view of the seventh exemplary structure of FIG. 58A.
  • the hinged vertical plane A - A’ is the cut plane of the vertical cross-sectional view of FIG. 58A.
  • FIG. 59 is a schematic vertical cross-sectional view of the seventh exemplary structure after formation of an alternating stack of insulating layers and sacrificial material layers and the support pillar structures and the formation of voids in the memory openings according to the seventh embodiment of the present disclosure.
  • FIG. 60A is a vertical cross-sectional view of the seventh exemplary structure after formation of the memory opening fill structures according to the seventh embodiment of the present disclosure.
  • FIG. 60B is a top-down view of the seventh exemplary structure of FIG. 60A.
  • the hinged vertical plane A - A’ is the cut plane of the vertical cross-sectional view of FIG. 60A.
  • FIG. 60C is a magnified view of a region of the seventh exemplary structure of FIGS. 60 A and 60B.
  • FIG. 61 is a vertical cross-sectional view of the seventh exemplary structure after attaching the logic die to the memory die according to the seventh embodiment of the present disclosure.
  • FIG. 62A is a vertical cross-sectional view of the seventh exemplary structure after removing the carrier substrate and the sacrificial material strips according to the seventh embodiment of the present disclosure.
  • FIG. 63G is a vertical cross-sectional view of a region of an alternative configuration of the seventh exemplary structure according to the seventh embodiment of the present disclosure.
  • FIG. 64 is a vertical cross-sectional view of the seventh exemplary structure after formation of the Schottky source structure according to the seventh embodiment of the present disclosure.
  • FIG. 65 is a vertical cross-sectional view of the seventh exemplary structure after formation of a backside dielectric layer and a source contact structure according to the seventh embodiment of the present disclosure.
  • FIG. 66 is a vertical cross-sectional view of an eighth exemplary structure after formation of an alternating stack of insulating layers and sacrificial material layers according to an eighth embodiment of the present disclosure.
  • FIG. 67 is a vertical cross-sectional view of the eighth exemplary structure after formation of stepped surfaces and a retro-stepped dielectric material portion according to the eighth embodiment of the present disclosure.
  • FIG. 68A is a vertical cross-sectional view of the eighth exemplary structure after formation of memory openings and support openings according to the eighth embodiment of the present disclosure.
  • FIG. 68B is a top-down view of the eighth exemplary structure of FIG. 68 A.
  • the vertical plane A - A is the cut plane of the vertical cross-sectional view of FIG. 68 A.
  • FIG. 69 is a schematic vertical cross-sectional view of the eighth exemplary structure after formation of sacrificial opening fill structures according to the eighth embodiment of the present disclosure.
  • FIG. 70 is a vertical cross-sectional view of the eighth exemplary structure after formation of support pillar structures according to the eighth embodiment of the present disclosure.
  • FIG. 71 is a schematic vertical cross-sectional view of the eighth exemplary structure after removal of sacrificial memory opening fill structures according to the eighth embodiment of the present disclosure.
  • FIGS. 72 A - 72F are sequential vertical cross-sectional views of a memory opening during formation of a memory opening fill structure according to an embodiment of the present disclosure.
  • FIG. 73 A is a schematic vertical cross-sectional view of the eighth exemplary structure after formation of memory opening fill structures according to the eighth embodiment of the present disclosure.
  • FIG. 73B is a top-down view of the eighth exemplary structure of FIG. 73 A.
  • the vertical plane A - A is the cut plane of the vertical cross-sectional view of FIG. 73 A.
  • FIG. 74A is a vertical cross-sectional view of the eighth exemplary structure after formation of lateral isolation trenches according to the eighth embodiment of the present disclosure.
  • FIG. 74B is a top-down view of the eighth exemplary structure of FIG. 74A.
  • the vertical plane A - A is the cut plane of the vertical cross-sectional view of FIG. 74A.
  • FIG. 75 is a vertical cross-sectional view of the eighth exemplary structure after formation of laterally-extending cavities according to the eighth embodiment of the present disclosure.
  • FIG. 76 is a schematic vertical cross-sectional view of the eighth exemplary structure after formation of electrically conductive layers according to the eighth embodiment of the present disclosure.
  • FIG. 77A is a vertical cross-sectional view of the eighth exemplary structure after formation of lateral isolation trench fill structures, layer contact via structures, and drain contact via structures according to the eighth embodiment of the present disclosure.
  • FIG. 78 is a vertical cross-sectional view of the eighth exemplary structure after formation of a memory die according to the eighth embodiment of the present disclosure.
  • FIG. 80 is a vertical cross-sectional view of the eighth exemplary structure after attaching the logic die to the memory die according to the eighth embodiment of the present disclosure.
  • FIG. 83 is a vertical cross-sectional view of the eighth exemplary structure after formation of a backside dielectric layer and a source contact structure according to the eighth embodiment of the present disclosure.
  • a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. If two or more elements are not in direct contact with each other or among one another, the two elements are “disjoined from” each other or “disjoined among” one another.
  • an element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, an element is located “directly on” a second element if there exist a physical contact between a surface of the element and a surface of the second element.
  • an element is “electrically connected to” a second element if there exists a conductive path consisting of at least one conductive material between the element and the second element.
  • a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.
  • a “layer” refers to a material portion including a region having a thickness.
  • a layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface.
  • a substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow.
  • a semiconductor die, or a semiconductor package can include a memory chip.
  • Each semiconductor package contains one or more dies (for example one, two, or four). The die is the smallest unit that can independently execute commands or report status.
  • Each die contains one or more planes (typically one or two). Identical, concurrent operations can take place on each plane, although with some restrictions.
  • Each plane contains a number of blocks, which are the smallest unit that can be erased in a single erase operation.
  • Each block contains a number of pages, which are the smallest unit that can be programmed, i.e., a smallest unit on which a read operation can be performed.
  • an optional sacrificial liner layer (such as a thin silicon oxide layer) and a sacrificial fill material can be deposited in the memory openings 49 and in the support openings 19.
  • the sacrificial fill material may comprise a carbon-based material (such as amorphous carbon or diamond-like carbon), a semiconductor material such as amorphous silicon or silicon-germanium), a polymer material, or a dielectric material (such as organosilicate glass or borosilicate glass). Excess portions of the sacrificial fill material may be removed from above the horizontal plane including the top surface of the topmost insulating layer 32T.
  • the support openings 19 can be formed at a later step at the same time as the memory openings, and the support pillar structures 20 can be formed in the support openings 19 at the same time as the memory opening fill structures are formed in the memory openings, as will be described below.
  • FIG. 7A a memory opening 49 is illustrated after the processing steps of FIG. 6.
  • a layer stack including a memory material layer 54 can be conformally deposited.
  • the layer stack may comprise an optional blocking dielectric layer 52, the memory material layer 54, and an optional dielectric liner 56.
  • the memory material layer 54 includes a memory material, i.e., a material that can store data bits therein.
  • the memory material layer 54 may comprise a charge storage material (such as silicon nitride), a ferroelectric material, a phase change memory material, or any other memory material that can store data bits by inducing a change in the electrical resistivity, ferroelectric polarization, or any other measurable physical property.
  • the optional dielectric liner 56 may comprise a tunneling dielectric layer.
  • a dielectric core layer 62L comprising a dielectric fill material, such as silicon oxide, can be deposited in remaining volumes of the memory openings 49. While the dielectric core layer 62L can be deposited employing a conformal deposition process, such as a chemical vapor deposition process, the conformity of the conformal deposition process may not be perfect. Thus, the thickness of a bottom portion of the dielectric core layer 62L at the bottom of each memory opening 49 may be less than the thickness of an upper portion of the dielectric core layer 62L at the top of each memory opening 49. [0149] Referring to FIG.
  • a doped semiconductor material having a doping of a second conductivity type can be deposited within each recessed region above the dielectric cores 62.
  • the second conductivity type is the opposite of the first conductivity type.
  • the dopant concentration in the deposited semiconductor material can be in a range from 5 x 10 18 /cm 3 to 2 x 10 21 /cm 3 , although lesser and greater dopant concentrations can also be employed.
  • the doped semiconductor material can be, for example, doped polysilicon.
  • Each portion of the layer stack including the memory material layer 54 that remains in a respective memory opening 49 constitutes a memory film 50.
  • a memory film 50 may comprise an optional blocking dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56.
  • Each contiguous combination of a memory film 50 and a vertical semiconductor channel 60 constitutes a memory stack structure 55.
  • Each combination a memory stack structure 55, a dielectric core 62, and a drain region 63 within a memory opening 49 constitutes a memory opening fill structure 58.
  • Each memory opening fill structure 58 comprises a respective vertical stack of memory elements, which may comprise portions of the memory material layer 54 located at levels of the sacrificial material layers 42, or generally speaking, at levels of spacer material layers that may be formed as, or may be subsequently replaced at least partly with, electrically conductive layers.
  • the support pillar structures 20 may be formed in the support openings 19 at the same time as the memory opening fill structures 58 are formed in the memory openings 49. In this case, the support pillar structures 20 comprise dummy memory opening fill structures having the same materials as the memory opening fill structures 58.
  • An anneal process can be performed to activate electrical dopants in the drain region 63 and in the vertical semiconductor channel 60.
  • any amorphous semiconductor material e.g., amorphous silicon
  • a polycrystalline semiconductor material e.g., polysilicon
  • Each of the lateral isolation trenches 79 may comprise a respective pair of lengthwise sidewalls that are parallel to the first horizontal direction hdl and vertically extend from the top surface of the contactlevel dielectric layer 80 to the top surface of the carrier substrate 9.
  • a surface of the carrier substrate 9 can be physically exposed underneath each lateral isolation trench 79.
  • the photoresist layer can be subsequently removed, for example, by ashing.
  • an etchant that selectively etches the material of the sacrificial material layers 42 with respect to the material of the insulating layers 32 can be introduced into the lateral isolation trenches 79, for example, employing an isotropic etch process. Lateral recesses 43 are formed in volumes from which the sacrificial material layers 42 are removed. The removal of the sacrificial material layers 42 can be selective to the materials of the insulating layers 32, the stepped dielectric material portion 65, and the material of the outermost layer of the memory films 50.
  • the sacrificial material layers 42 can include silicon nitride, and the materials of the insulating layers 32 and the stepped dielectric material portion 65 can include silicon oxide.
  • the etch process that removes the second material selective to the first material and the outermost layer of the memory films 50 can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the lateral isolation trenches 79.
  • the etch process can be a wet etch process in which the first exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art.
  • the support pillar structure 20, the stepped dielectric material portion 65, and the memory stack structures 55 provide structural support while the lateral recesses 43 are present within volumes previously occupied by the sacrificial material layers 42.
  • Each of the plurality of lateral recesses 43 can extend substantially parallel to the top surface of the carrier substrate 9.
  • a lateral recess 43 can be vertically bounded by a top surface of an underlying insulating layer 32 and a bottom surface of an overlying insulating layer 32.
  • each lateral recess 43 can have a uniform height throughout.
  • an outer blocking dielectric layer (not expressly illustrated) can be optionally formed.
  • the outer blocking dielectric layer if present, comprises a dielectric material that functions as a control gate dielectric for the control gates to be subsequently formed in the lateral recesses 43. In case the blocking dielectric layer 52 is present within each memory opening, the outer blocking dielectric layer is optional.
  • a metal fill material is deposited in the plurality of lateral recesses 43, on the sidewalls of the at least one the lateral isolation trench 79, and over the top surface of the contact-level dielectric layer 80 to form a metallic fill material layer.
  • the metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof.
  • the metallic fill material layer can consist essentially of at least one elemental metal.
  • the at least one elemental metal of the metallic fill material layer can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum.
  • a plurality of electrically conductive layers 46 can be formed in the plurality of lateral recesses 43, and a continuous metallic material layer can be formed on the sidewalls of each lateral isolation trench 79 and over the contact-level dielectric layer 80.
  • Each electrically conductive layer 46 includes a portion of the metallic barrier layer and a portion of the metallic fill material layer that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers 32.
  • the continuous metallic material layer includes a continuous portion of the metallic barrier layer and a continuous portion of the metallic fill material layer that are located in the lateral isolation trenches 79 or above the contact-level dielectric layer 80.
  • the deposited metallic material of the continuous electrically conductive material layer is etched back from the sidewalls of each lateral isolation trench 79 and from above the contact-level dielectric layer 80 by performing an isotropic etch process that etches the at least one conductive material of the continuous electrically conductive material layer.
  • Each remaining portion of the deposited metallic material in the lateral recesses 43 constitutes an electrically conductive layer 46.
  • Each electrically conductive layer 46 can be a conductive line structure.
  • the sacrificial material layers 42 are replaced with the electrically conductive layers 46.
  • the electrically conductive layers 46 can be formed by providing a metallic precursor gas into the lateral isolation trenches 79 and into the lateral recesses 43.
  • At least one uppermost electrically conductive layer 46 may comprise a drain side select gate electrode. At least one bottommost electrically conductive layer 46 may comprise a source side select gate electrode. The remaining electrically conductive layers 46 may comprise word lines. Each word line functions as a common control gate electrode for the plurality of vertical NAND strings (e.g., memory opening fill structures 58).
  • a dielectric fill material such as silicon oxide can be deposited in the lateral isolation trenches 79. Excess portions of the dielectric fill material can be removed from above the contact-level dielectric layer 80. Each remaining portion of the dielectric fill material that fills a respective one of the lateral isolation trenches 79 constitutes a lateral isolation trench fill structure 76, which may be a dielectric wall structure.
  • an insulating spacer having a tubular configuration can be formed in peripheral portions of each of the lateral isolation trenches 79, and a through-stack conductive via structure may be formed within a respective one of the insulating spacers.
  • each lateral isolation trench fill structure 76 may comprise a combination of a through-stack conductive via structure and an insulating spacer that laterally surrounds the through-stack conductive via structure.
  • Contact via structures (88, 86) can be formed through the contact-level dielectric layer 80, and optionally through the stepped dielectric material portion 65.
  • drain contact via structures 88 can be formed through the contact-level dielectric layer 80 on each drain region 63.
  • Layer contact via structures 86 can be formed on the electrically conductive layers 46 through the contact-level dielectric layer 80, and through the stepped dielectric material portion 65.
  • additional dielectric material layers and additional metal interconnect structures can be formed over the contact-level dielectric layer 80.
  • the additional dielectric material layers may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and/or at least one additional line-and-via-level dielectric layer.
  • the additional metal interconnect structures may comprise metal via structures, metal line structures, and/or integrated metal line-and-via structures.
  • the additional dielectric material layers that are formed above the contact-level dielectric layer 80 are herein referred to as memory-side dielectric material layers 960.
  • the additional metal interconnect structures are collectively referred to as memory-side dielectric material layers 960.
  • the memory-side dielectric material layers 960 comprise a bit-line-level dielectric material layer embedding bit lines, which are a subset of the memory-side metal interconnect structures 980.
  • the memory die 900 may comprise: a three-dimensional memory array underlying the first dielectric material layer 110 and comprising an alternating stack (32, 46) of insulating layers 32 and electrically conductive layers 46, a two-dimensional array of memory openings 49 vertically extending through the alternating stack (32, 46), and a two-dimensional array of memory opening fill structures 58 located in the two-dimensional array of memory openings 49 and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel 60; and a two-dimensional array of contact via structures (such as the drain contact via structures 88) overlying the three-dimensional memory array and electrically connected to a respective one of the vertical semiconductor channels 60.
  • a three-dimensional memory array underlying the first dielectric material layer 110 and comprising an alternating stack (32, 46) of insulating layers 32 and electrically conductive layers 46, a two-dimensional array of memory openings 49 vertically extending through the alternating stack (32, 46), and a two-dimensional array of memory opening fill structures 58 located in the
  • the peripheral circuit 720 can be configured to control operation of the vertical stack of memory elements in the memory array in the memory die 900.
  • the logic die 700 can be attached to the memory die 900, for example, by bonding the logic-side bonding pads 788 to the memory-side bonding pads 988 at a bonding interface.
  • the bonding between the memory die 900 and the logic die 700 may be performed employing a wafer-to-wafer bonding process in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700, by a die-to- bonding process, or by a die-to-die bonding process.
  • the logic-side bonding pads 788 within each logic die 700 can be bonded to the memory-side bonding pads 988 within a respective memory die 900.
  • the carrier substrate 9 can be removed, for example, by grinding, polishing, cleaving, an isotropic etch process, an anisotropic etch process, and/or a combination thereof. If a chemical mechanical polishing process or an etch process is employed as a terminal step for removing the carrier substrate 9, the bottommost insulating layer 32B may be employed as a polish stop or etch stop, respectively.
  • At least a terminal step of at least one removal process that is employed to remove the carrier substrate 9 may comprise a selective wet etch process that etches the material of the carrier substrate 9 (such as a semiconductor material of the carrier substrate 9) selective to dielectric materials of the memory films 50.
  • the terminal step of the at least one removal process may comprise a wet etch process using hot trimethyl-2 hydroxy ethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH).
  • hot TMY hot trimethyl-2 hydroxy ethyl ammonium hydroxide
  • TMAH tetramethyl ammonium hydroxide
  • a horizontal surface of a remaining portion of the bottommost electrically conductive layer 46B within the alternating stack (32, 46) can be physically exposed.
  • the bottommost layer of the alternating stack (32, 46) comprises the bottommost insulating layer 32B, and the bottommost insulating layer 32B can be completely removed after removing the carrier substrate 9. All surfaces of remaining material portions on the backside of the alternating stack (32, 46) can be located within a horizontal plane. If the outer blocking dielectric layers 44, such as aluminum oxide outer blocking dielectric layers 44 are present in the memory device, then a portion of the outer blocking dielectric layer 44 remains between the bottommost electrically conductive layer 46B and the neighboring insulating layer 32 in the alternating stack (32, 46).
  • each electrically conductive layer 46 within the alternating stack (32, 46) consists of a same set of at least one metallic material. In one embodiment, if a portion of the bottommost electrically conductive layer 46B is removed during the chemical mechanical polishing step, then all electrically conductive layers 46 within the alternating stack (32, 46) except the bottommost electrically conductive layer 46B have a first vertical thickness, and the bottommost electrically conductive layer 46B has a second vertical thickness that is less than the first vertical thickness.
  • an etch process can be performed to remove the material of the dielectric cores 62 selective to the materials of the vertical semiconductor channels 60, the memory films 50, and the bottommost electrically conductive layer 46.
  • a wet etch process employing dilute hydrofluoric acid can be performed to vertically recess bottom portions of the dielectric cores 62.
  • the duration of the etch process can be selected such that the vertically recessed horizontal surface of each dielectric core 62 is formed at the bottommost one of the insulating layers 32 that remain in the alternating stack (32, 46) or above the bottommost remaining one of the insulating layers 32 (i.e., past the bottommost remaining one of the insulating layers 32 in the direction of the source region 63).
  • a recess cavity 21 can be formed in each volume from which the material of the dielectric cores 62 is removed.
  • a cylindrical surface segment of an inner sidewall of each vertical semiconductor channel 60 can be physically exposed upon vertically recessing the bottom portions of the dielectric cores 62 and formation of the recess cavities 21.
  • the recess cavity 21 may extend above (in the direction of the source region 63) the second from the bottom electrically conductive layer 46 in the alternating stack (32, 46).
  • the source layer 22 comprises a metallic barrier liner 22B comprising a conductive metallic nitride material in direct contact with each of the bottommost electrically conductive layer 46B, the memory film 50, and the vertical semiconductor channel 60, and a metal layer 22M consisting essentially of an elemental metal and underlying the metallic barrier liner 22B.
  • the source layer 22 can be patterned into one or more portions that are connected to the bottommost electrically conductive layer 46B.
  • Each patterned source layer 22 comprises a Schottky source structure providing a Schottky junction to a respective set of vertical semiconductor channels 60.
  • a second exemplary structure according to a second embodiment of the present disclosure can be derived from the first exemplary structure illustrated in FIG. 1 by forming a layer stack including a planar dielectric layer 102, a stopper di electric layer 104, and a semiconductor material layer 106 on a top surface the carrier substrate 9 prior to formation of an alternating stack (32, 42) of insulating layers 32 and sacrificial material layers 42.
  • the planar dielectric layer 102 comprises a dielectric material, such as undoped silicate glass (e.g., silicon oxide) or doped silicate glass, and may have a thickness in the range from 30 nm to 300 nm, although lesser and greater thicknesses may also be employed.
  • the stopper dielectric layer 104 comprises a dielectric material different from that of the planar dielectric layer 102 that may be employed as a stopper material during a subsequent planarization process.
  • the stopper dielectric layer 104 comprises silicon nitride or a dielectric metal oxide, and may have a thickness in the range from 30 nm to 300 nm, although lesser and greater thicknesses may also be employed.
  • the semiconductor material layer 106 comprises a semiconductor material such as silicon (e.g., amorphous silicon or polysilicon) or silicon germanium.
  • the semiconductor material layer 106 may be doped with electrical dopants of a second conductivity type (e.g., n-type dopants, such as phosphorus and/or arsenic), which is the opposite of a first conductivity type that is employed to dope vertical semiconductor channels.
  • the atomic concentration of dopants of the second conductivity type in the semiconductor material layer 106 may be in the range from 5.0 x 10 18 /cm 3 to 2.0 x 10 21 /cm 3 , although lesser and greater atomic concentrations may also be employed.
  • the processing steps described with reference to FIGS. 2 - 8B can be subsequently performed.
  • the chemistry of the anisotropic etch process employed to form the memory openings 49 and the support openings 19 may be modified as needed in view of the presence of the layer stack of the semiconductor material layer 106, the stopper dielectric layer 104, and the planar dielectric layer 102.
  • bottom surfaces of the memory openings 49 and the support openings 19 may formed in an upper portion of the carrier substrate 9.
  • bottom surfaces of the memory opening fill structures 58 and the support pillar structures 20 may formed in an upper portion of the carrier substrate 9.
  • the processing steps described with reference to FIGS. 9A and 9B can be performed to form a contact-level dielectric layer 80, and to form lateral isolation trenches 79.
  • the semiconductor material layer 106 may be employed as an etch stop layer during formation of the lateral isolation trenches 79, such that the isolation trenches 79 do not extend all the way through the semiconductor material layer 106 and do not reach the stopper dielectric layer 104,.
  • FIGS. 25A - 25G are sequential vertical cross-sectional views of a region of the second exemplary structure during formation of a Schottky source structure according to the second embodiment of the present disclosure.
  • a sequence of selective etch processes can be performed to remove a physically exposed end portion of the memory film 50 selective to the vertical semiconductor channel 60 in each memory opening fill structure 58.
  • the sequence of selective etch processes may comprise a first selective etch process that etches the material of the blocking dielectric layer 52 selective to the material of the memory material layer 54, a second selective etch process that etches the material of the memory material layer 54 selective to the material of the dielectric liner 56, and a third selective etch process that etches the material of the dielectric liner 56 selective to the material of the vertical semiconductor channel 60.
  • a surface portion of the planar dielectric layer 102 can be collaterally recessed during removal of the physically exposed to end portion of each memory film 50.
  • the source layer 22 contacts the inner sidewall of the vertical semiconductor channel 60 and the bottom surface of the semiconductor material layer 106 underlying the alternating stack (32, 46).
  • the semiconductor material layer 106 contacts an outer sidewall of the memory film 50 and does not directly contact the vertical semiconductor channel 60.
  • the processing steps described with reference to FIGS. 10 - 13 can be performed to replace the sacrificial material layers 42 with electrically conductive layers 46.
  • Various contact via structures (88, 86) can be formed, and memory-side dielectric material layers 960 embedding memory-side metal interconnect structures 980 and memoryside bonding pads 988 can be formed.
  • a memory die 900 can be provided.
  • the processing steps described with reference to FIGS. 14 and 15 can be performed to provide a logic die 700, and to bond the logic die 700 to the memory die 900.
  • an isotropic etch process can be performed to remove the remaining portion of the planar dielectric layer 102 selective to the semiconductor materials of the semiconductor material layer 106 and the vertical semiconductor channels 60.
  • a wet etch process employing dilute hydrofluoric acid can be performed to remove the planar dielectric layer 102.
  • the bottom surface of the semiconductor material layer 106 can be exposed upon removal of the planar dielectric layer 102.
  • a chemical mechanical polishing process can be performed to remove portions of the memory opening fill structures 58 that protrude below the horizontal plane including the bottom surface of the semiconductor material layer 106.
  • the end portion of each dielectric core 62 that underlies the horizontal plane including the planar bottom surface of the semiconductor material layer 106 can be removed by the chemical mechanical polishing process.
  • each memory film 50 comprises an outer sidewall that contacts a cylindrical surface segment of the semiconductor material layer 106, and an annular planar bottom surface that contacts the source layer 22.
  • the source layer 22 contacts a cylindrical surface segment of an inner sidewall of the memory film 50.
  • a horizontal surface segment of the contact area between the source layer 22 and the vertical semiconductor channel 60 may be located within a horizontal plane including a horizontal interface between the source layer 22 and the semiconductor material layer 106.
  • an annular bottom surface of each memory film 50 contacts the source layer 22 within the horizontal plane including a bottom surface of the semiconductor material layer 106.
  • the source layer 22 can be patterned as described above.
  • the patterned source layer 22 comprises a Schottky source structure providing Schottky junctions to a respective set of vertical semiconductor channels 60.
  • a backside dielectric layer 26 can be deposited over the source layer 22. At least one source contact structure 6 is formed through the backside dielectric layer 26 in contact with the source layer 22.
  • a photoresist layer (not shown) can be formed over the planar dielectric layer 202, and can be lithographically patterned to form openings therein.
  • the pattern of the openings in the photoresist layer can be the same as the pattern of the memory openings 49 as described above.
  • the openings in the photoresist layer may have a greater lateral dimension (e.g., a diameter) than the lateral dimension of memory openings 49 to be subsequently formed.
  • An anisotropic etch process can be performed to transfer the pattern of the openings in the photoresist layer through the planar dielectric layer 202.
  • An array of cavities 15 can be formed in the planar dielectric layer 202.
  • the carrier substrate 9 comprises a first semiconductor material, such as single crystal silicon
  • the first sacrificial pedestals 11 comprise the same first semiconductor material, such as single crystal silicon.
  • the first sacrificial pedestals 11 may be formed by performing a selective deposition process such as a selective epitaxy process, or may be formed by a non-conformal semiconductor deposition process followed by a planarization process that removes a deposited semiconductor material from above the horizontal plane including the top surface of the planar dielectric layer 202 and by vertically recessing the semiconductor material below the horizontal plane including the top surface of the planar dielectric layer 202.
  • each first sacrificial pedestal 11 may be in a range from 20 % to 80 % of the thickness of the planar dielectric layer 202.
  • a second pedestal material can be deposited in remaining unfilled volumes of the cavities 15.
  • the second pedestal material comprises a sacrificial material that may be subsequently removed selective to the materials of the first sacrificial pedestals 11 and the planar dielectric layer 202.
  • the second pedestal material may comprise a carbon-based material, such as amorphous carbon or diamond-like carbon.
  • the second pedestal material may comprise an electrically conductive material, such as TiN or W.
  • Excess portions of the second pedestal material can be removed from above the horizontal plane including the top surface of the planar dielectric layer 202 by a planarization process, which may comprise a recess etch process or a chemical mechanical polishing process. Remaining portions of the second pedestal material constitute second sacrificial pedestals 13. A stack of a first sacrificial pedestal 11 and a second sacrificial pedestal 13 can be formed in each cavity 15.
  • each second sacrificial pedestal 13 may have a greater lateral dimension than a bottom portion of a memory opening to be subsequently formed. In one embodiment, each second sacrificial pedestal 13 may have a height that is greater than twice the sum of the thickness of a memory film to be subsequently formed and the thickness of a semiconductor channel to be subsequently formed.
  • each stack of a first sacrificial pedestal 11 and a second sacrificial pedestal 13 can be provided by forming an opening (i.e., a cavity 15) through the planar dielectric layer 202, by forming the first sacrificial pedestal 11 in a lower portion of the opening, and by forming the second sacrificial pedestal 13 in an upper portion of the opening.
  • the processing steps described with reference to FIG. 1 can be performed to form the alternating stack of insulating layers 32 and sacrificial material layers 42, and to form the drain-select-level isolation structures 72.
  • the processing steps described with reference to FIG. 2 can be performed to form stepped surfaces and a stepped dielectric material portion 65.
  • the processing steps described with reference to FIGS. 3A and 3B can be performed to form the memory openings 49 and support openings 19.
  • a terminal portion of the anisotropic etch process that forms the memory openings 49 and the support openings 19 may be selective to the material of the second sacrificial pedestals 13, such that the second sacrificial pedestals 13 are exposed at the bottom of the respective memory openings 49.
  • the second sacrificial pedestals 13 function as etch stop structures during the etch process.
  • the second sacrificial pedestals 13 can be removed selective to the first sacrificial pedestals 11, the alternating stack (32, 42), and the planar dielectric layer 202.
  • the second sacrificial pedestals 13 comprise a carbon-based material, such as amorphous carbon
  • an ashing process can be performed to remove the second sacrificial pedestals 13.
  • the second sacrificial pedestals 13 comprise an electrically conductive material, such as TiN or W
  • a selective wet etch process using an acid mixture can be performed to remove the second sacrificial pedestals 13.
  • the memory openings 49 are vertically extended by adding the volumes of the voids from which the second sacrificial pedestals 13 are removed.
  • Expanded memory openings 49’ can be formed by expanding the memory openings 49 through removal of the second sacrificial pedestals 13 selective to the first sacrificial pedestals 11.
  • Each of the expanded memory openings 49’ may have a respective bottom portion located at the level of the planar dielectric layer 202 and having a greater lateral dimension than a cylindrical portion of the expanded memory opening 49’ that vertically extends through the alternating stack (32, 42).
  • FIGS. 41 A and 41B the processing steps described with reference to FIGS. 4 and 5 can be performed to form the support pillar structures in the support openings 19. Subsequently, the processing steps described with reference to FIGS. 6, 7A - 7F, and 8A and 8B can be performed to form the memory opening fill structures 58 in the expanded memory openings 49’.
  • each bottom portion of the expanded memory opening 49’ embedded in the planar dielectric layer 202 may have a greater lateral dimension than a bottom portion of the overlying cylindrical portion of the expanded memory opening 49’ that vertically extends through the alternating stack (32, 42).
  • each bottom portion of the expanded memory opening 49’ may have a height that is greater than twice the sum of the thickness of a memory film 50 and the thickness of a semiconductor channel 60.
  • the dielectric core 62 of each memory opening fill structure 58 may have a hammerhead configuration in which a bottom plate portion 62P of the dielectric core 62 has a greater lateral dimension than an overlying cylindrical portion of the dielectric core 62.
  • each memory opening fill structure 58 may have a hammerhead configuration, in which a hammerhead portion 58H of the memory opening fill structure 58 is embedded in the planar dielectric layer 202 and has a greater lateral dimension than an overlying cylindrical portion of the memory opening fill structure 58.
  • the hammerhead portion 58H of each memory opening fill structure 58 may comprise a circular disc portion 50D of a memory film 50, a substantially vertical tubular portion 50T of the memory film 50, and a horizontal annular portion 50H of the memory film 50. Further, the hammerhead portion 58H of each memory opening fill structure 58 may comprise a circular disc portion 60D of a semiconductor channel 60, a substantially vertical tubular portion 60T of the semiconductor channel 60, and a horizontal annular portion 60H of the semiconductor channel 60. In addition, the hammerhead portion 58H of each memory opening fill structure 58 may comprise a plate portion 62P of a dielectric core 62.
  • the processing steps described with reference to FIGS. 9 A and 9B can be performed to form a contact-level dielectric layer 80, and to form lateral isolation trenches 79.
  • the carrier substrate 9 may be employed as an etch stop structure during formation of the lateral isolation trenches 79.
  • the processing steps described with reference to FIGS. 16A and 16B can be performed to remove the carrier substrate 9 and the first sacrificial pedestals 11 selective to the planar dielectric layer 202 and selective to the memory films 50 of the memory opening fill structures 58.
  • the carrier substrate 9 and the first sacrificial pedestals 11 may be removed selective to the planar dielectric layer 202 and the memory film 50 by performing a selective etch process.
  • Cavities 201 are formed in the volumes from which the first sacrificial pedestals 11 are removed.
  • FIGS. 45A - 45C are sequential vertical cross-sectional views of a region of the fourth exemplary structure during formation of a Schottky source structure according to the fourth embodiment of the present disclosure.
  • a sequence of selective etch processes can be performed to remove a physically exposed end portion of the memory film 50 selective to the semiconductor channel 60 in each memory opening fill structure 58.
  • the sequence of selective etch processes may comprise a first selective etch process that etches the material of the blocking dielectric layer 52 selective to the material of the memory material layer 54, a second selective etch process that etches the material of the memory material layer 54 selective to the material of the dielectric liner 56, and a third selective etch process that etches the material of the dielectric liner 56 selective to the material of the semiconductor channel 60. These steps remove the disc portion 50D of the memory film 50.
  • an isotropic etch process can be performed to remove a physically exposed end portion of each semiconductor channel 60.
  • a wet etch process employing hot trimethyl-2 hydroxy ethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) may be performed to remove the physically exposed end portion of each semiconductor channel 60. End surfaces of dielectric cores 62 can be exposed. This step removes the disc portion 60D of the semiconductor channel 60.
  • hot TMY hot trimethyl-2 hydroxy ethyl ammonium hydroxide
  • TMAH tetramethyl ammonium hydroxide
  • an etch process can be performed to vertically recess the dielectric material of the dielectric core 62 selective to the semiconductor material of the semiconductor channels 60.
  • the duration of the etch process can be selected such that recessed surfaces of the dielectric cores 62 are formed at or about the level of an insulating layer 32 that is more distal from the planar dielectric layer 202 than the bottommost electrically conductive layer 46B is from the planar dielectric layer 202.
  • the etch process also collaterally etches the planar dielectric layer 202.
  • the duration of the anisotropic etch process can be selected such that the planar dielectric layer 202 is not completely removed by the anisotropic etch process.
  • a physically exposed planar surface of the planar dielectric layer 202 may protrude farther outward than the remaining portions (e.g., the tubular portions 60T) of the semiconductor channels 60.
  • the combination of the planar dielectric layer 202 and the memory films 50 may have tapered sidewalls each laterally surrounding an end portion of a respective one of the semiconductor channels 60.
  • each tapered sidewall of the combination of the planar dielectric layer 202 and the memory films 50 may be in a range from 0.5 degree to 10 degrees, although lesser and greater taper angles may also be employed.
  • the blocking dielectric 52 and the tunneling dielectric 56 may also be collaterally recessed during the etch process if they comprise the same material as the dielectric core 62.
  • the primary tubular portion 60P contains the upper portion of the semiconductor channel 60 and also laterally surrounds the dielectric core 62.
  • the tubular base portion 60T extends vertically or substantially vertically (e.g., within 10 degrees of a vertical direction which is parallel to a central axis of the memory opening fill structure 58).
  • Each memory film 50 comprises: a primary tubular portion 50P that vertically extends through the alternating stack (32, 46); a horizontal annular portion 50H adjoined to a bottom end of the primary tubular portion 50P and contacting a bottom surface of the bottommost insulating layer 32B; and a tubular base portion 50T adjoined to an outer periphery of the horizontal annular portion 50T and having a tapered annular surface.
  • an anisotropic etch process can be performed to etch the materials of the memory films 50 selective to the materials of the metal capping layers 360 and selective to the material of the etch-stop dielectric layer 302 to further recess the memory films 50 and to expand the recess cavities 68 upward.
  • the anisotropic etch process may comprise a reactive ion etch process employing a fluorine-based etchant gas (such as CF4 or CHF3) as an etchant gas.
  • Recessed end surfaces of the memory films 50 may be formed at or around the level of an insulating layer 32 that is more distal from the etchstop dielectric layer 302 than the bottommost electrically conductive layer 46B is from the etch-stop dielectric layer 302.
  • Each recess cavity 68 may have an azimuthal extent around a vertical axis VA passing through a geometrical center GC of the memory opening fill structure 58, the azimuthal extent being not greater than 3TT/2.
  • an insulating material layer can be conformally deposited in the recess cavities 68 around the metal capping layers 360 and over the etch-stop dielectric layer 302.
  • the insulating material layer includes an insulating material, such as undoped silicate glass or a doped silicate glass.
  • the thickness of the insulating material layer can be greater than one half of the lateral distance between an inner sidewall and an outer sidewall of each recess cavity 68.
  • the entirety of each recess cavity 68 can be filled with the insulating material layer.
  • An isotropic etch process can be performed to remove portions of the insulating material layer that are located outside the recess cavities 68. Remaining portions of the insulating material layer that fill the recess cavities constitute the insulating spacers 312.
  • the insulating spacer 312 has a first azimuthal extent around a vertical axis VA passing through a geometrical center GC of the memory opening fill structure 58, the first azimuthal extent being not greater than 3TT/2.
  • the bottom surfaces of the memory film 50 contacts sidewalls of the insulating spacer 312.
  • a continuous source layer 22L can be formed directly on each metal capping layer 360, and on the physically-exposed surfaces of the insulating spacers 312 and the memory films 50 in the strip-shaped cavities 303, and on the physically- exposed surfaces the etch-stop dielectric layer 302.
  • the continuous source layer 22L comprises an elemental metal (such as W, Co, Cu, Ru, Mo, Ti, Ta, etc.).
  • the continuous source layer 22L may comprise the same metal (e.g., tungsten) as the metal capping layer 360.
  • the thickness of a planar portion of the metal layer 22M may be in a range from 30 nm to 300 nm, although lesser and greater thicknesses may also be employed.
  • a chemical mechanical polishing process can be performed to remove portions of the continuous source layer 22L located below the etch-stop dielectric layer 302, which acts as a polish stop layer.
  • portions of the continuous source layer 22L that are more distal from the alternating stack (32, 46) than the distal horizontal surface of the etch-stop dielectric layer 302 are removed.
  • Each remaining portion of the continuous source layer 22L that fills the volume of a respective strip-shaped cavity constitutes the source layer 22, which is also referred to as a source strip.
  • the distal planar surfaces of the source layers 22 may be coplanar with the distal planar surface of the etch-stop dielectric layer 302.
  • Each source layer 22 may contact surfaces of a respective pair of rows of metal capping layers 360, and contacts a horizontal bottom surface of the etch-stop dielectric layer 302 located between the pair of rows of the metal capping layers 360 (i.e., the bottom surface that is more proximal to the alternating stack (32, 46) than the distal horizontal surface of the etch-stop dielectric layer 302 is to the alternating stack (32, 46)).
  • Each source layer 22 is embedded within the etch-stop dielectric layer 302. The bottommost surface of the etch-stop dielectric layer 302 may be coplanar with the bottom surface of each source layer 22.
  • each memory opening fill structure 58 comprises a dielectric core 62 that is laterally surrounded by a vertical semiconductor channel 60.
  • a metal capping layer 360 located on the memory opening fill structure 58 may comprise residual silicon atoms at a variable atomic concentration that decreases with a distance from an interface with the dielectric core 62.
  • a bottom surface of the metal capping layer 360 is located below a horizontal plane including a horizontal interface between the source layer 22 and the etch-stop dielectric layer 302, and a top surface of the metal capping layer 360 is located above the horizontal plane.
  • each of the electrically conductive layers 46 is embedded within a respective outer blocking dielectric layer 44.
  • the etch-stop dielectric layer 302 is in direct contact with a horizontally-extending portion of a bottommost outer blocking dielectric layer 44.
  • an insulating spacer 312 may be in contact with the metal capping layer 360, the bottommost outer blocking dielectric layer 44, a bottommost insulating layer 32B within the alternating stack (32, 46), the vertical semiconductor channel 60, and the memory film 50.
  • FIG. 63G is a vertical cross-sectional view of a region of an alternative configuration of the seventh exemplary structure according to the seventh embodiment of the present disclosure. The alternative configuration illustrated in FIG.
  • 63 G may be derived from the seventh exemplary structure by forming a bottommost insulating layer 32B as the first layer of an alternating stack of insulating layers 32 and sacrificial material layers 42 at the processing steps of FIG. 59.
  • the etch-stop dielectric layer 302 may contact either the bottommost insulating layer 32B or the bottommost electrically conductive layer 46B in the alternating stack (32, 46).
  • the seventh exemplary structure is illustrated after the processing steps of FIG. 63F or after the processing steps of FIG. 64G.
  • the source layer 22 comprises a source layer strip which contacts two rows of metal capping layers 360 which contact two rows of memory opening fill structures 58 in a first memory block; the first memory block contains two source layer strips 22; a first source line 6 electrically contacts the two source layer strips 22 in the first memory block; and a second source line 6 different from the first source line 6 electrically contacts additional source layer strips 22 in second memory block which is located laterally adjacent to the first memory block.
  • the various embodiments of the present disclosure can be employed to provide a source structure including a Schottky source contact structure for a three-dimensional memory device.
  • the metal-semiconductor contact between each vertical semiconductor channel 60 and a source layer 22 or a metal capping layer 360 provides a Schottky contact, which provides a larger hole current to the vertical semiconductor channel 60 than a comparable Ohmic contact, during a GIDL erase step.
  • an eighth exemplary structure according to an eighth embodiment of the present disclosure can be derived from the first exemplary structure described with reference to FIG. 1 by increasing the thickness of the bottommost insulating layer 32B.
  • the thickness of the bottommost insulating layer 32B may be in a range from 30 nm to 300 nm, such as from 50 nm to 200 nm, although lesser and greater thicknesses may also be employed.
  • FIGS. 68 A and 68B the processing steps described with reference to FIGS. 3A and 3B can be performed to form memory openings 49 and support openings 19.
  • FIGS. 72 A - 72F are sequential vertical cross-sectional views of a memory opening 49 during formation of a memory opening fill structure 58 according to an embodiment of the present disclosure.
  • the processing steps described with reference to FIG. 36 can be performed to form sacrificial pedestals 11 in a bottom region of each memory opening 49.
  • the sacrificial pedestals 11 comprise a pedestal material, which is a material that can be subsequently removed selective to the material of the bottommost insulating layer 32B and selective to materials of memory films to be subsequently formed.
  • the sacrificial pedestals 11 may comprise and/or may consist essentially of a semiconductor material such as silicon or silicon-germanium.
  • the carrier substrate 9 comprises a first semiconductor material, such as single crystal silicon, and the sacrificial pedestals 11 comprise the same semiconductor material, such as single crystal silicon.
  • the semiconductor channel material layer 60L comprises atoms of dopants of the first conductivity type at a first atomic concentration that is less than 3 x 10 16 /cm 3 , and/or less than 1 x 10 16 /cm 3 , and/or less than 3 x 10 15 /cm 3 , and/or less than 1 x 10 15 /cm 3 .
  • the semiconductor channel material layer 60L comprises a p-type polysilicon or amorphous silicon layer doped with boron atoms at a concentration of 1 x 10 14 /cm 3 to 2 x 10 16 /cm 3 .
  • each portion of the layer stack including the memory material layer 54 that remains in a respective memory opening 49 constitutes a memory film 50.
  • a memory film 50 may comprise an optional blocking dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56.
  • Each contiguous combination of a memory film 50 and a vertical semiconductor channel 60 constitutes a memory stack structure 55.
  • Each combination a memory stack structure 55, a dielectric core 62, and a drain region 63 within a memory opening 49 constitutes a memory opening fill structure 58.
  • FIGS. 74A and 73B the processing steps described with reference to FIGS. 9A and 9B can be performed to form a contact-level dielectric layer 80 and lateral isolation trenches 79.
  • the processing steps described with reference to FIG. 10 can be performed to form laterally-extending cavities 43.
  • the processing steps described with reference to FIG. 11 can be performed to form electrically conductive layers 46 in the laterally-extending cavities 43.
  • an alternating stack (32, 46) of insulating layers 32 and spacer material layers can be over a carrier substrate 9.
  • the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers 46.
  • a memory opening 49 can be formed through the alternating stack of insulating layers 32 and spacer material layers, and a memory opening fill structure 58 including a vertical stack of memory elements and a vertical semiconductor channel 60 can be formed in the memory opening 49.
  • FIGS. 77A and 77B the processing steps described with reference to FIGS. 12A and 12B can be performed to form lateral isolation trench fill structures 76, layer contact via structures 86, and drain contact via structures 88.
  • FIG. 80 the processing steps described with reference to FIG. 15 can be performed to bond the logic die 700 to the memory die 900.
  • At least a terminal step of at least one removal process that is employed to remove the carrier substrate 9 may comprise a selective wet etch process that etches the material of the carrier substrate 9 (which may be a semiconductor material) and the semiconductor material of the sacrificial pedestals 11 selective to dielectric materials of the memory films 50.
  • the terminal step of the at least one removal process may comprise a wet etch process using hot trimethyl-2 hydroxy ethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH), which etches semiconductor materials selective to insulating materials.
  • hot TMY hot trimethyl-2 hydroxy ethyl ammonium hydroxide
  • TMAH tetramethyl ammonium hydroxide
  • Bottom end surfaces (i.e., backside end surfaces) of the memory films 50 and the backside end surfaces of the support pillars 20 can be physically exposed upon removal of the carrier substrate 9.
  • the optional outer blocking dielectric layers 44 are illustrated in FIG. 8 IB, each of which embeds a respective electrically conductive layer 46.
  • the bottommost electrically conductive layer 46B is the electrically conductive layer 46 that contacts the bottommost insulating layer 32B.
  • the optional outer blocking dielectric layers 44 may be omitted.
  • FIGS. 82 A - 82F are sequential vertical cross-sectional views of regions of the eighth exemplary structure during formation of n undoped semiconductor material layer 24 and a source structure according to respective first and second alternative configurations the eighth embodiment of the present disclosure.
  • the illustrated portion of the eighth exemplary structure is oriented upside down to reflect the orientation of the eighth exemplary structure while loaded into a respective process chamber to effect a respective processing step that is described with reference to each of the illustrated drawings.
  • etch process can be performed to remove a bottom end of each vertical semiconductor channel 60.
  • a second anisotropic or isotropic etch process can be performed to etch the bottom end portion of each vertical semiconductor channel 60.
  • each of the vertical semiconductor channels 60 may have a tubular configuration.
  • a bottom end of each dielectric core 62 can be physically exposed after the second etch process.
  • a third anisotropic or isotropic etch process can be performed to etch the material of the dielectric cores 62 selective to the material of the vertical semiconductor channels 60.
  • the third etch process may collaterally etch a horizontally- exposed surface portion of the insulating layer 32B and end portions of each memory film 50.
  • Each memory film 50 may have a tapered annular end surface after the third anisotropic etch process.
  • Each vertical semiconductor channel 60 may have a tapered annular end surface after the third etch process.
  • a recess cavity 21 that is laterally surrounded by a physically exposed surface portion of an inner sidewall of a vertical semiconductor channel 60 may be formed at a bottom portion of each memory opening 49 after the third anisotropic etch process.
  • an undoped semiconductor material layer 24 can be conformally deposited on a physically exposed surface of each dielectric cores 62, a cylindrical surface segment of the inner cylindrical sidewall of each vertical semiconductor channel 60, a tapered annular end surface of each vertical semiconductor channel 60, a tapered annular end surface of each memory film 50, and a horizontal bottom surface of the bottommost insulating layer 32B.
  • an “undoped semiconductor material” refers to a semiconductor material that is not intentionally doped during a manufacturing process and includes atoms of electrical dopants (p-type dopants and/or n-type dopants) at a net atomic concentration less than 1 x 10 16 /cm 3 .
  • a “net atomic concentration” for electrical dopants refers to the absolute value of the atomic concentration of p-type dopants less the atomic concentration of n-type dopants.
  • the undoped semiconductor material of the undoped semiconductor material layer 24 may be deposited by performing a chemical vapor deposition process that flows at least one semiconductor precursor gas without flowing any electrical dopant precursor gas during deposition.
  • the net atomic concentration of the atoms of electrical dopants in the undoped semiconductor material layer 24 is less than twice the first atomic concentration, such less than the first atomic concentration.
  • the net atomic concentration of the atoms of electrical dopants in the undoped semiconductor material layer 24 may be about the same as the first atomic concentration.
  • a bottom periphery of a contact area between the undoped semiconductor material layer 24 and the vertical semiconductor channel 60 is located below a first horizontal plane HP 1 including a bottom surface of a bottommost electrically conductive layer 46B of the electrically conductive layers 46, and a top periphery of the contact area is located above a second horizontal plane HP2 including a top surface of the bottommost electrically conductive layer 46B.
  • the memory opening fill structure 58 comprises a dielectric core 62 that is laterally surrounded by the vertical semiconductor channel 60, and the entirety of a contact area between the undoped semiconductor material layer 24 and the dielectric core 62 is located above the horizontal plane HP2 including the top surface of a bottommost electrically conductive layer 46B of the electrically conductive layers 46.
  • a doped source semiconductor layer 25 having a doping of the second conductivity type can be deposited on the undoped semiconductor material layer 24 to fill remaining volumes of the recess cavities 21 within each memory opening 49.
  • the source semiconductor layer 25 has a doping of the second conductivity type (e.g., n-type), which is the same type as the conductivity type of the drain regions 63.
  • the source semiconductor layer 25 is a heavily doped polysilicon or amorphous silicon layer which comprises dopants of the second conductivity type (e.g., phosphorus or arsenic) at a second atomic concentration that is greater than 5 x 10 18 /cm 3 .
  • the source semiconductor layer 25 comprises dopants of the second conductivity type at an atomic concentration between 1 x 10 19 /cm 3 and 5 x 10 22 /cm 3 .
  • the source semiconductor layer 25 comprises a horizontallyextending portion 25H that underlies a bottommost insulating layer 32B of the insulating layers 32, and upward-protruding portions 25U that protrude above a horizontal plane including a bottom surface of the bottommost insulating layer 32B and have a top surface above the horizontal plane HP2 including a top surface of a bottommost electrically conductive layer 46B of the electrically conductive layers 46.
  • An optional laser anneal may be performed to active the dopants in the source semiconductor layer 25, and to crystallize the source semiconductor layer 25 and the undoped semiconductor material layer 24. For example, if the source semiconductor layer 25 and the undoped semiconductor material layer 24 comprise amorphous silicon, then they are crystallized into polysilicon. If the source semiconductor layer 25 and the undoped semiconductor material layer 24 comprise polysilicon, then they are recrystallized into larger grain size polysilicon.
  • an optional metallic source contact layer 122 can be formed on the bottom surface of the source semiconductor layer 25.
  • the metallic source contact layer 122 comprises a metallic barrier liner 122B which comprises a conductive metallic nitride material, such as TiN, WN, TaN or MoN, that is formed directly on the bottom surface of the source semiconductor layer 25.
  • the thickness of the metallic barrier liner 122B may be in a range from 3 nm to 30 nm, although lesser and greater thicknesses may also be employed.
  • the metallic source contact layer 122 further comprises a metal layer 122M which consists essentially of an elemental metal (such as W, Co, Cu, Ru, Mo, Ti, Ta, etc.) and is deposited on the metallic barrier liner 122B.
  • the thickness of a planar portion of the metal layer 122M may be in a range from 30 nm to 300 nm, although lesser and greater thicknesses may also be employed.
  • a photoresist layer (not shown) can be applied over the metallic source contact layer 122, and can be lithographically patterned into photoresist material portions covering a respective cluster of memory opening fill structures 58.
  • An etch process such as an anisotropic etch process, can be performed to transfer the pattern in the photoresist material portions through the metallic source contact layer 122, the source semiconductor layer 25, and the undoped semiconductor material layer 24.
  • a backside dielectric layer 26 can be deposited over the source layer (122, 25, 24).
  • An electrically conductive source contact structure 6 can be formed through the backside dielectric layer 26 on the metallic source contact layer 122.
  • a semiconductor structure which comprises: an alternating stack (32, 46) of insulating layers 32 and electrically conductive layers 46 that alternate along a vertical direction; a memory opening 49 vertically extending through the alternating stack (32, 46); a memory opening fill structure 58 located in the memory opening 49 and comprising a vertical semiconductor channel 60 and a vertical stack of memory elements; and a layer stack of an undoped semiconductor material layer 24 and a source semiconductor layer 25, wherein the undoped semiconductor material layer 24 contacts a bottom end of the vertical semiconductor channel 60.
  • the undoped semiconductor material layer 24 comprises a horizontally-extending portion contacting a bottom surface of a bottommost insulating layer 32B of the insulating layers 32 and a vertically-extending tubular portion contacting a cylindrical surface segment of an inner sidewall of the vertical semiconductor channel 60.
  • the memory opening fill structure 58 comprises a memory film 50 including a memory material layer 54, wherein the vertical stack of memory elements comprises portions of the memory material layer 54 located at levels of the electrically conductive layers 46; and the undoped semiconductor material layer 24 comprises a funnel- shaped portion contacting a tapered end surface of the memory material layer 54.
  • the funnel-shaped portion of the undoped semiconductor material layer 24 further contacts a tapered end surface of the vertical semiconductor channel 60.
  • a bottom periphery of a contact area between the undoped semiconductor material layer 24 and the vertical semiconductor channel 60 is located below a first horizontal plane including a bottom surface of a bottommost electrically conductive layer 46B of the electrically conductive layers 46; and a top periphery of the contact area is located above a second horizontal plane including a top surface of the bottommost electrically conductive layer 46B.
  • the memory opening fill structure 58 comprises a dielectric core 62 that is laterally surrounded by the vertical semiconductor channel 60; and an entirety of a contact area between the undoped semiconductor material layer 24 and the dielectric core 62 is located above a horizontal plane including a top surface of a bottommost electrically conductive layer 46B of the electrically conductive layers 46.
  • the vertical semiconductor channel 60 has a doping of a first conductivity type; and the source semiconductor layer 25 has a doping of a second conductivity type that is an opposite of the first conductivity type.
  • the undoped semiconductor material layer 24 comprises atoms of electrical dopants at a net atomic concentration less than 1 x 10 16 /cm 3 ;
  • the vertical semiconductor channel 60 comprises atoms of dopants of the first conductivity type at a first atomic concentration that is less than 3 x 10 16 /cm 3 ;
  • the source semiconductor layer 25 comprises dopants of the second conductivity type at a second atomic concentration that is greater than 5 x 10 18 /cm 3 .
  • the net atomic concentration of the atoms of electrical dopants in the undoped semiconductor material layer 24 is less than twice the first atomic concentration.
  • the semiconductor structure comprises a metallic source contact layer 122 contacting a bottom surface of the source semiconductor layer 25.
  • the metallic source contact layer 122, the source semiconductor layer 25, and the undoped semiconductor material layer 24 have vertically coincident sidewalls.
  • the semiconductor structure comprises: a backside dielectric layer 26 underlying the metallic source contact layer 122; and an electrically conductive source contact structure 6 vertically extending through the backside dielectric layer 26 and electrically connected to the metallic source contact layer 122.
  • the vertical semiconductor channel 60 comprises first conductivity type polysilicon; the undoped semiconductor material layer 24 comprises undoped polysilicon; and the doped source semiconductor layer 25 comprises heavily doped second conductivity type polysilicon.
  • the alternating stack (32, 46), the memory opening fill structure 58, and the source semiconductor layer 25 are located in a memory die 900 that includes memory-side dielectric material layers 980 embedding memory-side metal interconnect structures 980 and memory-side bonding pads 988; and the semiconductor structure further comprises a logic die 700 including a peripheral circuit 720, and bonded to the memory die 900.
  • the undoped semiconductor material layer 24 enhances performance of the three-dimensional memory device by decreasing second conductivity dopant diffusion from the source semiconductor layer 25 into the vertical semiconductor channels 60.
  • P-i-n or p-n junctions can be formed within the undoped semiconductor material layer 24, and variations in the threshold voltages of the NAND strings can be reduced to provide more uniform channel current control for the NAND strings.
  • the undoped semiconductor material layer 24 provides a sharper interface between source semiconductor layer 25 and the vertical semiconductor channel 60 to enhance control of the source side gate-induced leakage current control during an erase operation.
  • auxiliary verb “can” is employed in this disclosure to describe formation of an element or performance of a processing step, an embodiment in which such an element or such a processing step is not performed is also expressly contemplated, provided that the resulting apparatus or device can provide an equivalent result.
  • the auxiliary verb “can” as applied to formation of an element or performance of a processing step should also be interpreted as “may” or as “may, or may not” whenever omission of formation of such an element or such a processing step is capable of providing the same result or equivalent results, the equivalent results including somewhat superior results and somewhat inferior results.

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Abstract

Une structure semi-conductrice comprend un empilement alterné de couches isolantes et de couches électroconductrices qui sont disposées en alternance dans une direction verticale, une ouverture de mémoire s'étendant verticalement à travers l'empilement alterné, une structure de remplissage d'ouverture de mémoire située dans l'ouverture de mémoire et comprenant un canal semi-conducteur vertical et un empilement vertical d'éléments de mémoire, et un empilement de couches fait d'une couche de matériau semi-conducteur non dopé et d'une couche semi-conductrice source. La couche de matériau semi-conducteur non dopé entre en contact avec une extrémité inférieure du canal semi-conducteur vertical.
PCT/US2024/054889 2024-01-16 2024-11-07 Dispositif mémoire tridimensionnel comprenant une structure de contact de source à jonction p-i-n et procédés pour le former Pending WO2025155366A1 (fr)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US18/413,859 US20250234543A1 (en) 2024-01-16 2024-01-16 Three-dimensional memory device including a schottky source contact structure and methods for forming the same
US18/413,990 2024-01-16
US18/413,918 US20250234544A1 (en) 2024-01-16 2024-01-16 Three-dimensional memory device including a schottky source contact structure and methods for forming the same
US18/413,918 2024-01-16
US18/413,990 US20250232812A1 (en) 2024-01-16 2024-01-16 Three-dimensional memory device including a schottky source contact structure and methods for forming the same
US18/413,859 2024-01-16
US18/658,557 US20250234545A1 (en) 2024-01-16 2024-05-08 Three-dimensional memory device including a p-i-n junction source contact structure and methods for forming the same
US18/658,557 2024-05-08

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Citations (4)

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Publication number Priority date Publication date Assignee Title
US20170294447A1 (en) * 2011-09-16 2017-10-12 Micron Technology, Inc. Three-dimensional structured memory devices
US20210335807A1 (en) * 2020-04-27 2021-10-28 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory device and method for forming the same
US20220302151A1 (en) * 2021-03-22 2022-09-22 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and methods for forming the same
US20230209831A1 (en) * 2021-12-27 2023-06-29 Micron Technology, Inc. Microelectronic devices including cap structures, and related electronic systems and methods

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170294447A1 (en) * 2011-09-16 2017-10-12 Micron Technology, Inc. Three-dimensional structured memory devices
US20210335807A1 (en) * 2020-04-27 2021-10-28 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory device and method for forming the same
US20220302151A1 (en) * 2021-03-22 2022-09-22 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and methods for forming the same
US20230209831A1 (en) * 2021-12-27 2023-06-29 Micron Technology, Inc. Microelectronic devices including cap structures, and related electronic systems and methods

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