WO2025208024A1 - Système et procédé de codage et de décodage dans un protocole de communication - Google Patents

Système et procédé de codage et de décodage dans un protocole de communication

Info

Publication number
WO2025208024A1
WO2025208024A1 PCT/US2025/022010 US2025022010W WO2025208024A1 WO 2025208024 A1 WO2025208024 A1 WO 2025208024A1 US 2025022010 W US2025022010 W US 2025022010W WO 2025208024 A1 WO2025208024 A1 WO 2025208024A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
decoding
encoding
receive
circuitry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/US2025/022010
Other languages
English (en)
Inventor
Stein JULUSMOEN
Amund AUNE
Ivar Holand
Lloyd Clark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Priority claimed from US19/093,416 external-priority patent/US20250310306A1/en
Publication of WO2025208024A1 publication Critical patent/WO2025208024A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

Definitions

  • the present disclosure relates generally to data communication, and more specifically to a system and method for encoding and decoding data in a communication protocol.
  • Communication with security integrated circuits can be through proprietary interfaces, or may rely on an inter-integrated circuit (I2C) bus.
  • Some 1-wire solutions protocols are based on communication protocols such as serial peripheral interface (SPI) or universal asynchronous receiver-transmitter (UART)/universal synchronous receiver-transmitter (USRT) that use one frame for each bit.
  • SPI serial peripheral interface
  • UART universal asynchronous receiver-transmitter
  • USB universal synchronous receiver-transmitter
  • interfacing addressable LEDs may be based on SPI, where the amount of time the signal is high or low defines whether the frame is a 0 or 1.
  • These communication protocols cause increased software overhead while encoding and decoding individual data bits due to significant computational demands on the software.
  • these communication protocols have limited data transfer efficiency, and restrict overall communication speed while transferring data one bit at a time.
  • the proprietary solutions often limit compatibility to specific ICs, hindering broader applicability. Therefore, there is a need for an improved system and method for encoding and
  • the system may include a transmitter and a receiver.
  • the transmitter may include a transmit data buffer to store data, an encoding circuitry operatively coupled to the transmit data buffer and a transmit shift register operatively coupled to the encoding circuitry.
  • the encoding circuitry may receive the data from the transmit data buffer in a bitwise manner, select an encoding method based on a first control signal received from a first control register and encode the data based on the selected encoding method and a first plurality of reference data values.
  • the transmit shift register may receive the encoded data and transmit the encoded data in the bitwise manner.
  • the receiver may include a receive shift register to receive the encoded data in a bitwise manner, a decoding circuitry operatively coupled to the receive shift register and a receive data buffer operatively coupled to the decoding circuitry.
  • the decoding circuitry may receive the encoded data from the receive shift register, which shifts the bitwise data into a full byte, before transferring the byte to the decoding circuitry in a parallel manner.
  • the decoding circuitry may select a decoding method based on a second control signal received from a second control register and decode the encoded data based on the selected decoding method and a second plurality of reference data values.
  • the receive data buffer may receive the decoded data.
  • a method to encode and decode in a communication protocol may include receiving data in a bitwise manner from a transmit data buffer of a transmitter, selecting an encoding method based on a first control signal received from a first control register of an encoding circuitry of the transmitter, encoding the data based on the selected encoding method and a first plurality of reference data values, receiving the encoded data in a parallel manner from a receive shift register of a receiver, selecting a decoding method based on a second control signal received from a second control register of a decoding circuitry of the receiver and decoding the encoded data based on the selected decoding method and a plurality of reference data value.
  • FIG. 2 shows a block diagram illustrating a transmitter of a system encoding in a communication protocol according to one or more examples.
  • FIG. 4 shows a flowchart illustrating a method for encoding and decoding in a communication protocol according to one or more examples.
  • FIG. 1 shows a block diagram illustrating a system 100 for encoding and decoding in a communication protocol according to various examples.
  • the system 100 may leverage a combination of hardware components and control logic within the communication protocol, such as a serial communication protocol, without limitation, to achieve encoding and decoding of a data transmitted in a bitwise manner.
  • encoding and decoding may be built into a UART/USRT or SPI so that CPU overhead may be reduced. For example, instead of the CPU wiring a byte for every bit transmitted, one byte may be written for 8 bits.
  • the system may encode each bit in the byte and may transmit each bit according to a selected encoding method.
  • software overhead may be reduced by a factor of 8, so that one or more 1-wire protocols may be treated like SPI or UART/USRT.
  • the system 100 may configure a plurality of settings of the serial communication protocol on a serial communication interface of the system 100.
  • the configuration of the plurality of settings may include setting a baud value, setting a number of communication pins, setting to bi-directional (full duplex) or single directional (half-duplex) communication, designating transmit or receive buffers, or selecting a synchronous or asynchronous mode of communication.
  • the system 100 may include three functional blocks: a clock generator 102, a transmitter 118, and a receiver 134.
  • the transmitter 118 and the receiver 134 may be arranged to handle serial transmission of the data sent from, and reception of the data sent to, the system 100, respectively.
  • the clock generator 102 may produce a regular stream of electrical pulses at a specific frequency to manage timing of data transmission and reception.
  • the clock generator 102 may include a baud register 104 and a baud rate generator 106.
  • the baud register 104 may store the baud value.
  • the baud value may be used by the baud rate generator 106 to calculate a baud rate.
  • the baud register 104 may be set when one of the plurality of settings is selected.
  • the system 100 may receive the baud value externally and may store the baud value in the baud register 104.
  • the baud rate generator 106 may receive an internal clock of the clock generator 102 and may calculate the baud rate based on a frequency of the received internal clock and the baud value of the baud register 104.
  • the baud rate generator 106 may receive a clock external to the clock generator 102 and may calculate the baud rate based on a frequency of the received external clock XCK and the baud value of the baud register 104.
  • the baud rate generator 106 may provide the baud rate to the transmitter 118 and the receiver 134.
  • the baud rate generator 106 may also provide the baud rate to a first pad 110, which may receive the external clock (XCK) signal that may be used to generate the baud rate according to one or more examples.
  • XCK external clock
  • the transmitter 118 may include a transmit data buffer 120 to store a data 122 (TX data 122), an encoding circuitry 124 operatively coupled to the transmit data buffer 120 and a transmit shift register 126 operatively coupled to the encoding circuitry 124 to shift out an encoded data in a bitwise manner.
  • the bitwise manner may correspond to one bit at a time.
  • the encoded data may be sent to a transmit pad 128 (TXD 128) which may be operatively coupled to the transmit shift register 126.
  • the transmit pad 128 may serve as an output path for the encoded data.
  • the transmit pad 128 (TXD) may transmit the encoded data in the bitwise manner, one bit at a time, synchronized with the baud rate provided by the baud rate generator 106.
  • the receiver 134 may receive a received data frame from a receive pad 130 (RXD) through a third selection circuitry 132 in the serial communication protocol.
  • the receiver 134 may receive the encoded data through the third selection circuitry 132.
  • the receiver 134 may include a receive shift register 136 operatively coupled to the third selection circuitry 132 to receive the encoded data, a decoding circuitry 138 operatively coupled to the receive shift register 136 and a receive data buffer 140 operatively coupled to the decoding circuitry 138 to receive and store a decoded data 142 (RX data 142).
  • the third selection circuitry 132 may function as a multiplexer.
  • the third selection circuitry 132 may receive the encoded data from the transmit shift register 126 of the transmitter 118 and the received data frame from the receive pad 130 (RXD).
  • the receive pad 130 (RXD) may serve as an input path for the received data frame.
  • the third selection circuitry 132 may transmit the encoded data in the bitwise manner, one bit at a time, synchronized with the baud rate provided by the baud rate generator 106.
  • the receive pad 130 (RXD) may be operatively coupled to the third selection circuitry 132.
  • the third selection circuitry 132 may allow transmitting and receiving data using the same transmit pad (TxD) 128, or to use separate transmit and receive pads (TxD and RxD) 128, 130. According to various examples, the third selection circuitry may be used to detect data collisions because data transmitted to the transmit pad 128 is also received by the receiver 134 via the third selection circuitry 132. The CPU (not shown) may compare the transmitted data to the received data to confirm that they are the same.
  • FIG. 2 shows a block diagram illustrating the transmitter 118 of the system 100 encoding in the communication protocol according to one or more examples.
  • the transmit data buffer 120 of the transmitter 118 may provide the data 122 (TX Data 122) for transmission.
  • the data 122 may be sent to a multiplexer 202 of the transmitter 118.
  • the data 122 may be fed into the encoding circuitry 124 of the transmitter 118.
  • the encoding circuitry 124 may include an encoder 204, a first reference register 206, a second reference register 208, and a first control register 210.
  • the encoding circuitry 124 may receive the data 122 from the transmit data buffer 120 in abitwise manner.
  • the encoding circuitry 124 may select an encoding method based on a first control signal received from the first control register 210.
  • the encoding circuitry 124 may encode the data 122 based on the selected encoding method and at least one of a first plurality of reference data values.
  • the transmit shift register 126 may receive the encoded data one byte at a time for multiple bytes (e.g., 8 bytes for an 8-bit frame), and transmit the encoded data in the bitwise manner.
  • the first plurality of reference data values for the encoding may include a first encoding data value and a second encoding data value.
  • the first encoding data value is 0.
  • the first encoding data value may be stored in the first reference register 206 of the encoding circuitry 124.
  • the second encoding data value is 1.
  • the second encoding data value may be stored in the second reference register 208 of the encoding circuitry 124.
  • the encoding method may be decided by a plurality of control bits within the first control register 210.
  • the first control register 210 may include information about using the first reference register 206 and the second reference register 208.
  • the encoder 204 may encode the data 122 and transmit the encoded data to the multiplexer 202. For example, if the encoder 204 receives an 8-bit string of alternating 0s and Is in data 122 (i.e., 01010101), the encoder would alternately transmit the frames of the first reference register 206 (storing first encoding data value 0) and the second reference register 208 (storing second encoding data 1). However, other encoding modes may be used.
  • the multiplexer 202 may send the encoded data to the transmit shift register 126 if the first control signal from the first control register 210 enables the encoding circuitry 124.
  • FIG. 3 shows a block diagram illustrating the receiver 134 of the system 100 for decoding data in the communication protocol according to one or more examples.
  • the receive shift register 136 of the receiver 134 may provide the encoded data.
  • the encoded data may be sent to the receive data buffer 140.
  • the encoded data may be fed into the decoding circuitry 138 of the receiver 134.
  • the decoding circuitry 138 may include a decoder 302, a first reference register 304, a second reference register 306, a third reference register 308 and a second control register 310.
  • the decoding circuitry 138 may receive the encoded data from the receive shift register 136 in a parallel manner. For example, the receive shift register 136 may shift the bitwise data into a full byte, before transferring the byte to the decoding circuitry 138 in a parallel manner.
  • the decoding circuitry 138 may select a decoding method based on a second control signal received from the second control register 310.
  • the decoding circuitry 138 may decode the encoded data based on the selected decoding method and a second plurality of reference data values.
  • the decoder 302 may output the decoded data to a multiplexer 312 of the receiver 134, which may also receive the encoded data from the receive shift register 136 and the second control signal from the second control register 310.
  • the multiplexer 312 may selectively output the encoded data or the decoded to the receive data buffer to store as received data 142 based on the second control signal.
  • the second plurality of reference data values for the decoding may include a first decoding data value, a second decoding data value and a third decoding data value.
  • the first decoding data value is 0.
  • the first decoding data value may be stored in the first reference register 304 of the decoding circuitry 138.
  • the second decoding data value is 1.
  • the second decoding data value may be stored in the second reference register 306 of the decoding circuitry 138.
  • the third decoding data value may be a mask value.
  • the third decoding data value may be stored in the third reference register 308 of the decoding circuitry 138.
  • the mask value may be used during a masked decoding method.
  • the masked decoding method may be used, without limitation, in an error correction, a data filtering and a protocol adaptation.
  • the decoding method may be decided by a plurality of control bits within the second control register 310.
  • the second control register 310 may include an information about using the first reference register 304, the second reference register 306 and the third reference register 308.
  • the decoder 302 may decode the encoded data and transmit the decoded data 142 (RX Data 142) to the receive data buffer 140.
  • the decoding circuitry 138 may receive multiple bytes, decode the multiple bytes, and transfer corresponding bits to the receive data buffer 140.
  • a “byte” of data refers to the data payload (i.e., not including start, stop, and parity bits), which may include 8 bits, though a greater or lesser number of bits may be used.
  • each received frame may correspond to one of the first and second reference registers 304, 306 of the decoding circuitry 138, which determines whether the frame is a 1 or 0.
  • FIG. 4 shows a flowchart 400 illustrating a method for encoding and decoding data in a communication protocol according to one or more examples. It may be noted that in order to explain the method operations of the flowchart 200, references will be made to the elements explained in FIG. 1, FIG. 2 and FIG. 3.
  • the flowchart 400 starts at operation 402.
  • the method may include receiving the data 122 in a bitwise manner from the transmit data buffer 120 of the transmitter 118.
  • the method may include selecting the encoding method based on the first control signal received from the first control register 210 of the encoding circuitry 124 of the transmitter 118.
  • the method may include encoding the data 122 based on the selected encoding method and the first plurality of reference data values.
  • the method may include receiving the encoded data in a parallel manner from the receive shift register 136 of the receiver 134.
  • the method may include selecting the decoding method based on the second control signal received from the second control register 310 of the decoding circuitry 138 of the receiver 134.
  • the method may include decoding the encoded data based on the selected decoding method and the second plurality of reference data values.
  • the flowchart 400 terminates at operation 416. It may be noted that the flowchart 400 is explained to have above stated process operations; however, those skilled in the art would appreciate that the flowchart 400 may have a greater or fewer number of process operations which may enable all the above stated embodiments of the present disclosure.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

L'invention concerne un système de codage et de décodage dans un protocole de communication, et peut comprendre un émetteur comportant un tampon de données d'émission pour stocker des données, un circuit de codage couplé fonctionnellement au tampon de données d'émission pour recevoir les données provenant du tampon de données d'émission et coder celles-ci sur la base d'un procédé de codage sélectionné, et un registre à décalage de transmission couplé fonctionnellement au circuit de codage pour recevoir les données codées et transmettre les données codées au niveau des bits. Le système peut comprendre un récepteur comportant un registre à décalage de réception pour recevoir les données codées, un circuit de décodage couplé fonctionnellement au registre à décalage de réception pour recevoir les données codées provenant du registre à décalage de réception d'une manière parallèle, et décoder les données codées sur la base d'un procédé de décodage sélectionné, et un tampon de données de réception couplé fonctionnellement au circuit de décodage pour recevoir les données décodées.
PCT/US2025/022010 2024-03-28 2025-03-28 Système et procédé de codage et de décodage dans un protocole de communication Pending WO2025208024A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202463570900P 2024-03-28 2024-03-28
US63/570,900 2024-03-28
US19/093,416 US20250310306A1 (en) 2024-03-28 2025-03-28 System and method for encoding and decoding in communication protocol
US19/093,416 2025-03-28

Publications (1)

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WO2025208024A1 true WO2025208024A1 (fr) 2025-10-02

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL75718A (en) * 1980-10-01 1986-04-29 Motorola Inc Multi-system paging device with power conservation
EP0188111A2 (fr) * 1984-12-18 1986-07-23 Advanced Micro Devices, Inc. Synchroniseurs de flux de données
US4868784A (en) * 1982-02-22 1989-09-19 Texas Instruments Incorporated Microcomputer with a multi-channel serial port having a single port address
US5103227A (en) * 1990-09-26 1992-04-07 At&T Bell Laboratories Modulus converter for fractional rate encoding
US5230010A (en) * 1990-09-26 1993-07-20 American Telephone & Telegraph Company Fractional rate modulation
US20020031219A1 (en) * 2000-07-18 2002-03-14 Technische Universitaet Berlin Transmitter, receiver and transceiver arrangement

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL75718A (en) * 1980-10-01 1986-04-29 Motorola Inc Multi-system paging device with power conservation
US4868784A (en) * 1982-02-22 1989-09-19 Texas Instruments Incorporated Microcomputer with a multi-channel serial port having a single port address
EP0188111A2 (fr) * 1984-12-18 1986-07-23 Advanced Micro Devices, Inc. Synchroniseurs de flux de données
US5103227A (en) * 1990-09-26 1992-04-07 At&T Bell Laboratories Modulus converter for fractional rate encoding
US5230010A (en) * 1990-09-26 1993-07-20 American Telephone & Telegraph Company Fractional rate modulation
US20020031219A1 (en) * 2000-07-18 2002-03-14 Technische Universitaet Berlin Transmitter, receiver and transceiver arrangement

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