WO2026007745A1 - Circuit de pixel, procédé d'attaque et appareil d'affichage - Google Patents

Circuit de pixel, procédé d'attaque et appareil d'affichage

Info

Publication number
WO2026007745A1
WO2026007745A1 PCT/CN2025/103032 CN2025103032W WO2026007745A1 WO 2026007745 A1 WO2026007745 A1 WO 2026007745A1 CN 2025103032 W CN2025103032 W CN 2025103032W WO 2026007745 A1 WO2026007745 A1 WO 2026007745A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
signal received
circuit
scan signal
signal terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/103032
Other languages
English (en)
Chinese (zh)
Other versions
WO2026007745A9 (fr
Inventor
朴宇成
赵永亮
安成国
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2026007745A1 publication Critical patent/WO2026007745A1/fr
Publication of WO2026007745A9 publication Critical patent/WO2026007745A9/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/10—Intensity circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

Definitions

  • the first compensation sub-circuit is also coupled to the fourth node.
  • the pixel circuit further includes a first reset sub-circuit coupled to a first initialization signal terminal, a first reset signal terminal, and the third node; a display frame period includes a reset phase; the second compensation sub-circuit is configured to, in the reset phase, in response to a third scan signal received at the third scan signal terminal, transmit a first initialization signal received at the first node to the fourth node.
  • the pixel circuit further includes a light-emitting sub-circuit, which is coupled to a first voltage signal terminal, a light-emitting signal terminal, a second node, a third node, and a fifth node; wherein, after the reset phase, the display frame cycle further includes a data write compensation phase and a light-emitting phase; the second compensation sub-circuit is further configured to, in the data write compensation phase, transmit the data signal received at the first node to the fourth node in response to a third scan signal received at the third scan signal terminal; and in the light-emitting phase, control the first node and the fourth node to be turned on in response to the third scan signal received at the third scan signal terminal.
  • the pixel circuit further includes a light-emitting sub-circuit, which is coupled to a first voltage signal terminal, a light-emitting signal terminal, a second node, a third node, and a fifth node; the fifth node is configured to be coupled to the anode of the light-emitting device; wherein, after the reset phase, the display frame cycle further includes a data write compensation phase and a light-emitting phase; the second compensation sub-circuit is further configured to, in the data write compensation phase, control the first node and the fourth node to turn off in response to a third scan signal received at the third scan signal terminal; and in the light-emitting phase, control the first node and the fourth node to turn off in response to a third scan signal received at the third scan signal terminal.
  • the second compensation sub-circuit is configured to, during the reset phase, control the first node and the fourth node to be turned off in response to a third scan signal received at the third scan signal terminal; and during the light-emitting phase, control the first node and the fourth node to be turned on in response to the third scan signal received at the third scan signal terminal.
  • the display frame period further includes a data write compensation phase; the second compensation sub-circuit is configured to, in the data write compensation phase, in response to a third scan signal received at the third scan signal terminal, transmit the data signal received at the first node to the fourth node.
  • a driving method for a pixel circuit for driving the pixel circuit described in any of the above embodiments, wherein a display frame cycle includes a reset phase; in the reset phase, a first reset sub-circuit responds to a first reset signal received at a first reset signal terminal and transmits a first initialization signal received at a first initialization signal terminal to a third node; a first compensation sub-circuit responds to a second scan signal received at a second scan signal terminal and transmits the first initialization signal received at the third node to a first node; a second compensation sub-circuit responds to a third scan signal received at a third scan signal terminal and transmits the first initialization signal received at the first node to a fourth node.
  • the signal is passed to the fourth node; during the light-emitting stage, the light-emitting sub-circuit responds to the light-emitting signal received at the light-emitting signal terminal and transmits the first voltage signal received at the first voltage signal terminal to the second node.
  • the driving transistor Under the control of the data signal at the first node, the data signal at the fourth node, and the first voltage signal at the second node, the driving transistor generates a driving current signal and transmits the driving current signal to the third node; the light-emitting sub-circuit also responds to the light-emitting signal received at the light-emitting signal terminal and transmits the current signal received at the third node to the fifth node; the second compensation sub-circuit responds to the third scan signal received at the third scan signal terminal and controls the first node and the fourth node to be turned on.
  • the display frame cycle further includes a data write compensation phase and a light emission phase; in the data write compensation phase, the data write sub-circuit, in response to a first scan signal received at the first scan signal terminal, transmits the data signal received at the data signal terminal to the second node; the driving transistor, under the control of the potential of the first node and the potential of the fourth node, transmits the data signal received at the second node to the third node; the first compensation sub-circuit, in response to a second scan signal received at the second scan signal terminal, transmits the data signal received at the third node to the first node; the second compensation sub-circuit, in response to a third scan signal received at the third scan signal terminal, transmits the data signal received at the third node to the first node.
  • a display frame cycle includes a reset phase and a light-emitting phase.
  • a first reset sub-circuit in response to a first reset signal received at a first reset signal terminal, transmits a first initialization signal received at a first initialization signal terminal to a third node;
  • a first compensation sub-circuit in response to a second scan signal received at a second scan signal terminal, transmits the first initialization signal received at the third node to a first node;
  • a second compensation sub-circuit in response to a third scan signal received at a third scan signal terminal, controls the first node and the fourth node to be turned off.
  • the display frame cycle further includes a data write compensation phase; in the data write compensation phase, the data write sub-circuit, in response to a first scan signal received at the first scan signal terminal, transmits the data signal received at the data signal terminal to the second node; the driving transistor, under the control of a first initialization signal at the first node and a first initialization signal at the fourth node, transmits the data signal received at the second node to the third node; the first compensation sub-circuit, in response to a second scan signal received at the second scan signal terminal, transmits the data signal received at the third node to the first node; the second compensation sub-circuit, in response to a third scan signal received at the third scan signal terminal, transmits the data signal received at the first node to the fourth node.
  • the display frame period further includes a data write compensation phase;
  • the data write compensation phase includes a first data write compensation phase and a second data write compensation phase;
  • the data write sub-circuit responds to a first scan signal received at the first scan signal terminal and transmits the data signal received at the data signal terminal to the second node;
  • the driving transistor under the control of a first initialization signal at the first node, transmits the data signal received at the second node to the third node;
  • the first compensation sub-circuit responds to a second scan signal received at the second scan signal terminal and transmits the data signal received at the third node to the first node; the second ...
  • the third scan signal received at the third scan signal terminal controls the first node and the fourth node to be cut off; during the second data write compensation stage, the data write sub-circuit responds to the first scan signal received at the first scan signal terminal and transmits the data signal received at the data signal terminal to the second node; the driving transistor, under the control of the first initialization signal at the first node, transmits the data signal received at the second node to the third node; the first compensation sub-circuit responds to the second scan signal received at the second scan signal terminal and transmits the data signal received at the third node to the first node; the second compensation sub-circuit responds to the third scan signal received at the third scan signal terminal and transmits the data signal received at the first node to the fourth node.
  • a display device including the pixel circuit of any of the above embodiments.
  • Figure 1 is a structural diagram of a display device according to some embodiments.
  • Figure 2 is another structural diagram of a display device according to some embodiments.
  • Figure 3 is a structural diagram of a display device including a display panel according to some embodiments.
  • Figure 4 is a structural diagram of a display panel including a substrate and pixel circuitry according to some embodiments
  • Figure 5 is a cross-sectional view along section line A-A in Figure 4.
  • Figure 6 is a structural diagram of a pixel circuit according to some embodiments.
  • Figure 7 is a structural diagram of a pixel circuit including transistors and capacitors according to some embodiments.
  • Figure 8 is a timing diagram of a pixel circuit according to some embodiments.
  • Figure 9 is a structural diagram of a pixel circuit according to some embodiments, showing the transistors being turned on or off.
  • Figure 10 is another structural diagram of the pixel circuit according to some embodiments, showing the transistors being turned on or off.
  • Figure 11 is another structural diagram of a pixel circuit according to some embodiments, showing the transistors being turned on or off.
  • Figure 12 is a timing diagram of a third scan signal terminal according to some embodiments.
  • Figure 13 is another timing diagram of the third scan signal terminal according to some embodiments.
  • Figure 14 is another structural diagram of the pixel circuit according to some embodiments, showing the transistors being turned on or off.
  • Figure 15 is another structural diagram of a pixel circuit according to some embodiments, showing the transistors being turned on or off.
  • Figure 16 is another structural diagram of the pixel circuit according to some embodiments, showing the transistors being turned on or off.
  • Figure 17 is another timing diagram of the third scan signal terminal according to some embodiments.
  • Figure 18 is another timing diagram of the third scan signal terminal according to some embodiments.
  • Figure 19 is another timing diagram of the third scan signal terminal according to some embodiments.
  • first and second are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of that feature.
  • a plurality of means two or more.
  • Coupled and “connected,” and their derivative expressions, may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other.
  • the term “coupled” may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”.
  • the phrase “if it is determined that...” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that...”, “in response to determination that...”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.
  • parallel As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).
  • parallel includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°
  • equal includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.
  • a layer or element when referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.
  • the capacitor can be a capacitor device fabricated separately through a process, such as by fabricating dedicated capacitor electrodes.
  • Each capacitor electrode can be implemented using a metal layer, a semiconductor layer (e.g., doped polysilicon), etc.
  • the capacitor can also be the parasitic capacitance between transistors, or it can be implemented through the transistor itself and other devices or circuits, or it can utilize the parasitic capacitance between the circuit's own lines.
  • the first node, second node, third section, fourth node, and fifth node do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.
  • a "low level” refers to a level that enables the included operated transistor to conduct
  • a "high level” refers to a level that prevents the included operated transistor from conducting (i.e., the transistor is turned off).
  • a "low level” refers to a level that enables the included operated transistor to turn off
  • a "high level” refers to a level that enables the included operated transistor to conduct.
  • a display device 1000 which can be any device that displays either moving (e.g., video) or fixed (e.g., still image) text or images.
  • the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, in-vehicle display, or flight display.
  • PDA personal digital assistant
  • AR augmented reality
  • VR virtual reality
  • in-vehicle display or flight display.
  • the display device 1000 can be a portable display product.
  • the display device 1000 can be a mobile phone as shown in Figure 1.
  • the display device 1000 can be a wearable device.
  • the display device 1000 can be a watch as shown in Figure 2.
  • the display device 1000 includes a display panel 100, a driving circuit board 200, a housing 300, and a cover plate 400.
  • the display panel 100 has a light-emitting side 100A and a non-light-emitting side 100B.
  • the light-emitting side 100A refers to the side of the display panel 100 that can emit light (the upper side of the display panel 100 in Figure 3)
  • the non-light-emitting side 100B refers to the other side opposite to the light-emitting side 100A (the lower side of the display panel 100 in Figure 3).
  • the driving circuit board 200 is located on the non-light-emitting side of the display panel 100 and is connected to the display panel 100 to provide light-emitting signals to the display panel 100.
  • the housing 300 can be a box-shaped structure with an opening.
  • the display panel 100 and the driving circuit board 200 can be disposed inside the housing 300.
  • the cover plate 400 is disposed on the light-emitting side of the display panel 100 and is located at the opening of the housing 300.
  • the longitudinal section of the housing 300 can be U-shaped, for example.
  • the display panel 100 and the driving circuit board 200 are disposed inside the housing 300, and the cover plate 400 is disposed at the opening of the housing 300.
  • the aforementioned display panel 100 comes in various types, and can be selected and configured according to actual needs.
  • the display panel 100 described above may be: an organic light-emitting diode (OLED) display panel 100, a quantum dot light-emitting diode (QLED) display panel 100, an active matrix organic light-emitting diode (AMOLED) display panel 100, a liquid crystal display (LCD) display panel 100, or a mini/micro light-emitting display (MLED) display panel 100, etc.
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • AMOLED active matrix organic light-emitting diode
  • LCD liquid crystal display
  • MLED mini/micro light-emitting display
  • OLED display panel 100 uses an OLED display panel 100 as an example to illustrate some embodiments of this disclosure.
  • the display panel 100 includes a substrate 10 and a plurality of sub-pixels 20.
  • the substrate 10 may be made of polymer resin or glass.
  • the substrate 10 may be flexible, and the material used for the substrate 10 may include polymer resins such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenyl sulfide granules (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP).
  • the substrate 10 may be rigid, including a glass material containing SiO2 as the main component.
  • a plurality of sub-pixels 20 are disposed on the substrate 10.
  • the plurality of sub-pixels 20 can be arranged in multiple rows and columns, for example.
  • Each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X
  • each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y.
  • the first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.
  • the aforementioned plurality of sub-pixels 20 may include a first sub-pixel with a first emission color, a second sub-pixel with a second emission color, and a third sub-pixel with a third emission color.
  • the first, second, and third colors are three primary colors.
  • the first color may be red, the second color blue, and the third color green; however, this embodiment does not impose specific limitations.
  • sub-pixel 20 includes pixel circuit 21 and light-emitting device 22.
  • the display panel 100 further includes a pixel circuit stack 30 and a light-emitting device stack 40 located on the substrate 10 along a direction perpendicular to and away from the substrate 10.
  • the pixel circuit stack 30 includes multiple pixel circuits 21, and each pixel circuit 21 includes multiple transistors 211 and a storage capacitor 212 (C).
  • the transistor 211 used in the circuit provided in the embodiments of this disclosure can be a thin-film transistor, a field-effect transistor, or other switching devices with the same characteristics.
  • thin-film transistors are used as an example for illustration.
  • transistor 211 is an oxide thin-film transistor, which has a high carrier mobility.
  • transistor 211 may be a low-temperature polycrystalline silicon thin-film transistor, which has high mobility and fast charging.
  • the multiple transistors 211 include low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors. In this way, the low-temperature polycrystalline silicon transistors and oxide transistors can be integrated on a single display panel 100, which can reduce the power consumption of the display panel 100 and improve the display quality of the display panel 100.
  • transistor 211 includes an active portion 2111, a source 2112, a drain 2113, and a gate 2114, with the source 2112 and drain 2113 respectively in contact with the active portion 2111.
  • Storage capacitor 212 includes two plates disposed opposite to each other.
  • source 2112 and drain 2113 mentioned above can be interchanged, that is, 2112 in Figure 5 represents the drain and 2113 represents the source.
  • the pixel circuit 21 described above has various structures, which can be selected and configured according to actual needs.
  • the structure of the pixel circuit 21 may include “2T1C”, “3T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C”, etc.
  • T represents transistor 211
  • the number before “T” indicates the number of transistors 211
  • C represents storage capacitor 212
  • the number before “C” indicates the number of storage capacitors 212.
  • the multiple transistors in the pixel circuit 21 may include both P-type and N-type transistors. In other examples, the multiple transistors in the pixel circuit 21 may all be P-type transistors or may be N-type transistors. This simplifies the manufacturing process, reduces the manufacturing difficulty of the display panel 100, and improves the product yield.
  • the light-emitting device stack 40 includes an anode layer 241, a light-emitting functional layer 242, and a cathode layer 243 stacked together.
  • the anode layer 241 includes multiple anodes 2411
  • the cathode layer 243 includes multiple cathodes 2431.
  • An anode 2411 and a cathode 2431 are arranged opposite to each other.
  • the anode 2411 can be electrically connected, for example, to the source 2112 or drain 2113 of a plurality of transistors 211 that serve as driving transistors.
  • Figures 5 and 6 illustrate this by showing the anode 2411 and the drain 2113 of transistor 211 being electrically connected. In this way, the pixel circuit 21 can drive the corresponding light-emitting device 22 to emit light.
  • the aforementioned light-emitting functional layer 242 may include only the light-emitting layer, or it may include at least one of the following: an electron transport layer (ETL), an electron injection layer (EIL), a hole blocking layer (HBL), a hole transport layer (HTL), a hole injection layer (HIL), and an electron blocking layer (EBL), in addition to the light-emitting layer.
  • ETL electron transport layer
  • EIL electron injection layer
  • HBL hole blocking layer
  • HTL hole transport layer
  • HIL hole injection layer
  • HIL hole injection layer
  • EBL electron blocking layer
  • the display panel 100 further includes an encapsulation layer 50.
  • the encapsulation layer 50 is located on the side of the light-emitting device stack 40 away from the substrate 10, and the encapsulation layer 50 is used to encapsulate the light-emitting device 22 to improve the service life of the light-emitting device 22.
  • the encapsulation layer 50 can be an encapsulation film or an encapsulation substrate, and the embodiments disclosed herein are not specifically limited thereto.
  • the encapsulation layer 50 may include a single encapsulation film, or it may include two or more encapsulation films stacked together.
  • the encapsulation layer 50 includes a first inorganic encapsulation layer 51, a first organic encapsulation layer 52, and a second inorganic encapsulation layer 53 stacked along a direction perpendicular to and away from the substrate 10.
  • the materials of the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide.
  • the material of the first organic encapsulation layer 52 includes a polymer resin, such as polyimide.
  • the pixel circuit 21 includes a driving transistor T1, a data writing sub-circuit 201, a first compensation sub-circuit 202, a first reset sub-circuit 203, and a light-emitting sub-circuit 204.
  • the driving transistor is a single-gate transistor, the first terminal of the driving transistor T1 is connected to the second node N2, the second terminal is connected to the third node N3, and the control terminal is connected to the first node N1.
  • the driving transistor T1 is configured to control the conduction and cutoff of the circuit between the second node N2 and the third node N3 under the control of the potential of the first node N1, and to generate a driving current signal based on the potential of the first node N1 and the potential of the second node N2.
  • the data writing sub-circuit 201 is coupled to the second node N2, the first scan signal terminal GATE1, and the data signal terminal DATA.
  • the data writing sub-circuit 201 is configured to control the on and off states of the data signal terminal DATA and the second node N2 in response to a first scan signal received at the first scan signal terminal GATE1.
  • the data writing sub-circuit 201 includes a data writing transistor T2.
  • the first terminal of the data writing transistor T2 is connected to the data signal terminal DATA, the second terminal is connected to the second node N2, and the control terminal is connected to the first scan signal terminal GATE1.
  • the first compensation sub-circuit 202 is coupled to the first node N1, the third node N3, and the second scan signal terminal GATE2.
  • the first compensation sub-circuit 202 is configured to control the on and off states of the first node N1 and the third node N3 in response to a second scan signal received at the second scan signal terminal GATE2.
  • the first compensation sub-circuit 202 includes a first compensation transistor T3.
  • the first terminal of the first compensation transistor T3 is coupled to the third node N3, the second terminal is coupled to the first node N1, and the control terminal and the second scan signal terminal GATE2 are coupled.
  • the first reset sub-circuit 203 is coupled to the first initialization signal terminal VINIT1, the first reset signal terminal RESET1, and the third node N3.
  • the first reset sub-circuit 203 is configured to control the on and off states of the first initialization signal terminal VINIT1 and the third node N3 in response to a first reset signal received at the first reset signal terminal RESET1.
  • the first reset sub-circuit 203 includes a first reset transistor T4.
  • the first terminal of the first reset transistor T4 is connected to the first initialization signal terminal VINIT1, the second terminal is connected to the third node N3, and the control terminal is connected to the second scan signal terminal GATE2.
  • the light-emitting sub-circuit 204 is coupled to a first voltage signal terminal VDD, a light-emitting signal terminal EM, a second node N2, a third node N3, and a fifth node N5.
  • the fifth node N5 is configured to be connected to the anode of the light-emitting device 22.
  • the light-emitting sub-circuit 204 is configured to control the conduction and cutoff of the first voltage signal terminal VDD and the second node N2, and to control the control and cutoff of the third node N3 and the fifth node N5, in response to the light-emitting signal received at the light-emitting signal terminal EM.
  • the light-emitting sub-circuit 204 includes a first light-emitting sub-circuit 2041 and a second light-emitting sub-circuit 2042.
  • the first light-emitting sub-circuit 2041 is coupled to a first voltage signal terminal VDD, a first light-emitting signal terminal EM1, and a second node N2.
  • the first light-emitting sub-circuit 2041 is configured to control the conduction and cutoff of the first voltage signal terminal VDD and the second node N2 in response to a first light-emitting signal received at the first light-emitting signal terminal EM1.
  • the second light-emitting sub-circuit 2042 is coupled to a third node N3, a second light-emitting signal terminal EM2, and a fifth node N5.
  • the second light-emitting sub-circuit 2042 is configured to control the control and cutoff of the third node N3 and the fifth node N5 in response to a light-emitting signal received at the second light-emitting signal terminal EM2.
  • the signal received at the first light-emitting signal terminal EM1 is the same as the signal received at the second light-emitting signal terminal EM2.
  • the first light-emitting sub-circuit 204 includes a first light-emitting transistor T5.
  • the first electrode of the first light-emitting transistor T5 is connected to the first voltage signal terminal VDD
  • the second electrode is connected to the second node N2
  • the control electrode is connected to the first light-emitting signal terminal EM1.
  • the second light-emitting sub-circuit 2042 includes a second light-emitting transistor T6.
  • the first electrode of the second light-emitting transistor T6 is coupled to the third node N3, the second electrode is coupled to the anode of the light-emitting device 22, and the control electrode is coupled to the second light-emitting signal terminal EM2.
  • a display frame cycle P includes a reset phase P1, a data writing compensation phase P2, and an illumination phase P3.
  • the first reset sub-circuit 203 is configured to, during the reset phase P1, transmit the first initialization signal received at the first initialization signal terminal VINIT1 to the third node N3.
  • the first compensation sub-circuit 202 is configured to, during the reset phase P1, in response to the second scan signal received at the second scan signal terminal GATE2, transmit the first initialization signal received at the third node N3 to the first node N1.
  • the first initialization signal received by the first initialization signal terminal VINIT1 can be transmitted to the third node N3 through the first reset sub-circuit 203, thereby initializing the third node N3.
  • This can improve the problem of the potential of the previous image frame remaining in the third node N3 affecting the display image of the next image frame, thereby improving the brightness uniformity of the display panel 100.
  • the data writing sub-circuit 201 is configured to, in the data writing compensation phase P2, in response to the first scan signal received at the first scan signal terminal GATE1, transmit the data signal received at the data signal terminal DATA to the second node N2.
  • the driving transistor T1 is configured to, in the data writing compensation phase P2, under the control of the potential of the first node N1, transmit the data signal received at the second node N2 to the third node N3.
  • the first compensation sub-circuit 202 is configured to, in the data writing compensation phase P2, in response to the second scan signal received at the second scan signal terminal GATE2, transmit the data signal received at the third node N3 to the first node N1.
  • the light-emitting sub-circuit 204 is configured to transmit the first voltage signal received at the first voltage signal terminal VDD to the second node N2.
  • the driving transistor T1 is configured to, during the light-emitting phase P3, generate a driving current signal under the control of the data signal at the first node N1 and the first voltage signal at the second node N2, and transmit the driving current signal to the third node N3.
  • the light-emitting sub-circuit 204 is also configured, during the light-emitting phase P3, in response to the light-emitting signal received at the light-emitting signal terminal EM, to transmit the current signal received at the third node N3 to the fifth node N5, so that the light-emitting device 22 emits light.
  • the brightness uniformity of the display panel is poor during the light emission process, resulting in a poor display effect.
  • the inventors discovered that the threshold voltage of the driving transistor can drift (e.g., positive or negative bias).
  • the pixel circuit can only compensate for the threshold voltage of the unbiased driving transistor, not the drifted threshold voltage. This leads to inconsistent gate-source voltage differences of the driving transistors in multiple pixel circuits even when all sub-pixels are at the same grayscale, resulting in inconsistent brightness of multiple light-emitting devices and poor brightness uniformity of the display panel.
  • the driving transistor T1 is a dual-gate transistor, that is, the driving transistor T1 includes a first control electrode and a second control electrode.
  • the first control electrode of the driving transistor T1 is connected to a first node N1, and the second control electrode is connected to a fourth node N4.
  • the first control electrode is the top gate of the driving transistor T1, and the second control electrode is the bottom gate of the driving transistor T1.
  • the pixel circuit 21 also includes a second compensation sub-circuit 205.
  • the second compensation sub-circuit 205 is coupled to the first node N1, the fourth node N4 and the third scan signal terminal GATE3; the second compensation sub-circuit 205 is configured to control the on and off of the first node N1 and the fourth node N4 in response to the third scan signal received at the third scan signal terminal GATE3.
  • the second compensation sub-circuit 205 includes a second compensation transistor T7, the first terminal of the second compensation transistor T7 is connected to the first node N1, the second terminal is connected to the fourth node N4, and the control terminal is connected to the third scan signal terminal GATE3.
  • the instruction manual specifies that the formula for calculating the subthreshold swing of the driving transistor T1 is as follows:
  • V ⁇ sub> g ⁇ /sub> is the gate voltage
  • I ⁇ sub>ds ⁇ /sub> is the source-drain current
  • k is the Boltzmann constant
  • T is the temperature
  • q is the electron charge
  • Co ⁇ sub> ox ⁇ /sub> is the gate oxide capacitance per unit area of the driving transistor
  • CB is the depletion region capacitance
  • C ⁇ sub> it ⁇ /sub> is the interface trap capacitance of the driving transistor.
  • the second compensation sub-circuit 205 can control the first and second control electrodes of the driving transistor T1 to be turned on or off, thereby changing the size of the depletion region capacitance and adjusting the subthreshold swing of the driving transistor T1.
  • the first compensation sub-circuit 202 is also coupled to the fourth node N4.
  • the first compensation sub-circuit 202 includes a first compensation transistor T3.
  • the first terminal of the first compensation transistor T3 is connected to the third node N3, the second terminal is connected to the first node N1, the first control terminal is connected to the second scan signal terminal GATE2, and the second control terminal is connected to the fourth node N4.
  • the first and second control terminals of the first compensation transistor T3 are positioned opposite each other.
  • CB CBG1 + CBG1 + CBG3 , where CBG3 is the capacitance of the depletion region of the second control electrode of the first compensation transistor T3.
  • the second compensation sub-circuit 205 is configured to, during the reset phase P1, in response to the third scan signal received at the third scan signal terminal GATE3, transmit the first initialization signal received at the first node N1 to the fourth node N4.
  • the first node N1 and the fourth node N4 are turned on by the second compensation circuit 205.
  • the size of the depletion region capacitance can be changed to adjust the size of the subthreshold swing of the driving transistor T1, thereby compensating for the threshold voltage of the drifted driving transistor T1. This reduces the difference between the gate-source voltage differences of the driving transistor T1 in the multiple pixel circuits 21, which helps to reduce the difference in brightness between the multiple light-emitting devices 22 and improve the brightness uniformity of the display panel 100.
  • the top gate and bottom gate of the driving transistor T1 have the same potential, which reduces the risk of carriers in the active part of the driving transistor T1 flowing to either the top gate or the bottom gate, thereby reducing the risk of carriers being captured by defects in the top gate and bottom gate, which helps to reduce the risk of threshold voltage drift.
  • the second compensation sub-circuit 205 is further configured to, during the data writing compensation phase P2, transmit the data signal received at the first node N1 to the fourth node N4 in response to the third scan signal received at the third scan signal terminal GATE3; and during the light emission phase P3, control the first node N1 and the fourth node N4 to conduct in response to the third scan signal received at the third scan signal terminal GATE3. That is, during the reset phase P1, the data writing compensation phase P2, and the light emission phase P3, the second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to conduct in response to the third scan signal received at the third scan signal terminal GATE3.
  • This configuration has several advantages. First, it compensates for threshold voltages with large negative biases (e.g., negative bias greater than 0.5V), reducing the difference in gate-source voltage between the driving transistors T1 in the multiple pixel circuits 21. This helps reduce the brightness differences between the multiple light-emitting devices 22, improving the brightness uniformity of the display panel 100. Second, simultaneously compensating for the bottom and top gates shortens the compensation time of the driving transistors T1, reducing the display frame period and improving the refresh rate of the display panel 100, thereby enhancing its display performance.
  • large negative biases e.g., negative bias greater than 0.5V
  • the second compensation sub-circuit 205 is further configured to, during the data writing compensation phase P2, control the first node N1 and the fourth node N4 to be turned off in response to the third scan signal received at the third scan signal terminal GATE3; and during the light emission phase P3, control the first node N1 and the fourth node N4 to be turned off in response to the third scan signal received at the third scan signal terminal GATE3. That is, during the reset phase P1, the second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to be turned on in response to the third scan signal received at the third scan signal terminal GATE3. During the data writing compensation phase P2 and the light emission phase P3, the second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to be turned off in response to the third scan signal received at the third scan signal terminal GATE3.
  • the threshold voltage with a small forward bias (e.g., a forward bias less than or equal to 0.5V) can be compensated, reducing the difference between the gate-source voltage differences of the driving transistors T1 in the multiple pixel circuits 21. This helps to reduce the difference in brightness between the multiple light-emitting devices 22 and improve the brightness uniformity of the display panel 100.
  • the second compensation sub-circuit 205 is configured to, in the reset phase P1, control the first node N1 and the fourth node N4 to be turned off in response to the third scan signal received at the third scan signal terminal GATE3; and in the light emission phase P3, control the first node N1 and the fourth node N4 to be turned on in response to the third scan signal received at the third scan signal terminal GATE3.
  • the first node N1 and the fourth node N4 are turned off by the second compensation sub-circuit 205, and during the light-emitting phase P3, the first node N1 and the fourth node N4 are turned on by the second compensation sub-circuit 205.
  • the size of the depletion region capacitance can be changed to adjust the subthreshold swing of the driving transistor T1, thereby compensating for the drifted threshold voltage of the driving transistor T1. This reduces the difference in gate-source voltage between the driving transistors T1 in the multiple pixel circuits 21, which helps to reduce the difference in brightness between the multiple light-emitting devices 22 and improves the brightness uniformity of the display panel 100.
  • the second compensation sub-circuit 205 is configured to, during the data write compensation phase P2, transmit the data signal received at the first node N1 to the fourth node N4 in response to the third scan signal received at the third scan signal terminal GATE3.
  • This configuration allows for several advantages. First, it compensates for threshold voltages with low negative bias (e.g., positive bias less than or equal to 0.5V), reducing the difference in gate-source voltage between the driving transistors T1 in the multiple pixel circuits 21. This helps reduce the brightness differences between the multiple light-emitting devices 22, improving the brightness uniformity of the display panel 100. Second, simultaneously compensating for the bottom and top gates shortens the compensation time of the driving transistors T1, reducing the display frame period and improving the refresh rate of the display panel 100, thereby enhancing its display performance.
  • low negative bias e.g., positive bias less than or equal to 0.5V
  • the second compensation sub-circuit 205 is configured to cut off the first node N1 and the fourth node N4 in response to the third scan signal received at the third scan signal terminal GATE3 during the data write compensation phase P2.
  • This configuration allows for compensation of the almost drift-free threshold voltage, reducing the difference between the gate-source voltage differences of the driving transistors T1 in the multiple pixel circuits 21. This helps to reduce the difference in brightness between the multiple light-emitting devices 22 and improve the brightness uniformity of the display panel 100.
  • the data write compensation phase P2 includes a first data write compensation phase P21 and a second data write compensation phase P22.
  • the second compensation sub-circuit 205 is configured to, in the first data write compensation phase P21, in response to the third scan signal received at the third scan signal terminal GATE3, cut off the first node N1 and the fourth node N4.
  • the second compensation sub-circuit 205 is configured to, in the second data write compensation phase P22, in response to the third scan signal received at the third scan signal terminal GATE3, transmit the data signal received at the first node N1 to the fourth node N4.
  • This configuration can compensate for threshold voltages with large forward bias (e.g., forward bias greater than 0.5V), reduce the difference between gate-source voltage differences of driving transistors T1 in multiple pixel circuits 21, and help reduce the difference in brightness between multiple light-emitting devices 22, thereby improving the brightness uniformity of the display panel 100.
  • large forward bias e.g., forward bias greater than 0.5V
  • the pixel circuit 21 further includes a second reset sub-circuit 206, which is coupled to the second initialization signal terminal VINIT2, the second reset signal terminal RESET2, and the fifth node N5.
  • the second reset sub-circuit 206 is configured to control the on and off states of the second initialization signal terminal VINIT2 and the fifth node N5 in response to a second reset signal received at the second reset signal terminal RESET2.
  • the second reset sub-circuit 206 includes a second reset transistor T8.
  • the first terminal of the second reset transistor T8 is connected to the second initialization signal terminal VINIT2, the second terminal is connected to the fifth node N5, and the control terminal is connected to the second reset signal segment.
  • the second initialization signal received by the second initialization signal terminal VINIT2 can be transmitted to the fifth node N5 through the second reset sub-circuit 206, thereby initializing the fifth node N5.
  • This can improve the problem of the potential of the previous image frame remaining in the fifth node N5 affecting the display image of the next image frame, thereby improving the brightness uniformity of the display panel 100.
  • the second reset signal received at the second reset signal terminal RESET2 is the same as the first reset signal received at the first reset signal terminal RESET1. In this way, the reset of the third node N3 and the reset of the fifth node N5 can both be controlled by the second scan signal terminal GATE2, thereby simplifying the circuit structure.
  • the pixel circuit 21 further includes a first storage sub-circuit 207, which is coupled to a first voltage signal terminal VDD and a first node N1; the first storage sub-circuit 207 is configured to store the potential of the first node N1.
  • the first storage sub-circuit 207 includes a first storage capacitor C1, the first plate of the first storage capacitor C1 is connected to the first voltage signal terminal VDD, and the second plate is connected to the first node N1.
  • the following detailed description of the operation of the pixel circuit 21 within one display frame cycle, in conjunction with the timing diagram, is provided.
  • the following embodiment uses P-type transistors as the driving transistor T1, the data writing transistor T2, the first reset transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, and the second compensation transistor T7, and an N-type transistor as the first compensation transistor T3.
  • the above-mentioned display frame cycle includes a reset phase P1, a data writing compensation phase P2, and an illumination phase P3.
  • the first reset sub-circuit 203 in response to the first reset signal received at the first reset signal terminal RESET1, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the third node N3.
  • the first compensation sub-circuit 202 in response to the second scan signal received at the second scan signal terminal GATE2, transmits the first initialization signal received at the third node N3 to the first node N1.
  • the second compensation sub-circuit 205 in response to the third scan signal received at the third scan signal terminal GATE3, transmits the first initialization signal received at the first node N1 to the fourth node N4.
  • each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212.
  • the first reset signal is 0, the third scan signal is 0, the first light emission signal is 1, the second light emission signal is 1, the first scan signal is 1 and the second scan signal is 1, where "0" represents a low level and "1" represents a high level.
  • the first reset signal terminal RESET1 and the third scan signal terminal GATE3 are input at low level
  • the second scan signal terminal GATE2 is input at high level
  • the first reset transistor T4, the second compensation transistor T7 and the first compensation transistor T3 are all turned on.
  • the first light-emitting signal terminal EM1 When the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the first scan signal terminal GATE1 are input at a low level, the first light-emitting transistor T5, the second light-emitting transistor T6, and the data writing transistor T2 are all turned off.
  • the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the third node N3 through the first reset transistor T4, the first initialization signal received at the third node N3 is transmitted to the first node N1 through the first compensation transistor T3, and the first initialization signal received at the first node N1 is transmitted to the fourth node N4 through the second compensation transistor T7.
  • the data writing sub-circuit 201 in response to the first scan signal received at the first scan signal terminal GATE1, transmits the data signal received at the data signal terminal DATA to the second node N2. Under the control of the potential of the first node N1, the driving transistor T1 transmits the data signal received at the second node N2 to the third node N3.
  • the first compensation sub-circuit 202 in response to the second scan signal received at the second scan signal terminal GATE2, transmits the data signal received at the third node N3 to the first node N1.
  • the second compensation sub-circuit 205 in response to the third scan signal received at the third scan signal terminal GATE3, transmits the data signal received at the first node N1 to the fourth node N4.
  • each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212.
  • the first scan signal is 0, the third scan signal is 0, the second scan signal is 1, the first reset signal is 1, the first light emission signal is 1, and the second light emission signal is 1, where "0" represents a low level and "1" represents a high level.
  • the first scan signal terminal GATE1 and the third scan signal terminal GATE3 are input at low level
  • the second scan signal terminal GATE2 is input at high level
  • the data writing transistor T2, the first compensation transistor T3, and the second compensation transistor T7 are all turned on.
  • the first reset transistor T4 When the first reset signal terminal RESET1, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are input with a low level, the first reset transistor T4, the first light-emitting transistor T5, and the second light-emitting transistor T6 are all turned off.
  • the data signal received at the data signal terminal DATA is transmitted to the second node N2 through the data writing transistor T2, meaning the potential of the second node N2 is Vdata.
  • the potential of the first node N1 is Vint1.
  • the potential difference between the first node N1 and the second node N2 is Vint1 - Vdata.
  • the data signal at the second node N2 is transmitted to the first node N1 through the second compensation transistor T7.
  • the potential of the first node N1 gradually increases from Vin1.
  • the driving transistor T1 is turned off, and the data writing compensation phase P2 ends.
  • the larger of the data signal Vdata and the threshold voltages Vth1 and Vth2 is written into the first storage capacitor C1.
  • the threshold voltage Vth1 of the top gate of the driving transistor T1 is compensated, and the threshold voltage Vth2 of the bottom gate is also compensated.
  • compensating for both the bottom and top gates at the same time can shorten the compensation time of the driving transistor T1, shorten the display frame period, and help improve the refresh rate of the display panel 100, thereby improving the display effect of the display panel 100.
  • the light-emitting sub-circuit 204 in response to the light-emitting signal received at the light-emitting signal terminal EM, transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. Under the control of the data signal at the first node N1 and the first voltage signal at the second node N2, the driving transistor T1 generates a driving current signal and transmits it to the third node N3.
  • the light-emitting sub-circuit 204 also, in response to the light-emitting signal received at the light-emitting signal terminal EM, transmits the current signal received at the third node N3 to the fifth node N5.
  • the second compensation sub-circuit 205 in response to the third scan signal received at the third scan signal terminal GATE3, controls the first node N1 and the fourth node N4 to conduct.
  • each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212.
  • the first emission signal is 0, the second emission signal is 0, the third scan signal is 0, the second scan signal is 0, the first scan signal is 1, and the first reset signal is 1, where "0" represents a low level and "1" represents a high level.
  • the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the third scan signal terminal GATE3 are input with low level, and the first light-emitting transistor T5, the second light-emitting transistor T6, and the second compensation transistor T7 are all turned on.
  • the first scan signal terminal GATE1 and the first reset signal terminal RESET1 are input at high level, the second scan signal terminal GATE2 is input at low level, and the data writing transistor T2, the first compensation transistor T3 and the first reset transistor T4 are all cut off.
  • the first voltage signal at the first voltage signal terminal VDD is transmitted to the second node N2 through the first light-emitting transistor T5, that is, the potential of the second node N2 is Vdd.
  • the potential of the first node N1 is the higher of Vdata+Vth1 and Vdata+Vth2.
  • the driving transistor T1 generates a driving current under the control of the potentials of the first node N1, the fourth node N4, and the second node N2.
  • the driving transistor T1 operates in the saturation region. According to the saturation current formula, the driving current generated by the driving transistor T1 (the current input to the light-emitting device 22) is:
  • W/L is the channel width-to-length ratio of driving transistor T1; ⁇ is the carrier mobility; Cox is the channel capacitance per unit area of driving transistor T1; Vgs is the gate-source voltage difference of driving transistor T1; and Vth is the threshold voltage of driving transistor T1.
  • the magnitude of the current Ioled of the input light-emitting device 22 is related to the potential Vdata of the written data signal and the first voltage signal, and is independent of the threshold voltage Vth of the driving transistor T1. This avoids the problem that the different threshold voltages of the driving transistors T1 of each pixel circuit 21 caused by the manufacturing process affect the magnitude of the driving current, and thus affect the display effect.
  • the third scan signal is 1, the third scan signal terminal is input with a high level, and the second compensation transistor T7 is turned off.
  • the second compensation sub-circuit 205 responds to the third scan signal received at the third scan signal terminal GATE3, controlling the first node N1 and the fourth node N4 to be turned off.
  • the driving transistor T1 When the potential of the first node N1 rises to Vdata + Vth, the driving transistor T1 is turned off, and the data writing compensation phase P2 ends. This writes the data signal Vdata and the threshold voltage Vth into the first storage capacitor C1.
  • the potential of the first node N1 is Vdata + Vth, and the driving transistor T1 generates a driving current under the control of the potentials of the first node N1 and the second node N2.
  • the first reset sub-circuit 203 in response to the first reset signal received at the first reset signal terminal RESET1, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the third node N3.
  • the first compensation sub-circuit 202 in response to the second scan signal received at the second scan signal terminal GATE2, transmits the first initialization signal received at the third node N3 to the first node N1.
  • the second compensation sub-circuit 205 in response to the third scan signal received at the third scan signal terminal GATE3, controls the first node N1 and the fourth node N4 to be turned off.
  • each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212.
  • the first reset signal is 0, the second scan signal is 1, the first light emission signal is 1, the second light emission signal is 1, the first scan signal is 1, and the third scan signal is 1, where "0" represents a low level and "1" represents a high level.
  • the first reset signal terminal RESET12 is input at a low level
  • the second scan signal terminal GATE2 is input at a high level
  • both the first reset transistor T4 and the first compensation transistor T3 are turned on.
  • the first light-emitting signal terminal EM1 When the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the first scan signal terminal GATE1, and the third scan signal terminal GATE3 are input with a high level, the first light-emitting transistor T5, the second light-emitting transistor T6, the data writing transistor T2, and the second compensation transistor T7 are all turned off.
  • the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the third node N3 through the first reset transistor T4, and the first initialization signal received at the third node N3 is transmitted to the first node N1 through the first compensation transistor T3.
  • the light-emitting sub-circuit 204 in response to the light-emitting signal received at the light-emitting signal terminal EM, transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. Under the control of the data signal at the first node N1 and the first voltage signal at the second node N2, the driving transistor T1 generates a driving current signal and transmits it to the third node N3.
  • the light-emitting sub-circuit 204 also, in response to the light-emitting signal received at the light-emitting signal terminal EM, transmits the current signal received at the third node N3 to the fifth node N5.
  • the second compensation sub-circuit 205 in response to the third scan signal received at the third scan signal terminal GATE3, controls the first node N1 and the fourth node N4 to conduct.
  • each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212.
  • the first emission signal is 0, the second emission signal is 0, the second scan signal is 0, the third scan signal is 0, the first scan signal is 1, and the first reset signal is 1, where "0" represents a low level and "1" represents a high level.
  • the first light-emitting signal terminal EM1 the second light-emitting signal terminal EM2 and the third scan signal terminal GATE3 are input with low level, and the first light-emitting transistor T5, the second light-emitting transistor T6 and the second compensation transistor T7 are all turned on.
  • the first scan signal terminal GATE1 and the first reset signal terminal RESET1 are input at high level, the second scan signal terminal GATE2 is input at low level, and the data writing transistor T2, the first compensation transistor T3 and the first reset transistor T4 are all cut off.
  • the data writing sub-circuit 201 in response to the first scan signal received at the first scan signal terminal GATE1, transmits the data signal received at the data signal terminal DATA to the second node N2. Under the control of the potential of the first node N1, the driving transistor T1 transmits the data signal received at the second node N2 to the third node N3.
  • the first compensation sub-circuit 202 in response to the second scan signal received at the second scan signal terminal GATE2, transmits the data signal received at the third node N3 to the first node N1.
  • the second compensation sub-circuit 205 in response to the third scan signal received at the third scan signal terminal GATE3, transmits the data signal received at the first node N1 to the fourth node N4.
  • each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212.
  • the first scan signal is 0, the third scan signal is 0, the second scan signal is 1, the first reset signal is 1, the first light emission signal is 1, and the second light emission signal is 1, where "0" represents a low level and "1" represents a high level.
  • the first scan signal terminal GATE1 and the third scan signal terminal GATE3 are input at low level
  • the second scan signal terminal GATE2 is input at high level
  • the data writing transistor T2, the first compensation transistor T3, and the second compensation transistor T7 are all turned on.
  • the first reset transistor T4 When the first reset signal terminal RESET1, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are input with a low level, the first reset transistor T4, the first light-emitting transistor T5, and the second light-emitting transistor T6 are all turned off.
  • the data signal received at the data signal terminal DATA is transmitted to the second node N2 through the data writing transistor T2, meaning the potential of the second node N2 is Vdata.
  • the potential of the first node N1 is Vint1.
  • the potential difference between the first node N1 and the second node N2 is Vint1 - Vdata.
  • the data signal at the second node N2 is transmitted to the first node N1 through the second compensation transistor T7.
  • the potential of the first node N1 gradually increases from Vin1.
  • the driving transistor T1 is turned off, and the data writing compensation phase P2 ends.
  • the larger of the data signal Vdata and the threshold voltages Vth1 and Vth2 is written into the first storage capacitor C1.
  • the second compensation sub-circuit 205 controls the first node N1 and the fourth node N4 to be cut off in response to the third scan signal received at the third scan signal terminal GATE3.
  • the second compensation sub-circuit 205 responds to the third scan signal received at the third scan signal terminal Gate3, controlling the first node N1 and the fourth node N4 to be turned off.
  • the third scan signal is 1, and the second compensation transistor T7 is turned off.
  • the driving transistor T1 is turned off, and the data writing compensation stage P2 ends.
  • the data signal Vdata and the threshold voltage Vth are written to the first storage capacitor C1.
  • the potential of the first node N1 is Vdata+Vth
  • the driving transistor T1 generates a driving current under the control of the potential of the first node N1 and the potential of the second node N2.
  • the data write compensation phase P2 includes a first data write compensation phase P21 and a second data write compensation phase P22.
  • the second compensation transistor T7 when the third scan signal is 1 and a high level is input at the third scan signal terminal, the second compensation transistor T7 is turned off.
  • the second compensation sub-circuit 205 responds to the third scan signal received at the third scan signal terminal GATE3, controlling the first node N1 and the fourth node N4 to be turned off.
  • the third scan signal when the third scan signal is 0, a low level is input at the third scan signal terminal, and the second compensation transistor T7 is turned on.
  • the second compensation sub-circuit 205 in response to the third scan signal received at the third scan signal terminal GATE3, transmits the data signal received at the first node N1 to the fourth node N4.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

L'invention concerne un circuit de pixel (21), un procédé d'attaque et un appareil d'affichage (1000). Le circuit de pixel (21) comprend un transistor d'attaque (T1), un sous-circuit d'écriture de données (201), un premier sous-circuit de compensation (202) et un second sous-circuit de compensation (205). Une première électrode du transistor d'attaque (T1) est connectée à un deuxième nœud (N2), une deuxième électrode de celui-ci est connectée à un troisième nœud (N3), une première électrode de commande de celui-ci est connectée à un premier nœud (N1), et une seconde électrode de commande de celui-ci est connectée à un quatrième nœud (N4) ; le sous-circuit d'écriture de données (201) est couplé au deuxième nœud (N2), à une première borne de signal de balayage (GATE1) et à une borne de signal de données (DATA) ; le premier sous-circuit de compensation (202) est couplé au premier nœud (N1), au troisième nœud (N3) et à une deuxième borne de signal de balayage (GATE2) ; le second sous-circuit de compensation (205) est couplé au premier nœud (N1), au quatrième nœud (N4) et à une troisième borne de signal de balayage (GATE3) ; et le second sous-circuit de compensation (205) est configuré pour commander la mise sous tension/hors tension du premier nœud (N1) et du quatrième nœud (N4) en réponse à la réception d'un troisième signal de balayage au niveau de la troisième borne de signal de balayage (GATE3).
PCT/CN2025/103032 2024-07-03 2025-06-24 Circuit de pixel, procédé d'attaque et appareil d'affichage Pending WO2026007745A1 (fr)

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CN118737045A (zh) * 2024-07-03 2024-10-01 京东方科技集团股份有限公司 像素电路及驱动方法、显示装置
CN119446093B (zh) * 2024-12-17 2025-10-17 武汉华星光电半导体显示技术有限公司 显示面板及其驱动方法

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US20160042694A1 (en) * 2014-08-07 2016-02-11 Samsung Display Co., Ltd. Pixel circuit and organic light-emitting diode display including the same
CN114512100A (zh) * 2020-10-29 2022-05-17 乐金显示有限公司 显示装置及其驱动方法
CN114550653A (zh) * 2022-02-17 2022-05-27 京东方科技集团股份有限公司 像素驱动电路以及显示装置
CN114758617A (zh) * 2022-03-29 2022-07-15 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
CN115376450A (zh) * 2022-08-31 2022-11-22 昆山国显光电有限公司 驱动电路及其控制方法、显示面板
CN118737045A (zh) * 2024-07-03 2024-10-01 京东方科技集团股份有限公司 像素电路及驱动方法、显示装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160042694A1 (en) * 2014-08-07 2016-02-11 Samsung Display Co., Ltd. Pixel circuit and organic light-emitting diode display including the same
CN114512100A (zh) * 2020-10-29 2022-05-17 乐金显示有限公司 显示装置及其驱动方法
CN114550653A (zh) * 2022-02-17 2022-05-27 京东方科技集团股份有限公司 像素驱动电路以及显示装置
CN114758617A (zh) * 2022-03-29 2022-07-15 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
CN115376450A (zh) * 2022-08-31 2022-11-22 昆山国显光电有限公司 驱动电路及其控制方法、显示面板
CN118737045A (zh) * 2024-07-03 2024-10-01 京东方科技集团股份有限公司 像素电路及驱动方法、显示装置

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