WO2026007746A1 - Unité d'alimentation, module d'alimentation en pont complet triphasé, système d'alimentation électrique et véhicule - Google Patents

Unité d'alimentation, module d'alimentation en pont complet triphasé, système d'alimentation électrique et véhicule

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Publication number
WO2026007746A1
WO2026007746A1 PCT/CN2025/103034 CN2025103034W WO2026007746A1 WO 2026007746 A1 WO2026007746 A1 WO 2026007746A1 CN 2025103034 W CN2025103034 W CN 2025103034W WO 2026007746 A1 WO2026007746 A1 WO 2026007746A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive layer
bridge
power
unit
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/103034
Other languages
English (en)
Chinese (zh)
Inventor
谢月
吴海平
吴彦
陈刚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BYD Co Ltd
Original Assignee
BYD Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BYD Co Ltd filed Critical BYD Co Ltd
Publication of WO2026007746A1 publication Critical patent/WO2026007746A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • This application belongs to the field of power supply technology, and in particular relates to a power unit, a three-phase full-bridge power module, a power supply system, and a vehicle.
  • Three-phase full-bridge power modules are important components in power electronic devices and are widely used in many fields, such as new energy vehicles. They can convert the DC current output by the battery into AC current to drive devices that require AC power, such as motors.
  • a power unit is a component of a three-phase full-bridge power module.
  • a typical power unit includes a single-layer ceramic substrate and half-bridge or full-bridge units disposed on the surface of this substrate.
  • a full-bridge unit is also composed of two half-bridge units.
  • Each half-bridge unit may include an upper-bridge power chip, a lower-bridge power chip, and a commutation circuit interconnecting the upper and lower-bridge power chips.
  • Existing technologies suffer from excessively high parasitic inductance in the power unit's packaging structure. This excessive inductance typically causes a series of problems during the switching process, including overvoltage during turn-off, voltage and current oscillations, mis-switching, and electromagnetic interference.
  • This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a power unit, a three-phase full-bridge power module, a power supply system, and a vehicle that can reduce parasitic inductance in the power unit packaging structure.
  • this application provides a power unit, including a first substrate and at least one half-bridge unit formed on the first substrate.
  • the half-bridge unit includes an upper bridge power chip and a lower bridge power chip.
  • the second electrode of the upper bridge power chip and the first electrode of the lower bridge power chip are both electrically connected to the AC output conductive path of the power unit.
  • the first electrode of the upper bridge power chip and the second electrode of the lower bridge power chip are respectively electrically connected to two different conductive layers.
  • the two different conductive layers are at least partially stacked and form the DC input conductive path of the power unit.
  • a first conductive layer and a second conductive layer are formed on the upper surface of the first substrate
  • An upper-bridge power chip is disposed on a first conductive layer, and the first electrode of the upper-bridge power chip is electrically connected to the first conductive layer.
  • the lower bridge power chip is disposed on the second conductive layer.
  • the second electrode of the upper bridge power chip and the first electrode of the lower bridge power chip are both electrically connected to the second conductive layer.
  • the second conductive layer is the AC output conductive path of the power unit.
  • the aforementioned power unit also includes:
  • the second substrate is disposed on the first conductive layer, and a third conductive layer is formed on the upper surface of the second substrate.
  • the third conductive layer and the first conductive layer are at least partially stacked, and the second electrode of the lower bridge power chip is electrically connected to the third conductive layer.
  • the first and third conductive layers form the DC input conductive path for the power unit.
  • the upper-bridge power chip and/or the lower-bridge power chip are MOSFETs, with the first electrode being the drain and the second electrode being the source.
  • the first conductive layer is the DC positive input conductive path of the power unit, and the third conductive layer is the DC negative input conductive path of the power unit.
  • the upper bridge power chip and/or the lower bridge power chip are IGBTs
  • the first electrode is the collector
  • the second electrode is the emitter
  • the first conductive layer is the DC positive input conductive path of the power unit
  • the third conductive layer is the DC negative input conductive path of the power unit.
  • a fourth conductive layer is also formed on the upper surface of the first substrate.
  • the fourth conductive layer is electrically connected to the control electrode of the upper bridge power chip.
  • a fifth conductive layer is also formed on the upper surface of the first substrate, and the fifth conductive layer is electrically connected to the control electrode of the lower bridge power chip.
  • the number of the upper bridge power chip and the lower bridge power chip is at least two, and the at least two upper bridge power chips and the at least two lower bridge power chips extend along the length direction of the first substrate.
  • the fourth conductive layer, the first conductive layer, the second conductive layer and the fifth conductive layer of the half-bridge unit are sequentially disposed.
  • the second electrode includes a power second electrode and a driving second electrode, and a sixth conductive layer and a seventh conductive layer are also formed on the upper surface of the first substrate.
  • the power second electrode of the upper bridge power chip is electrically connected to the second conductive layer, and the driving second electrode of the upper bridge power chip is electrically connected to the sixth conductive layer, forming a Kelvin connection;
  • the power second electrode of the lower bridge power chip is electrically connected to the third conductive layer, and the driving second electrode of the lower bridge power chip is electrically connected to the seventh conductive layer, forming a Kelvin connection.
  • the upper bridge power chip, the lower bridge power chip, and the second substrate are fixed to the upper surface of the first substrate by a connecting layer.
  • the second substrate is fixed to the first conductive layer on the side adjacent to the second conductive layer by a connection layer, and the upper bridge power chip is located on the side of the first conductive layer away from the second conductive layer.
  • the second electrode of the upper bridge power chip is electrically connected to the second conductive layer through a first connection line, and the first connection line crosses the second substrate;
  • the second terminal of the lower bridge power chip is electrically connected to the third conductive layer through the second connection line.
  • the first connecting wire is either a bonding wire or a copper sheet; the second connecting wire is either a bonding wire or a copper sheet.
  • the first substrate includes a first insulating substrate, a first copper layer located on the upper surface of the first insulating substrate, and a second copper layer located on the lower surface of the first insulating substrate.
  • the first copper layer is etched to obtain at least one of the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, and the seventh conductive layer.
  • the second substrate includes a second insulating substrate and a third copper layer located on the upper surface of the second insulating substrate, the third copper layer serving as a third conductive layer.
  • it also includes at least one of the following:
  • the DC positive input terminal and the direct negative input terminal are electrically connected to one of the first conductive layer and the third conductive layer, respectively.
  • the AC output terminal is electrically connected to the second conductive layer.
  • the first upper bridge drive terminal is electrically connected to the fourth conductive layer
  • the first lower bridge drive terminal is electrically connected to the fifth conductive layer
  • the second upper bridge drive terminal is electrically connected to the sixth conductive layer
  • the second lower bridge drive terminal is electrically connected to the seventh conductive layer.
  • a DC positive input terminal and a direct negative input terminal are disposed at a first end of the first substrate along the length direction, and are at least partially stacked.
  • the AC output terminal is located at the second end of the first substrate along its length.
  • the DC positive input terminal, the direct negative input terminal, and the AC output terminal are all disposed in the middle section of the first substrate in the length direction, with the DC positive input terminal and the direct negative input terminal disposed adjacent to each other.
  • two half-bridge units are formed on the first substrate, namely a first half-bridge unit and a second half-bridge unit;
  • the second conductive layer of the first half-bridge unit and the second conductive layer of the second half-bridge unit are integrally disposed, and the first conductive layer of the first half-bridge unit and the first conductive layer of the second half-bridge unit are respectively disposed on the outer side of the integrally disposed second conductive layer in the width direction.
  • the first conductive layer of the first half-bridge unit and the first conductive layer of the second half-bridge unit are electrically connected.
  • the fourth conductive layer and/or the sixth conductive layer are disposed outside the first conductive layer in the width direction;
  • the fifth and seventh conductive layers are disposed in the hollow area in the middle of the second conductive layer, and the lower bridge power chip of the first half-bridge unit and the lower bridge power chip of the second half-bridge unit are respectively disposed on both sides of the hollow area.
  • the cutout area includes multiple sub-cutout areas
  • the fifth conductive layer and the seventh conductive layer include multiple sub-conductive layers respectively disposed in the sub-cutout areas
  • the multiple sub-conductive layers of the fifth conductive layer are electrically connected to each other
  • the multiple sub-conductive layers of the seventh conductive layer are electrically connected to each other
  • the control electrode of the lower bridge power chip is respectively connected to the adjacent sub-conductive layer of the fifth conductive layer
  • the drive electrode of the lower bridge power chip is respectively connected to the adjacent sub-conductive layer of the seventh conductive layer.
  • a conductive connection layer is provided in the hollowed-out area at the edge of the first substrate, and the fourth conductive layer of the first half-bridge unit and the fourth conductive layer of the second half-bridge unit are electrically connected through the conductive connection layer, and/or the sixth conductive layer of the first half-bridge unit and the sixth conductive layer of the second half-bridge unit are electrically connected through the conductive connection layer.
  • this application provides a three-phase full-bridge power module, including three power units as described above, as well as a heat sink and a housing;
  • the lower surface of the first substrate in each of the three power units is fixed on the heat dissipation substrate, and the outer casing covers the three power units.
  • embodiments of this application also provide a power supply system, including a battery and the aforementioned three-phase full-bridge power module.
  • embodiments of this application also provide a vehicle including the aforementioned power system.
  • the half-bridge unit includes a first substrate, and an upper bridge power chip and a lower bridge power chip formed on the first substrate.
  • the second terminal of the upper bridge power chip and the first terminal of the lower bridge power chip serve as AC output terminals, both electrically connected to the AC output conductive path of the power unit.
  • the first terminal of the upper bridge power chip and the second terminal of the lower bridge power chip serve as DC input terminals, respectively electrically connected to two different conductive layers.
  • the two different conductive layers are at least partially stacked and form the DC input conductive path of the power unit.
  • the currents in the two different conductive layers flow in opposite directions, resulting in negative mutual inductance. This mutual inductance cancellation effect reduces the total parasitic inductance in the power unit.
  • the two conductive layers are at least partially stacked to form a stacked structure, making the distance between the conductive planes formed by the two layers extremely small. Generally, the closer the distance, the better the mutual inductance cancellation effect. Therefore, in this application embodiment, it helps to reduce the parasitic inductance inside the power unit.
  • Figure 1 is a schematic diagram of the structure of a power chip in an embodiment of this application.
  • Figure 3 is a top view of a power unit in an embodiment of this application.
  • Figure 4 is a top view of the upper surface of the first substrate in an embodiment of this application.
  • Figure 5 is a schematic diagram of the connection of the power unit in an embodiment of this application.
  • Figure 6 is a second schematic diagram of the connection of the power unit in an embodiment of this application.
  • FIG. 7 is a schematic diagram of the power unit with connection terminals in an embodiment of this application.
  • FIG. 8 is a schematic diagram of the power unit with connection terminals in an embodiment of this application.
  • FIG. 9 is an equivalent circuit diagram of the power unit in the embodiment shown in Figure 7;
  • Figure 10 is a top view of another power unit in an embodiment of this application.
  • Figure 11 is a top view of the first substrate in the embodiment shown in Figure 10;
  • Figure 12 is a top view of the second substrate in the embodiment shown in Figure 10;
  • Figure 13 is a schematic diagram of the connection of the power unit in the embodiment shown in Figure 10;
  • Figure 14 is a schematic diagram of the structure of the power unit with connection terminals in an embodiment of this application.
  • Figure 15 is a schematic diagram of the structure of the three-phase full-bridge power module in an embodiment of this application.
  • Figure 16 is a schematic diagram of the structure of the three-phase full-bridge power module in an embodiment of this application.
  • Figure 17 is a schematic diagram of a power supply system according to an embodiment of this application.
  • Figure 18 is a schematic diagram of a vehicle according to an embodiment of this application.
  • Figure 19 is a schematic diagram of another vehicle in an embodiment of this application.
  • the half-bridge unit in the power unit provided in this application includes a first substrate, and an upper-bridge power chip and a lower-bridge power chip formed on the first substrate.
  • the second terminal of the upper-bridge power chip and the first terminal of the lower-bridge power chip serve as AC output terminals, both electrically connected to the AC output conductive path of the power unit.
  • the first terminal of the upper-bridge power chip and the second terminal of the lower-bridge power chip serve as DC input terminals, respectively electrically connected to two different conductive layers.
  • the two different conductive layers are at least partially stacked and form the DC input conductive path of the power unit.
  • the currents in the two different conductive layers flow in opposite directions, exhibiting negative mutual inductance, forming a mutual inductance cancellation effect, thereby reducing the total parasitic inductance in the power unit.
  • the two conductive layers in this application are at least partially stacked, forming a stacked structure, making the distance between the conductive planes formed by the two layers extremely small. Generally, the closer the distance, the better the mutual inductance cancellation effect, as this application helps to reduce the parasitic inductance inside the power unit.
  • the two conductive layers that serve as the DC input conductive path can be at least partially stacked in various ways.
  • the two conductive layers can be disposed on different surfaces of the first substrate, or more substrates can be added and the two conductive layers can be disposed on different substrates.
  • the power unit includes a first substrate 2 and at least one half-bridge unit formed on the first substrate 2.
  • Each half-bridge unit may include a first conductive layer 21 and a second conductive layer 22 formed on the upper surface of the first substrate 2.
  • An upper bridge power chip 101 is disposed on the first conductive layer 21, and the first electrode of the upper bridge power chip 101 is electrically connected to the first conductive layer 21.
  • a lower bridge power chip 102 is disposed on the second conductive layer 22, and the second electrode of the upper bridge power chip 101 and the first electrode of the lower bridge power chip 102 are both electrically connected to the second conductive layer 22.
  • the second conductive layer 22 is the AC output conductive path of the power unit.
  • the power unit also includes a second substrate 3, which is disposed on the first conductive layer 21, and a third conductive layer 31 is formed on the upper surface of the second substrate 3.
  • the third conductive layer 31 and the first conductive layer 21 are at least partially stacked, and the second electrode of the lower bridge power chip 102 is electrically connected to the third conductive layer 31.
  • the first conductive layer 21 and the third conductive layer 31 are the DC input conductive paths of the power unit. Specifically, they can be DC positive input conductive paths or DC negative input conductive paths. That is, if the first conductive layer 21 is a DC positive input conductive path, then the third conductive layer 31 is a DC negative input conductive path, or if the first conductive layer 21 is a DC negative input conductive path, then the third conductive layer 31 is a DC positive input conductive path.
  • the third conductive layer 31 and the first conductive layer 21 are at least partially stacked to form a 3D multilayer circuit structure.
  • the current directions of the DC positive input conductive path and the DC negative input conductive path are opposite, which can form good coupling to reduce inductance.
  • the stacked structure reduces the distance between the two, further enhancing the mutual inductance cancellation effect and achieving extremely low parasitic inductance in the power unit.
  • the upper-bridge power chip 101 and lower-bridge power chip 102 in the above embodiments of this application can be power chips of the same type and structure, or they can be power chips of different types and structures.
  • Figure 1 is a schematic diagram of the structure of a power chip in an embodiment of this application. As shown in Figure 1, the power chip can be a vertically structured power chip, including a first electrode 11 on the bottom surface, a second electrode 12 on the top surface, and a control electrode 13. Figure 1 mainly shows the top surface of the power chip, with the bottom surface on the opposite side.
  • the second electrode 12 when the second electrode 12 is the source electrode, the second electrode 12 can be divided into a power second electrode 121 and a drive second electrode 122, so that they can be connected to the external power circuit and drive circuit respectively. However, the two are connected inside the chip and have equal potentials. Or, in some cases, the second electrode 12 is not divided, and the second electrode 12 can be connected to both the power circuit and the drive circuit at the same time.
  • the power chip types include, but are not limited to, vertical structure chips such as MOSFETs and IGBTs.
  • the aforementioned first electrode 11 is the drain, the second electrode 12 is the source, and the control electrode 13 is the gate.
  • the aforementioned first conductive layer 21 is the DC positive input conductive path of the power unit
  • the third conductive layer 31 is the DC negative input conductive path of the power unit; or, the aforementioned first electrode 11 is the source, the second electrode 12 is the drain, and the control electrode 13 is the gate.
  • the aforementioned first conductive layer 21 is the DC negative input conductive path of the power unit
  • the third conductive layer 31 is the DC positive input conductive path of the power unit.
  • the first electrode 11 is the collector
  • the second electrode 12 is the emitter
  • the control electrode 13 is the gate.
  • the first conductive layer 21 is the DC positive input conductive path of the power unit
  • the third conductive layer 31 is the DC negative input conductive path of the power unit.
  • the first electrode 11 is the emitter
  • the second electrode 12 is the collector
  • the control electrode 13 is the gate.
  • the first conductive layer 21 is the DC negative input conductive path of the power unit
  • the third conductive layer 31 is the DC positive input conductive path of the power unit.
  • both the upper bridge power chip 101 and the lower bridge power chip 102 are MOSFETs or IGBTs, or where the upper bridge power chip 101 is a MOSFET and the lower bridge power chip 102 is an IGBT, or where the upper bridge power chip 101 is an IGBT and the lower bridge power chip 102 is a MOSFET.
  • the electrode types and connection relationships of each power chip are as described above.
  • both the upper bridge power chip 101 and the lower bridge power chip 102 are MOSFETs, and the first electrode is the drain and the second electrode is the source.
  • FIG. 2 is a cross-sectional structural diagram of a power unit according to an embodiment of this application.
  • the power unit includes a first substrate 2 and a half-bridge unit located on the first substrate.
  • the half-bridge unit may include a second substrate 3, an upper bridge power chip 101, and a lower bridge power chip 102.
  • the second substrate 3 is disposed on the upper surface of the first substrate 2 to form a stacked substrate, and the upper bridge power chip 101 and the lower bridge power chip 102 are also disposed on the upper surface of the first substrate 2.
  • the first substrate 2 can be a double-sided copper-clad ceramic substrate, such as an AMB substrate or a DBC substrate.
  • the ceramic substrate is the first insulating substrate 20, whose main functions are support, insulation, and heat conduction.
  • Copper layers can be disposed on both the upper and lower surfaces of the ceramic substrate.
  • a first copper layer can be disposed on the upper surface and a second copper layer can be disposed on the lower surface.
  • the first copper layer on the upper surface mainly functions to conduct electricity and can be etched to obtain the desired pattern, such as the first conductive layer 21 and the second conductive layer 22 mentioned above.
  • the second copper layer mainly functions to conduct heat and can be connected to the heat dissipation substrate.
  • the second substrate 3 has a lower requirement for heat conduction and offers several structural options.
  • it can be double-sided copper-clad with a second insulating substrate 30 in the middle, such as an AMB substrate, DBC substrate, or other ceramic substrate, or a thick copper PCB board, FPC flexible substrate, etc.
  • the second substrate 3 can be connected to the first substrate 2 via a connecting layer 4.
  • the main function of the second insulating substrate 30 is to provide support and insulation.
  • the second substrate 3 can have a third copper layer only on its upper surface, serving as the third conductive layer 31.
  • the second insulating substrate 30 can additionally possess adhesive capabilities, allowing the third copper layer to be bonded to the upper surface of the first substrate 2 via the second insulating substrate 30.
  • copper is used to prepare the conductive layers, but other materials with conductive properties can also be used to prepare the conductive layers.
  • the upper bridge power chip 101 and the lower bridge power chip 102 can also be connected to the upper surface of the first substrate 2 through the connection layer 4, which has good electrical and thermal conductivity.
  • the connection layer 4 can be a sintered silver layer or a solder layer, and the corresponding connection process can be sintering or welding.
  • the first copper layer on the upper surface of the first substrate 2 and the third copper layer on the upper surface of the second substrate 3 constitute a stacked conductive plane.
  • the first copper layer and the third copper layer in the embodiments of this application have a stacked structure, making the distance between the conductive planes formed by the two extremely small, which helps to achieve extremely low parasitic inductance.
  • Figure 3 is a top view of a power unit according to an embodiment of this application.
  • a first copper layer is provided on the upper surface of the first substrate 2
  • a first conductive layer 21 and a second conductive layer 22 can be obtained by etching.
  • a fourth conductive layer 23 can be formed on the upper surface of the first substrate 2.
  • the fourth conductive layer 23 is electrically connected to the gate of the control electrode 13 of the upper bridge power chip 101.
  • a fifth conductive layer 26 is also formed on the upper surface of the first substrate 2.
  • the fifth conductive layer 26 is electrically connected to the control electrode 13 of the lower bridge power chip 102.
  • the control electrode 13 is the gate.
  • the control electrode 13 is the gate.
  • the second electrode 12 of the upper bridge power chip 101 and the lower bridge power chip 102 can be divided into a power second electrode 121 and a driving second electrode 122
  • a sixth conductive layer 24 and a seventh conductive layer 25 can also be formed on the upper surface of the first substrate 2.
  • the power second electrode 121 of the upper bridge power chip 101 is electrically connected to the second conductive layer 22
  • the driving second electrode 122 of the upper bridge power chip 102 is electrically connected to the sixth conductive layer 24, forming a Kelvin connection.
  • the power second electrode 121 of the lower bridge power chip 102 is electrically connected to the third conductive layer 31, and the driving second electrode 122 of the upper bridge power chip 102 is electrically connected to the seventh conductive layer 25, forming a Kelvin connection.
  • the aforementioned driving second electrode 122 serves as the driving source. Furthermore, as shown in Figure 3, there are at least two upper-bridge power chips 101 and at least two lower-bridge power chips 102, and both extend along the length direction of the first substrate 2, i.e., direction A, while the conductive layers are arranged along direction B.
  • the number of upper-bridge power chips 101 and lower-bridge power chips 102 in the half-bridge unit can also be greater, and they can continue to extend along the length direction A.
  • Figure 4 is a top view of the upper surface of the first substrate in an embodiment of this application.
  • the fourth conductive layer 23, the first conductive layer 21, the second conductive layer 22, and the fifth conductive layer 26 of the half-bridge unit are sequentially disposed in the width direction of the first substrate.
  • a sixth conductive layer 24 can be formed between the fourth conductive layer 23 and the first conductive layer 21, and a seventh conductive layer 25 can be formed between the second conductive layer 22 and the fifth conductive layer 26.
  • the aforementioned sixth conductive layer 24 and seventh conductive layer 25 do not need to be formed on the upper surface of the first substrate 2.
  • the specific locations of the sixth conductive layer 24 and seventh conductive layer 25, as well as the fourth conductive layer 23 and fifth conductive layer 26, can also be configured such that the sixth conductive layer 24 and seventh conductive layer 25 are on the outer side.
  • the second substrate 3 can be fixed on the first conductive layer 21 on the side adjacent to the second conductive layer 22 by the connection layer 4, while the upper bridge power chip 101 is located on the first conductive layer 21 on the side away from the second conductive layer 22.
  • Figures 5 and 6 are schematic diagrams of the power unit connection in the embodiments of this application.
  • the second electrode 12 of the upper bridge power chip 101 can be electrically connected to the second conductive layer 22 through a first connecting line, and the first connecting line crosses the second substrate 3.
  • the first connecting line mentioned above can be the first bonding line 51 in the example shown in Figure 5, or it can be the first copper sheet 62 in the embodiment shown in Figure 6.
  • the second electrode 12 of the lower-bridge power chip 102 can be electrically connected to the third conductive layer 31 via a second connecting line.
  • This second connecting line can be the second bonding wire 52 in the example shown in Figure 5, or the second copper sheet 61 in the embodiment shown in Figure 6.
  • control electrodes 13 of the upper bridge power chip 101 and the lower bridge power chip 102 can be electrically connected to the fourth conductive layer 23 and the fifth conductive layer 26 respectively via a third connecting line.
  • the third connecting line can be a third bonding line 53.
  • the power second electrode 121 can be electrically connected to the second conductive layer 22 via a first connecting line, and to the third conductive layer 31 via a second connecting line; while the drive second electrodes 122 of the upper bridge power chip 101 and the lower bridge power chip 102 can be electrically connected to the sixth conductive layer 24 and the seventh conductive layer 25 respectively via a fourth connecting line, which can be a fourth bonding line 54.
  • the difference between the first and second connecting lines lies in whether they are bonded wires or copper sheets.
  • copper sheet 61 can be connected to the second electrode 12 of the power chip, such as the power second electrode 121, as well as the second conductive layer 22 and the third conductive layer 31, by welding or sintering.
  • bonded wires can typically be used.
  • FIGs 7 and 8 are schematic diagrams of the power unit's connection terminals in an embodiment of this application.
  • each conductive layer of the power unit in this embodiment has a corresponding connection terminal, such as a DC positive input terminal 71 and a direct negative input terminal 72, which can be electrically connected to one of the first conductive layer 21 and the third conductive layer 31, respectively.
  • the DC positive input terminal 71 is electrically connected to the first conductive layer 21, while the direct negative input terminal 72 is electrically connected to the third conductive layer 31.
  • the first electrode 11 of the upper bridge power chip 101 and the lower bridge power chip 102 can be the drain
  • the second electrode 12 can be the source
  • the first conductive layer 21 can be the DC positive circuit of the power unit
  • the third conductive layer 31 can be the DC negative input conductive path of the power unit.
  • the DC positive input terminal 71 can be electrically connected to the third conductive layer 31, while the direct negative input terminal 72 can be electrically connected to the first conductive layer 21.
  • an AC output terminal 73 which can be electrically connected to the second conductive layer 22, and AC power can be output from the power unit through the AC output terminal 73.
  • it may also include:
  • the first upper bridge drive terminal 74 is electrically connected to the aforementioned fourth conductive layer 23;
  • the first lower bridge drive terminal 75 is electrically connected to the aforementioned fifth conductive layer 26;
  • the second upper bridge drive terminal 76 is electrically connected to the aforementioned sixth conductive layer 24;
  • the second lower bridge drive terminal 77 is electrically connected to the aforementioned seventh conductive layer 25.
  • the DC positive input terminal 71 and the direct negative input terminal 72 are disposed at the first end of the first substrate 2 along its length, with a certain insulating distance between them, and are at least partially stacked. This stacking arrangement reduces the parasitic inductance introduced by the DC positive input terminal 71 and the direct negative input terminal 72.
  • the AC output terminal 73 is disposed at the second end of the first substrate along its length. The placement of the AC output terminal 73 at the other end of the length facilitates the layout of external circuitry.
  • Each drive terminal can be disposed at either the first or the second end.
  • each terminal may be connected to the corresponding conductive layer by ultrasonic welding, soldering, or sintering.
  • the DC positive input terminal 71, the direct negative input terminal 72, and the AC output terminal 73 can all be located in the middle section of the first substrate 2 along its length.
  • the DC positive input terminal 71 and the direct negative input terminal 72 are arranged adjacent to each other, which reduces the parasitic inductance introduced by the terminals. All of the terminals are led out vertically upwards.
  • the upper bridge power chip 101 is divided into two groups, located on both sides of the DC positive input terminal 71, and the lower bridge power chip 102 is divided into two groups, located on both sides of the AC output terminal 73.
  • This terminal arrangement method can further reduce the parasitic inductance introduced by the conductors inside the power unit and effectively improve dynamic current sharing.
  • FIG 9 is an equivalent circuit diagram of the power unit in the embodiment shown in Figure 7.
  • the overall commutation circuit is as follows: the positive DC current terminal is connected to the first conductive layer 21 through the positive DC input terminal 71.
  • the first conductive layer 21 is connected to the first terminal of the upper bridge power chip 101, which is the drain.
  • the second power terminal of the upper bridge power chip 101 i.e., the power source terminal, is connected to the second conductive layer 22.
  • the second conductive layer 22 is connected to the first terminal of the lower bridge power chip 102.
  • the second power terminal of the lower bridge power chip 102 i.e., the power source terminal, is connected to the third conductive layer 31.
  • the third conductive layer 31 is connected to the negative DC input terminal 72.
  • the second conductive layer 22 is electrically connected to the AC output terminal 73, which can then be connected to an external output load.
  • parasitic inductance is introduced into each conductor segment of the overall converter circuit, with the inductance introduced by the first conductive layer 21 and the third conductive layer 31 typically dominating.
  • the main inductance is segmented with the connection position of each power chip as the node, and the parasitic inductance introduced by the conductive layer between two adjacent power chips is marked.
  • the self-inductance of each conductive layer segment on the first conductive layer 21 is L1
  • the self-inductance of each conductive layer segment on the third conductive layer 31 is L2
  • the mutual inductance between them is M.
  • the aforementioned inductance L is the main component of the power unit inductance and also a major factor causing dynamic uneven current, which needs to be reduced as much as possible.
  • the aforementioned mutual inductance M is negative. Therefore, the total inductance of the circuit can be reduced by strengthening the coupling between the first conductive layer 21 and the third conductive layer 31.
  • the coupling coefficient is related to the distance between the two conductive layers; the smaller the distance, the larger the coupling coefficient and the smaller the total parasitic inductance.
  • the stacked structure proposed in this embodiment can significantly reduce the overall distance between the first conductive layer 21 and the third conductive layer 31, thereby achieving a higher coupling coefficient and extremely low parasitic inductance.
  • Simulation results of the technical solution provided in this embodiment show that the coupling coefficient between each segment of the first conductive layer 21 and the third conductive layer 31 in the embodiment shown in Figure 7 reaches -0.85, while the coupling coefficient between planar commutation loops in a traditional power unit is approximately -0.05 to -0.5.
  • the inductance introduced by the commutation loop inside the power unit shown in Figure 7 (including the AMB substrate and the connection lines between the power chips) is only about 1 to 2 nH, far lower than the 5 to 10 nH of traditional power units. Therefore, the technical solution provided in this embodiment can effectively reduce the parasitic inductance introduced by the conductive paths inside the power unit and effectively improve dynamic current sharing.
  • the width of the first substrate can be extended to create more half-bridge units. These extended half-bridge units can be connected in parallel to form a half-bridge module with greater current carrying capacity.
  • the specific number of extensions can be set according to actual needs; for example, another half-bridge unit can be added.
  • Figure 10 is a top view of another power unit in an embodiment of this application. As shown in Figure 10, this power unit includes a first substrate 2 and two half-bridge units formed on the first substrate 2, namely, a first half-bridge unit 1001 and a second half-bridge unit 1002.
  • the first half-bridge unit 1001 and the second half-bridge unit 1002 can respectively have the structural features described in the above embodiments.
  • Figure 11 is a top view of the first substrate in the embodiment shown in Figure 10
  • Figure 12 is a top view of the second substrate in the embodiment shown in Figure 10
  • Figure 13 is a connection diagram of the power unit in the embodiment shown in Figure 10.
  • conductive layers that are close in position and have the same function in the first half-bridge unit 1001 and the second half-bridge unit 1002 can be merged or connected on the first substrate 2 to optimize the layout, improve integration and performance.
  • the second conductive layers 22 of the first half-bridge unit 1001 and the second half-bridge unit 1002 can be connected to each other to form an integral structure.
  • the first conductive layer 21 of the first half-bridge unit 1001 and the first conductive layer 21 of the second half-bridge unit 1002 can be respectively disposed on the outer side of the integrally disposed second conductive layer 22 in the width direction.
  • a connection structure can be added so that the first conductive layers 21 of the two half-bridge units are also electrically connected to form an integral structure.
  • the electrical connection can be made by bonding wires, copper sheets, etc., or as shown in FIG11, an interconnecting conductive layer 29 communicating with the first conductive layers on both sides is formed on the upper surface of the first substrate to form an integral first conductive layer.
  • At least one of the fourth conductive layer 23 electrically connected to the control electrode of the upper bridge power chip 101 of the two half-bridge units, and the sixth conductive layer 24 electrically connected to the driving second electrode of the upper bridge power chip 101 of the two half-bridge units can be disposed on the outer side of the first conductive layer 21 in the width direction.
  • At least one of the fifth conductive layer 25 electrically connected to the control electrode of the lower bridge power chip 102 of the two half-bridge units, and the seventh conductive layer 26 electrically connected to the driving second electrode of the lower bridge power chip 102 of the two half-bridge units can be disposed within the hollow area 27 in the middle of the second conductive layer 22.
  • the lower bridge power chip 102 of the first half-bridge unit 1001 and the lower bridge power chip 102 of the second half-bridge unit 1002 are respectively disposed on both sides of the hollow area 27.
  • the hollowed-out area 27 includes multiple sub-hollowed-out areas
  • the fifth conductive layer 25 and the seventh conductive layer 26 can include multiple sub-conductive layers respectively disposed in the different sub-hollowed-out areas.
  • the multiple sub-conductive layers of the fifth conductive layer 25 can be electrically connected to each other, and the multiple sub-conductive layers of the seventh conductive layer 26 can also be electrically connected to each other.
  • the control electrode of the lower bridge power chip 102 is respectively connected to the adjacent sub-conductive layers of the fifth conductive layer 25, and the driving electrode of the lower bridge power chip 102 is respectively connected to the adjacent sub-conductive layers of the seventh conductive layer 26.
  • a conductive connection layer 28 may be provided in the cutout region 27 located at the edge of the first substrate 2.
  • the fourth conductive layer 23 of the first half-bridge unit 1001 and the fourth conductive layer 23 of the second half-bridge unit 1002 are electrically connected through the conductive connection layer 28, and/or, the sixth conductive layer 24 of the first half-bridge unit 1001 and the sixth conductive layer 24 of the second half-bridge unit 1002 may also be electrically connected through the conductive connection layer 28.
  • Figure 13 illustrates an example of electrical connection via bonding wires.
  • the second electrode of the upper bridge power chip 101 of the two half-bridge units can be electrically connected to the second conductive layer 22 via a first bonding wire 51, which crosses the second substrate 3.
  • the second electrode 12 of the lower bridge power chip 102 of the two half-bridge units can be electrically connected to the third conductive layer 31 via a second bonding wire 52. Both the first bonding wire 51 and the second bonding wire 52 can be replaced with copper sheets.
  • control electrodes 13 of the upper bridge power chip 101 and the lower bridge power chip 102 can be electrically connected to the fourth conductive layer 23 and the fifth conductive layer 26 respectively via the third bonding wire 53.
  • the power second electrode 121 can be electrically connected to the second conductive layer 22 via the first bonding wire 51 and to the third conductive layer 31 via the second bonding wire 52; while the drive second electrodes 122 of the upper bridge power chip 101 and the lower bridge power chip 102 can be electrically connected to the sixth conductive layer 24 and the seventh conductive layer 25 respectively via the fourth bonding wire 54.
  • the two fourth conductive layers 23 disposed outside the second conductive layer 22 can be connected to the conductive connection layer 28 of the hollow area via the third bonding line 53, and the two sixth conductive layers 24 disposed outside the second conductive layer 22 can be connected to the conductive connection layer 28 of the hollow area via the fourth bonding line 54.
  • FIG 14 is a schematic diagram of the power unit's connection terminals in an embodiment of this application.
  • the DC positive connection terminal 71 is electrically connected to the first conductive layer 21, and the DC negative connection terminal 72 is electrically connected to the third conductive layer 31.
  • Both the DC positive connection terminal 71 and the DC negative connection terminal 72 are disposed at the first end of the first substrate, and are at least partially stacked, which can effectively reduce parasitic inductance.
  • the AC output terminal 73 may be disposed at the second end of the first substrate, and further includes:
  • the first upper bridge drive terminal 74 is electrically connected to the aforementioned fourth conductive layer 23;
  • the first lower bridge drive terminal 75 is electrically connected to the aforementioned fifth conductive layer 26;
  • the second upper bridge drive terminal 76 is electrically connected to the aforementioned sixth conductive layer 24;
  • the second lower bridge drive terminal 77 is electrically connected to the aforementioned seventh conductive layer 25.
  • the required number of half-bridge units can be selected according to power requirements to obtain different power ranges. Structurally, it can be extended in the manner described in the above embodiments to be suitable for an extremely wide power range.
  • FIGS 15 and 16 are schematic diagrams of the structure of the three-phase full-bridge power module in this application embodiment.
  • Figure 16 shows the addition of a housing 9 to Figure 15.
  • the three-phase full-bridge power module includes three power units as shown in any of Figures 1-14, a heat sink 8, and a housing 9. The lower surface of the first substrate 2 of each of the three power units is fixed on the heat sink 8, and the housing 9 covers the three power units.
  • an opening can be made in the housing 9 to expose at least one of the following: DC positive input terminal, direct negative input terminal, AC output terminal, first upper bridge drive terminal, second upper bridge drive terminal, first lower bridge drive terminal, and second lower bridge drive terminal of each of the power units.
  • the aforementioned heat dissipation substrate 8 serves both mechanical fixing and thermal conduction purposes.
  • the first substrate 2 may have copper layers on both its upper and lower surfaces.
  • the copper layer on the upper surface has been etched into the conductive layers of the power unit, while the copper layer on the lower surface primarily serves a thermal conduction function. In this case, it can be connected to the aforementioned heat dissipation substrate 8, thereby achieving good heat dissipation.
  • the aforementioned outer casing 9 primarily serves a protective and insulating function.
  • the three-phase full-bridge power module provided in this application includes any of the power units shown in Figures 1-14.
  • the first conductive layer 21 and the third conductive layer 31 are stacked and connected to the DC positive input terminal and the DC negative input terminal, respectively. This results in the current directions of the first conductive layer 21 and the third conductive layer 31 being opposite, thus having negative mutual inductance.
  • This mutual inductance cancellation effect reduces the total parasitic inductance in the power unit and effectively improves dynamic current sharing.
  • FIG 17 is a schematic diagram of a power supply system according to an embodiment of this application.
  • the power supply system includes a battery 171 and the aforementioned three-phase full-bridge power module 172.
  • the battery 171 can output direct current (DC), which can be converted into alternating current (AC) by the three-phase full-bridge power module 172 and further output to electrical equipment that needs to operate on AC power.
  • DC direct current
  • AC alternating current
  • the power supply system provided in this embodiment has the technical features and effects of the above embodiments, which will not be repeated in this embodiment.
  • FIG 18 is a schematic diagram of the structure of a vehicle according to an embodiment of this application.
  • the vehicle includes the aforementioned power system 18.
  • the power system 18 can supply power to various electrical devices on the vehicle.
  • the three-phase full-bridge power module in the power system 18 can convert DC power to AC power.
  • This embodiment has the corresponding technical features and effects described in the above embodiments, which will not be repeated in this embodiment.
  • the structure of the vehicle can also be referred to Figure 19.
  • first,” “second,” etc. used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first,” “second,” etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more.
  • “and/or” indicates at least one of the connected objects, and the character “/” generally indicates that the preceding and following objects are in an “or” relationship.
  • first feature and “second feature” may include one or more of the features.
  • first feature being “above” or “below” the second feature may include the first and second features being in direct contact, or the first and second features being in contact through another feature between them.
  • the terms “above,” “over,” and “on top” for the first feature and the second feature include the first feature being directly above or diagonally above the second feature, or simply indicate that the first feature is at a higher horizontal level than the second feature.
  • references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples,” etc. indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application.
  • the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.
  • the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)

Abstract

La présente demande divulgue une unité d'alimentation, un module d'alimentation en pont complet triphasé, un système d'alimentation électrique et un véhicule. L'unité d'alimentation comprend une puce de puissance de pont supérieur et une puce de puissance de pont inférieur, un second pôle de la puce de puissance de pont supérieur et un premier pôle de la puce de puissance de pont inférieur étant tous deux électriquement connectés à un circuit conducteur de sortie de courant alternatif de l'unité d'alimentation, et un premier pôle de la puce de puissance de pont supérieur et un second pôle de la puce de puissance de pont inférieur étant électriquement connectés à deux couches conductrices différentes, respectivement. Les deux couches conductrices différentes sont au moins partiellement empilées et forment un circuit conducteur d'entrée à courant continu de l'unité d'alimentation.
PCT/CN2025/103034 2024-07-05 2025-06-24 Unité d'alimentation, module d'alimentation en pont complet triphasé, système d'alimentation électrique et véhicule Pending WO2026007746A1 (fr)

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CN222980507U (zh) * 2024-07-05 2025-06-13 比亚迪半导体股份有限公司 功率单元、三相全桥功率模块、电源系统和车辆
CN120581507B (zh) * 2025-08-04 2025-12-23 潍柴动力股份有限公司 一种功率模块

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CN118136619A (zh) * 2024-05-08 2024-06-04 浙江晶能微电子有限公司 功率模块的半桥结构、功率模块及车辆
CN222980507U (zh) * 2024-07-05 2025-06-13 比亚迪半导体股份有限公司 功率单元、三相全桥功率模块、电源系统和车辆

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US20230335457A1 (en) * 2020-12-25 2023-10-19 Byd Semiconductor Company Limited Power module
CN220233181U (zh) * 2023-07-21 2023-12-22 江苏涵润汽车电子有限公司 一种功率模块
CN117374040A (zh) * 2023-10-16 2024-01-09 浙江晶能微电子有限公司 功率模块及车辆
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