WO2026009092A1 - Dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur

Info

Publication number
WO2026009092A1
WO2026009092A1 PCT/IB2025/056477 IB2025056477W WO2026009092A1 WO 2026009092 A1 WO2026009092 A1 WO 2026009092A1 IB 2025056477 W IB2025056477 W IB 2025056477W WO 2026009092 A1 WO2026009092 A1 WO 2026009092A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor layer
semiconductor
film
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/IB2025/056477
Other languages
English (en)
Japanese (ja)
Inventor
倉田求
村川努
手塚祐朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of WO2026009092A1 publication Critical patent/WO2026009092A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs

Definitions

  • One aspect of the present invention relates to a transistor and a semiconductor device. Furthermore, another aspect of the present invention relates to a method for manufacturing a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention include semiconductor devices, signal processing devices, arithmetic devices, memory devices, input devices, input/output devices, sensors, imaging devices, display devices, light-emitting devices, power storage devices, electronic devices, and driving methods or manufacturing methods thereof.
  • a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a transistor or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics.
  • AI chips are also being developed as semiconductor devices.
  • AI chips include GPUs, FPGAs (Field Programmable Gate Arrays), and application-specific integrated circuits (ASICs). These semiconductor devices are used in a variety of electronic devices, including computers and personal digital assistants.
  • various memory storage methods have been developed to suit different applications, such as temporary storage during computational processing and long-term data storage. Typical memory storage methods include DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and flash memory.
  • transistors are widely used in electronic devices such as integrated circuits and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, oxide semiconductors are also attracting attention as other materials.
  • Patent Document 1 discloses a low-power CPU that utilizes the property of low leakage current.
  • Patent Document 2 discloses a memory device that can retain stored content for a long period of time.
  • An object of one embodiment of the present invention is to provide a semiconductor device having a novel structure.
  • An object of one embodiment of the present invention is to improve at least one of the problems of the prior art.
  • One aspect of the present invention is a semiconductor device having a first semiconductor layer, a pair of first spacer layers, a pair of first conductive layers, a second conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer.
  • the pair of first spacer layers are spaced apart and located above the first insulating layer.
  • the first semiconductor layer is located above the pair of first spacer layers.
  • the first semiconductor layer has a first region that does not overlap with the pair of first spacer layers.
  • the pair of first conductive layers are spaced apart and have portions located above the first semiconductor layer. Each of the pair of first conductive layers has portions that contact at least two side surfaces of the first semiconductor layer.
  • the third insulating layer has portions that are located on the pair of first conductive layers, portions that contact the side surfaces of the pair of first conductive layers, and a portion that contacts the first insulating layer.
  • the second insulating layer has portions that contact the top, bottom, and side surfaces of the first semiconductor layer in the first region of the first semiconductor layer.
  • the second conductive layer has portions that surround the top, bottom, and side surfaces of the first semiconductor layer via the second insulating layer.
  • Another aspect of the present invention is a semiconductor device having first and second semiconductor layers, a pair of first and second spacer layers, a pair of first conductive layers, a second conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a pair of third conductive layers.
  • the pair of first spacer layers are spaced apart and located above the first insulating layer.
  • the first semiconductor layer is located above the pair of first spacer layers.
  • the first semiconductor layer has a first region that does not overlap with the pair of first spacer layers.
  • the pair of second spacer layers are spaced apart and located above the first semiconductor layer.
  • the second semiconductor layer is located above the pair of second spacer layers.
  • the second semiconductor layer has a second region that does not overlap with the pair of second spacer layers.
  • the pair of first conductive layers are spaced apart and have portions located above the first and second semiconductor layers.
  • Each of the pair of first conductive layers has a portion in contact with at least two side surfaces of the first semiconductor layer and a portion in contact with at least two side surfaces of the second semiconductor layer.
  • the third insulating layer has a portion located on the pair of first conductive layers, a portion in contact with the side surfaces of the pair of first conductive layers, and a portion in contact with the first insulating layer.
  • the second insulating layer has a portion in contact with the top, bottom, and side surfaces of the first semiconductor layer in a first region of the first semiconductor layer, and a portion in contact with the top, bottom, and side surfaces of the second semiconductor layer in a second region of the second semiconductor layer.
  • the second conductive layer has a portion surrounding the top, bottom, and side surfaces of the first semiconductor layer via the second insulating layer, and a portion surrounding the top, bottom, and side surfaces of the second semiconductor layer via the second insulating layer.
  • the first semiconductor layer has a portion that is in contact with the pair of first spacer layers.
  • the second semiconductor layer has a portion that is in contact with the pair of second spacer layers.
  • the first semiconductor layer is indium oxide and the first spacer layer is a metal oxide containing indium, gallium, and zinc.
  • the second semiconductor layer is indium oxide and the second spacer layer is a metal oxide containing indium, gallium, and zinc.
  • the semiconductor device has a pair of third conductive layers. It is preferable that the pair of third conductive layers contact the upper surface of the first semiconductor layer and have portions located between the first semiconductor layer and the pair of first conductive layers.
  • the pair of third conductive layers contact the upper surface of the second semiconductor layer and have a portion located between the second semiconductor layer and the pair of first conductive layers.
  • a transistor capable of passing a large current can be provided.
  • a transistor with favorable electrical characteristics can be provided.
  • a transistor that can be miniaturized can be provided.
  • a transistor that occupies a small area can be provided.
  • a transistor with high reliability can be provided.
  • One embodiment of the present invention can provide a semiconductor device in which transistors can be arranged at high density. Furthermore, a semiconductor device with low power consumption can be provided.
  • One aspect of the present invention provides a semiconductor device with a novel configuration.
  • One aspect of the present invention can improve at least one of the problems of the prior art.
  • 1A, 1B, 1C, and 1D show examples of the configuration of a semiconductor device.
  • 2A, 2B, 2C, and 2D show examples of the configuration of a semiconductor device.
  • 3A, 3B, 3C, and 3D show examples of the configuration of a semiconductor device.
  • 4A, 4B, 4C, and 4D show examples of the configuration of a semiconductor device.
  • 5A and 5B show examples of the configuration of a semiconductor device.
  • 6A, 6B, 6C, and 6D are diagrams illustrating a method for manufacturing a semiconductor device.
  • 7A, 7B, 7C, and 7D are diagrams illustrating a method for manufacturing a semiconductor device.
  • 8A, 8B, and 8C are diagrams illustrating a method for manufacturing a semiconductor device.
  • FIGS. 9A and 9B are diagrams illustrating the carrier concentration dependence of Hall mobility
  • Fig. 9C is a cross-sectional view illustrating an indium oxide film
  • 10A and 10B show examples of the configuration of a semiconductor device.
  • Fig. 11A is an equivalent circuit diagram of a logic circuit
  • Fig. 11B is a diagram showing the circuit symbol of the logic circuit
  • Fig. 11C is a timing chart explaining the operation of the logic circuit.
  • Figures 12A and 12D are equivalent circuit diagrams of logic circuits
  • Figures 12B, 12C, 12E, and 12F are diagrams showing circuit symbols for logic circuits.
  • 13A and 13B are diagrams illustrating an example of an electronic component.
  • 14A, 14B, and 14C are diagrams showing an example of a mainframe computer
  • Fig. 14D is a diagram showing an example of space equipment
  • Fig. 14E is a diagram showing an example of a storage system applicable to a data center.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or stacking). Furthermore, the ordinal numbers used for components in one part of this specification may not match the ordinal numbers used for those components in other parts of this specification or in the claims.
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching to control conduction or non-conduction.
  • transistor includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).
  • a transistor that uses an oxide semiconductor in a semiconductor layer and a transistor that has an oxide semiconductor in a channel formation region may be referred to as an OS (Oxide Semiconductor) transistor.
  • a transistor that has silicon in a channel formation region may be referred to as a Si transistor.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source. It has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and drain through the channel formation region.
  • a channel formation region refers to a region of a semiconductor layer that overlaps (or faces) a gate electrode via a gate insulating film, and is located between a region in contact with the source electrode and a region in contact with the drain electrode.
  • source and drain may be interchangeable when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms “source” and “drain” may be used interchangeably in this specification.
  • the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance.
  • the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the on state.
  • the channel width direction refers to the direction perpendicular to the channel length direction. Note that, depending on the structure or shape of the transistor, the channel length direction and channel width direction may not be defined as a single direction.
  • off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state).
  • the off state refers to a state in which the voltage Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).
  • Vgs refers to the potential difference between the source and gate with the source as the reference.
  • on-state current refers to the drain current when a transistor is in the on state (also referred to as the "conducting state").
  • the on state refers to a state in which Vgs is equal to or higher than Vth for an n-channel transistor, and a state in which Vgs is equal to or lower than the threshold voltage for a p-channel transistor.
  • connection includes “electrical connection.”
  • electrical connection includes connection via "something that has some kind of electrical function.”
  • something that has some kind of electrical function is not particularly limited as long as it allows electrical signals to be exchanged between the connected objects.
  • something that has some kind of electrical function includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.
  • a planar view refers to a view from the normal direction of the surface on which the component is formed or the surface of the support (e.g., substrate) on which the component is formed.
  • parallel refers to a state in which two lines are arranged at an angle of between -10 degrees and 10 degrees, inclusive. Therefore, it also includes cases where the angle is between -5 degrees and 5 degrees, inclusive.
  • approximately parallel refers to a state in which two lines are arranged at an angle of between -20 degrees and 20 degrees, inclusive.
  • perpendicular refers to a state in which two lines are arranged at an angle of between 80 degrees and 100 degrees, inclusive. Therefore, it also includes cases where the angle is between 85 degrees and 95 degrees, inclusive.
  • approximately perpendicular refers to a state in which two lines are arranged at an angle of between 70 degrees and 110 degrees, inclusive.
  • film and “layer” are interchangeable.
  • insulating layer may be interchangeable with the term “insulating film.”
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • a nitride oxide refers to a material whose composition contains more nitrogen than oxygen.
  • silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.
  • One embodiment of the present invention is a transistor having a semiconductor layer.
  • the transistor has a gate insulating film that covers part of the top, bottom, and side surfaces of the semiconductor layer.
  • the transistor has a gate electrode that surrounds part of the top, bottom, and side surfaces of the semiconductor layer with the gate insulating film interposed therebetween.
  • a region of the semiconductor layer surrounded by the gate electrode with the gate insulating film interposed therebetween functions as a channel formation region.
  • the semiconductor layer is not a single layer, but two or more layers.
  • the multiple semiconductor layers are preferably stacked vertically and spaced apart.
  • a gate insulating film is provided to cover the upper, lower, and side surfaces of each of the multiple semiconductor layers.
  • a gate electrode is provided to surround the upper, lower, and side surfaces of each of the multiple semiconductor layers via the gate insulating film.
  • the gate electrode has a portion located between the semiconductor layers stacked vertically and spaced apart. Regions of the multiple semiconductor layers surrounded by the gate electrode via the gate insulating film function as channel formation regions. Because a gate electric field is applied to each of the multiple channel formation regions from the upper, lower, and side surfaces, they function as channel formation regions of a single transistor, increasing the effective channel width. This further increases the on-state current compared to a single semiconductor layer. Furthermore, because multiple semiconductor layers are arranged vertically, a transistor with a small occupation area can be fabricated.
  • a spacer layer is provided below the semiconductor layer.
  • the spacer layer functions to ensure space below the semiconductor layer for providing a gate insulating film and gate electrode.
  • a pair of spacer layers is provided between two vertically adjacent semiconductor layers, and these spacer layers ensure the space between the channel formation regions of the two semiconductor layers.
  • a pair of spacer layers is provided between the semiconductor layer and the insulating base layer provided below the semiconductor layer.
  • a pair of spacer layers is provided below the lowest semiconductor layer and between the insulating base layer. The spacer layers ensure the above-mentioned space between the channel formation region of the semiconductor layer and the insulating base layer.
  • the semiconductor layer is a single layer, it is preferable that a pair of first electrodes be provided above the semiconductor layer.
  • a pair of first electrodes be provided above the uppermost semiconductor layer.
  • One of the pair of first electrodes can function as a source electrode, and the other can function as a drain electrode. It is preferable that each of the pair of first electrodes has a portion in contact with at least two side surfaces of the semiconductor layer.
  • the semiconductor layer is a single layer, it is preferable that a pair of second electrodes be provided between the semiconductor layer and the pair of first electrodes.
  • a pair of second electrodes be provided between the uppermost semiconductor layer and the pair of first electrodes. It is preferable that the pair of second electrodes be in contact with the semiconductor layer.
  • One of the pair of second electrodes can function as part of the source electrode, and the other can function as part of the drain electrode.
  • each of the pair of first electrodes preferably contacts at least two side surfaces of the semiconductor layer and is in contact with the second electrode.
  • each of the pair of first electrodes preferably contacts at least two side surfaces of the semiconductor layer and is in contact with the top surface of the semiconductor layer.
  • each of the pair of first electrodes preferably contacts at least two side surfaces of each of the two or more semiconductor layers and is in contact with the second electrode.
  • each of the pair of first electrodes preferably contacts at least two side surfaces of each of the two or more semiconductor layers and is in contact with the top surface of the uppermost semiconductor layer. This increases the contact area between the semiconductor layer and the source electrode or drain electrode, allowing a large current to flow when the transistor is on.
  • the spacer layer is preferably made of a semiconductor or a conductor.
  • the side surfaces of the spacer layer are in contact with the pair of first electrodes.
  • the top surface of the spacer layer is in contact with the semiconductor layer. Therefore, by making the spacer layer a semiconductor or a conductor, it is possible to reduce the electrical resistance between the semiconductor layer having the portion that functions as the channel formation region and the pair of first electrodes.
  • the spacer layer has an etching selectivity with respect to the semiconductor layer. It is preferable that the spacer layer has an etching selectivity with respect to at least the channel formation region of the semiconductor layer. It is also preferable that the spacer layer has an etching selectivity with respect to the pair of first electrodes, the pair of second electrodes, and the base insulating layer.
  • FIG. 1A shows a schematic top view of the transistor 100.
  • FIGS. 1B, 1C, and 1D show schematic cross-sectional views taken along the lines A1-A2, B1-B2, and B3-B4 in FIG. 1A, respectively.
  • FIGS. 2A, 2C, and 2D show schematic perspective views taken along the lines A1-A2, B1-B2, and B3-B4 in FIG. 1A, respectively.
  • FIGS. 1B and 2A include cross sections of the transistor 100 in the channel length direction.
  • FIGS. 1C and 2C include cross sections of the transistor 100 in the channel width direction.
  • FIGS. 1D and 2D include cross sections of the source electrode or drain electrode of the transistor 100 in the channel width direction.
  • the transistor 100 has at least a semiconductor layer 13, an insulating layer 18, a conductive layer 19 (conductive layers 19a and 19b), a pair of conductive layers 14 (conductive layer 14a and conductive layer 14b), a pair of conductive layers 15 (conductive layer 15a and conductive layer 15b), and a pair of spacer layers 12 (spacer layer 12a and spacer layer 12b).
  • a portion of the insulating layer 18 functions as a gate insulating film.
  • a portion of the conductive layer 19 functions as a gate electrode.
  • the pair of conductive layers 14 (conductive layer 14a and conductive layer 14b) each function as part of a source electrode or drain electrode.
  • the pair of conductive layers 15 (conductive layer 15a and conductive layer 15b) each function as part of a source electrode or drain electrode.
  • the transistor 100 is provided on an insulating layer 11 provided above a substrate (not shown).
  • the insulating layer 11 functions as a base insulating layer.
  • Spacer layer 12a and spacer layer 12b are provided on insulating layer 11 at a distance from each other.
  • Semiconductor layer 13 is provided on and overlaps spacer layer 12a and spacer layer 12b.
  • Semiconductor layer 13 also has regions that do not overlap spacer layer 12a and spacer layer 12b.
  • Conductive layer 14a and conductive layer 14b are provided on semiconductor layer 13 at a distance from each other.
  • Conductive layer 15a has a portion provided on conductive layer 14a
  • conductive layer 15b has a portion provided on conductive layer 14b.
  • Semiconductor layer 13 has regions that do not overlap with conductive layers 14a and 14b or conductive layers 15a and 15b.
  • Each of the conductive layers 15a and 15b contacts the side surfaces of the semiconductor layer 13.
  • the conductive layers 15a and 15b are provided so as to contact three side surfaces of the semiconductor layer 13. This configuration increases the contact area between the semiconductor layer 13 and the conductive layers 15a and 15b, which function as source and drain electrodes, allowing a large current to flow when the transistor is in the on state.
  • the insulating layer 18 has at least portions that contact the upper surface, lower surface, and a pair of opposing side surfaces of the semiconductor layer 13 in an area that does not overlap with the spacer layer 12, conductive layer 14, or conductive layer 15.
  • the conductive layer 19 is provided via the insulating layer 18 to surround the upper surface, lower surface, and a pair of opposing side surfaces of the semiconductor layer 13 in a region that does not overlap with any of the spacer layer 12, the conductive layer 14, and the conductive layer 15.
  • the region of the semiconductor layer 13 that is surrounded by the conductive layer 19 via the insulating layer 18 functions as a channel formation region.
  • FIG. 2B is a perspective view of the conductive layer 19, the semiconductor layer 13, and the spacer layer 12 of the transistor 100.
  • the conductive layer 19 applies an electric field to the channel formation region of the semiconductor layer 13 from the upper surface, lower surface, and a pair of opposing side surfaces.
  • the transistor can be miniaturized while maintaining a high on-current.
  • the area occupied by the transistor can be reduced while maintaining a high on-current.
  • transistors can be arranged at a high density while maintaining a high on-current.
  • the length L2 of the conductive layer 19 that faces the underside of the semiconductor layer 13 via the insulating layer 18 is longer than the distance L1 between the conductive layers 15a and 15b that are spaced apart. This reduces the offset region of the transistor and further increases the on-current.
  • Insulating layer 16 is provided to cover semiconductor layer 13, conductive layer 14, and conductive layer 15. In addition, insulating layer 16 has a region in contact with the side surfaces of conductive layer 15a and conductive layer 15b, and a region in contact with insulating layer 11. Insulating layer 16 is preferably a film having at least one or both of oxygen barrier properties and hydrogen barrier properties. A highly reliable transistor can be obtained by configuring insulating layer 16 and insulating layer 11 to surround semiconductor layer 13.
  • Insulating layer 17 is provided to cover insulating layer 16.
  • a slit is provided in insulating layer 17, and insulating layer 18 and conductive layer 19 are provided inside the slit.
  • the slit is provided to include an area that overlaps with the area between the pair of conductive layers 15, and has a portion that is roughly parallel to the channel width direction of the transistor.
  • Insulating layer 18 is provided along the inside of the slit, and conductive layer 19 is provided to fill the slit.
  • the conductive layer 14 or the conductive layer 15 can form a good connection with the semiconductor layer 13.
  • the spacer layer 12 is preferably made of a semiconductor or conductor. Alternatively, an oxide semiconductor is preferably used. Alternatively, a conductive oxide is preferably used. Alternatively, a conductive material is preferably used. By using such a material, the spacer layer 12 itself can function as a source or drain.
  • the difference in etching rate between the semiconductor layer 13 and the spacer layer 12 is large.
  • the etching rate of the spacer layer 12 is preferably faster than the etching rate of the semiconductor layer 13. Therefore, it is preferable that the semiconductor layer 13 and the spacer layer 12 use materials that differ in at least one of film formation conditions, constituent elements, composition, or crystallinity. Furthermore, it is preferable that the etching rate of the spacer layer 12 is faster than the etching rates of the conductive layer 14, the conductive layer 15, the insulating layer 16, the insulating layer 17, and the insulating layer 11.
  • indium oxide for the semiconductor layer 13
  • In-Ga-Zn oxide also known as IGZO
  • the indium oxide used in the semiconductor layer 13 is preferably deposited by atomic layer deposition (ALD), and the IGZO used in the spacer layer 12 is preferably deposited by ALD.
  • ALD atomic layer deposition
  • IGZO film formed by sputtering for the semiconductor layer 13
  • IGZO film formed by ALD for the spacer layer 12.
  • IGZO for the semiconductor layer 13 and zinc oxide for the spacer layer 12.
  • the IGZO used for the semiconductor layer 13 is preferably deposited by sputtering, and the zinc oxide used for the spacer layer 12 is preferably deposited by ALD.
  • ⁇ Modification 1> 3A to 3D show a configuration example in which the conductive layer 14 (conductive layer 14a, conductive layer 14b) shown in FIG. 1B and the like is not provided.
  • the conductive layer 15a contacts a part of the upper surface of the semiconductor layer 13
  • the conductive layer 15b contacts another part of the upper surface of the semiconductor layer 13.
  • ⁇ Modification 2> 4A to 4D show a configuration example in which the conductive layer 14 (conductive layer 14a, conductive layer 14b) shown in FIG. 1B and the like is not provided, and an insulating layer 41 is provided between the insulating layer 11 and the spacer layer 12.
  • the absence of the conductive layer 14 facilitates the process of etching the conductive layer 15 to separate it into the conductive layer 15a and the conductive layer 15b, thereby improving productivity and yield.
  • the insulating layer 16 is provided to cover the semiconductor layer 13, to be in contact with the side surfaces of the conductive layer 15a and the conductive layer 15b, and to be in contact with the insulating layer 11.
  • the insulating layer 11 and the insulating layer 16 are preferably films having at least one or both of an oxygen barrier property and a hydrogen barrier property.
  • a highly reliable transistor can be provided by using the insulating layer 16 and the insulating layer 11 to surround the semiconductor layer 13 and the insulating layer 41.
  • Figure 5A shows an example of the configuration of a transistor in which the semiconductor layer 13 in Figure 2A, which shows the A1-A2 cross section of the transistor 100 shown in Figure 1A, is made into two layers.
  • Figure 5B shows an example of the configuration of a transistor in which the semiconductor layer 13 in Figure 2A is made into five layers.
  • the transistor has two semiconductor layers 13 (semiconductor layer 13-1, semiconductor layer 13-2), two spacer layers 12 (spacer layer 12-1a and spacer layer 12-2a, and spacer layers 12-1b and 12-2b), conductive layer 14 (conductive layer 14a, conductive layer 14b), conductive layer 15 (conductive layer 15a, conductive layer 15b), insulating layer 18, and conductive layer 19 (conductive layer 19a, conductive layer 19b).
  • Spacer layer 12-1a and spacer layer 12-1b are provided on insulating layer 11 at a distance from each other.
  • Semiconductor layer 13-1 is provided overlapping spacer layer 12-1a and spacer layer 12-1b.
  • Spacer layer 12-2a and spacer layer 12-2b are provided on semiconductor layer 13-1 at a distance from each other.
  • Semiconductor layer 13-2 is provided overlying spacer layer 12-2a and spacer layer 12-2b.
  • Conductive layer 14a and conductive layer 14b are spaced apart and in contact with the upper surface of semiconductor layer 13-2.
  • Conductive layer 15a has a portion that is provided on conductive layer 14a
  • conductive layer 15b has a portion that is provided on conductive layer 14b.
  • Conductive layer 15a and conductive layer 15b are each provided in contact with three side surfaces of semiconductor layer 13 (semiconductor layer 13-1, semiconductor layer 13-2). The side surface of conductive layer 14 facing insulating layer 18 and the side surface of conductive layer 15 facing insulating layer 18 are aligned or approximately aligned in a planar view.
  • Insulating layer 18 has portions that contact the upper and lower surfaces and a pair of opposing side surfaces of regions of semiconductor layer 13-1 that do not overlap with spacer layer 12-1a, spacer layer 12-1b, spacer layer 12-2a, or spacer layer 12-2b. Insulating layer 18 also has portions that contact at least the upper and lower surfaces and a pair of opposing side surfaces of regions of semiconductor layer 13-2 that do not overlap with spacer layer 12-2a, spacer layer 12-2b, conductive layer 14a, conductive layer 14b, conductive layer 15a, or conductive layer 15b.
  • the conductive layer 19 is provided to surround the upper and lower surfaces and a pair of opposing side surfaces of the above-mentioned regions of the semiconductor layer 13-2 and the semiconductor layer 13-1, via the insulating layer 18.
  • the configuration shown in FIG. 5B includes five semiconductor layers 13 (semiconductor layers 13-1 to 13-5), five spacer layers 12 (spacer layers 12-1a to 12-5a, and spacer layers 12-1b to 12-5b), conductive layers 14 (conductive layers 14a and 14b), conductive layers 15 (conductive layers 15a and 15b), an insulating layer 18, and conductive layers 19 (conductive layers 19a and 19b).
  • Conductive layer 14a and conductive layer 14b are provided separately and in contact with the upper surface of semiconductor layer 13-5.
  • Conductive layer 15a has a portion provided on conductive layer 14a, and conductive layer 15b has a portion provided on conductive layer 14b.
  • Conductive layer 15a and conductive layer 15b are each provided in contact with three side surfaces of semiconductor layer 13 (semiconductor layers 13-1 to 13-5).
  • the insulating layer 18 has portions that contact at least the upper and lower surfaces, and a pair of opposing side surfaces, of the semiconductor layers 13-1 to 13-5 in areas that do not overlap with the spacer layers 12-1a to 12-5b.
  • the conductive layer 19 is provided to surround the top surface, bottom surface, and a pair of opposing side surfaces of the semiconductor layers 13-1 to 13-5 via the insulating layer 18.
  • the regions of the semiconductor layers 13-1 to 13-5 surrounded by the conductive layer 19 via the insulating layer 18 function as channel formation regions.
  • Figure 5A shows an example in which the semiconductor layer 13 has a two-layer structure
  • Figure 5B shows an example in which it has a five-layer structure
  • the semiconductor layer may have three, four, six or more layers.
  • Substrates on which transistors are formed may be, for example, insulating substrates, semiconductor substrates, or conductive substrates.
  • insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates.
  • semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride.
  • Examples of semiconductor substrates having an insulating region within the aforementioned semiconductor substrate include silicon-on-insulator (SOI) substrates.
  • Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Substrates containing metal nitrides and substrates containing metal oxides can also be used. Examples of substrates include an insulating substrate having a conductive layer or semiconductor layer provided thereon, a semiconductor substrate having a conductive layer or insulating layer provided thereon, and a conductive substrate having a semiconductor layer or insulating layer provided thereon.
  • a substrate provided with elements may be used, such as a capacitor, a resistor, a switch (including a transistor), a light-emitting element, a memory element, or the like.
  • the semiconductor layer 13 preferably includes an oxide semiconductor.
  • the oxide semiconductor preferably uses a metal oxide.
  • indium oxide is preferable to use indium oxide as the semiconductor layer 13.
  • the metal oxide that can be used for the semiconductor layer 13 preferably contains at least In or Zn. Furthermore, the metal oxide preferably contains two or three elements selected from In, element M, and Zn.
  • Element M is a metal element or semimetal element with a high bond energy with oxygen, for example, a metal element or semimetal element with a bond energy with oxygen higher than that of indium. Specific examples of element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb.
  • Element M contained in the metal oxide is preferably one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred.
  • a metal oxide containing In, element M, and Zn may be referred to as In-M-Zn oxide.
  • the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of element M.
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of the element M.
  • the semiconductor layer 13 can be made of In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, or In-W oxide.
  • Ga-Zn oxide may also be used.
  • a material containing Zn is preferred because it facilitates high crystallinity.
  • the metal oxide may contain one or more metal elements with higher period numbers in the periodic table.
  • metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.
  • the metal oxide may contain one or more non-metallic elements.
  • the presence of non-metallic elements in the metal oxide may increase the field-effect mobility of the transistor.
  • non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • Metal oxides can be formed preferably by sputtering or ALD. It is particularly preferable to form metal oxide films using ALD, which has excellent coating properties.
  • the composition of the formed metal oxide may differ from the composition of the target. In particular, the zinc content in the formed metal oxide may decrease to around 50% of that of the target.
  • the content of a certain metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide.
  • the content of metal element X can be expressed as Ax /( Ax + Ay + Az ) .
  • a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 13 it is possible to create a transistor that is highly reliable when a positive bias is applied. In other words, it is possible to create a transistor with a small amount of threshold voltage variation in a PBTS (Positive Bias Temperature Stress) test. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.
  • Ga content makes it possible to produce a transistor with high reliability against light.
  • NBTIS Near Bias Temperature Illumination Stress
  • metal oxides in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In have a larger band gap, which makes it possible to reduce the threshold voltage fluctuations in NBTIS testing of transistors.
  • the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide. This therefore suppresses fluctuations in the transistor's electrical characteristics and improves reliability.
  • the semiconductor layer 13 may have a stacked structure including two or more metal oxide layers.
  • the two or more metal oxide layers included in the semiconductor layer 13 may have the same or substantially the same composition.
  • a stacked structure of metal oxide layers with the same composition for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.
  • a stacked structure of two or more oxide semiconductor layers with different compositions may also be used.
  • the ALD method it is possible to form a metal oxide layer whose composition varies continuously in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical properties and reliability.
  • a metal oxide layer with a stacked structure may be formed using both the sputtering method and the ALD method.
  • the semiconductor layer 13 has a two-layer structure
  • a high-mobility material highly conductive material
  • a high-mobility material may be used on the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 13 and the source electrode or drain electrode, thereby reducing parasitic resistance and allowing for a transistor with a high on-state current.
  • the semiconductor layer 13 has a three-layer structure
  • a crystalline metal oxide layer for the semiconductor layer 13.
  • a metal oxide layer having a single crystal structure, a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, or a nanocrystalline (nc) structure can be used.
  • CAAC c-axis aligned crystal
  • nc nanocrystalline
  • Indium oxide is preferably used for the semiconductor layer 13. It is particularly preferable to use a single-crystal indium oxide film. It is preferable to use a crystalline film for the semiconductor layer 13, and it is particularly preferable to use indium oxide with a single-crystal structure. However, indium oxide with a polycrystalline or microcrystalline structure can also be used. By using indium oxide with a single-crystal structure, carrier scattering at grain boundaries can be suppressed, resulting in a transistor with high field-effect mobility. It also results in a highly reliable transistor. When using indium oxide with a polycrystalline structure, it is preferable that no grain boundaries are observed at least in the channel formation region (the region overlapping with the conductive layer 19). This allows indium oxide with a polycrystalline structure to achieve the same effects as indium oxide with a single-crystal structure.
  • the thickness of the semiconductor layer 13 is preferably 1 nm or more and 50 nm or less, more preferably 2.5 nm or more and 30 nm or less, more preferably 2.5 nm or more and 20 nm or less, more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 10 nm or less.
  • indium oxide is a film in which hydrogen and/or oxygen move more easily than, for example, an IGZO (In-Ga-Zn-O-based oxide) film. Therefore, indium oxide is a film in which hydrogen and/or oxygen are more easily supplied and discharged than, for example, an IGZO film. This means that excess oxygen or excess hydrogen, which can become carriers or fixed charges, is less likely to accumulate in the semiconductor layer 13, resulting in a transistor with good electrical characteristics and reliability.
  • IGZO In-Ga-Zn-O-based oxide
  • the semiconductor layer 13 has a reduced concentration of elements that reduce crystallinity.
  • the concentration of elements such as boron and aluminum is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.
  • the gallium concentration in the semiconductor layer 13 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.
  • OS transistors have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have extremely low source-drain leakage current in an off state (hereinafter also referred to as off-state current), and can retain charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of OS transistors can reduce the power consumption of semiconductor devices.
  • a semiconductor device can be applied to, for example, a processor, a memory device, or various ICs.
  • the transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed circuit operation and low power consumption can be achieved simultaneously.
  • OS transistors exhibit smaller variations in electrical characteristics due to radiation exposure than Si transistors, meaning they have high radiation resistance, making them suitable for use in environments where radiation may be present. OS transistors can also be said to be highly reliable against radiation. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).
  • electromagnetic radiation e.g., X-rays and gamma rays
  • particle radiation e.g., alpha rays, beta rays, proton rays, and neutron rays.
  • the semiconductor material that can be used for the semiconductor layer 13 is not limited to oxide semiconductors.
  • semiconductors made of single elements or compound semiconductors can be used.
  • semiconductors made of single elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. Note that these semiconductor materials may contain impurities as dopants.
  • the semiconductor layer 13 may include a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a single layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a high on-state current can be provided.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum tellurium (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten tellurium (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenide (typically ZrSe 2 ).
  • MoS 2 molybdenum sulfide
  • MoSe 2 molybdenum selenide
  • MoTe 2 moly MoTe 2
  • tungsten sulfide typically WS 2
  • tungsten selenide typically
  • the crystallinity of the semiconductor material used for the semiconductor layer 13 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, or a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a crystalline semiconductor is preferable because it can suppress deterioration of the transistor characteristics.
  • ⁇ Gate insulating film> As transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers.
  • Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer.
  • EOT equivalent oxide thickness
  • using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select materials according to the function of the insulating layer.
  • the insulating layer 18 functions as a gate insulating film of the transistor.
  • an oxide semiconductor is used for the semiconductor layer 13
  • silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used.
  • a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 18.
  • the insulating layer 18 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.
  • the insulating layer 18 is preferably formed by stacking insulating films with a high dielectric constant (high-k). It is also preferable to use a stack structure of an insulating film with a high dielectric constant (high-k) and an insulating film with high dielectric strength.
  • high-k high dielectric constant
  • hafnium oxide, zirconium oxide, and aluminum oxide can be used as the insulating layer 18.
  • an insulating film stacked in the order of zirconium oxide, aluminum oxide, and zirconium oxide also referred to as ZAZ
  • an insulating film stacked in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide also referred to as ZAZA
  • an insulating film stacked in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used.
  • Examples of insulating films with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • the aforementioned ZAZ and ZAZA are also examples of insulating films with a high dielectric constant.
  • Silicon oxide or silicon oxynitride can be used as an insulating film with high dielectric strength. Silicon oxide or silicon oxynitride can also be considered insulating films that suppress leakage current.
  • ferroelectric insulating film may be used as the insulating layer 18.
  • ferroelectric insulating films include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide.
  • the insulating layer 18 has a two-layer structure, it is preferable to use an insulating film that has the function of capturing or fixing hydrogen as the film located on the semiconductor layer 13 side, and an insulating film that has barrier properties against hydrogen as the film located on the conductive layer 19 side that functions as the gate electrode. This makes it possible to suppress the diffusion of hydrogen from the conductive layer 19 side to the semiconductor layer 13, resulting in a highly reliable transistor.
  • the insulating layer 18 has a three-layer structure, it is preferable to use an insulating film with high dielectric strength or an insulating film that suppresses leakage current for the film located on the semiconductor layer 13 side, an insulating film with barrier properties against hydrogen, an insulating film with barrier properties against oxygen, or an insulating film that functions to suppress the permeation of impurities such as water and hydrogen and oxygen for the film located on the conductive layer 19 side, and an insulating film that functions to capture or fix hydrogen for the film located between these.
  • the film located on the conductive layer 19 side prevents oxygen from diffusing toward the conductive layer 19 side, suppressing oxidation of the conductive layer 19.
  • the insulating layer 18 has a four-layer structure, it is preferable to use an insulating film with oxygen barrier properties for the film located closest to the semiconductor layer 13, an insulating film with high dielectric strength or an insulating film that suppresses leakage current for the film next closest to the semiconductor layer 13, an insulating film with the function of capturing or fixing hydrogen for the film next closest to the semiconductor layer 13, and an insulating film with hydrogen barrier properties, an insulating film with oxygen barrier properties, or an insulating film with the function of suppressing the permeation of impurities such as water and hydrogen and oxygen for the film located closest to the conductive layer 19.
  • a structure in addition to the above-mentioned three-layer structure, a structure can be created in which an additional film is located on the semiconductor layer 13 side.
  • Using an insulating film with oxygen barrier properties for the film in contact with the semiconductor layer 13 can suppress oxygen desorption from the semiconductor layer 13.
  • Aluminum oxide not only has oxygen barrier properties but also the function of capturing or fixing hydrogen, thereby effectively preventing hydrogen from diffusing into the semiconductor layer 13.
  • each insulating film is preferably a thin film.
  • the total film thickness of the insulating layer 18 1 nm or more and 20 nm or less, preferably 2 nm or more and 10 nm or less, the subthreshold swing value (also referred to as the S value) of the transistor can be reduced.
  • a four-layer structure is used in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 13 side, and the thicknesses of these films are preferably 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 13 side.
  • a four-layer structure is used in which a hafnium oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 13 side, and the thicknesses of these films are preferably 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 13 side.
  • a two-layer structure in which a silicon oxide film and a hafnium oxide film are stacked in this order from the semiconductor layer 13 side, and the thicknesses of these films are preferably 1 nm and 1.5 nm from the semiconductor layer 13 side.
  • carrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the permeation of a corresponding substance).
  • hydrogen refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen, such as a water molecule or OH ⁇ .
  • impurities when impurities are described as a corresponding substance, they refer to impurities in a channel formation region or a semiconductor layer, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (such as N 2 O, NO, or NO 2 ), a copper atom, and the like.
  • oxygen when oxygen is described as a corresponding substance, it refers to at least one of, for example, an oxygen atom, an oxygen molecule, and the like.
  • Examples of insulating films that function to prevent the permeation of oxygen and impurities such as water and hydrogen include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • Nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can also be used.
  • Insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may also contain zirconium, such as oxides containing hafnium and zirconium (hafnium zirconium oxide). Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adsorb hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and/or grain boundaries.
  • the ability to capture or fix the corresponding substance can also be said to have the property of making the corresponding substance difficult to diffuse. Therefore, the ability to capture or fix the corresponding substance can be rephrased as barrier properties.
  • Examples of insulating film materials with barrier properties against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, hafnium aluminate, hafnium zirconium oxide, silicon nitride, silicon nitride oxide, and gallium oxide films.
  • Examples of insulating film materials that have oxygen barrier properties include oxides containing either or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, hafnium aluminate, and hafnium silicate.
  • the conductive layer 14 and the conductive layer 15 are in contact with the semiconductor layer 13.
  • an oxide semiconductor is used as the semiconductor layer 13
  • an insulating oxide e.g., aluminum oxide
  • Conductive layers 14 and 15 in contact with semiconductor layer 13 are preferably made of, for example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. These are preferred because they are conductive materials that are resistant to oxidation or materials that maintain their conductivity even when oxidized.
  • conductive oxides such as indium oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, and In-Sn-Si oxide can be used.
  • Conductive oxides containing indium are particularly preferred due to their high conductivity.
  • oxide materials such as In-Ga-Zn oxide that can be used for the semiconductor layer 13 can also be used as a conductive layer by increasing the carrier concentration.
  • conductive layer 14 and conductive layer 15 can each be a single-layer structure of the above-mentioned conductive oxide film, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on a tungsten film, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film, a two-layer structure in which a conductive oxide film is stacked on a tungsten film, or a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order.
  • Conductive layers 14, 15, and 19 are preferably made of a low-resistance conductive material.
  • a metal element selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing such a metal element.
  • Nitrides of the above metals or alloys, or oxides of the above metals or alloys may also be used.
  • conductive layers 14 and 15 can be formed using a layered structure of the above-mentioned conductive oxide or conductive nitride and the above-mentioned metal.
  • a layered structure of tantalum nitride and tungsten is preferable.
  • the nitrides and oxides that can be used for the conductive layers 14 and 15 may be applied to the conductive layer 19.
  • a layered structure of titanium nitride and tungsten is preferable.
  • the insulating layer 17 can be used as an interlayer insulating film.
  • it is preferably formed by a film formation method such as a sputtering method or a plasma CVD method.
  • a film formation method such as a sputtering method or a plasma CVD method.
  • hydrogen gas is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, supply of hydrogen to the semiconductor layer 13 can be suppressed, and the electrical characteristics of the transistor 100 can be stabilized.
  • the insulating layer 17 preferably has a low dielectric constant.
  • a material with a low dielectric constant as the interlayer insulating film reduces the parasitic capacitance that occurs between wiring.
  • insulating layer 17 functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a higher film formation rate than other insulating layers.
  • insulating layer 17 may be a silicon oxide film formed by plasma CVD using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si( OC2H5 )4 ) . This can improve productivity.
  • TEOS Tetra-Ethyl-Ortho-Silicate, chemical formula: Si( OC2H5 )4
  • the insulating layer 11 which functions as a base insulating layer, also functions as an interlayer insulating layer.
  • the insulating layer 11 can be made of the same insulating material as can be used for the insulating layer 17 described above.
  • the electrical characteristics of a transistor using a metal oxide film can be stabilized by surrounding it with an insulating film that has the function of suppressing the permeation of impurities such as water and hydrogen and oxygen.
  • an insulating film that has the function of suppressing the permeation of impurities such as water and hydrogen and oxygen it is preferable to use an insulating film that has the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating film that has the function of capturing or fixing hydrogen, an insulating film that has barrier properties against hydrogen, or an insulating film that has barrier properties against oxygen.
  • Using these insulating layers can suppress the diffusion of hydrogen into the semiconductor layer 13. Furthermore, oxidation of the conductive layer 14 or the conductive layer 15 can be suppressed.
  • the spacer layer 12 it is particularly preferable to use a material that can be used for the semiconductor layer 13 or a material that can be used for the conductive layer 14.
  • the spacer layer 12 can also be made of a material that can be used for the conductive layer 14 and the conductive layer 15, or a material that can be used for the insulating layer 16 or the insulating layer 17.
  • Thin film etching can be performed using methods such as dry etching, wet etching, and sandblasting.
  • the insulating layer 11 can be an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.
  • the insulating layer 11 can be formed by sputtering, CVD, vacuum deposition, PLD, ALD, or other methods. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the top surface of the insulating layer 11 is flat.
  • a film that will become the spacer layer 12 is deposited on the insulating layer 11.
  • This film can be formed by a deposition method such as sputtering or ALD.
  • a deposition method such as sputtering or ALD.
  • IGZO or zinc oxide is used for the film that will become the spacer layer 12, it can be formed by sputtering or ALD.
  • a metal oxide film is used for the film that will become the spacer layer 12, the description of the method for forming the film that will become the semiconductor layer 13 described in this specification can be referenced.
  • the thickness of the film that will become the spacer layer 12 is determined by the thicknesses of the insulating layer 18 and conductive layer 19 (thickness in the region that overlaps with the semiconductor layer 13) that will be formed later.
  • the thickness of the film that will become the spacer layer 12 is at least twice the thickness of the insulating layer 18.
  • the thickness of the film that will become the spacer layer 12 is more than twice but not more than 10 times the thickness of the insulating layer 18, preferably 2.5 to 10 times, and more preferably 3 to 10 times.
  • the semiconductor layer 13 can be a metal oxide (oxide semiconductor) film having semiconductor properties.
  • the metal oxide film can be formed by a sputtering method, an ALD method, or the like, as appropriate.
  • IGZO or indium oxide can be used.
  • the description in Embodiment 2 can be referred to.
  • the metal oxide film preferably has crystallinity.
  • the metal oxide film preferably has a single crystal structure, a polycrystalline structure, or a CAAC structure.
  • a treatment to enhance the crystallinity of the metal oxide film during or after the formation of the metal oxide film.
  • treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave-excited plasma treatment (also simply referred to as microwave plasma treatment), and light (e.g., ultraviolet light) irradiation treatment.
  • heat treatment and microwave-excited plasma treatment may be performed simultaneously.
  • microwave-excited plasma treatment may be performed after heat treatment.
  • Treatment to enhance the crystallinity of a metal oxide film may also be performed after the metal oxide film is formed. Specifically, this treatment may be performed directly on the formed metal oxide film, or may be performed through another film, such as an insulating film, formed on the metal oxide film.
  • microwave-excited plasma treatment may be performed after the metal oxide film is formed.
  • an insulating film e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.
  • heat treatment or microwave-excited plasma treatment may be performed on the metal oxide film through the insulating film.
  • the treatment to enhance the crystallinity of a metal oxide film can also serve as a treatment to remove impurities from the metal oxide film.
  • impurities for example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be suitably removed.
  • oxygen vacancies in the metal oxide film can be reduced by performing the treatment to enhance the crystallinity of a metal oxide film in an oxygen gas atmosphere.
  • the temperature of the heat treatment or the temperature of the substrate
  • room temperature e.g., 25°C
  • 100°C or higher and 700°C or lower 100°C or higher and 600°C or lower
  • 300°C or higher and 450°C or lower it is preferable to set the temperature of the heat treatment (or the temperature of the substrate) to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.
  • indium oxide for the film that will become semiconductor layer 13 and IGZO for the film that will become spacer layer 12.
  • IGZO for the film that will become spacer layer 12
  • Metal oxide films can be formed, for example, by sputtering using a metal oxide target.
  • the metal oxide film be a dense film with as few defects as possible. It is also preferable that the metal oxide film be a highly pure film with as little impurities as possible, such as hydrogen and water. It is particularly preferable to use a crystalline metal oxide film as the metal oxide film.
  • oxygen gas when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.).
  • an inert gas e.g., helium gas, argon gas, xenon gas, etc.
  • the higher the ratio of oxygen gas to the total film-forming gas when forming the metal oxide film hereinafter also referred to as the oxygen flow ratio
  • the higher the ratio of oxygen gas to the total film-forming gas when forming the metal oxide film hereinafter also referred to as the oxygen flow ratio
  • the lower the oxygen flow ratio the less highly crystallinity the metal oxide film can be, and a transistor with increased on-state current can be obtained.
  • the conditions for forming the metal oxide film include a substrate temperature of room temperature or higher and 250°C or lower, preferably room temperature or higher and 200°C or lower, and more preferably room temperature or higher and 140°C or lower.
  • a substrate temperature of room temperature or higher and lower than 140°C is preferred as it increases productivity.
  • a film formation method such as thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD).
  • thermal ALD Atomic Layer Deposition
  • PEALD Pasma Enhanced ALD
  • the thermal ALD method is preferred because it exhibits extremely high step coverage.
  • the PEALD method is also preferred because it not only exhibits high step coverage but also allows for low-temperature film formation.
  • the film when using a metal oxide for the semiconductor film, the film can be formed by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.
  • a precursor containing indium when depositing indium oxide, a precursor containing indium can be used.
  • three precursors can be used: a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.
  • two precursors can be used: a precursor containing indium and a precursor containing gallium and zinc.
  • precursors containing gallium that can be used include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.
  • zinc-containing precursors that can be used include dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc.
  • O2 or O3 as the oxidizing agent, and it is particularly preferable to use O3 .
  • Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. Adjusting these factors also makes it possible to deposit a film whose composition changes continuously. It is also possible to deposit two or more films with different compositions in succession.
  • the heat treatment is performed at a temperature of 250°C to 650°C, preferably 400°C to 600°C.
  • the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the oxygen gas concentration is preferably about 20%.
  • the heat treatment may also be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.
  • the gas used in the heat treatment be highly purified.
  • the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • the semiconductor layer is shown as a single layer, but it may also have a laminated structure.
  • it may have a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer is formed by sputtering, or a three-layer structure in which the first layer is formed by the ALD method, the second layer is formed by sputtering, and the third layer is formed by either the ALD method or the sputtering method.
  • Forming the first layer by the ALD method is preferable because it can suppress mixing, but it is also possible to form the first layer by sputtering and the second layer by the ALD method.
  • the semiconductor layer may also have a laminated structure of four or more layers.
  • a film that will become the conductive layer 14 is deposited on the film that will become the semiconductor layer 13.
  • the film that will become the conductive layer 14 can be deposited using a deposition method such as sputtering, ALD, or CVD.
  • a resist mask is formed on the film that will become the conductive layer 14, and the portions of the film that will become the spacer layer 12, the film that will become the semiconductor layer 13, and the film that will become the conductive layer 14 that are not covered by the resist mask are etched.
  • the island-shaped film 62 that will become the conductive layer 14 can be used as a metal hard mask when etching the semiconductor layer 13.
  • the semiconductor device shown in Figures 3A to 3D can be fabricated by forming the island-shaped film 61 that will become the spacer layer 12, the semiconductor layer 13, and the island-shaped film 62, and then removing the island-shaped film 62.
  • FIG. 6A shows an example in which the side surfaces of each layer are perpendicular to the upper surface of the insulating layer 11, but depending on the etching conditions, the side surfaces of each layer may have a tapered shape.
  • a tapered shape refers to a shape in which at least a portion of the side surface of the structure is inclined relative to the substrate surface or the surface on which it is formed.
  • a film that will become conductive layer 15 is formed to cover island-shaped film 61, semiconductor layer 13, and island-shaped film 62.
  • a resist mask is formed on the film that will become conductive layer 15. Portions of the film that will become conductive layer 15 that are not covered by the resist mask are etched to form island-shaped film 63 that will become conductive layer 15 ( Figure 6B).
  • an insulating layer 16 is formed on the island-shaped film 63 that will become the conductive layer 15.
  • the insulating layer 16 can be formed by a film formation method such as sputtering, ALD, or CVD. It is preferable to use an insulating layer that has the function of capturing or fixing hydrogen as the insulating layer 16. It is also preferable to use an insulating layer that has barrier properties against hydrogen as the insulating layer 16.
  • Insulating layer 17 is formed on insulating layer 16.
  • Insulating layer 17 can be formed by a film formation method such as sputtering, ALD, or CVD. After insulating layer 17 is formed, it is planarized by a planarization process. For example, CMP (Chemical Mechanical Polishing) can be used as the planarization process ( Figure 6C).
  • CMP Chemical Mechanical Polishing
  • a resist mask is formed on insulating layer 17.
  • the portions of insulating layer 17, insulating layer 16, island-shaped film 63, and island-shaped film 62 not covered by the resist mask are etched to form trenches 64.
  • conductive layers 15a and 15b are formed from island-shaped film 63
  • conductive layers 14a and 14b are formed from island-shaped film 62.
  • Conductive layers 15a and 15b are separated by trench 64.
  • Conductive layers 14a and 14b are separated by trench 64.
  • a portion of semiconductor layer 13 and a portion of spacer layer 12 are exposed within trench 64.
  • Anisotropic dry etching is preferably used to form trench 64 ( Figure 6D).
  • the island-shaped film 61 in the trench 64 is etched.
  • spacer layers 12a and 12b are formed from the island-shaped film 61.
  • the spacer layers 12a and 12b are separated by the trench 64 ( Figures 7A and 7B).
  • Isotropic etching is preferably used to etch the island-shaped film 61. Wet etching can be used as the isotropic etching.
  • Figure 7B is a schematic perspective view of Figure 7A cut in the channel length direction.
  • wet etching for example, hydrofluoric acid, phosphoric acid, oxalic acid, nitric acid, acetic acid, hydrochloric acid, or an aqueous solution of tetramethylammonium hydroxide (TMAH), or a mixed solution or mixed aqueous solution containing two or more of these, can be used.
  • TMAH tetramethylammonium hydroxide
  • the chemical solution used for wet etching may be alkaline or acidic.
  • FIGS 8A to 8C show perspective schematic views including the horizontal cross section C shown in Figure 7A.
  • the shapes of the spacer layer 12a and the spacer layer 12b can vary. As long as the spacer layer 12a and the spacer layer 12b can be separated, any of the shapes shown in Figures 8A to 8C may be used.
  • the top surface shape of the spacer layer 12a and the spacer layer 12b in Figure 8A is rectangular.
  • the top surface shape of the spacer layer 12a and the spacer layer 12b in Figure 8B has a convex arc toward the opposing spacer layer.
  • the top surfaces of spacer layer 12a and spacer layer 12b in FIG. 8C have a concave arc shape facing the opposing spacer layer.
  • the length of the semiconductor layer 13 in the channel length direction in a planar view within the trench 64 is preferably longer than the length in the channel width direction.
  • the length of the semiconductor layer 13 in the channel length direction in a planar view within the trench 64 is preferably at least twice as long as the length in the channel width direction.
  • a film that will become the insulating layer 18 is deposited.
  • the film that will become the insulating layer 18 is preferably formed using ALD, which has better step coverage than other deposition methods.
  • a film that will become the conductive layer 19 is deposited.
  • CMP is performed to remove the films that will become the insulating layer 18 and the conductive layer 19 from the insulating layer 17 ( Figures 7C and 7D ).
  • Figure 7D shows a perspective schematic view of Figure 7C cut in the channel length direction.
  • the conductive layer 19 can have, for example, a two-layer structure consisting of conductive layers 19a and 19b.
  • the conductive layer 19a be deposited using a deposition method that has better step coverage than the conductive layer 19b. As shown in Figure 7D , by separating the semiconductor layer 13 and the insulating layer 11 using the spacer layers 12a and 12b, at least the insulating layer 18 and the conductive layer 19a are deposited in the space between the semiconductor layer 13 and the insulating layer 11.
  • the transistor 100 can be manufactured.
  • This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification. Furthermore, when multiple configuration examples are shown in one embodiment in this specification, the configuration examples can be appropriately combined.
  • indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO).
  • crystalline indium oxide crystal IO
  • crystalline IO crystalline indium oxide
  • examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.
  • Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.
  • oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.
  • Fig. 9A is a schematic diagram showing the carrier concentration dependence of the Hall mobility for silicon (Si) and indium oxide (InO x ), and Fig. 9B is a schematic diagram showing the carrier concentration dependence of the Hall mobility for IGZO.
  • IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as indicated by the arrows in Figure 9B.
  • indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as indicated by the arrows in Figure 9A (see Non-Patent Document 1).
  • This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility.
  • the higher the purity and intrinsic indium oxide the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties closer to silicon. Note that the characteristics of indium oxide shown in Figure 9A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 9A.
  • the low carrier concentration range R1 has extremely high hole mobility, and can therefore be considered a carrier concentration range suitable for, for example, a channel formation region of a transistor.
  • range R1 is a range including a carrier concentration value of 1 ⁇ 10 15 cm ⁇ 3 , for example, a range of 1 ⁇ 10 14 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the hole mobility value can be increased to approximately 270 cm 2 /(V ⁇ s).
  • the region where the carrier concentration is in range R1 can contain elements that lower the carrier concentration.
  • elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered.
  • elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.
  • the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film.
  • Range R2 is a range in which the carrier concentration value includes 1 ⁇ 10 20 cm ⁇ 3 , for example, a range of 1 ⁇ 10 19 cm ⁇ 3 or more and 1 ⁇ 10 22 cm ⁇ 3 or less. By sufficiently increasing the carrier concentration, it is expected that the resistivity can be reduced to 1 ⁇ 10 ⁇ 4 ⁇ cm or less.
  • the region where the carrier concentration is in range R2 can contain elements that increase the carrier concentration.
  • the region contains elements that are common to the source electrode and drain electrode of the transistor.
  • elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron.
  • elements whose oxides have conductive or semiconductive properties are more preferable.
  • indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor.
  • indium oxide can be considered an oxide capable of valence electron control.
  • strain can form in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions.
  • indium oxide allows for valence electron control, so strain does not need to be formed in the film as with IGZO. Minimizing strain in the film is expected to improve reliability.
  • n-i-n junction a junction between an n-type region, an i-type region, and an n-type region
  • valence electron control in silicon-based transistors is generally known.
  • valence electron control in indium oxide-based transistors is a novel technological concept that would not normally be conceived.
  • the transistor containing indium oxide in this specification has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) A high on-state current (in other words, high mobility). (2) A low off-state current. (3) Normally-off operation is possible. (4) High reliability. (5) A high cutoff frequency (fT).
  • the transistor containing indium oxide in this specification has high mobility, a low off-state current, and is normally-off operation. This transistor has high mobility and is different from a normally-on transistor.
  • the indium oxide film be crystalline (i.e., have crystal grains).
  • films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also known as microcrystalline films).
  • polycrystalline indium oxide films are preferred, and single-crystal films are even more preferred.
  • Single-crystal films do not have grain boundaries. Impurities that impede carrier flow (typically, insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries.
  • Using a single-crystal film can suppress carrier scattering at grain boundaries, resulting in a transistor with high field-effect mobility. It also offers the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.
  • polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films.
  • a polycrystalline film it is preferable to use a film with as large a crystal grain size as possible and as few crystal grain boundaries as possible. Note that in a transistor using a polycrystalline film of indium oxide, if there are no crystal grain boundaries in the channel formation region or no crystal grain boundaries are observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to use single-crystal indium oxide.
  • the crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • a semiconductor layer in which no crystal grain boundaries are observed in the channel formation region a semiconductor layer in which the channel formation region is contained in a single crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions within the channel formation region can be referred to as a single crystal film.
  • a semiconductor layer in which, within a single crystal grain in the channel formation region, the direction of the other crystal axis changes continuously around a certain crystal axis or a certain crystal orientation as the axis of rotation can be referred to as a single crystal film.
  • the channel formation region refers to the region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode.
  • the current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, source electrode, and drain electrode.
  • Impurities in the indium oxide film in the channel formation region can act as a source of carrier scattering, which can reduce field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Impurities in the indium oxide film include boron and silicon.
  • the indium oxide film preferably has a concentration of these impurities of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, and other elements can be contained in the film formation gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above impurities.
  • the indium oxide film in the channel formation region may contain elements that can become the same trivalent cations as indium, as long as the crystals maintain a cubic crystal structure (bixbyite type).
  • examples include elements in Group 13 of the periodic table, such as gallium and aluminum, and elements in Group 3 of the periodic table. These elements exist primarily as trivalent cations in oxides, allowing the carrier concentration of indium oxide to be maintained low.
  • the field-effect mobility of the transistor can be increased to 50 cm 2 /(V ⁇ s) or more, preferably 100 cm 2 /(V ⁇ s) or more, more preferably 150 cm 2 /(V ⁇ s) or more, even more preferably 200 cm 2 /(V ⁇ s) or more, and still more preferably 250 cm 2 /(V ⁇ s) or more.
  • an indium oxide film is its high oxygen permeability (diffusibility) compared to an IGZO film.
  • oxygen (O) diffusing into an indium oxide film passes through the indium oxide film and is released as oxygen molecules (O 2 ). It may also react with hydrogen contained in the film and be released as water molecules (H 2 O).
  • oxygen vacancies ( VO ) exist in the film the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen easily diffuses into an indium oxide film, it can be said that oxygen vacancies are more easily compensated for compared to an IGZO film.
  • indium oxide films are easier to reduce oxygen vacancies in than IGZO films, and by applying such indium oxide films to transistors, it is possible to create transistors that exhibit extremely high reliability.
  • the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and is released as hydrogen molecules (H 2 ). Alternatively, hydrogen reacts with oxygen contained in the film and is released as water molecules.
  • Transistors using indium oxide film are accumulation-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is a constant value, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, using indium oxide, which has a small effective electron mass, in a transistor can increase the transistor's on-current or field-effect mobility.
  • Table 1 shows the effective masses of single-crystal indium oxide (here, In 2 O 3 ) and single-crystal silicon (Si).
  • indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes.
  • the effective mass of electrons in indium oxide is characterized by being almost independent of the crystal orientation. Therefore, by using crystalline indium oxide for a transistor, a transistor with high field-effect mobility and high frequency characteristics (also referred to as f characteristics) can be realized.
  • f characteristics also referred to as f characteristics
  • the off-state current per 1 ⁇ m of channel width can be 1 fA (1 ⁇ 10 ⁇ 15 A) or less or 1 aA (1 ⁇ 10 ⁇ 18 A) or less in an environment of 125° C., and 1 aA (1 ⁇ 10 ⁇ 18 A) or less or 1 zA (1 ⁇ 10 ⁇ 21 A) or less in an environment of room temperature (25° C.).
  • indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.
  • a seed layer so that it is in contact with at least a portion of the crystalline indium oxide film.
  • a material containing crystals with a small difference in lattice constant also called lattice mismatch
  • lattice mismatch lattice mismatch
  • a substrate e.g., a single-crystal substrate
  • ⁇ a can be set to between -5% and 5%, preferably between -4% and 4%, more preferably between -3% and 3%, and even more preferably between -2% and 2%.
  • the indium oxide crystals have a cubic crystal structure (bixbyite type).
  • yttria-stabilized zirconia (YSZ) crystals can have a cubic crystal structure (fluorite type).
  • the lattice mismatch of the indium oxide crystals with the cubic YSZ crystals is within the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.
  • the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation.
  • a film having crystals of a hexagonal or trigonal crystal structure can be used under an indium oxide film having crystals of a cubic crystal structure.
  • hexagonal or trigonal crystals include a wurtzite structure, a YbFe2O4 structure, a Yb2Fe3O7 structure, and modified structures thereof.
  • An example of a crystal having a YbFe2O4 structure or a Yb2Fe3O7 structure is IGZO.
  • This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.
  • FIGS 10A and 10B show a Si transistor 1100 and an OS transistor 1200 provided above it. Note that the transistor 100 described in Embodiment 1 can be used as the OS transistor 1200.
  • the Si transistor 1100 will now be described.
  • the Si transistor 1100 is a Fin-type transistor.
  • Figure 10A shows a schematic cross-sectional view in the channel length direction
  • Figure 10B shows a schematic cross-sectional view in the channel width direction.
  • the Si transistor 1100 is provided on a substrate 1011 and includes a conductive layer 1018a that functions as a gate electrode, an insulating layer 1017 that functions as a gate insulating film, a semiconductor region 1013 that functions as a channel formation region, and a low-resistance region 1014 that functions as a source region or drain region.
  • the substrate 1011 may be, for example, a silicon substrate or an SOI (Silicon On Insulator) substrate.
  • An element isolation layer 1012, an insulating layer 1015, and dummy gate electrodes 1018b and 1018c are provided on a substrate 1011.
  • the insulating layer 1015 functions as a sidewall.
  • insulating layers 1016, 1019, 1020, 1021, 1023, 1025, 1026, 1027, 1029, and 1030 are provided, and these insulating layers function as interlayer insulating films.
  • the insulating layers 1019, 1021, 1025, 1027, and 1030 function as barrier films.
  • the conductive layers 1022, 1024, and 1028 function as plugs, electrodes, or wiring.
  • An OS transistor 1200 is provided on the insulating layer 11.
  • the conductive layer 1032 functions as a plug provided in the insulating layer 17.
  • the insulating layer 1031 is provided so as to cover the side surface of the conductive layer 1032 provided in the insulating layer 17.
  • the insulating layer 1031 is preferably an insulating layer having at least one or both of oxygen barrier properties and hydrogen barrier properties.
  • Insulating layers 1033, 1034, 1035, and 1036 are provided above the OS transistor 1200 and function as interlayer insulating films.
  • the insulating layers 1033 and 1035 function as barrier films.
  • the conductive layer 1037 functions as an electrode or wiring.
  • one of the source and drain of the Si transistor 1100 (here, the low-resistance region 1014) is connected to one of the source and drain of the OS transistor 1200 through a conductive layer.
  • the gate of the Si transistor 1100 is connected to the gate of the OS transistor 1200 through a conductive layer.
  • Si transistors have higher field-effect mobility and faster operating speed than OS transistors. Furthermore, OS transistors have significantly lower off-state current than Si transistors. In particular, OS transistors that use indium oxide in the semiconductor layer in which the channel is formed have extremely low off-state current and high field-effect mobility comparable to that of Si transistors. Using a combination of OS transistors and Si transistors enables the realization of CMOS circuits that consume low power and operate at high speeds.
  • configuration examples of logic circuits such as a NOT circuit, a NOR circuit, and a NAND circuit, will be described as examples of circuits using Si transistors and OS transistors.
  • Fig. 11A is a circuit diagram showing an example of the configuration of a NOT circuit (NOT).
  • a NOT circuit is also called an inverting circuit or an inverter circuit.
  • Fig. 11B shows the circuit symbol for a NOT circuit.
  • Fig. 11C is a timing chart explaining the operation of the NOT circuit.
  • the NOT circuit shown in FIG. 11A includes transistors Tr11 and Tr12.
  • Transistor Tr11 is a Si transistor functioning as a p-type transistor
  • transistor Tr12 is an OS transistor functioning as an n-type transistor.
  • a potential H e.g., a high power supply potential VDD
  • the other of the source and drain of transistor Tr11 is connected to one of the source and drain of transistor Tr12 and terminal Y.
  • a potential L e.g., a low power supply potential VSS
  • the gates of transistors Tr11 and Tr12 are connected to terminal A.
  • terminal A functions as the input terminal
  • terminal Y functions as the output terminal.
  • a potential H is input to terminal A of the NOT circuit
  • a potential L is output from terminal Y
  • a potential H is output from terminal Y (see Figure 11C).
  • the NOT circuit has the function of correcting an input signal that has been distorted by wiring resistance, parasitic capacitance, noise, etc., to a signal that is not distorted or has reduced distortedness, and outputting the corrected signal (also known as a "waveform shaping function").
  • the NOT circuit also has the function of amplifying the voltage amplitude of the input signal and outputting it.
  • the output of the NOT circuit is supplied to a load such as a capacitance element Cx and a transistor Trx. Because power is supplied to the output of the NOT circuit via transistor Tr11 or transistor Tr12, the ability to drive a load connected to the output can be improved.
  • the NOT circuit has the function of improving its ability to drive a load (also known as a "driving force improvement function").
  • FIG. 12A is a circuit diagram showing a configuration example of a two-input, one-output NOR circuit (NOR). Also, FIG. 12B shows a circuit symbol for the NOR circuit.
  • the NOR circuit shown in FIG. 12A includes transistors Tr21, Tr22, Tr23, and Tr24. Si transistors functioning as p-channel transistors are used as the transistors Tr21 and Tr22, and OS transistors functioning as n-channel transistors are used as the transistors Tr23 and Tr24.
  • a potential H is supplied to either the source or drain of transistor Tr21.
  • the other source or drain of transistor Tr21 is connected to either the source or drain of transistor Tr22.
  • the other source or drain of transistor Tr22 is connected to either the source or drain of transistor Tr23, one source or drain of transistor Tr24, and terminal Y.
  • a potential L is supplied to the other source or drain of transistor Tr23 and the other source or drain of transistor Tr24.
  • the gate of transistor Tr21 is connected to the gate of transistor Tr23 and terminal A. Further, the gate of transistor Tr22 is connected to the gate of transistor Tr24 and terminal B.
  • the NOR circuit shown in Figures 12A and 12B has the function of outputting a potential H from terminal Y when a potential L is input to both terminal A and terminal B. Furthermore, it has the function of outputting a potential L from terminal Y when a potential H is input to one or both of terminals A and B.
  • an OR circuit can be realized by connecting the input of a NOT circuit to the output of a NOR circuit.
  • [NAND circuit] 12D is a circuit diagram showing a configuration example of a two-input, one-output NAND circuit (NAND). Also, FIG. 12E shows a circuit symbol of the NAND circuit.
  • the NAND circuit shown in FIG. 12D includes transistors Tr31, Tr32, Tr33, and Tr34. Si transistors functioning as p-channel transistors are used as the transistors Tr31 and Tr32, and OS transistors functioning as n-channel transistors are used as the transistors Tr33 and Tr34.
  • a potential H is supplied to one of the source or drain of transistor Tr31 and one of the source or drain of transistor Tr32.
  • the other of the source or drain of transistor Tr31 and the other of the source or drain of transistor Tr32 are connected to one of the source or drain of transistor Tr33 and terminal Y.
  • the other of the source or drain of transistor Tr33 is connected to one of the source or drain of transistor Tr34.
  • a potential L is supplied to the other of the source or drain of transistor Tr34.
  • the gate of transistor Tr31 is connected to the gate of transistor Tr34 and terminal B.
  • the gate of transistor Tr32 is connected to the gate of transistor Tr33 and terminal A.
  • the NAND circuits shown in Figures 12D and 12E have the function of outputting a potential L from terminal Y when a potential H is input to both terminal A and terminal B. Furthermore, they have the function of outputting a potential H from terminal Y when a potential L is input to one or both of terminal A and terminal B.
  • an AND circuit can be realized by combining a NAND circuit with a NOT circuit.
  • This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.
  • the semiconductor device of one embodiment of the present invention is suitable for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers because it can provide a transistor with high on-state current and a small area.
  • FIG. 13A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted.
  • the electronic component 980 shown in FIG. 13A has a semiconductor device 981 inside a mold 984.
  • FIG. 13A omits some details in order to show the interior of the electronic component 980.
  • the electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are electrically connected to electrode pads 986, and the electrode pads 986 are electrically connected to the semiconductor device 981 via wires 987.
  • the electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and electrically connected on the printed circuit board 988 to complete the mounting substrate 989.
  • the semiconductor device 981 also has a drive circuit layer 982 and a memory layer 983.
  • the memory layer 983 is configured by stacking multiple memory cell arrays.
  • the stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding.
  • TSV Through Silicon Via
  • bonding technology such as Cu-Cu direct bonding.
  • connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, making it possible to increase the number of connection pins.
  • Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also known as memory bandwidth).
  • the multiple memory cell arrays included in the memory layer 983 are formed using OS transistors and that the multiple memory cell arrays are monolithically stacked.
  • OS transistors By configuring the multiple memory cell arrays as a monolithic stack, it is possible to improve either or both of the memory bandwidth and the memory access latency.
  • bandwidth refers to the amount of data transferred per unit time
  • access latency refers to the time from access to the start of data exchange.
  • Si transistors are used for the memory layer 983, it is more difficult to achieve a monolithic stack configuration than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stack configuration.
  • the semiconductor device 981 may also be referred to as a die.
  • a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • FIG. 13B shows a perspective view of electronic component 990.
  • Electronic component 990 is an example of a SiP (System in Package) or MCM (Multi-Chip Module).
  • Electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and multiple semiconductor devices 981 provided on interposer 991.
  • Electronic component 990 shows an example in which semiconductor device 981 is used as a high bandwidth memory (HBM). Furthermore, semiconductor device 994 can be used in integrated circuits such as a CPU, GPU, or FPGA (Field Programmable Gate Array).
  • HBM high bandwidth memory
  • semiconductor device 994 can be used in integrated circuits such as a CPU, GPU, or FPGA (Field Programmable Gate Array).
  • the package substrate 992 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 991 can be, for example, a silicon interposer or a resin interposer.
  • the interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992.
  • the interposer is sometimes called a "rewiring substrate” or "intermediate substrate.”
  • through electrodes are provided in the interposer 991, and the integrated circuits and package substrate 992 are connected using these through electrodes.
  • TSVs can also be used as through electrodes.
  • the interposer on which the HBM is mounted must have fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.
  • SiPs and MCMs that use silicon interposers that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is less likely. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. It is particularly preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.
  • a composite structure may be used that combines a memory cell array stacked using TSVs with a monolithic stacked memory cell array.
  • a heat sink may also be provided on top of the electronic component 990.
  • a heat sink it is preferable to align the height of the integrated circuit provided on the interposer 991.
  • the electronic component 990 shown in this embodiment it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.
  • Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate.
  • Figure 13B shows an example in which the electrodes 993 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 993 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.
  • Electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • Fig. 14A shows a perspective view of a mainframe computer 5600.
  • the mainframe computer 5600 shown in Fig. 14A has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the mainframe computer 5600 may also be called a supercomputer.
  • the computer 5620 can have the configuration shown in the perspective view in FIG. 14B, for example.
  • the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.
  • PC card 5621 shown in Figure 14C is an example of a processing board equipped with a CPU, GPU, memory device, etc.
  • PC card 5621 has board 5622.
  • Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629.
  • Figure 14C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, please refer to the descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 described below.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • the semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting these terminals into sockets (not shown) provided on the board 5622.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 990 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 can be, for example, a memory device.
  • the electronic component 990 can be used as the semiconductor device 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, artificial intelligence learning and inference.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment.
  • a semiconductor device includes an OS transistor.
  • OS transistors Compared to Si transistors, OS transistors exhibit smaller variations in electrical characteristics due to radiation exposure. In other words, OS transistors have high radiation resistance and are therefore highly reliable and suitable for use in environments where radiation may be incident.
  • OS transistors are suitable for use in outer space.
  • OS transistors can be used as transistors for semiconductor devices installed in space shuttles, artificial satellites, or space probes.
  • outer space refers to an altitude of 100 km or higher, for example.
  • the outer space described in this specification can include one or more of the thermosphere, mesosphere, and stratosphere.
  • outer space is an environment with radiation levels more than 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • Figure 14D shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 14D also shows a planet 6804 in space.
  • the secondary battery 6805 may be provided with a battery management system (also referred to as BMS) or a battery control circuit.
  • a battery management system also referred to as BMS
  • a battery control circuit Using an OS transistor in the battery management system or battery control circuit described above is preferable because it consumes low power and has high reliability even in space.
  • the control device 6807 also has a function of controlling the satellite 6800.
  • the control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the control device 6807 is preferably a semiconductor device including an OS transistor according to one embodiment of the present invention.
  • a semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.
  • OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance compared to Si transistors.
  • the semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center.
  • the data center is required to perform long-term management of data, such as ensuring data immutability.
  • the building must be large enough to accommodate the installation of storage devices and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.
  • the power required to store data can be reduced and the semiconductor device that stores data can be made smaller. This allows for the storage system to be made smaller, the power supply for storing data to be made smaller, and the cooling equipment to be made smaller. This allows for space savings in the data center.
  • the semiconductor device of one embodiment of the present invention has low power consumption, which allows for reduced heat generation from the circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.
  • Figure 14E shows a storage system applicable to a data center.
  • the storage system 7010 shown in Figure 14E has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage).
  • the host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).
  • SAN Storage Area Network
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • Storage 7003 uses flash memory to reduce data access speed, i.e., the time required to store and output data, but this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage.
  • data access speed i.e., the time required to store and output data
  • this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage.
  • storage systems typically provide cache memory within the storage to reduce the time required to store and output data.
  • the aforementioned cache memory is used within the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and storage 7003 is stored in the cache memory within the storage control circuit 7002 and storage 7003, and then output to the host 7001 or storage 7003.
  • OS transistors as transistors for storing data in the cache memory and maintaining a potential corresponding to the data
  • the frequency of refreshes can be reduced, and power consumption can be lowered.
  • by stacking the memory cell array miniaturization is possible.
  • This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.
  • Insulating layer 12: Spacer layer, 12a: Spacer layer, 12b: Spacer layer, 13: Semiconductor layer, 14: Conductive layer, 14a: Conductive layer, 14b: Conductive layer, 15: Conductive layer, 15a: Conductive layer, 15b: Conductive layer, 16: Insulating layer, 17: Insulating layer, 18: Insulating layer, 19: Conductive layer, 19a: Conductive layer, 19b: Conductive layer, 41: Insulating layer, 61: Island-shaped film, 62: Island-shaped film, 63: Island-shaped film, 64: Trench, 100: Transistor, 980: Electronic component, 981: Semiconductor device, 982: Drive circuit layer, 983: Memory layer, 984: Mold, 985: Land, 986: Electrode pad, 987: Wire, 988: Print Substrate, 989: mounting substrate, 990: electronic component, 991: interposer, 992: package substrate, 993: electrode, 994: semiconductor device, 1011: substrate, 1011:

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  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne un transistor permettant de transporter de grands courants ou occupant peu d'espace. L'invention concerne un dispositif à semi-conducteur comprenant ce qui suit. Une paire de premières couches d'espacement sont espacées et situées au-dessus d'une première couche isolante. Une première couche semi-conductrice est située au-dessus de la paire de premières couches d'espacement et a une région qui ne chevauche pas la paire de premières couches d'espacement. Une paire de premières couches conductrices sont espacées et ont une partie située au-dessus de la première couche semi-conductrice. Une troisième couche isolante a une partie située sur la paire de premières couches conductrices, une partie en contact avec une surface latérale de la paire de premières couches conductrices, et une partie en contact avec la première couche isolante. Une seconde couche isolante a une partie en contact avec une surface supérieure, une surface inférieure et une surface latérale dans la région de la première couche semi-conductrice qui ne chevauche pas la paire de premières couches d'espacement. Une seconde couche conductrice a une partie entourant la surface supérieure, la surface inférieure et la surface latérale de la première couche semi-conductrice, la seconde couche isolante étant interposée entre celles-ci.
PCT/IB2025/056477 2024-07-03 2025-06-26 Dispositif semi-conducteur Pending WO2026009092A1 (fr)

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JP2024-107405 2024-07-03
JP2024107405 2024-07-03

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220093474A1 (en) * 2020-09-24 2022-03-24 Intel Corporation Extension of nanocomb transistor arrangements to implement gate all around
JP2023152817A (ja) * 2022-03-31 2023-10-17 株式会社半導体エネルギー研究所 半導体装置
JP2024024581A (ja) * 2022-08-09 2024-02-22 三星電子株式会社 半導体素子及びその製造方法
WO2024079586A1 (fr) * 2022-10-14 2024-04-18 株式会社半導体エネルギー研究所 Dispositif à semi-conducteur et dispositif de stockage

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220093474A1 (en) * 2020-09-24 2022-03-24 Intel Corporation Extension of nanocomb transistor arrangements to implement gate all around
JP2023152817A (ja) * 2022-03-31 2023-10-17 株式会社半導体エネルギー研究所 半導体装置
JP2024024581A (ja) * 2022-08-09 2024-02-22 三星電子株式会社 半導体素子及びその製造方法
WO2024079586A1 (fr) * 2022-10-14 2024-04-18 株式会社半導体エネルギー研究所 Dispositif à semi-conducteur et dispositif de stockage

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