WO2026009461A1 - Dispositif à semi-conducteur et dispositif de conversion de puissance - Google Patents

Dispositif à semi-conducteur et dispositif de conversion de puissance

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Publication number
WO2026009461A1
WO2026009461A1 PCT/JP2024/037320 JP2024037320W WO2026009461A1 WO 2026009461 A1 WO2026009461 A1 WO 2026009461A1 JP 2024037320 W JP2024037320 W JP 2024037320W WO 2026009461 A1 WO2026009461 A1 WO 2026009461A1
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WO
WIPO (PCT)
Prior art keywords
layer
wiring layer
semiconductor device
thermal conductivity
high thermal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2024/037320
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English (en)
Japanese (ja)
Inventor
浩 小林
昌樹 田屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of WO2026009461A1 publication Critical patent/WO2026009461A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Definitions

  • This disclosure relates to semiconductor devices and power conversion devices.
  • cooling of the element is important. It is well known that in semiconductor devices with single-sided cooling, cooling efficiency can be improved by using a lead frame to direct the heat flow to the cooling surface instead of using wires in the wiring layer on the surface of the element.
  • a simple copper lead frame does not result in a significant improvement, as the flow path is longer than if the heat flow were directed directly from the back of the element to the cooling surface, resulting in higher thermal resistance. Therefore, it has been proposed to add a high thermal conductivity layer, such as graphite, which has a higher thermal conductivity than copper, to a high conductivity layer, such as copper, and use it in the lead frame.
  • the thermal conductivity of the high thermal conductivity layer is anisotropic, depending on the stacking direction of the high electrical conductivity layer and the high thermal conductivity layer, the thermal resistance of the wiring layer may become large.
  • This disclosure has been made to solve the above-mentioned problems, and its purpose is to provide a semiconductor device including a wiring layer with reduced thermal resistance, and a power conversion device including such a semiconductor device.
  • a semiconductor device includes a substrate, a semiconductor element, and a wiring layer.
  • the substrate has a first main surface.
  • the semiconductor element is disposed on the first main surface. Electrodes are provided on the semiconductor element.
  • the wiring layer is connected to the electrodes.
  • the wiring layer includes a high thermal conductivity layer and a high electrical conductivity layer.
  • the high electrical conductivity layer is stacked on the high thermal conductivity layer. The stacking direction of the high thermal conductivity layer and the high electrical conductivity layer is perpendicular to the extension direction of the wiring layer in a plan view of the first main surface.
  • the power conversion device comprises a main conversion circuit and a control circuit.
  • the main conversion circuit has the semiconductor device described above and converts and outputs input power.
  • the control circuit outputs a control signal to the main conversion circuit to control the main conversion circuit.
  • FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment; 1 is a schematic front view of a semiconductor device according to a first embodiment; FIG. 1 is a schematic plan view of a first modified example of the semiconductor device according to the first embodiment.
  • FIG. 10 is a schematic front view of a first modified example of the semiconductor device according to the first embodiment.
  • FIG. 10 is a schematic front view of a second modified example of the semiconductor device according to the first embodiment.
  • FIG. 10 is a schematic plan view of a third modified example of the semiconductor device according to the first embodiment;
  • FIG. 10 is a schematic front view of a third modified example of the semiconductor device according to the first embodiment.
  • FIG. 10 is a schematic plan view of a fourth modified example of the semiconductor device according to the first embodiment; FIG.
  • FIG. 11 is a schematic front view of a fifth modified example of the semiconductor device according to the first embodiment.
  • FIG. 10 is a schematic front view of a semiconductor device according to a second embodiment.
  • FIG. 11 is a partially enlarged schematic front view of region XI in FIG. 10 .
  • FIG. 10 is a partially enlarged schematic front view of a first modification of the semiconductor device according to the second embodiment;
  • FIG. 11 is a schematic plan view of a semiconductor device according to a third embodiment.
  • 14 is a schematic cross-sectional view taken along line XIV-XIV in FIG. 13.
  • FIG. 11 is a schematic cross-sectional view of a wiring layer and a conductive bridge member in a semiconductor device according to a third embodiment.
  • FIG. 10 is a schematic cross-sectional view of a modified example of a wiring layer and a conductive bridge member in a semiconductor device according to a third embodiment.
  • FIG. 10 is a schematic cross-sectional view of a modified example of a wiring layer and a conductive bridge member in a semiconductor device according to a third embodiment.
  • FIG. 10 is a schematic cross-sectional view of a modified example of a wiring layer and a conductive bridge member in a semiconductor device according to a third embodiment.
  • FIG. 10 is a schematic cross-sectional view of a modified example of a wiring layer and a conductive bridge member in a semiconductor device according to a third embodiment.
  • FIG. 10 is a schematic cross-sectional view of a modified example of a wiring layer and a conductive bridge member in a semiconductor device according to a third embodiment.
  • FIG. 10 is a schematic cross-sectional view of a modified example of a wiring layer and a conductive bridge member in a semiconductor device according to a third embodiment.
  • FIG. FIG. 10 is a schematic plan view of a semiconductor device according to a fourth embodiment.
  • FIG. 10 is a schematic front view of a semiconductor device according to a fourth embodiment.
  • FIG. 10 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to a fifth embodiment is applied.
  • Fig. 1 is a schematic plan view of a semiconductor device 100 according to a first embodiment.
  • Fig. 2 is a schematic front view of the semiconductor device 100 according to the first embodiment.
  • the semiconductor device 100 shown in Figures 1 and 2 is, for example, a power semiconductor device 100, and mainly comprises a substrate 1, a semiconductor element 2, a wiring layer 3, and leads 4.
  • the substrate 1 has a first major surface 10a and a second major surface 10b.
  • the first major surface 10a is the surface on which the semiconductor element 2 is mounted.
  • the second major surface 10b is the surface opposite the first major surface 10a.
  • the substrate 1 includes an upper metal layer 11, an insulating plate 12, and a lower metal layer 13.
  • the upper metal layer 11 is disposed on the insulating plate 12.
  • the insulating plate 12 is disposed on the lower metal layer 13. In the z direction, the upper metal layer 11 is located opposite the lower metal layer 13 when viewed from the insulating plate 12.
  • the surface (top surface) of the upper metal layer 11 forms the first major surface 10a.
  • the back surface (bottom surface) of the lower metal layer 13 forms the second major surface 10b.
  • the directions in which the first major surface 10a extends are the x direction and the y direction.
  • the y direction is perpendicular to the x direction.
  • the direction perpendicular to the first major surface 10a is the z direction.
  • the z direction is perpendicular to the x direction and the y direction.
  • the material that constitutes the upper metal layer 11 may include, for example, copper (Cu), aluminum (Al), a copper alloy, or an aluminum alloy.
  • the material that constitutes the upper metal layer 11 is a material that has high electrical conductivity and high thermal conductivity.
  • the upper metal layer 11 includes a first conductive portion 11a, a second conductive portion 11b, and a third conductive portion 11c.
  • the first conductive portion 11a, the second conductive portion 11b, and the third conductive portion 11c are arranged spaced apart from one another on the insulating plate 12.
  • the first conductive portion 11a has a rectangular shape.
  • the second conductive portion 11b has an L-shape.
  • the third conductive portion 11c has a rectangular shape.
  • the first conductive portion 11a, the second conductive portion 11b, and the third conductive portion 11c may each have any shape.
  • the insulating plate 12 is, for example, a ceramic insulating substrate. That is, the material constituting the insulating plate 12 is, for example, an insulating ceramic.
  • the material constituting the insulating plate 12 may be, for example, any one of silicon nitride (Si 3 N 4 ), aluminum nitride (AlN), and aluminum oxide (Al 2 O 3 ).
  • the material constituting the lower metal layer 13 may be the same as or different from the material constituting the upper metal layer 11.
  • the thickness of the lower metal layer 13 in the z direction may be the same as or different from the thickness of the upper metal layer 11 in the z direction.
  • the thickness of the lower metal layer 13 in the z direction may be smaller than the thickness of the upper metal layer 11 in the z direction.
  • the volume of the lower metal layer 13 may be made the same as the volume of the upper metal layer 11.
  • FIG. 3 is a schematic plan view of a first variation of the semiconductor device 100 according to the first embodiment.
  • FIG. 3 corresponds to FIG. 1.
  • FIG. 4 is a schematic front view of a first variation of the semiconductor device 100 according to the first embodiment.
  • FIG. 4 corresponds to FIG. 2.
  • the semiconductor device 100 shown in FIGS. 3 and 4 basically has the same configuration as the semiconductor device 100 shown in FIGS. 1 and 2 and can achieve the same effects, but the configuration of the substrate 1 is different.
  • the substrate 1 includes a metal block layer 14, an insulating sheet layer 15, and a base plate 16.
  • the metal block layer 14 is disposed on the insulating sheet layer 15.
  • the insulating sheet layer 15 is disposed on the base plate 16. In the z direction, the metal block layer 14 is located opposite the base plate 16 when viewed from the insulating sheet layer 15.
  • the surface of the metal block layer 14 forms the first main surface 10a.
  • the back surface of the base plate 16 forms the second main surface 10b.
  • the material that makes up the metal block layer 14 is a material with high electrical conductivity and high thermal conductivity, such as copper (Cu) or a copper alloy.
  • the metal block layer 14 includes a first block 14a, a second block 14b, and a third block 14c.
  • the first block 14a, the second block 14b, and the third block 14c are arranged spaced apart from one another on the insulating sheet layer 15.
  • the insulating sheet layer 15 is a thin film that is thinner in the z direction than the insulating plate 12.
  • the base plate 16 is made of a material with high thermal conductivity, such as Cu or Al-Si-C.
  • the base plate 16 may also include a cooler.
  • the cooler is provided, for example, on the second main surface 10b.
  • the cooler is, for example, a fin.
  • the semiconductor element 2 is disposed on the first major surface 10a of the second conductive portion 11b.
  • the semiconductor element 2 is provided with an electrode 21.
  • the electrode 21 includes, for example, a main electrode 22 and a control electrode 23.
  • the main electrode 22 includes a front main electrode 22a and a back main electrode 22b. As shown in FIG. 2, the back main electrode 22b is connected to the first major surface 10a via a joint 51.
  • the control electrode 23 controls the main current.
  • the surface main electrode 22a and the control electrode 23 are disposed on the surface (top surface) of the semiconductor element 2.
  • the back surface main electrode 22b is disposed on the back surface (bottom surface) of the semiconductor element 2.
  • the surface main electrode 22a and the control electrode 23 are disposed spaced apart from each other on the surface of the semiconductor element 2.
  • the material that constitutes the electrode 21 has high electrical and thermal conductivity.
  • the electrode 21 may be formed by copper (Cu) plating or nickel (Ni) plating.
  • the electrode 21 may also be a plate made of copper or a copper alloy. The plate may be bonded directly to the semiconductor element 2, or may be bonded to the semiconductor element 2 via a bonding material that uses a sintered material containing fine particles of silver (Ag) or copper (Cu), etc.
  • the short-circuit resistance of the semiconductor element 2 is improved.
  • An electric field strength mitigation portion 24 is provided on the surface of the semiconductor element 2.
  • the electric field strength mitigation portion 24 mitigates the electric field strength formed by the electrode 21.
  • the electric field strength mitigation portion 24 is arranged to surround the electrode 21.
  • the electric field strength mitigation portion 24 is formed on the outer periphery of the surface of the semiconductor element 2.
  • the electric field strength mitigation portion 24 may be annular in shape.
  • the electric field strength mitigation portion 24 may be a termination structure called a guard ring.
  • the shape of the electric field strength reduction portion 24 does not have to be annular.
  • the electric field strength reduction portion 24 may be a termination structure known as a JTE (Junction Termination Extension) structure.
  • the electric field strength reduction portion 24 is, for example, a p-type region formed by ion implantation.
  • the electric field strength reduction portion 24 may be formed on the surface of the semiconductor element 2 as shown in FIG. 2, or may be formed inside the semiconductor element 2.
  • the semiconductor element 2 is a so-called power semiconductor element 2 that controls electric power. Any material may be used as the material for the semiconductor element 2. Materials such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ), and diamond may be used as the material for the semiconductor element 2. Gallium oxide, in particular, has low thermal conductivity. Therefore, when the material for the semiconductor element 2 contains gallium oxide (Ga 2 O 3 ), the effect of dissipating heat from the main electrode 22 located near the heat source is enhanced. Specifically, the amount of heat flowing to the wiring layer 3 increases.
  • the semiconductor element 2 is an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but it may also be a diode or have other functions.
  • the type of semiconductor element is not particularly limited, but it may be, for example, a vertical semiconductor element.
  • the semiconductor device 100 may also be a semiconductor device 100 that uses flip-chip mounting in which the surface main electrode 22a is connected to the substrate 1.
  • the wiring layer 3 is connected to the electrode 21 and the substrate 1. Specifically, one end of the wiring layer 3 is connected to the surface main electrode 22a via a joint 52. The other end of the wiring layer 3 is connected to the first main surface 10a of the third conductive portion 11c via a joint 53. Heat generated in the semiconductor element 2 flows along the extension direction of the wiring layer 3.
  • the wiring layer 3 includes a plurality of high thermal conductivity layers 32 and a plurality of high electrical conductivity layers 31.
  • the high electrical conductivity layers 31 are arranged adjacent to the high thermal conductivity layers 32.
  • the wiring layer 3 is formed by alternately stacking the high thermal conductivity layers 32 and the high electrical conductivity layers 31.
  • the material that makes up the high thermal conductivity layer 32 is, for example, graphite. As will be described later, graphite is anisotropic.
  • the material that makes up the high electrical conductivity layer 31 is, for example, copper (Cu) or a copper alloy.
  • the high thermal conductivity layer 32 has high thermal conductivity in the in-plane direction. Furthermore, the high electrical conductivity layer 31 has high electrical conductivity. By doing so, it is possible to obtain a wiring layer 3 that maintains high electrical conductivity and has reduced thermal resistance.
  • the wiring layer 3 extends from the second conductive portion 11b toward the third conductive portion 11c.
  • the extension direction of the wiring layer 3 in a plan view of the first major surface 10a is, for example, the x direction.
  • the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 in a plan view of the first major surface 10a is, for example, the y direction.
  • the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is perpendicular to the extension direction of the wiring layer 3 in a plan view of the first major surface 10a.
  • the wiring layer 3 is positioned at a distance from the electric field strength mitigation section 24 so that the electric field formed by the wiring layer 3 does not affect the electric field strength mitigation section 24.
  • the wiring layer 3 needs to be positioned at a distance of at least 0.1 mm from the electric field strength mitigation section 24.
  • the wiring layer 3 may also be positioned at a distance of 0.2 mm or more from the electric field strength mitigation section 24, and may also be positioned at a distance of 0.3 mm or more taking into account manufacturing variations.
  • the wiring layer 3 has a side surface 34.
  • the side surface 34 is connected to the surface main electrode 22a via a joint 52.
  • the side surface 34 is connected to the first main surface 10a of the third conductive portion 11c via a joint 53.
  • the side surface 34 faces the electric field strength mitigation portion 24.
  • a portion of the wiring layer 3 extends so as to surround the electric field strength mitigation portion 24.
  • the shape of the side surface 34 when viewed from the y direction is, for example, U-shaped.
  • the side surface 34 includes a first region s1, a second region s2, and a third region s3.
  • the first region s1 is connected to the second region s2 and the joint 52.
  • the first region s1 extends in the z direction. From a different perspective, the first region s1 extends perpendicular to the first major surface 10a.
  • the second region s2 is connected to the first region s1 and the third region s3.
  • the second region s2 extends in the x direction. From a different perspective, the second region s2 extends parallel to the first major surface 10a.
  • the third region s3 is connected to the second region s2 and the joint 53. The third region s3 extends in the z direction.
  • the third region s3 extends perpendicular to the first major surface 10a.
  • the first region s1, second region s2, and third region s3 each have a linear shape.
  • the wiring layer 3 is positioned at a distance from the electric field intensity mitigation portion 24.
  • joints 51, 52, and 53 may be a material with high electrical conductivity and high thermal conductivity.
  • Joints 51, 52, and 53 may be formed using a sintered material containing fine particles of silver (Ag) or copper (Cu), or may be formed using solder.
  • Joints 51, 52, and 53 may be formed by liquid phase diffusion of Sn-Cu, Sn-Ag, or the like. This allows the joint thickness in the z direction to be 0.02 mm or less. As a result, the thermal resistance at joints 51, 52, and 53 can be reduced.
  • the control electrode 23 is connected to the first main surface 10a of the first conductive portion 11a via a metal connection portion 6.
  • the material constituting the metal connection portion 6 may be, for example, copper (Cu), aluminum (Al), a copper alloy, or an aluminum alloy.
  • the metal connection portion 6 may be a wire formed by wire bonding, or may be a clip.
  • the metal connection portion 6 is positioned at a distance from the electric field strength mitigation portion 24 so that the electric field formed by the metal connection portion 6 does not affect the electric field strength mitigation portion 24. As shown in Figure 2, the metal connection portion 6 extends so as to surround the electric field strength mitigation portion 24.
  • the leads 4 are provided on the first main surface 10a. As shown in FIG. 2, the leads 4 extend in the z-direction.
  • the material constituting the leads 4 may be terminals made of copper.
  • the lead 4 may be directly connected to the upper metal layer 11. Specifically, the lead 4 may be connected to the upper metal layer 11 using ultrasonic welding or laser welding. The lead 4 may also be indirectly connected to the upper metal layer 11 using a bonding material such as solder. The bonding material used to connect the lead 4 to the upper metal layer 11 may be the same as the bonding material used to form the joints 51, 52, and 53.
  • the lead 4 includes a first lead 41, a second lead 42, and a third lead 43.
  • the first lead 41 is connected to the first main surface 10a of the first conductive portion 11a.
  • the first lead 41 is spaced apart from the metal connection portion 6 in the y direction.
  • the second lead 42 is connected to the first main surface 10a of the second conductive portion 11b.
  • the second lead 42 is spaced apart from the semiconductor element 2 in the x direction.
  • the third lead 43 is connected to the first main surface 10a of the third conductive portion 11c.
  • the third lead 43 is spaced apart from the wiring layer 3 in the x direction.
  • FIG. 5 is a schematic front view of a second variant of the semiconductor device 100 according to the first embodiment.
  • FIG. 5 corresponds to FIG. 2.
  • the semiconductor device 100 shown in FIG. 5 basically has the same configuration as the semiconductor device 100 shown in FIGS. 1 and 2, and can achieve the same effects, but differs in that it includes a case 82. Note that, for ease of explanation, FIG. 5 shows the internal structure of the case 82.
  • the semiconductor device 100 may be used as a case-type module.
  • the semiconductor device 100 includes a sealing portion 81, a case 82, and a mounting portion 83.
  • the lower metal layer 13 is connected to the mounting portion 83 via a joint 54.
  • the bonding material forming the joint 54 may be the same as the bonding material forming the joints 51, 52, and 53. Electric current and heat pass through the joint 54 in the z direction (thickness direction). Therefore, the material forming the joint 54 has high thermal conductivity.
  • the substrate 1, semiconductor element 2, wiring layer 3, and case 82 are mounted on the surface (top surface) of the mounting portion 83.
  • a cooler may be provided on the back surface (bottom surface) of the mounting portion 83.
  • the cooler may be, for example, a pin fin, or a cooling fin of some other shape.
  • a part of the cooler may be connected to the back surface (bottom surface) of the mounting portion 83, or the entire cooler may be connected to the back surface (bottom surface) of the mounting portion 83.
  • the cooler may be connected to the mounting portion 83 via a TIM (Thermal Interface Material).
  • the substrate 1, semiconductor element 2, and wiring layer 3 are arranged inside the case 82. Inside the case 82, the substrate 1, semiconductor element 2, and wiring layer 3 are sealed by a sealing portion 81.
  • the leads 4 extend from the substrate 1 toward the outside of the sealing portion 81.
  • the sealing portion 81 has insulating properties.
  • the sealing portion 81 is formed by potting or supplying a sheet material.
  • the material that constitutes the sealing portion 81 is not particularly limited, but may be, for example, silicone gel or epoxy resin.
  • the semiconductor device 100 may be a case-type module as shown in Figure 5, a transfer mold-type module, or some other type of module.
  • the circuit configuration of the semiconductor device 100 shown in Figures 1 and 2 is a so-called 1-in-1 type in which one semiconductor element 2 is mounted in one module.
  • the circuit configuration of the semiconductor device 100 may also be a 2-in-1 type in which two semiconductor elements 2 are mounted in one module, or a so-called 6-in-1 type in which six semiconductor elements 2 are mounted in one module.
  • FIG. 6 is a schematic plan view of modified example 3 of semiconductor device 100 according to embodiment 1.
  • FIG. 6 corresponds to FIG. 1.
  • FIG. 7 is a schematic front view of modified example 3 of semiconductor device 100 according to embodiment 1.
  • FIG. 7 corresponds to FIG. 2.
  • Semiconductor device 100 shown in FIGS. 6 and 7 basically has the same configuration as semiconductor device 100 shown in FIGS. 1 and 2 and can achieve the same effects, but differs in that the circuit configuration of semiconductor device 100 is a 2-in-1 type that forms a half bridge.
  • the upper metal layer 11 includes a first conductive portion 11a, a second conductive portion 11b, a third conductive portion 11c, a fourth conductive portion 11d, and a fifth conductive portion 11e.
  • the first conductive portion 11a, the second conductive portion 11b, the third conductive portion 11c, the fourth conductive portion 11d, and the fifth conductive portion 11e are arranged spaced apart from one another on the insulating plate 12.
  • the semiconductor element 2 includes a first semiconductor element 2a and a second semiconductor element 2b.
  • the first semiconductor element 2a is disposed on the first major surface 10a in the second conductive portion 11b.
  • the second semiconductor element 2b is disposed on the first major surface 10a in the third conductive portion 11c.
  • the wiring layer 3 includes a first wiring layer 3a on the upper arm side and a second wiring layer 3b on the lower arm side. One end of the first wiring layer 3a is connected to the surface main electrode 22a of the first semiconductor element 2a via a joint 52. The other end of the first wiring layer 3a is connected to the first main surface 10a of the third conductive portion 11c via a joint 53.
  • One end of the second wiring layer 3b is connected to the surface main electrode 22a of the second semiconductor element 2b via a joint 52.
  • the other end of the second wiring layer 3b is connected to the first main surface 10a of the fourth conductive portion 11d via a joint 53 (not shown).
  • the first wiring layer 3a extends from the second conductive portion 11b toward the third conductive portion 11c. As shown in FIG. 6, the extension direction of the first wiring layer 3a in a plan view of the first main surface 10a is the x direction. Furthermore, the stacking direction of the high thermal conductivity layer 32 and the high conductivity layer 31 in a plan view of the first main surface 10a is, for example, the y direction.
  • the second wiring layer 3b extends from the third conductive portion 11c toward the fourth conductive portion 11d.
  • the extension direction of the second wiring layer 3b in a planar view of the first major surface 10a is the y direction.
  • the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 in a planar view of the first major surface 10a is, for example, the x direction.
  • the extension direction (x direction) of the first wiring layer 3a is perpendicular to the extension direction (y direction) of the second wiring layer 3b. In other words, the stacking directions of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 in each of the first wiring layer 3a and the second wiring layer 3b are perpendicular to each other.
  • the first wiring layer 3a and the second wiring layer 3b may be arranged parallel to each other.
  • the first wiring layer 3a and the second wiring layer 3b may be arranged in a line.
  • the control electrode 23 of the first semiconductor element 2a is connected to the first major surface 10a of the first conductive portion 11a via the metal connection portion 6.
  • the control electrode 23 of the second semiconductor element 2b is connected to the first major surface 10a of the fifth conductive portion 11e via the metal connection portion 6.
  • the leads 4 include a first lead 41, a second lead 42, a third lead 43, a fourth lead 44, and a fifth lead 45.
  • the first lead 41 is connected to the first main surface 10a of the first conductive portion 11a.
  • the second lead 42 is connected to the first main surface 10a of the second conductive portion 11b.
  • the third lead 43 is connected to the first main surface 10a of the third conductive portion 11c.
  • the fourth lead 44 is connected to the first main surface 10a of the fourth conductive portion 11d.
  • the fifth lead 45 is connected to the first main surface 10a of the fifth conductive portion 11e.
  • the first lead 41 and fifth lead 45 extract signals to the outside.
  • the second lead 42 is connected to a terminal with P-type conductivity.
  • the third lead 43 is connected to an AC terminal.
  • the fourth lead 44 is connected to a terminal with N-type conductivity.
  • the fourth lead 44 and the second wiring layer 3b may be connected above the substrate 1 in the z direction.
  • a lead frame may be connected to the second wiring layer 3b.
  • the material constituting the lead frame may be, for example, copper, which has high conductivity.
  • An insulating layer may be sandwiched between the lead frame and the first wiring layer 3a.
  • the lead frame may be arranged so as to form a parallel plate with respect to the first wiring layer 3a. In this way, parasitic inductance in the semiconductor device 100 can be suppressed.
  • FIG. 8 is a schematic plan view of a fourth variant of the semiconductor device 100 according to the first embodiment.
  • FIG. 8 corresponds to FIG. 1.
  • the semiconductor device 100 shown in FIG. 8 basically has the same configuration as the semiconductor device 100 shown in FIGS. 1 and 2, and can achieve the same effects, but differs in that multiple semiconductor elements 2 are arranged on the first main surface 10a of the second conductive portion 11b.
  • the semiconductor element 2 includes a first semiconductor element 2a and a second semiconductor element 2b.
  • the first semiconductor element 2a and the second semiconductor element 2b are each arranged on the first main surface 10a of the second conductive portion 11b.
  • the second semiconductor element 2b is arranged spaced apart from the first semiconductor element 2a in the y direction.
  • the wiring layer 3 includes a first wiring layer 3a and a second wiring layer 3b. One end of the first wiring layer 3a is connected to the surface main electrode 22a of the first semiconductor element 2a via a joint 52 (not shown). The other end of the first wiring layer 3a is connected to the first main surface 10a of the third conductive portion 11c via a joint 53 (not shown).
  • One end of the second wiring layer 3b is connected to the surface main electrode 22a of the second semiconductor element 2b via a joint 52 (not shown).
  • the other end of the second wiring layer 3b is connected to the first main surface 10a of the third conductive portion 11c via a joint 53 (not shown).
  • the first wiring layer 3a and the second wiring layer 3b each extend from the second conductive portion 11b toward the third conductive portion 11c. As shown in FIG. 8, the extension direction of the first wiring layer 3a and the second wiring layer 3b in a plan view of the first main surface 10a is the x direction.
  • the first wiring layer 3a and the second wiring layer 3b are arranged parallel to each other.
  • the first wiring layer 3a and the second wiring layer 3b are arranged spaced apart from each other in the y direction.
  • control electrode 23 of each of the first semiconductor element 2a and the second semiconductor element 2b is connected to the first major surface 10a of the first conductive portion 11a via the metal connection portion 6.
  • multiple semiconductor elements 2 may be arranged on the substrate 1.
  • the number of semiconductor elements 2 may be two or more, or may be three or more.
  • a feature of the semiconductor device 100 according to the first embodiment is that, as shown in FIG. 1, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is perpendicular to the extension direction of the wiring layer 3 in a plan view of the first main surface 10a.
  • the extension direction of the wiring layer 3 is the x direction. Therefore, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is the y direction. If the extension direction of the wiring layer 3 is the y direction, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 may also be the x direction. In this way, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is horizontal to the first main surface 10a.
  • An example of a material that constitutes the high thermal conductivity layer 32 is graphite.
  • Graphite has a layered structure. Graphite is anisotropic. Specifically, the thermal conductivity of graphite is high in the in-plane directions in which the hexagonal rings are arranged (the x and z directions in the semiconductor device 100 according to the first embodiment). On the other hand, the thermal conductivity of graphite is low in directions perpendicular to the in-plane directions (the y direction in the semiconductor device 100 according to the first embodiment). In other words, the thermal conductivity of graphite in the in-plane directions is higher than the thermal conductivity in the directions perpendicular to the in-plane directions. Therefore, when heat generated in the semiconductor element 2 flows in a direction perpendicular to the in-plane direction of the high thermal conductivity layer 32, the thermal resistance of the wiring layer 3 increases.
  • the extension direction of the wiring layer 3 in a plan view of the first principal surface 10a is the x direction. Therefore, the direction in which heat flows in the wiring layer 3 is the x direction.
  • the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is the y direction. In other words, the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is perpendicular to the extension direction of the wiring layer 3 in a plan view of the first principal surface 10a. Because the high thermal conductivity layer 32 is arranged in this manner, the direction in which heat flows is along the in-plane direction of the graphite. In the high thermal conductivity layer 32, the thermal conductivity in the direction (x direction) perpendicular to the stacking direction (y direction) is greater than the thermal conductivity in the stacking direction (y direction). Therefore, the thermal resistance of the wiring layer 3 can be reduced.
  • the number of layers in the wiring layer 3, which is formed by alternately stacking high thermal conductivity layers 32 and high electrical conductivity layers 31, may be two or more.
  • the wiring layer 3 may be formed from one high thermal conductivity layer 32 and one high electrical conductivity layer 31.
  • the number of layers in the wiring layer 3 may be three or more.
  • the wiring layer 3 may be formed from two high thermal conductivity layers 32 and one high electrical conductivity layer 31.
  • One high electrical conductivity layer 31 may be sandwiched between two high thermal conductivity layers 32. Increasing the number of layers in this way helps to reduce bias in the temperature distribution and current density distribution within the wiring layer 3.
  • the number of layers in the wiring layer 3 may be 5 or 7. In this way, the number of layers in the wiring layer 3 may be an odd number. In this way, the wiring layer 3 is configured with mirror symmetry in the y direction. As a result, it is possible to suppress imbalances in the flow of current and heat in the y direction. Thermal stress occurs in the wiring layer 3 due to the difference in the linear expansion coefficients of the high thermal conductivity layer 32 and the high electrical conductivity layer 31. However, since the number of layers in the wiring layer 3 is an odd number, the wiring layer 3 is configured with mirror symmetry in the y direction. As a result, thermal stress occurring in the y direction is suppressed.
  • the conductivity of graphite is approximately 10 6 S/m. Therefore, the conductivity of graphite is lower than the conductivity of other conductors.
  • the conductivity of copper (Cu) is approximately 5 ⁇ 10 7 S/m. Therefore, the conductivity of copper is approximately 50 times higher than that of graphite. Therefore, when high thermal conductivity layer 32 is made of graphite and high conductivity layer 31 is made of copper, most of the current flowing in wiring layer 3 flows in high conductivity layer 31.
  • the thickness of a typical lead frame is approximately 0.64 mm. If the width w of the wiring layer 3 in the z direction is approximately the same as the thickness of a typical lead frame, the electrical resistance of the wiring layer 3 increases. As a result, the wiring layer 3 becomes a heat source.
  • the effective cross-sectional area of the high conductivity layer 31, as viewed in the direction in which the wiring layer 3 extends, may be equal to or greater than the cross-sectional area of a typical lead frame.
  • the width w of the wiring layer 3 in the direction (z direction) perpendicular to the extension direction (x direction) of the wiring layer 3 and the stacking direction (y direction) of the high thermal conductivity layer 32 and the high conductivity layer 31 may be 1.0 mm or more, 1.3 mm or more, or 2.0 mm or more. In this way, the cross-sectional area of the high conductivity layer 31 is reduced, suppressing electrical resistance.
  • each high conductivity layer 31 in the y direction may be 1.0 mm or less, or 0.64 mm or less. This reduces eddy current loss caused by the skin effect.
  • the thickness t of each high conductivity layer 31 in the y direction will be less than 0.1 mm. If the thickness t of each high conductivity layer 31 in the y direction is less than 0.1 mm, the wiring layer 3 will not be self-supporting. Therefore, the thickness t of each high conductivity layer 31 in the y direction may be 0.1 mm or more. In this way, the wiring layer 3 will be self-supporting.
  • the shape of the high thermal conductivity layer 32 may be the same as the shape of the high electrical conductivity layer 31.
  • the cross-sectional area of the wiring layer 3 as viewed from the x direction at any position in the x direction is maximized.
  • the electrical resistance and thermal resistance of the wiring layer 3 are suppressed.
  • Figure 9 is a schematic front view of Variation 5 of the semiconductor device 100 according to the first embodiment.
  • Figure 9 corresponds to Figure 2.
  • the semiconductor device 100 shown in Figure 9 basically has the same configuration as the semiconductor device 100 shown in Figures 1 and 2, and can achieve the same effects, but differs in that a metal coating layer 33 is provided on at least a portion of the surface of the wiring layer 3.
  • the wiring layer 3 is connected to the surface main electrode 22a via the joint 52.
  • the wiring layer 3 is also connected to the first main surface 10a of the third conductive portion 11c via the joint 53.
  • the compatibility between the joints 52, 53 and the surface of the wiring layer 3 is improved. As a result, thermal and electrical contact resistance is reduced at the interfaces between the joints 52, 53 and the wiring layer 3.
  • the metal coating layer 33 may be formed by plating.
  • the metal coating layer 33 may be, for example, a silver (Ag) plating layer, a copper (Cu) plating layer, a nickel (Ni) plating layer, or a tin (Sn) plating layer.
  • the metal coating layer 33 may be, for example, a plating layer with a multilayer structure in which different materials are stacked.
  • the material that makes up the metal coating layer 33 is not particularly limited, and may be a material other than those listed above.
  • the metal coating layer 33 does not have to be formed by plating; for example, it may be formed by physical vapor deposition or chemical vapor deposition.
  • the metal coating layer 33 only needs to be provided on at least the surface where the wiring layer 3 is connected to the joints 52 and 53, and may be formed on the entire surface of the wiring layer 3.
  • the wiring layer 3 can be manufactured using any method.
  • the high thermal conductivity layer 32 and the high electrical conductivity layer 31 may be joined via a brazing material.
  • the high thermal conductivity layer 32 and the high electrical conductivity layer 31 are joined by heating and pressurizing the brazing material.
  • the brazing material may be, for example, an active metal brazing material.
  • the high thermal conductivity layer 32 and the high electrical conductivity layer 31 may be joined using a bonding material.
  • the bonding material may be a non-metallic material such as resin.
  • the high thermal conductivity layer 32 and the high electrical conductivity layer 31 may also be joined directly.
  • the high thermal conductivity layer 32 may be formed using a chemical vapor deposition (CVD) method.
  • the wiring layer 3 may be manufactured by using the high electrical conductivity layer 31 as a base material and depositing the high thermal conductivity layer 32 on the surface of the high electrical conductivity layer 31.
  • the high thermal conductivity layer 32 and the high electrical conductivity layer 31 may each be shaped using punching, laser processing, or electrical discharge processing.
  • the shaped high thermal conductivity layers 32 and high electrical conductivity layers 31 are then alternately stacked to bond the high thermal conductivity layers 32 and high electrical conductivity layers 31.
  • high thermal conductivity layers 32 and high electrical conductivity layers 31 may be alternately stacked, and the high thermal conductivity layers 32 and high electrical conductivity layers 31 may then be bonded together, after which the stacked high thermal conductivity layers 32 and high electrical conductivity layers 31 may be shaped using punching, laser machining, or electrical discharge machining.
  • a wiring layer 3 manufactured in this way by bonding high thermal conductivity layers 32 and high electrical conductivity layers 31 and then shaping them has superior dimensional accuracy to a wiring layer 3 manufactured by bonding high thermal conductivity layers 32 and high electrical conductivity layers 31 after shaping them.
  • a semiconductor device 100 includes a substrate 1, a semiconductor element 2, and a wiring layer 3.
  • the substrate 1 has a first main surface 10a.
  • the semiconductor element 2 is disposed on the first main surface 10a.
  • An electrode 21 is provided on the semiconductor element 2.
  • the wiring layer 3 is connected to the electrode 21.
  • the wiring layer 3 includes a high thermal conductivity layer 32 and a high electrical conductivity layer 31.
  • the high electrical conductivity layer 31 is stacked on the high thermal conductivity layer 32.
  • the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31 is a direction (y direction) perpendicular to the extending direction (x direction) of the wiring layer 3 in a plan view of the first main surface 10a.
  • the direction of heat flow is along the in-plane direction of the high thermal conductivity layer 32.
  • the thermal conductivity in the direction perpendicular to the stacking direction (y direction) (x direction) is greater than the thermal conductivity in the stacking direction (y direction). Therefore, it is possible to obtain a wiring layer 3 that maintains high conductivity and has reduced thermal resistance.
  • the material constituting the high thermal conductivity layer 32 is graphite.
  • the thermal conductivity in the direction perpendicular to the stacking direction (y direction) is greater than the thermal conductivity in the stacking direction (y direction).
  • Graphite is anisotropic. Therefore, by arranging the graphite so that the direction of heat flow is the in-plane direction (x direction or z direction) where the thermal conductivity of the graphite is high, the thermal resistance of the wiring layer 3 can be reduced.
  • the material constituting the semiconductor element 2 includes gallium oxide.
  • Gallium oxide has low thermal conductivity, so when the material constituting the semiconductor element 2 contains gallium oxide (Ga 2 O 3 ), the effect of dissipating heat from the main electrode 22 located near the heat source is increased.
  • the wiring layer 3 is formed by alternately stacking high thermal conductivity layers 32 and high electrical conductivity layers 31, and the number of layers is three or more.
  • the number of stacked layers is odd.
  • the wiring layer 3 is configured to be mirror-symmetric in the y direction, which suppresses thermal stress occurring in the y direction, and as a result, suppresses warping occurring in the wiring layer 3.
  • the width w of the wiring layer 3 in the direction (z direction) perpendicular to the extension direction (x direction) and stacking direction (y direction) of the wiring layer 3 is 1.0 mm or more.
  • the thickness t of the high conductivity layer 31 in the stacking direction (y direction) is 0.1 mm or more and 1.0 mm or less.
  • the shape of the high thermal conductivity layer 32 when viewed in the stacking direction (y direction) is the same as the shape of the high electrical conductivity layer 31.
  • the cross-sectional area of the wiring layer 3 as viewed from the x direction at any position in the x direction is maximized.
  • the electrical resistance and thermal resistance of the wiring layer 3 are reduced.
  • a metal coating layer 33 is provided on at least a portion of the surface of the wiring layer 3.
  • Fig. 10 is a schematic front view of a semiconductor device 100 according to a second embodiment.
  • Fig. 10 corresponds to Fig. 2.
  • Fig. 11 is a partially enlarged schematic front view of region XI in Fig. 10.
  • the semiconductor device 100 shown in Figs. 10 and 11 basically has the same configuration as the semiconductor device 100 shown in Figs. 1 and 2 and can obtain the same effects, but differs in that the first region s1 and the third region s3 are inclined with respect to the first main surface 10a.
  • the electrical resistance and thermal resistance of the wiring layer 3 are inversely proportional to the cross-sectional area of the wiring layer 3. However, the electrical resistance and thermal resistance of the wiring layer 3 are proportional to the length of the wiring layer 3.
  • the length of the wiring layer 3 is the distance from the surface main electrode 22a to the first main surface 10a of the third conductive portion 11c along the direction in which the wiring layer 3 extends.
  • part of the side surface 34 extends at an angle relative to the first main surface 10a, thereby reducing the length of the wiring layer 3. As a result, the electrical resistance and thermal resistance of the wiring layer 3 are reduced.
  • the side surface 34 of the wiring layer 3 is positioned at a distance of at least 0.1 mm from the electric field intensity mitigation portion 24 so that the electric field formed by the wiring layer 3 does not affect the electric field intensity mitigation portion 24.
  • the width Le of the second region s2 in the x direction may be greater than the width We of the electric field intensity mitigation portion 24 in the x direction.
  • the shortest distance De1 from the first region s1 to the electric field intensity mitigation portion 24, the shortest distance De2 from the second region s2 to the electric field intensity mitigation portion 24, and the shortest distance De3 from the third region s3 to the electric field intensity mitigation portion 24 are each 0.1 mm or greater. In this way, the influence of the electric field formed by the wiring layer 3 on the electric field intensity mitigation portion 24 is suppressed.
  • FIG. 12 is a partially enlarged schematic front view of Variation 1 of the semiconductor device 100 according to Embodiment 2.
  • FIG. 12 corresponds to FIG. 11.
  • the semiconductor device 100 shown in FIG. 12 basically has the same configuration as the semiconductor device 100 shown in FIGS. 10 and 11, and can achieve the same effects, but differs in that the side surface 34 includes curved portions R1 and R2.
  • the first region s1 and the second region s2 are connected via the curved surface portion R1.
  • the second region s2 and the third region s3 are connected via the curved surface portion R2.
  • the shape of each of the curved surface portions R1 and R2 when viewed from the y direction may be curved or arc-shaped.
  • the width Le of the second region s2 in the x direction can be made the same as the width We of the electric field intensity mitigation portion 24 in the x direction.
  • the shape of each of the curved surface portions R1 and R2 may be any shape.
  • the semiconductor element 2 is provided with the electric field strength absorbing portion 24.
  • the wiring layer 3 is spaced apart from the electric field strength absorbing portion 24 by 0.1 mm or more.
  • Fig. 13 is a schematic plan view of a semiconductor device 100 according to a third embodiment.
  • Fig. 13 corresponds to Fig. 8.
  • Fig. 14 is a schematic cross-sectional view taken along line XIV-XIV in Fig. 13.
  • Fig. 15 is a schematic cross-sectional view of a wiring layer 3 and a conductive bridge member 7 in a semiconductor device 100 according to a third embodiment.
  • the semiconductor device 100 shown in Figs. 13 to 15 basically has the same configuration as the semiconductor device 100 shown in Fig. 8 and can achieve the same effects, but differs in that the wiring layer 3 includes a conductive bridge member 7.
  • the conductive bridge member 7 is arranged so as to be sandwiched between the first wiring layer 3a and the second wiring layer 3b in the y direction. As shown in FIG. 13, the conductive bridge member 7 connects the first wiring layer 3a and the second wiring layer 3b.
  • the conductive bridge member 7 is conductive.
  • the semiconductor device 100 has improved resistance to oscillation. As a result, using a wide bandgap semiconductor for the semiconductor element 2 enables the semiconductor device 100 to operate at high speeds.
  • the conductive bridge member 7 is positioned at a distance of 0.1 mm or more from the electric field intensity mitigation portion 24 so that the electric field formed by the conductive bridge member 7 does not affect the electric field intensity mitigation portion 24.
  • the shape of the conductive bridge member 7 when viewed from the y direction may be the same as the shape of the wiring layer 3. In this way, the thermal resistance in the wiring layer 3 can be suppressed.
  • At least one of the thickness Ty of the conductive bridge member 7 in the y direction (the stacking direction of the high thermal conductivity layer 32 and the high electrical conductivity layer 31) and the thickness Tz of the conductive bridge member 7 in the z direction may be 1.0 mm or less. This reduces eddy current loss, and as a result, the electrical resistance in the wiring layer 3 can be suppressed.
  • FIGS. 16 to 20 are schematic cross-sectional views of modified examples of the wiring layer 3 and conductive bridge member 7 in the semiconductor device 100 according to the third embodiment.
  • the cross-sectional shape of the conductive bridge member 7 as viewed from the x direction may be U-shaped.
  • a groove GR may be provided in the center of the conductive bridge member 7 in the y direction. The groove GR extends in the x direction.
  • the thicknesses Ty and Tz of the conductive bridge member 7 can be reduced. As a result, eddy current loss can be reduced. In other words, the electrical resistance in the wiring layer 3 can be suppressed.
  • the cross-sectional shape of the conductive bridge member 7 when viewed from the x direction may be O-shaped.
  • a hollow HL may be provided in the center of the conductive bridge member 7 in the z and y directions.
  • the hollow HL extends in the x direction.
  • the thicknesses Ty and Tz of the conductive bridge member 7 can be reduced. As a result, eddy current loss can be reduced. In other words, the electrical resistance in the wiring layer 3 can be suppressed.
  • multiple grooves GR may be provided in the conductive bridge member 7.
  • the multiple grooves GR extend in the x direction. In this way, the electrical resistance in the wiring layer 3 can be reduced.
  • the conductive bridge member 7 includes a high thermal conductivity bridge layer 71 and a high electrical conductivity bridge layer 72.
  • the high electrical conductivity bridge layer 72 is laminated on the high thermal conductivity bridge layer 71.
  • the high thermal conductivity bridge layers 71 and the high electrical conductivity bridge layers 72 are laminated alternately.
  • the stacking direction of the high thermal conductivity bridge layer 71 and the high electrical conductivity bridge layer 72 is the z direction, as shown in Figure 19.
  • the material constituting the high thermal conductivity bridge layer 71 may be the same as that of the high thermal conductivity layer 32, such as graphite.
  • the material constituting the high electrical conductivity bridge layer 72 may be the same as that of the high electrical conductivity layer 31, such as copper. In this way, the thermal resistance in the wiring layer 3 can be suppressed.
  • the conductive bridge member 7 includes a high conductivity bridge layer 72 and an insulating bridge layer 73.
  • the high conductivity bridge layer 72 is stacked on the insulating bridge layer 73.
  • the insulating bridge layers 73 and the high conductivity bridge layers 72 are stacked alternately.
  • the potential of the conductive bridge member 7 is uniform across the conductive bridge member 7 when viewed from the x direction.
  • the insulating bridge layer 73 does not need to have a high withstand voltage. Therefore, the material constituting the insulating bridge layer 73 may be, for example, polyimide.
  • a thin film may be used as the insulating bridge layer 73.
  • the area occupied by the high conductivity bridge layer 72 increases. In this way, the electrical resistance in the wiring layer 3 can be reduced.
  • the wiring layer 3 includes a first wiring layer 3 a, a second wiring layer 3 b, and a conductive bridge member 7.
  • the second wiring layer 3 b is disposed apart from the first wiring layer 3 a.
  • the conductive bridge member 7 connects the first wiring layer 3 a and the second wiring layer 3 b.
  • the semiconductor device 100 has improved resistance to oscillation.
  • the thickness Ty of the conductive bridge member 7 in the stacking direction (y direction) is 1.0 mm or less.
  • the conductive bridge member 7 includes a high thermal conductivity bridge layer 71 and a high electrical conductivity bridge layer 72.
  • the high electrical conductivity bridge layer 72 is stacked on the high thermal conductivity bridge layer 71.
  • the high thermal conductivity bridge layers 71 and the high electrical conductivity bridge layers 72 are stacked alternately.
  • the conductive bridge member 7 includes a high conductivity bridge layer 72 and an insulating bridge layer 73.
  • the insulating bridge layer 73 is stacked on the high conductivity bridge layer 72.
  • a thin film such as polyimide can be used as the insulating bridge layer 73.
  • the area occupied by the high conductivity bridge layer 72 in the cross section of the conductive bridge member 7 increases. In this way, the electrical resistance in the wiring layer 3 can be reduced.
  • Fig. 21 is a schematic plan view of a semiconductor device 100 according to a fourth embodiment.
  • Fig. 21 corresponds to Fig. 1.
  • Fig. 22 is a schematic front view of the semiconductor device 100 according to the fourth embodiment.
  • Fig. 22 corresponds to Fig. 2.
  • the semiconductor device 100 shown in Figs. 21 and 2 basically has the same configuration as the semiconductor device 100 shown in Figs. 1 and 2 and can obtain the same effects, but differs in that it includes a metal block portion 35.
  • the wiring layer 3 is connected to the surface main electrode 22a via the metal block portion 35.
  • the wiring layer 3 is connected to the first main surface 10a of the third conductive portion 11c via the metal block portion 35.
  • the wiring layer 3 may be connected to the metal block portion 35 via a joint 57.
  • the metal block portion 35 may be connected to the surface main electrode 22a via a joint 56.
  • the metal block portion 35 may be connected to the first main surface 10a of the third conductive portion 11c via a joint 58.
  • the material that makes up the metal block portion 35 may be a material with high electrical conductivity and high thermal conductivity, such as copper (Cu) or a copper alloy.
  • the material forming joints 56, 57, and 58 may be a material with high thermal conductivity.
  • the bonding material forming joints 56, 57, and 58 may be the same as the bonding material forming joints 51, 52, and 53. Joints 56, 57, and 58 may also be formed using solder.
  • the shape of the wiring layer 3 when viewed from the y direction can be made rectangular.
  • the yield in manufacturing the wiring layer 3 improves. As a result, the manufacturing cost of the wiring layer 3 can be reduced.
  • the semiconductor device 100 includes a metal block portion 35.
  • the wiring layer 3 is connected to the electrode 21 via the metal block portion 35.
  • the shape of the wiring layer 3 can be made rectangular.
  • the yield in manufacturing the wiring layer 3 improves.
  • the manufacturing cost of the wiring layer 3 can be reduced.
  • Embodiment 5 a description will be given of a power conversion device to which the semiconductor devices described in the above-mentioned Embodiments 1 to 4 are applied. Although the present disclosure is not limited to a specific power conversion device, the following will describe a case in which the present disclosure is applied to a three-phase inverter as Embodiment 5.
  • FIG. 23 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.
  • the power conversion system shown in FIG. 23 is composed of a power supply 400, a power conversion device 200, and a load 300.
  • the power supply 400 is a DC power supply and supplies DC power to the power conversion device 200.
  • the power supply 400 can be composed of various elements, such as a DC system, a solar cell, or a storage battery. It may also be composed of a rectifier circuit or an AC/DC converter connected to an AC system.
  • the power supply 400 may also be composed of a DC/DC converter that converts DC power output from a DC system into a specified power.
  • the power conversion device 200 is a three-phase inverter connected between the power source 400 and the load 300, converts the DC power supplied from the power source 400 into AC power, and supplies the AC power to the load 300. As shown in FIG. 23, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.
  • Load 300 is a three-phase electric motor driven by AC power supplied from power conversion device 200. Note that load 300 is not limited to a specific application and is an electric motor mounted on various electrical devices, such as a hybrid vehicle, electric vehicle, railcar, elevator, or air conditioning device.
  • the power conversion device 200 will be described in detail below.
  • the main conversion circuit 201 includes switching elements and freewheel diodes (neither of which is shown). When the switching elements switch, the DC power supplied from the power source 400 is converted into AC power and supplied to the load 300.
  • the main conversion circuit 201 in this embodiment is a two-level three-phase full-bridge circuit that can be configured from six switching elements and six freewheel diodes connected in anti-parallel to each switching element.
  • a semiconductor device 100 is configured as a semiconductor module 202 for at least one of the switching elements and freewheel diodes of the main conversion circuit 201.
  • Six switching elements are connected in series in pairs to form upper and lower arms, each of which constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit.
  • the output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.
  • the main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element.
  • the drive circuit may be built into the semiconductor module 202, or may be provided separately from the semiconductor module 202.
  • the drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from the control circuit 203 (described below), it outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off.
  • the drive signal When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or less than the threshold voltage of the switching element.
  • the control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300.
  • the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output.
  • the control circuit 203 then outputs a control command (control signal) to the drive circuit provided in the main conversion circuit 201 so that an on signal is output to the switching element that should be in the on state at each point in time, and an off signal is output to the switching element that should be in the off state.
  • the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element in accordance with this control signal.
  • the semiconductor device 100 is applied as a semiconductor module 202 to at least one of the switching elements and free wheel diodes of the main conversion circuit 201, thereby improving electrical insulation and improving the reliability of the power conversion device.
  • the free wheel diodes may be integral with the switching elements, or may be substituted by the body diodes of the switching elements.
  • the present disclosure is not limited to this and can be applied to various power conversion devices.
  • a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used, and when supplying power to a single-phase load, the present disclosure may also be applied to a single-phase inverter.
  • the present disclosure can also be applied to a DC/DC converter or AC/DC converter.
  • the power conversion device to which this disclosure is applied is not limited to cases in which the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can even be used as a power conditioner for a solar power generation system, a power storage system, etc.
  • Appendix 1 a substrate having a first major surface; a semiconductor element disposed on the first main surface and provided with an electrode; a wiring layer connected to the electrode, the wiring layer includes a high thermal conductivity layer and a high electrical conductivity layer stacked on the high thermal conductivity layer, a stacking direction of the high thermal conductivity layer and the high electrical conductivity layer is perpendicular to an extending direction of the wiring layer in a plan view of the first main surface.
  • Appendix 2 the material constituting the high thermal conductivity layer is graphite; 2.
  • the semiconductor device wherein the high thermal conductivity layer has a thermal conductivity in a direction perpendicular to the stacking direction that is greater than the thermal conductivity in the stacking direction.
  • (Appendix 3) 3.
  • (Appendix 4) 4.
  • (Appendix 5) 5.
  • a width of the wiring layer in a direction perpendicular to the extending direction and the stacking direction is 1.0 mm or more; 6.
  • (Appendix 7) 7.
  • (Appendix 8) 4.
  • the semiconductor element is provided with an electric field intensity mitigation portion, 9.
  • the wiring layer includes a first wiring layer, a second wiring layer spaced apart from the first wiring layer, and a conductive bridge member connecting the first wiring layer and the second wiring layer.
  • the conductive bridge member has a thickness of 1.0 mm or less in the stacking direction.
  • the conductive bridge member includes a high thermal conductivity bridge layer and a high electrical conductivity bridge layer laminated on the high thermal conductivity bridge layer; 12.
  • the conductive bridge member includes a high conductivity bridge layer and an insulating bridge layer stacked on the high conductivity bridge layer.
  • a metal block portion is provided.
  • the wiring layer is connected to the electrode via the metal block portion.
  • Appendix 15 a main conversion circuit including the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 14, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit.
  • Control electrode, 24. Electric field intensity mitigation portion 31. High conductivity layer, 32. High heat Conductivity layer, 33; metal coating layer, 34; side surface, 35; metal block portion, 41; first lead, 42; second lead, 43; third lead, 44; fourth lead, 45; fifth lead, 51, 52, 53, 54, 55, 56, 57, 58; joint portion, 71; high thermal conductivity bridge layer, 72; high electrical conductivity bridge layer, 73; insulating bridge layer, 81; sealing portion, 82 Case, 83 mounting portion, 100 semiconductor device, 200 power conversion device, 201 main conversion circuit, 202 semiconductor module, 203 control circuit, 300 load, 400 power supply, De1, De2, De3 shortest distance, GR groove, HL hollow, Le width, R1, R2 curved portion, s1 first region, s2 second region, s3 third region, w width, We width.

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Abstract

L'invention concerne un dispositif à semi-conducteur (100) comprenant un substrat (1), un élément semi-conducteur (2) et une couche de câblage (3). Le substrat (1) présente une première surface principale (10a). L'élément semi-conducteur (2) est disposé sur la première surface principale (10a). L'élément semi-conducteur (2) est doté d'une électrode (21). La couche de câblage (3) est connectée à l'électrode (21). La couche de câblage (3) comprend une couche à conductivité thermique élevée (32) et une couche à conductivité élevée (31). La couche à conductivité élevée (31) est stratifiée sur la couche à conductivité thermique élevée (32). Le sens de stratification de la couche à conductivité thermique élevée (32) et de la couche à conductivité élevée (31) est un sens perpendiculaire au sens d'extension de la couche de câblage (3) dans une vue en plan de la première surface principale (10a).
PCT/JP2024/037320 2024-07-04 2024-10-21 Dispositif à semi-conducteur et dispositif de conversion de puissance Pending WO2026009461A1 (fr)

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JP2024-108356 2024-07-04
JP2024108356 2024-07-04

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03197129A (ja) * 1989-11-16 1991-08-28 Le Carbone Lorraine 金属により機械的、電気的及び熱的に強化された可撓性黒鉛を含む多層材料とその製造方法
JP2006001232A (ja) * 2004-06-21 2006-01-05 Hitachi Metals Ltd 高熱伝導・低熱膨脹複合体およびその製造方法
JP2008124242A (ja) * 2006-11-13 2008-05-29 Matsushita Electric Ind Co Ltd 熱伝導基板とその製造方法及び回路モジュール
WO2016098890A1 (fr) * 2014-12-18 2016-06-23 株式会社カネカ Stratifiés de graphite, procédés de production de stratifiés de graphite, objet structurel de transport thermique, et objet de transport thermique en forme de tige
JP2019071399A (ja) * 2016-11-21 2019-05-09 ローム株式会社 パワーモジュールおよびその製造方法、グラファイトプレート、および電源装置

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Publication number Priority date Publication date Assignee Title
JPH03197129A (ja) * 1989-11-16 1991-08-28 Le Carbone Lorraine 金属により機械的、電気的及び熱的に強化された可撓性黒鉛を含む多層材料とその製造方法
JP2006001232A (ja) * 2004-06-21 2006-01-05 Hitachi Metals Ltd 高熱伝導・低熱膨脹複合体およびその製造方法
JP2008124242A (ja) * 2006-11-13 2008-05-29 Matsushita Electric Ind Co Ltd 熱伝導基板とその製造方法及び回路モジュール
WO2016098890A1 (fr) * 2014-12-18 2016-06-23 株式会社カネカ Stratifiés de graphite, procédés de production de stratifiés de graphite, objet structurel de transport thermique, et objet de transport thermique en forme de tige
JP2019071399A (ja) * 2016-11-21 2019-05-09 ローム株式会社 パワーモジュールおよびその製造方法、グラファイトプレート、および電源装置

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