WO2026033706A1 - Circuit additionneur linéaire - Google Patents

Circuit additionneur linéaire

Info

Publication number
WO2026033706A1
WO2026033706A1 PCT/JP2024/028362 JP2024028362W WO2026033706A1 WO 2026033706 A1 WO2026033706 A1 WO 2026033706A1 JP 2024028362 W JP2024028362 W JP 2024028362W WO 2026033706 A1 WO2026033706 A1 WO 2026033706A1
Authority
WO
WIPO (PCT)
Prior art keywords
collector
transistors
transistor
resistor
differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2024/028362
Other languages
English (en)
Japanese (ja)
Inventor
宗彦 長谷
照男 徐
斉 脇田
宏行 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
NTT Inc USA
Original Assignee
Nippon Telegraph and Telephone Corp
NTT Inc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, NTT Inc USA filed Critical Nippon Telegraph and Telephone Corp
Priority to PCT/JP2024/028362 priority Critical patent/WO2026033706A1/fr
Publication of WO2026033706A1 publication Critical patent/WO2026033706A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

Definitions

  • the present invention relates to a linear addition circuit capable of linearly adding multiple wideband analog signals.
  • Non-Patent Document 1 a multiplexer using resistors R100 to R102 as shown in Figure 14 has been known as a means for realizing a wideband analog signal addition function.
  • Non-Patent Document 1 When configuring a multiplexer with impedance Z0 , the values of resistors R100 to R102 are Z0 /3.
  • the multiplexer shown in Figure 14 has problems such as unavoidable attenuation of signal strength and difficulty in ensuring isolation between ports.
  • an adder circuit like the one shown in Figure 15 is also commonly known (Non-Patent Document 2).
  • This adder circuit consists of an operational amplifier A200 and resistors R200 to R202.
  • the adder circuit in Figure 15 is not suitable for achieving an addition function over an ultra-wide frequency range, such as several tens of GHz.
  • baseband signals used in current communications are differential signals. Therefore, for communications applications, it is preferable to achieve the addition function using a fully differential, wideband configuration.
  • the present invention has been made to solve the above problems, and aims to provide a fully differential linear addition circuit that can linearly add multiple wideband analog signals.
  • the linear addition circuit of the present invention comprises a plurality of unit cells arranged in parallel, each receiving a different differential input signal, and first and second collector resistors provided between a first power supply voltage and the plurality of unit cells.
  • Each unit cell comprises a differential pair consisting of a first transistor to the base of which a positive-phase input signal of the differential input signals is input and a second transistor to the base of which an inverted input signal of the differential input signals is input; emitter degeneration resistors connected to the emitters of the first and second transistors; and a current source provided between the emitters of the first and second transistors and the second power supply voltage.
  • the first collector resistor is connected to the collectors of the plurality of second transistors that output positive-phase output signals of the differential output signals
  • the second collector resistor is connected to the collectors of the plurality of first transistors that output inverted output signals of the differential output signals.
  • each port is separated via a transistor, ensuring sufficient isolation between ports. Furthermore, because the present invention has a fully differential configuration, it is possible to realize a circuit suitable for processing differential baseband signals commonly used in communications.
  • FIG. 1 is a circuit diagram showing the configuration of a linear addition circuit according to a first embodiment of the present invention.
  • 2A to 2C are diagrams showing examples of waveforms of a differential input signal and a differential output signal.
  • FIG. 3 is a circuit diagram showing the configuration of a linear addition circuit according to a second embodiment of the present invention.
  • FIG. 4 is a circuit diagram showing the configuration of a linear addition circuit according to a third embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing the configuration of a linear addition circuit according to a fourth embodiment of the present invention.
  • FIG. 6 is a circuit diagram showing the configuration of a linear addition circuit according to a fifth embodiment of the present invention.
  • FIG. 1 is a circuit diagram showing the configuration of a linear addition circuit according to a first embodiment of the present invention.
  • 2A to 2C are diagrams showing examples of waveforms of a differential input signal and a differential output signal.
  • FIG. 3 is a circuit diagram showing the configuration of a linear addition
  • FIG. 7 is a circuit diagram showing another configuration of a linear addition circuit according to the fifth embodiment of the present invention.
  • FIG. 8 is a circuit diagram showing another configuration of a linear addition circuit according to the fifth embodiment of the present invention.
  • FIG. 9 is a circuit diagram showing another configuration of a linear addition circuit according to the fifth embodiment of the present invention.
  • FIG. 10 is a circuit diagram showing the configuration of a linear addition circuit according to a sixth embodiment of the present invention.
  • FIG. 11 is a circuit diagram showing another configuration of a linear addition circuit according to the sixth embodiment of the present invention.
  • FIG. 12 is a circuit diagram showing another configuration of a linear addition circuit according to the sixth embodiment of the present invention.
  • FIG. 13 is a circuit diagram showing another configuration of a linear addition circuit according to the sixth embodiment of the present invention.
  • FIG. 14 is a circuit diagram showing the configuration of a multiplexer.
  • FIG. 15 is a circuit diagram showing the configuration of the adder circuit.
  • FIG. 1 is a circuit diagram showing the configuration of a linear addition circuit according to a first embodiment of the present invention.
  • the linear adder circuit includes a differential pair 1-1 consisting of a bipolar transistor Q1P having a base to which a positive-phase input signal V IN1 — P is input and a bipolar transistor Q1N having a base to which an inverted-phase input signal V IN1 — N is input, a differential pair 1-2 consisting of a bipolar transistor Q2P having a base to which a positive-phase input signal V IN2 — P is input and a bipolar transistor Q2N having a base to which an inverted-phase input signal V IN2 — N is input, emitter degeneration resistors R E1P and R E1N having one end connected to the emitters of the transistors Q1P and Q1N, emitter degeneration resistors R E2P and R E2N having one end connected to the emitters of the transistors Q2P and Q2N , a constant current source I
  • the differential pair 1-1, emitter degeneration resistors R E1P and R E1N , and constant current source I EE1 constitute unit cell 10-1.
  • the differential pair 1-2, emitter degeneration resistors R E2P and R E2N , and constant current source I EE2 constitute unit cell 10-2.
  • the linear addition circuit of this embodiment has two unit cells 10-1 and 10-2 arranged in parallel, and the collectors of the transistors that output signals of the same polarity in the two unit cells 10-1 and 10-2 are connected to the same collector resistor.
  • this embodiment is characterized in that the current value IEE of the constant current sources IEE1 and IEE2 and the resistance value RE of the emitter degeneration resistors RE1P , RE1N , RE2P , and RE2N are set so as to satisfy equations (1) and (2).
  • V IN1 _ max is the maximum value of the voltage levels of the differential input signals V IN1 _ P and V IN1 _ N
  • V IN1 _ min is the minimum value of the voltage levels of the differential input signals V IN1 _ P and V IN1 _ N
  • V IN2 _ max is the maximum value of the voltage levels of the differential input signals V IN2 _ P and V IN2 _ N
  • V IN2 _ min is the minimum value of the voltage levels of the differential input signals V IN2 _ P and V IN2 _ N.
  • Equation (1) represents the voltage amplitude of the differential input signals V IN1 _ P and V IN1 _ N
  • the right side of equation (2) represents the voltage amplitude of the differential input signals V IN2 _ P and V IN2 _ N.
  • the product of the current value IEE and the resistance value RE is set to be larger than the amplitude of the differential input signal.
  • V OUT _ min is the minimum value of the voltage levels of the differential output signals V OUT _ P and V OUT _ N.
  • equations (3) and (4) indicate that transistors Q1P, Q1N, Q2P, and Q2N operate with the base voltage level always lower than the collector voltage level. This feature minimizes the base-collector capacitance of transistors Q1P, Q1N, Q2P, and Q2N and also suppresses dynamic fluctuations in the base-collector capacitance, thereby achieving faster addition processing, wider bandwidth, and suppression of dynamic distortion.
  • FIG. 3 is a circuit diagram showing the configuration of a linear adder circuit according to a second embodiment of the present invention.
  • one constant current source IEE1 or IEE2 each with a current value of IEE
  • two constant current sources IEE1P , IEE1N , IEE2P , and IEE2N are provided for each differential pair.
  • Current source IEE1P is provided between the emitter of transistor Q1P and power supply voltage VEE
  • current source IEE1N is provided between the emitter of transistor Q1N and power supply voltage VEE
  • Current source IEE2P is provided between the emitter of transistor Q2P and power supply voltage VEE
  • current source IEE2N is provided between the emitter of transistor Q2N and power supply voltage VEE .
  • emitter degeneration resistors R E1P , R E1N , R E2P , and R E2N are arranged in series between the transistors and the constant current sources.
  • emitter degeneration resistors R E1 and R E2 each with a resistance of 2R E , are provided for each differential pair.
  • Emitter degeneration resistor R E1 is provided between the emitter of transistor Q1P and the emitter of transistor Q1N
  • emitter degeneration resistor R E2 is provided between the emitter of transistor Q2P and the emitter of transistor Q2N.
  • a bias voltage V CAS is applied to the bases of transistors Q-1P, Q-1N, Q-2P, and Q-2N.
  • the collectors of transistors Q-1P and Q-2P are connected to collector resistor R CN , and the collectors of transistors Q-1N and Q-2N are connected to collector resistor R CP .
  • the emitters of transistors Q-1P, Q-1N, Q-2P, and Q-2N are connected to the collectors of transistors Q1P, Q1N, Q2P, and Q2N.
  • the differential pair 1-1, emitter degeneration resistors R E1P and R E1N , constant current source I EE1 , and transistors Q-1P and Q-1N constitute a unit cell 10b-1.
  • the differential pair 1-2, emitter degeneration resistors R E2P and R E2N , constant current source I EE2 , and transistors Q-2P and Q-2N form a unit cell 10b-2.
  • Figure 7 shows a configuration in which the constant current sources IEE1P , IEE1N , IEE2P , and IEE2N of the circuit of the second embodiment are replaced with variable current sources IEE1PV , IEE1NV , IEE2PV , and IEE2NV .
  • VCS1P , VCS1N , VCS2P , and VCS2N are external control voltages for the variable current sources IEE1PV , IEE1NV , IEE2PV , and IEE2NV .
  • Figure 8 shows a configuration in which the constant current sources IEE1 and IEE2 of the circuit of the third embodiment are replaced with variable current sources IEE1V and IEE2V .
  • a configuration in which m (m is an integer of 3 or more) unit cells 10-1 to 10-m are connected in parallel is shown in Fig. 10.
  • the circuit in Fig. 10 is a circuit that adds m differential input signals V IN1 (V IN1 _ P , V IN1 _ N ), V IN2 (V IN2 _ P , V IN2 _ N ), ..., V INm (V INm _ P , V INm _ N ).
  • Figure 11 shows a configuration in which m unit cells 10a-1 to 10a-m are connected in parallel.
  • Figure 12 shows a configuration in which m unit cells 10b-1 to 10b-m are connected in parallel.
  • Figure 13 shows a configuration in which m unit cells 10c-1 to 10c-m are connected in parallel.
  • VINX_max is the maximum value of the voltage levels of the differential input signals VINX_P and VINX_N
  • VINX_min is the minimum value of the voltage levels of the differential input signals VINX_P and VINX_N (X is an integer from 1 to m ) .
  • formulas (5) and (6) can be generalized to yield formula (10).
  • V INX _ max ⁇ V CAS - V BEON ... (10)
  • the circuit constants can be set so that each unit cell satisfies equations (8) and (9).
  • the circuit constants can be set so that each unit cell satisfies equations (7) to (10).
  • the constant current sources IEE1 , IEE2 , IEE1P , IEE1N , IEE2P , and IEE2N may be replaced with variable current sources IEE1V , IEE2V , IEE1PV , IEE1NV , IEE2PV , and IEE2NV .
  • the linear addition circuit of the present invention comprises a plurality of unit cells arranged in parallel, each receiving a different differential input signal, and first and second collector resistors provided between a first power supply voltage and the plurality of unit cells.
  • Each unit cell comprises a differential pair consisting of a first transistor to the base of which a positive-phase input signal of the differential input signals is input, and a second transistor to the base of which an inverted-phase input signal of the differential input signals is input; emitter degeneration resistors connected to the emitters of the first and second transistors; and a current source provided between the emitters of the first and second transistors and the second power supply voltage.
  • the first collector resistor is connected to the collectors of the plurality of second transistors that output positive-phase output signals of the differential output signals
  • the second collector resistor is connected to the collectors of the plurality of first transistors that output inverted-phase output signals of the differential output signals.
  • each unit cell further includes third and fourth transistors arranged between the first and second collector resistors and the first and second transistors, and having bases to which a bias voltage is input; the third transistor has a collector connected to the second collector resistor and an emitter connected to the collector of the first transistor; and the fourth transistor has a collector connected to the first collector resistor and an emitter connected to the collector of the second transistor.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

Ce circuit additionneur linéaire comprend des cellules unitaires (10-1, 10-2) et des résistances de collecteur (RCP, RCN). Chaque cellule unitaire est formée d'une paire différentielle (1-1, 1-2) comprenant un premier transistor (Q1P, Q2P) et un deuxième transistor (Q1N, Q2N), une résistance de dégénération d'émetteur (RE1P, RE1N, RE2P, RE2N), et une source de courant (IEE1, IEE2). La résistance de collecteur (RCP) est connectée au collecteur du deuxième transistor (Q1N, Q2N) qui émet un signal de sortie de phase normale (VOUT_P), et la résistance de collecteur (RCN) est connectée au collecteur du premier transistor (Q1P, Q2P) qui émet un signal de sortie de phase inversée (VOUT_N).
PCT/JP2024/028362 2024-08-08 2024-08-08 Circuit additionneur linéaire Pending WO2026033706A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2024/028362 WO2026033706A1 (fr) 2024-08-08 2024-08-08 Circuit additionneur linéaire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2024/028362 WO2026033706A1 (fr) 2024-08-08 2024-08-08 Circuit additionneur linéaire

Publications (1)

Publication Number Publication Date
WO2026033706A1 true WO2026033706A1 (fr) 2026-02-12

Family

ID=98734798

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2024/028362 Pending WO2026033706A1 (fr) 2024-08-08 2024-08-08 Circuit additionneur linéaire

Country Status (1)

Country Link
WO (1) WO2026033706A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05252035A (ja) * 1992-03-05 1993-09-28 Mitsubishi Electric Corp 差動増幅器，比較器およびａ／ｄ変換器
JPH07176960A (ja) * 1993-12-20 1995-07-14 Nec Eng Ltd 帰還形増幅回路
JP2000156616A (ja) * 1998-11-19 2000-06-06 Sony Corp 多入力差動増幅回路
US20100295615A1 (en) * 2009-04-23 2010-11-25 Texas Instruments Deutschland Gmbh Cml output driver
JP2014099762A (ja) * 2012-11-14 2014-05-29 Fujitsu Ltd 増幅回路
JP2014103519A (ja) * 2012-11-19 2014-06-05 Fujitsu Ltd エンファシス信号生成回路
WO2014181869A1 (fr) * 2013-05-09 2014-11-13 日本電信電話株式会社 Circuit d'attaque de modulateur optique et émetteur optique

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05252035A (ja) * 1992-03-05 1993-09-28 Mitsubishi Electric Corp 差動増幅器，比較器およびａ／ｄ変換器
JPH07176960A (ja) * 1993-12-20 1995-07-14 Nec Eng Ltd 帰還形増幅回路
JP2000156616A (ja) * 1998-11-19 2000-06-06 Sony Corp 多入力差動増幅回路
US20100295615A1 (en) * 2009-04-23 2010-11-25 Texas Instruments Deutschland Gmbh Cml output driver
JP2014099762A (ja) * 2012-11-14 2014-05-29 Fujitsu Ltd 増幅回路
JP2014103519A (ja) * 2012-11-19 2014-06-05 Fujitsu Ltd エンファシス信号生成回路
WO2014181869A1 (fr) * 2013-05-09 2014-11-13 日本電信電話株式会社 Circuit d'attaque de modulateur optique et émetteur optique

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