WO2026038416A1 - Comparateur et dispositif d'imagerie - Google Patents

Comparateur et dispositif d'imagerie

Info

Publication number
WO2026038416A1
WO2026038416A1 PCT/JP2025/022344 JP2025022344W WO2026038416A1 WO 2026038416 A1 WO2026038416 A1 WO 2026038416A1 JP 2025022344 W JP2025022344 W JP 2025022344W WO 2026038416 A1 WO2026038416 A1 WO 2026038416A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
gate
comparator
switches
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2025/022344
Other languages
English (en)
Japanese (ja)
Inventor
俊夫 安江
崇 馬上
大輔 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Publication of WO2026038416A1 publication Critical patent/WO2026038416A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters

Definitions

  • This technology relates to a comparator and an imaging device. More specifically, this technology relates to a comparator and an imaging device capable of differential input.
  • a comparator is sometimes used to compare input signals.
  • a comparator that compares a pixel signal with a ramp wave in order to perform analog-to-digital (AD) conversion of the pixel signal has been disclosed (see, for example, Patent Document 1).
  • the power supply voltage of the comparator needs to be higher during the reset phase to balance the differential input compared to the comparison phase, which could lead to an increase in the power supply voltage.
  • This technology was developed in light of these circumstances, and aims to improve the flexibility of the voltage applied to the comparator during the reset phase to balance the differential input.
  • This technology has been developed to solve the above-mentioned problems, and its first aspect is a comparator including a first transistor to whose gate a first input is applied, a second transistor to whose gate a second input is applied, a third transistor connected in series with the first transistor, a fourth transistor connected in series with the second transistor and having its gate connected to the gate of the third transistor, a fifth transistor connected to the first transistor and the second transistor, a bias capacitor connected to the gate of the fifth transistor, and a first switching unit that switches the connection of the gates of the third transistor and the fourth transistor between a first bias voltage and the drain of the third transistor.
  • This has the effect of reducing the voltage drop of the third transistor and the fourth transistor by the threshold voltage of the third transistor and the fourth transistor based on the switching operation of the first switching unit.
  • a second switching unit may be provided that switches the connection between the gate of the fifth transistor and the drain of the first transistor or the second transistor. This brings about the effect that when the gate of the fifth transistor is disconnected from the drain of the first transistor or the second transistor, the gate voltage of the fifth transistor is set based on the bias voltage generated by the bias capacitor.
  • the first switching unit may include a first switch that switches the input of a first bias voltage to the gate of the third transistor, and a second switch that switches the connection between the gate and drain of the third transistor, and the second switching unit may include a third switch that switches the connection between the gate of the fifth transistor and the drain of the third transistor.
  • the second switching unit may further include a fourth switch that switches the connection between the gate of the fifth transistor and the drain of the fourth transistor. This provides the effect of setting the power supply voltage of the comparator to be equal in the reset phase and the comparison phase while realizing the reset operation and comparison operation of the comparator.
  • the first switch, the third switch, and the fourth switch in the reset phase, may be turned on and the second switch may be turned off, and in the comparison phase, the first switch, the third switch, and the fourth switch may be turned off and the second switch may be turned on.
  • the device may further include an offset capacitor connected in series to the bias capacitor, and a third switching unit that switches the connection between the offset capacitor and the bias capacitor. This has the effect of absorbing imbalances in the threshold voltages of the first transistor, second transistor, and fifth transistor based on the offset voltage generated by the offset capacitor.
  • the third switching unit may include a fifth switch that switches the input of a first offset voltage to the first terminal of the offset capacitance, a sixth switch that switches the input of a second offset voltage to the second terminal of the offset capacitance, a seventh switch that switches the connection between the offset capacitance and the bias capacitance, and an eighth switch that switches the connection between the first terminal of the offset capacitance and the drain of the first transistor or the second transistor.
  • the circuit may further include a first dummy transistor that operates as a dummy for the first transistor and generates the first offset voltage, and a second dummy transistor that operates as a dummy for the fifth transistor and generates the second offset voltage. This has the effect of accumulating charge in the offset capacitance so as to absorb any imbalance in the threshold voltages of the first transistor, second transistor, and fifth transistor.
  • the third switching unit may include a fifth switch that switches the input of a first offset voltage to the first terminal of the offset capacitance, a sixth switch that switches the input of a second offset voltage to the second terminal of the offset capacitance, a seventh switch that switches the connection between the offset capacitance and the bias capacitance, and a ninth switch that switches the connection between the first terminal of the offset capacitance and the drain of the fifth transistor. This allows charge to be accumulated in the offset capacitance without affecting the reset operation of the comparator.
  • the first offset voltage may be lower than the second offset voltage. This has the effect of storing charge in the offset capacitance so as to absorb any imbalance in the threshold voltages of the first, second, and fifth transistors without increasing the power supply voltage of the comparator.
  • the circuit may further include a mirror transistor that generates the first offset voltage based on current mirror operation, and a second dummy transistor that operates as a dummy for the fifth transistor and generates the second offset voltage. This has the effect of making the first offset voltage lower than the second offset voltage, while storing charge in the offset capacitance so as to absorb any imbalance in the threshold voltages of the first transistor, second transistor, and fifth transistor.
  • a first AZ (Auto Zero) switch connected between the gate and drain of the first transistor, and a second AZ switch connected between the gate and drain of the second transistor may be further provided. This brings about the effect of switching the connection between the gate and drain of each of the first transistor and the second transistor so as to absorb any imbalance in the differential input of the comparator.
  • the device may further include a first input capacitance connected in series to the gate of the first transistor and a second input capacitance connected in series to the gate of the second transistor. This has the effect of absorbing imbalances in the differential inputs of the comparator based on the charges stored in the first input capacitance and the second input capacitance.
  • a third input capacitor may be further provided connected in parallel to the first input capacitor with respect to the gate of the first transistor. This provides the effect of absorbing imbalances in the differential inputs of the comparator based on the charges accumulated in the first input capacitor, second input capacitor, and third input capacitor, while fixing the voltage applied to the second input capacitor.
  • a signal voltage may be input to the first input capacitance, a fixed voltage may be input to the second input capacitance, and a reference voltage may be input to the third input capacitance. This provides the effect of comparing the signal voltage with the reference voltage while applying a fixed voltage to one of the differential inputs of the comparator.
  • the circuit may further include a tenth transistor whose gate is connected to the drain of the second transistor, an eleventh transistor connected in series with the tenth transistor, and a fourth switching unit that switches the connection of the gate of the tenth transistor.
  • the fourth switching unit may further include a twelfth switch that switches the input of a second bias voltage to the gate of the tenth transistor, and a thirteenth switch that switches the connection between the drain of the second transistor and the gate of the tenth transistor. This provides the effect of amplifying the comparator output while setting the power supply voltage of the comparator equal in the reset phase and the comparison phase.
  • a second aspect of the present invention provides a pixel array unit in which pixels are arranged in a matrix in row and column directions, and a column ADC unit that performs AD (Analog to Digital) conversion on a column basis for pixel signals output from the pixels, the column ADC unit including a comparator that compares the pixel signals with a reference signal, the comparator including a first transistor having a gate to which a first input is applied, an imaging device including a second transistor having a gate to which a second input is applied, a third transistor connected in series with the first transistor, a fourth transistor connected in series with the second transistor and having a gate connected to the gate of the third transistor, a fifth transistor connected to the first transistor and the second transistor, a bias capacitor connected to the gate of the fifth transistor, and a first switching unit that switches the connection of the gates of the third transistor and the fourth transistor between a first bias voltage and the drain of the third transistor, whereby, based on the switching operation of the first switching unit, a pixel signal is AD converted while
  • the comparator may further include a second switching unit that switches the connection between the gate of the fifth transistor and the drain of the first transistor or the second transistor. This brings about the effect that, when the gate of the fifth transistor is disconnected from the drain of the first transistor or the second transistor, the gate voltage of the fifth transistor is set based on the bias voltage generated by the bias capacitor, while the pixel signal is AD converted.
  • the comparator may further include an offset capacitor connected in series to the bias capacitor, and a third switching unit that switches the connection between the offset capacitor and the bias capacitor. This provides the effect of AD-converting the pixel signal while absorbing imbalances in the threshold voltages of the first, second, and fifth transistors based on the offset voltage generated by the offset capacitor.
  • FIG. 2 is a circuit diagram illustrating a configuration example of a reset phase of the comparator according to the first embodiment.
  • FIG. 2 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to the first embodiment.
  • 5A and 5B are diagrams illustrating voltages applied to each transistor of the comparator in the reset phase and the comparison phase according to the first embodiment.
  • FIG. 10 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to a second embodiment.
  • FIG. 10 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to a second embodiment.
  • FIG. 11 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to a third embodiment.
  • FIG. 11 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to a third embodiment.
  • FIG. 13 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to a fourth embodiment.
  • FIG. 13 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to a fourth embodiment.
  • FIG. 13 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to a fifth embodiment.
  • FIG. 13 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to a fifth embodiment.
  • FIG. 13 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to a sixth embodiment.
  • FIG. 13 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to a sixth embodiment.
  • FIG. 13 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to a sixth embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to a seventh embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to a seventh embodiment.
  • FIG. 23 is a diagram illustrating a first example of voltages applied to each transistor of the comparator in the reset phase and the comparison phase according to the seventh embodiment.
  • FIG. 23 is a diagram illustrating a second example of voltages applied to each transistor of the comparator in the reset phase and the comparison phase according to the seventh embodiment.
  • FIG. 23 is a diagram illustrating a third example of voltages applied to each transistor of the comparator in the reset phase and the comparison phase according to the seventh embodiment.
  • FIG. 13 is a circuit diagram illustrating a configuration example of an offset circuit according to a seventh embodiment.
  • FIG. 19 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to an eighth embodiment.
  • FIG. 19 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to an eighth embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to a ninth embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to a ninth embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to a ninth embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to a ninth embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to an eleventh embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to an eleventh embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to a twelfth embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to a twelfth embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to a thirteenth embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to a thirteenth embodiment.
  • 23A and 23B are diagrams illustrating voltages applied to each transistor of the comparator in the reset phase and the comparison phase according to the thirteenth embodiment.
  • FIG. 13 is a circuit diagram illustrating a configuration example of an offset circuit according to a seventh embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a reset phase of a comparator according to a fourteenth embodiment.
  • FIG. 23 is a circuit diagram illustrating a configuration example of a comparison phase of a comparator according to a fourteenth embodiment.
  • FIG. 23 is a configuration example of a comparison phase of a comparator according to a fourteenth embodiment.
  • FIG. 23 is a block diagram illustrating an example of the configuration of an imaging apparatus according to a fifteenth embodiment.
  • FIG. 23 is a block diagram illustrating a configuration example of a solid-state imaging device according to a fifteenth embodiment.
  • FIG. 23 is a diagram illustrating an example of a circuit configuration of a pixel provided in a solid-state imaging device according to a fifteenth embodiment.
  • FIG. 23 is a block diagram showing an example of the configuration of each column of a solid-state imaging device according to a fifteenth embodiment.
  • 23 is a timing chart showing an example of waveforms at various parts during signal readout of a solid-state imaging device according to a fifteenth embodiment.
  • 1 is a block diagram illustrating a schematic configuration example of a vehicle control system.
  • FIG. 2 is an explanatory diagram showing an example of an installation position of an imaging unit.
  • First embodiment an example in which the connection of the gate of a load transistor can be switched between its drain and a bias voltage, and the connection of the gate of a current source transistor and the drains of both differential transistors can be switched
  • Second embodiment an example in which the connection of the gate of the load transistor can be switched between its drain and a bias voltage, and the connection of the gate of the current source transistor and the drains of both the differential transistors can be switched, the load transistor is configured as an NMOS transistor, and the differential transistor and the current source transistor are configured as PMOS transistors
  • Third embodiment (example in which the first input of the differential transistor is generated based on the parallel input of the signal voltage and the reference voltage, and the second input of the differential transistor is set to a fixed potential) 4.
  • Fourth embodiment (an example in which the connection of the gate of a load transistor can be switched between its drain and a bias voltage, and the connection of the gate of a current source transistor and one of the drains of a differential transistor can be switched) 5.
  • Fifth embodiment an example in which the connection of the gate of the load transistor can be switched between its drain and a bias voltage, and the connection of the gate of the current source transistor and the other drain of the differential transistor can be switched) 6.
  • connection of the gate of the load transistor can be switched between its drain and a bias voltage, the connection of the gate of the current source transistor and the drains of both differential transistors can be switched, and an amplifier is provided to amplify the comparator output
  • connection of the gate of a load transistor can be switched between its drain and a bias voltage, the connection of the gate of a current source transistor and one of the drains of a differential transistor can be switched, and an offset capacitance can be connected in series with the bias capacitance connected to the gate of the current source transistor.
  • Twelfth embodiment an example in which an offset capacitor can be connected in parallel to a bias capacitor connected to a gate of a current source transistor, an amplifier is provided to amplify the comparator output, a first input of a differential transistor is generated based on parallel inputs of a signal voltage and a reference voltage, and a second input of the differential transistor is set to a fixed potential.
  • Thirteenth embodiment an example in which the connection between the gate of a current source transistor and one of the sources of a differential transistor can be switched, and an offset capacitance can be connected in parallel to the bias capacitance connected to the gate of the current source transistor.
  • FIG. 1 is a circuit diagram showing an example of the configuration of the reset phase of a comparator according to a first embodiment.
  • comparator CM1 balances comparator inputs DV1 and DV2 based on auto-zero operation, and then outputs voltage VO according to the difference between comparator inputs DV1 and DV2.
  • Comparator CM1 comprises PMOS transistors T3 and T4, NMOS transistors T1, T2, and T5, AZ (Auto Zero) switches Z1 and Z2, bias capacitor CB, and switching units K1 and K2.
  • PMOS transistors T3 and T4 operate as load transistors
  • NMOS transistors T1 and T2 operate as differential transistors
  • NMOS transistor T5 can operate as a current source transistor.
  • PMOS transistor T3 and NMOS transistor T1 are connected in series.
  • PMOS transistor T4 and NMOS transistor T2 are connected in series.
  • the sources of PMOS transistors T3 and T4 are connected to the power supply voltage VDD, and the gates of PMOS transistors T3 and T4 are connected to each other.
  • the input signal VIN is input to the gate of NMOS transistor T1 via input capacitor C1.
  • the input signal VIP is input to the gate of NMOS transistor T2 via input capacitor C2.
  • the input signals VIN and VIP can generate a differential input.
  • AZ switch Z1 is connected between the gate and drain of NMOS transistor T1
  • AZ switch Z2 is connected between the gate and drain of NMOS transistor T2.
  • the sources of each NMOS transistor T1 and T2 are connected to ground potential via NMOS transistor T5.
  • Each AZ switch Z1 and Z2 is opened and closed based on the auto-zero signal AZ.
  • a bias capacitor CB is connected to the gate of the NMOS transistor T5.
  • the NMOS transistor T5 can operate as a constant current source based on the bias voltage generated by the bias capacitor CB.
  • the switching unit K1 switches the connection of the gates of PMOS transistors T3 and T4 between bias voltage VB1 and the drain of PMOS transistor T3.
  • the switching unit K1 includes switches W1 and W2.
  • Switch W1 switches the input of bias voltage VB1 to the gates of PMOS transistors T3 and T4.
  • Switch W2 switches the connection between the gate and drain of PMOS transistor T3.
  • the switching unit K2 switches the connection between the gate of NMOS transistor T5 and the drains of NMOS transistors T1 and T2.
  • the switching unit K2 includes switches W3 and W4.
  • the switch W3 switches the connection between the gate of NMOS transistor T5 and the drain of NMOS transistor T1.
  • the switch W4 switches the connection between the gate of NMOS transistor T5 and the drain of NMOS transistor T2.
  • Switching signal SN is input to switches W1, W3, and W4, and switching signal SP is input to switch W2.
  • Switching signal SN is the inverted version of switching signal SP.
  • the AZ switches Z1 and Z2 are turned on based on the auto-zero signal AZ. At this time, charge is accumulated in the input capacitors C1 and C2 based on the current flowing through the PMOS transistors T3 and T4, so that the comparator inputs DV1 and DV2 are balanced.
  • switches W1, W3, and W4 are turned on based on switching signal SN, and switch W2 is turned off based on switching signal SP.
  • a bias voltage VB1 is applied to the gates of PMOS transistors T3 and T4, causing current to flow through the PMOS transistors T3 and T4.
  • the voltage drop across the PMOS transistors T3 and T4 is equivalent to the source-drain voltage Vds1 of the PMOS transistors T3 and T4.
  • the voltage drop across the PMOS transistors T3 and T4 is equivalent to the gate-source voltage Vgs1 of the PMOS transistors T3 and T4.
  • the power supply voltage VDD can be reduced by the threshold voltage Vth1 of the PMOS transistors T3 and T4.
  • the gate potential of NMOS transistor T5 is equal to the drain potential of NMOS transistors T1 and T2. Therefore, the sum of the voltage drop across NMOS transistors T1 and T2 and the voltage drop across NMOS transistor T5 is equal to the gate-source voltage Vgs3 of NMOS transistor T5.
  • the voltage drop across NMOS transistors T1 and T2 is equal to the gate-source voltage Vgs2 of NMOS transistors T1 and T2.
  • the voltage drop across NMOS transistor T5 is equal to the source-drain voltage Vds3 of NMOS transistor T5. At this time, charge according to the drain potential of NMOS transistors T1 and T2 is accumulated in bias capacitance CB.
  • Figure 2 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the first embodiment.
  • comparator inputs DV1 and DV2 are compared by comparator CM1, and a voltage VO corresponding to the comparison result is output from comparator CM1.
  • AZ switches Z1 and Z2 are turned off based on the auto-zero signal AZ.
  • switches W1, W3, and W4 are turned off based on switching signal SN, and switch W2 is turned on based on switching signal SP.
  • the gates of PMOS transistors T3 and T4 are then connected to the drain of PMOS transistor T3, and current flows through PMOS transistors T3 and T4. At this time, the voltage drop across PMOS transistors T3 and T4 is equivalent to the gate-source voltage Vgs1 of PMOS transistors T3 and T4.
  • NMOS transistor T5 becomes equal to the bias potential generated by bias capacitance CB.
  • NMOS transistor T5 can operate in the saturation region based on the bias potential generated by bias capacitance CB.
  • the voltage drop across NMOS transistor T5 becomes equal to the source-drain voltage Vds3 of NMOS transistor T5.
  • the voltage drop across NMOS transistors T1 and T2 becomes equal to the source-drain voltage Vds2 of NMOS transistors T1 and T2.
  • the threshold voltage Vth2 of the NMOS transistors T1 and T2 in the comparison phase can be compensated for by the threshold voltage Vth1 of the PMOS transistors T3 and T4 in the reset phase, making it possible to equalize the power supply voltage VDD in the reset phase and comparison phase.
  • Figure 3 shows the voltages applied to each transistor of the comparator in the reset phase and comparison phase according to the first embodiment. Note that in the figure, “a” indicates the voltage applied to each transistor of comparator CM1 in the comparison phase, and “b” indicates the voltage applied to each transistor of comparator CM1 in the reset phase.
  • the power supply voltage VDD is allocated to the gate-source voltage Vgs1 of PMOS transistors T3 and T4, the source-drain voltage Vds2 of NMOS transistors T1 and T2, and the source-drain voltage Vds3 of NMOS transistor T5.
  • the power supply voltage VDD is allocated to the gate-source voltage Vgs1 of PMOS transistors T3 and T4 and the gate-source voltage Vgs3 of NMOS transistor T5.
  • Part of the gate-source voltage Vgs3 of NMOS transistor T5 is allocated to the gate-source voltage Vgs2 of NMOS transistors T1 and T2.
  • the reset phase can be operated based on the power supply voltage VDD reduced by the threshold voltage Vth1 of PMOS transistors T3 and T4, making it possible to lower the power supply voltage during the reset phase.
  • the PMOS transistors T3 and T4 operate as current sources based on the bias voltage VB1. This allows the voltage drop across the PMOS transistors T3 and T4 during the reset phase to be reduced by the threshold voltage Vth1, enabling a lower power supply voltage for the comparator CM1.
  • a bias capacitor CB is connected to the gate of NMOS transistor T5, and the charge that generates the bias voltage for NMOS transistor T5 is stored in bias capacitor CB during the reset phase. This allows NMOS transistor T5 to operate even when the gate of NMOS transistor T5 is disconnected from the drains of PMOS transistors T3 and T4 during the comparison phase, thereby realizing the comparison operation of comparator CM1.
  • PMOS transistors T3 and T4 are used as load transistors
  • NMOS transistors T1 and T2 are used as differential transistors
  • NMOS transistor T5 is used as a current source transistor.
  • NMOS transistors are used as load transistors
  • PMOS transistors are used as differential transistors and current source transistors.
  • FIG. 4 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the second embodiment
  • FIG. 5 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the second embodiment.
  • this comparator CM2 has NMOS transistors T3' and T4' and PMOS transistors T1', T2', and T5' instead of the PMOS transistors T3 and T4 and NMOS transistors T1, T2, and T5 of the first embodiment described above.
  • the rest of the configuration of the comparator CM2 of the second embodiment is the same as the configuration of the comparator CM1 of the first embodiment described above.
  • NMOS transistor T3' and PMOS transistor T1' are connected in series with each other.
  • NMOS transistor T4' and PMOS transistor T2' are connected in series with each other.
  • the sources of each NMOS transistor T3', T4' are connected to ground potential, and the gates of each NMOS transistor T3', T4' are connected to each other.
  • the input signal VIN is input to the gate of the PMOS transistor T1' via the input capacitor C1.
  • the input signal VIP is input to the gate of the PMOS transistor T2' via the input capacitor C2.
  • AZ switch Z1 is connected between the gate and drain of PMOS transistor T1', and AZ switch Z2 is connected between the gate and drain of PMOS transistor T2'.
  • the sources of each of PMOS transistors T1' and T2' are connected to the power supply voltage VDD via PMOS transistor T5'.
  • a bias capacitor CB is connected to the gate of the PMOS transistor T5'.
  • the PMOS transistor T5' can operate as a constant current source based on the bias voltage generated by the bias capacitor CB.
  • the switching unit K1 switches the connection of the gates of NMOS transistors T3' and T4' between the bias voltage VB1' and the drain of NMOS transistor T3'.
  • the switch W1 switches the input of the bias voltage VB1' to the gates of NMOS transistors T3' and T4'.
  • the switch W2 switches the connection between the gate and drain of NMOS transistor T3'.
  • Switching unit K2 switches the connection between the gate of PMOS transistor T5' and the drains of PMOS transistors T1' and T2'.
  • Switch W3 switches the connection between the gate of PMOS transistor T5' and the drain of PMOS transistor T1'.
  • Switch W4 switches the connection between the gate of PMOS transistor T5' and the drain of PMOS transistor T1'.
  • the operation of AZ switches Z1, Z2 and switches W1 to W4 is the same as the operation of AZ switches Z1, Z2 and switches W1 to W4 in the first embodiment described above.
  • NMOS transistors T3' and T4' are used as load transistors
  • PMOS transistors T1' and T2' are used as differential transistors
  • PMOS transistor T5' is used as a current source transistor. This makes it possible to lower the power supply voltage of comparator CM2 even when the polarity of the transistors used in comparator CM2 is changed.
  • the input signal VIN is input to the NMOS transistor T1 via the input capacitor C1
  • the input signal VIP is input to the NMOS transistor T2 via the input capacitor C2.
  • a signal voltage and a reference voltage are input in parallel to the NMOS transistor T1 via their respective input capacitors, and the input of the NMOS transistor T2 is set to a fixed potential via the input capacitor C2.
  • FIG. 6 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the third embodiment
  • FIG. 7 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the third embodiment.
  • this comparator CM3 is the same as the comparator CM1 of the first embodiment described above, with an input capacitor C3 added.
  • the rest of the configuration of the comparator CM3 of the third embodiment is the same as the configuration of the comparator CM1 of the first embodiment described above.
  • Input capacitor C3 is connected in parallel to input capacitor C1 with respect to the gate of NMOS transistor T1.
  • signal voltage VSI and reference voltage VRF are input in parallel to the gate of NMOS transistor T1 via input capacitors C1 and C3, respectively.
  • the reference voltage VRF may be a ramp wave.
  • the signal voltage VSI may be a pixel signal read out from the pixel.
  • input capacitor C2 is connected to a fixed potential. The fixed potential may be ground potential.
  • the operation of AZ switches Z1, Z2 and switches W1 to W4 is the same as the operation of AZ switches Z1, Z2 and switches W1 to W4 in the first embodiment described above.
  • the signal voltage VSI and reference voltage VRF are input in parallel to NMOS transistor T1 via input capacitors C1 and C3, respectively, and the input of NMOS transistor T2 is set to a fixed potential.
  • an input capacitor C3 is added to the comparator CM1 of the first embodiment described above, and the signal voltage VSI and reference voltage VRF are input in parallel to the gate of the NMOS transistor T1 via the input capacitors C1 and C3, respectively.
  • an input capacitor C3 may be added to the comparator CM2 of the second embodiment described above, and the signal voltage VSI and reference voltage VRF may be input in parallel to the gate of the PMOS transistor T1' via the input capacitors C1 and C3, respectively.
  • connection between the gate of the NMOS transistor T5 and the drain of each of the NMOS transistors T1 and T2 is switched between the reset phase and the comparison phase.
  • connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1 is switched between the reset phase and the comparison phase.
  • FIG. 8 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the fourth embodiment
  • FIG. 9 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the fourth embodiment.
  • this comparator CM4 has a switching unit K12 instead of the switching unit K2 of the first embodiment described above.
  • the rest of the configuration of the comparator CM4 of the fourth embodiment is the same as the configuration of the comparator CM1 of the first embodiment described above.
  • the switching unit K12 switches the connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1.
  • the switching unit K12 is the same as the switching unit K2 of the first embodiment described above, except that the switch W4 has been removed.
  • the rest of the configuration of the switching unit K12 of the fourth embodiment is the same as the configuration of the switching unit K2 of the first embodiment described above.
  • the operation of AZ switches Z1, Z2 and switches W1 to W3 is the same as the operation of AZ switches Z1, Z2 and switches W1 to W3 in the first embodiment described above.
  • connection between the gate of NMOS transistor T5 and the drain of NMOS transistor T1 is switched between the reset phase and the comparison phase. This allows for a lower power supply voltage for comparator CM4 while reducing the number of components compared to comparator CM1.
  • the switch W4 is removed from the comparator CM1 of the first embodiment described above.
  • the switch W4 may be removed from the comparator CM2 of the second embodiment described above.
  • the input capacitor C3 of the third embodiment described above may be added to the comparator CM1 of the first embodiment described above or the comparator CM2 of the second embodiment described above, and the signal voltage VSI and the reference voltage VRF may be input in parallel via the input capacitors C1 and C3, respectively.
  • connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1 is switched between the reset phase and the comparison phase.
  • connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2 is switched between the reset phase and the comparison phase.
  • FIG. 10 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the fifth embodiment
  • FIG. 11 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the fifth embodiment.
  • this comparator CM5 has a switching unit K22 instead of the switching unit K2 of the first embodiment described above.
  • the rest of the configuration of the comparator CM5 of the fifth embodiment is the same as the configuration of the comparator CM1 of the first embodiment described above.
  • the switching unit K22 switches the connection between the gate of NMOS transistor T5 and the drain of NMOS transistor T2.
  • the switching unit K22 is the same as the switching unit K2 of the first embodiment described above, except that switch W3 has been removed.
  • the other configuration of the switching unit K22 of the fifth embodiment is the same as the configuration of the switching unit K2 of the first embodiment described above.
  • the operation of the AZ switches Z1, Z2 and switches W1, W2, and W4 is the same as the operation of the AZ switches Z1, Z2 and switches W1, W2, and W4 in the first embodiment described above.
  • connection between the gate of NMOS transistor T5 and the drain of NMOS transistor T2 is switched between the reset phase and the comparison phase. This allows for a lower power supply voltage for comparator CM5 while reducing the number of components compared to comparator CM1.
  • the switch W3 is removed from the comparator CM1 of the first embodiment described above.
  • the switch W3 may be removed from the comparator CM2 of the second embodiment described above.
  • the input capacitor C3 of the third embodiment described above may be added to the comparator CM1 of the first embodiment described above or the comparator CM2 of the second embodiment described above, and the signal voltage VSI and the reference voltage VRF may be input in parallel via the input capacitors C1 and C3, respectively.
  • the PMOS transistors T3 and T4 are operated as current sources based on the bias voltage VB1, and the charge that generates the bias voltage for the NMOS transistor T5 is stored in the bias capacitor CB.
  • the PMOS transistors T3 and T4 are operated as current sources based on the bias voltage VB1, and the charge that generates the bias voltage for the NMOS transistor T5 is stored in the bias capacitor CB, and an amplifier that amplifies the comparator output is provided.
  • FIG. 12 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the sixth embodiment
  • FIG. 13 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the sixth embodiment.
  • comparator CM6 is the same as comparator CM1 of the first embodiment described above, with the addition of a PMOS transistor T10, an NMOS transistor T11, a switch W14, a switching unit K4, and a capacitor C4.
  • the rest of the configuration of comparator CM6 of the sixth embodiment is the same as the configuration of comparator CM1 of the first embodiment described above.
  • the PMOS transistor T10 and the NMOS transistor T11 are connected in series.
  • the source of the PMOS transistor T10 is connected to the power supply voltage VDD.
  • a switch W14 is connected between the gate and drain of the NMOS transistor T11.
  • a capacitor C4 is connected to the gate of the NMOS transistor T11.
  • a switching unit K4 is connected to the gate of the PMOS transistor T10, and an output voltage VO is output from the drain of the NMOS transistor T11.
  • the switching unit K4 switches the connection of the gate of the PMOS transistor T10 between the bias voltage VB3 and the drain of the PMOS transistor T4.
  • the switching unit K4 includes switches W12 and W13.
  • the switch W12 switches the input of the bias voltage VB3 to the gate of the PMOS transistor T10.
  • the switch W13 switches the connection between the gate of the PMOS transistor T10 and the drain of the PMOS transistor T4.
  • Switching signal SN is input to switches W12 and W14, and switching signal SP is input to switch W13.
  • the operation of the AZ switches Z1, Z2 and switches W1 to W4 is the same as the operation of the AZ switches Z1, Z2 and switches W1 to W4 in the first embodiment described above.
  • switches W12 and W14 are turned on based on switching signal SN, and switch W13 is turned off based on switching signal SP.
  • bias voltage VB3 is applied to the gate of PMOS transistor T10, causing current to flow through PMOS transistor T10.
  • the voltage drop across PMOS transistor T10 is equivalent to the source-drain voltage Vds4 of PMOS transistor T10.
  • the gate potential of NMOS transistor T11 is equal to the drain potential of NMOS transistor T11. At this time, a charge corresponding to the drain potential of NMOS transistor T11 is accumulated in capacitor C4.
  • comparator inputs DV1 and DV2 are compared by comparator CM6, and a voltage VO corresponding to the comparison result is amplified and output from comparator CM6.
  • switches W12 and W14 are turned off based on switching signal SN, and switch W13 is turned on based on switching signal SP.
  • the gate of PMOS transistor T10 is then connected to the drain of PMOS transistor T4, and voltage VO corresponding to the drain potential of PMOS transistor T4 is output from the drain of PMOS transistor T10.
  • NMOS transistor T11 becomes equal to the bias potential generated by capacitor C4.
  • NMOS transistor T11 can operate in the saturation region based on the bias potential generated by capacitor C4.
  • the comparator CM1 of the first embodiment described above is provided with an amplifier that amplifies and outputs the comparison result.
  • any of the comparators CM2 to CM5 of the second to fifth embodiments described above may be provided with an amplifier that amplifies and outputs the comparison result.
  • the PMOS transistors T3 and T4 are operated as current sources based on the bias voltage VB1, and the charge that generates the bias voltage for the NMOS transistor T5 is stored in the bias capacitor CB.
  • the PMOS transistors T3 and T4 are operated as current sources based on the bias voltage VB1, and the charge that generates the bias voltage for the NMOS transistor T5 can be stored in the bias capacitor CB, and an offset capacitor can be connected in series with the bias capacitor CB.
  • FIG. 14 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the seventh embodiment
  • FIG. 15 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the seventh embodiment.
  • this comparator CM7 has a switching unit K3 instead of the switching unit K2 of the first embodiment described above. Furthermore, this comparator CM7 has an offset capacitance CF added to the comparator CM1 of the first embodiment described above.
  • the rest of the configuration of the comparator CM7 of the seventh embodiment is the same as the configuration of the comparator CM1 of the first embodiment described above.
  • the offset capacitance CF applies an offset voltage between the gate of NMOS transistor T5 and the drain of NMOS transistor T1. At this time, the offset capacitance CF can be connected in series to the bias capacitance CB via the switching unit K3. The offset voltage generated by the offset capacitance CF can be given by the difference between the offset voltages VOF1 and VOF2.
  • the switching unit K3 switches the connection between the offset capacitance CF and the bias capacitance CB.
  • the switching unit K3 includes switches W5 to W8.
  • the switch W5 switches the input of the offset voltage VOF1 to the first terminal of the offset capacitance CF.
  • the switch W6 switches the input of the offset voltage VOF2 to the second terminal of the offset capacitance CF.
  • the switch W7 switches the connection between the first terminal of the offset capacitance CF and the drain of the NMOS transistor T1.
  • the switch W8 switches the connection between the offset capacitance CF and the bias capacitance CB.
  • Switches W5 and W6 receive a switching signal SP, while switches W7 and W8 receive a switching signal SN.
  • the operation of the AZ switches Z1, Z2 and switches W1, W2 is the same as the operation of the AZ switches Z1, Z2 and switches W1, W2 in the first embodiment described above.
  • switches W7 and W8 are turned on based on switching signal SN, and switches W5 and W6 are turned off based on switching signal SP.
  • offset capacitance CF is connected between the gate of NMOS transistor T5 and the drain of NMOS transistor T1, and the difference between offset voltages VOF1 and VOF2 is applied.
  • the difference between offset voltages VOF1 and VOF2 is adjusted so that the drain-source voltage Vds3 of NMOS transistor T5 becomes the minimum drain-source voltage.
  • the imbalance in the threshold voltages of NMOS transistors T1, T2, and T5 can be absorbed based on the offset voltage generated by offset capacitance CFd.
  • the power supply voltage VDD can be reduced to a minimum regardless of the balance in the threshold voltages of each NMOS transistor T1, T2, and T5, thereby reducing power consumption.
  • switches W5 and W6 turn off, disconnecting offset capacitance CF from offset voltages VOF1 and VOF2, preventing a decrease in the accuracy of auto-zero operation caused by the source of offset voltages VOF1 and VOF2.
  • switches W7 and W8 are turned off based on switching signal SN, and switches W5 and W6 are turned on based on switching signal SP.
  • offset voltages VOF1 and VOF2 are applied to offset capacitance CF with offset capacitance CF disconnected from the gate of NMOS transistor T5 and the drain of NMOS transistor T1.
  • offset voltages VOF1 and VOF2 are applied to both terminals of offset capacitance CF, and a charge corresponding to the difference between offset voltages VOF1 and VOF2 is accumulated in offset capacitance CF.
  • Figure 16 is a diagram showing a first example of the voltages applied to each transistor of the comparator in the reset phase and comparison phase according to the seventh embodiment. Note that in the figure, “a” indicates the voltage applied to each transistor of comparator CM7 in the reset phase, and “b” indicates the voltage applied to each transistor of comparator CM7 in the comparison phase.
  • the drain-source voltage of NMOS transistor T5 is adjusted to a minimum value, Vds3, based on the offset voltage Vof applied to offset capacitance CF, and the drain-source voltage Vds3 of NMOS transistor T5 is set to a minimum value, Vds3min.
  • the drain voltages of NMOS transistors T1 and T2 are optimized by connecting an offset capacitor CF between the gate of NMOS transistor T5 and the drain of NMOS transistor T1 and applying an offset voltage Vof.
  • This optimal voltage is the voltage from which the minimum drain-source voltage Vds3min of NMOS transistor T5 is obtained by subtracting the gate-source voltage Vgs2 of NMOS transistors T1 and T2.
  • the drain-source voltage Vds3 of NMOS transistor T5 can be given by the sum of the minimum drain-source voltage Vds3min and the threshold voltage Vth3 of NMOS transistor T5.
  • NMOS transistor T5 For example, suppose the gate-source voltage Vgs3 and threshold voltage Vth3 of NMOS transistor T5 are too large relative to the gate-source voltage Vgs2 of each NMOS transistor T1, T2. In this case, by adding a negative offset voltage Vof such that VOF1 ⁇ VOF2, the drain-source voltage Vds3 of NMOS transistor T5 can be lowered, eliminating the excess and achieving the minimum drain-source voltage Vds3min. On the other hand, suppose the gate-source voltage Vgs3 and threshold voltage Vth3 of NMOS transistor T5 are too small relative to the gate-source voltage Vgs2 of each NMOS transistor T1, T2.
  • the drain-source voltage Vds3 of NMOS transistor T5 can be raised, eliminating the deficiency and achieving the minimum drain-source voltage Vds3min.
  • the offset capacitance CF is disconnected from the drains of NMOS transistors T1 and T2 and the gate of NMOS transistor T5. At this time, the voltage drop across NMOS transistor T5 is equivalent to the source-drain voltage Vds3 of NMOS transistor T5, allowing it to operate in the saturation region.
  • Figure 17 is a diagram showing a second example of the voltages applied to each transistor of the comparator in the reset phase and comparison phase according to the seventh embodiment. Note that in the figure, “a” indicates the voltage applied to each transistor of comparator CM7 in the reset phase, and “b” indicates the voltage applied to each transistor of comparator CM7 in the comparison phase.
  • the dynamic range (maximum allowable amplitude) of the input signal can be expanded while leaving the power supply voltage VDD unchanged.
  • a typical comparison circuit determines the operating point closer to the power supply during the reset phase, and the input signal has a dynamic range in the downward direction from that point.
  • This dynamic range DLI is in the same direction as a typical comparison circuit.
  • single-slope AD conversion used in CMOS image sensors requires a dynamic range in the downward direction of the signal. For this reason, a method of providing a dynamic range DLI based on the offset voltage Vof can be effectively applied to single-slope AD conversion.
  • Figure 18 is a diagram showing a third example of the voltages applied to each transistor of the comparator in the reset phase and comparison phase according to the seventh embodiment. Note that in the figure, “a” indicates the voltage applied to each transistor of comparator CM7 in the reset phase, and “b” indicates the voltage applied to each transistor of comparator CM7 in the comparison phase.
  • the balance between the falling and rising dynamic ranges DLI and DHI can be freely changed depending on the application based on the offset voltage Vof of the offset capacitance CF.
  • FIG. 19 is a circuit diagram showing an example configuration of an offset circuit according to the seventh embodiment.
  • offset circuit OF1 generates offset voltages VOF1 and VOF2. At this time, offset circuit OF1 is able to generate offset voltages VOF1 and VOF2 based on the dummy operation of NMOS transistors T1, T2, and T5.
  • Offset circuit OF1 includes an operational amplifier OP, PMOS transistors T21 to T23, NMOS transistors T24 to T26, and resistors R1 and R2. Note that PMOS transistors T21 to T23 are an example of mirror transistors as defined in the claims. NMOS transistors T25 and T26 are an example of dummy transistors as defined in the claims.
  • PMOS transistor T21 and NMOS transistor T24 are connected in series.
  • PMOS transistor T22 and NMOS transistor T25 are connected in series.
  • PMOS transistor T23 and NMOS transistor T26 are connected in series.
  • the source of each of PMOS transistors T21 to T23 is connected to the power supply voltage VDD.
  • the source of NMOS transistor T24 is connected to ground potential via resistor R1.
  • the source of NMOS transistor T25 is connected to ground potential.
  • the source of NMOS transistor T26 is connected to ground potential via resistor R2.
  • the gate of PMOS transistor T21 is connected to the drain.
  • the gate of NMOS transistor T25 is connected to the drain.
  • the gate of NMOS transistor T26 is connected to the drain.
  • a bias voltage VB11 is applied to the gates of PMOS transistors T21 to T23.
  • the gate of NMOS transistor T24 is connected to the output of operational amplifier OP.
  • An offset voltage VOF2 is output from the drain of NMOS transistor T25.
  • An offset voltage VOF1 is output from the drain of NMOS transistor T26.
  • a reference voltage VST is applied to the non-inverting input of operational amplifier OP.
  • the inverting input of operational amplifier OP is connected to the source of NMOS transistor T24.
  • NMOS transistor T25 can operate as a dummy for NMOS transistor T5.
  • the same type of transistor as NMOS transistor T5 can be used for NMOS transistor T25.
  • NMOS transistor T26 can operate as a dummy for NMOS transistor T1.
  • the same type of transistor as NMOS transistor T1 can be used for NMOS transistor T26.
  • the source potential of NMOS transistor T24 is compared with the reference voltage VST, and current flows through NMOS transistor T24 so that the source potential of NMOS transistor T24 matches the reference voltage VST.
  • the current flowing through NMOS transistor T24 is copied and flows through each of NMOS transistors T25 and T26.
  • the voltage generated across resistor R2 determines the drain-source voltage of NMOS transistor T5. Any imbalance in the threshold voltages of NMOS transistors T25 and T26 is reflected in offset voltages VOF1 and VOF2.
  • the PMOS transistors T3 and T4 operate as current sources based on the bias voltage VB1, allowing the charge that generates the bias voltage for the NMOS transistor T5 to be stored in the bias capacitor CB, and the offset capacitor CF to be connected in series with the bias capacitor CB.
  • This makes it possible to absorb imbalances in the threshold voltages of the NMOS transistors T1, T2, and T5 based on the offset voltage generated by the offset capacitor CF.
  • the offset capacitance CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1 during the reset phase. In the eighth embodiment, the offset capacitance CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2 during the reset phase.
  • FIG. 20 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the eighth embodiment
  • FIG. 21 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the eighth embodiment.
  • this comparator CM8 has a switching unit K3' instead of the switching unit K3 of the seventh embodiment described above.
  • the rest of the configuration of the comparator CM8 of the eighth embodiment is the same as the configuration of the comparator CM7 of the seventh embodiment described above.
  • the switching unit K3' switches the connection between the gate of NMOS transistor T5 and the drain of NMOS transistor T2.
  • the switching unit K3' includes a switch W7' instead of the switch W7 of the seventh embodiment described above.
  • the switch W7' switches the connection between the first terminal of the offset capacitance CF and the drain of NMOS transistor T2.
  • the rest of the configuration of the switching unit K3' of the eighth embodiment is the same as the configuration of the switching unit K3 of the seventh embodiment described above.
  • AZ switches Z1 and Z2 and switches W1, W2, W5, W6, W7', and W8 is the same as the operation of AZ switches Z1 and Z2 and switches W1, W2, W5 to W8 in the seventh embodiment described above.
  • an offset capacitance CF is connected between the gate of NMOS transistor T5 and the drain of NMOS transistor T2. This makes it possible to absorb imbalances in the threshold voltages of the NMOS transistors T1, T2, and T5 based on the offset voltage generated by the offset capacitance CF.
  • an offset capacitance CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1, and PMOS transistors T3 and T4 are used as load transistors, NMOS transistors T1 and T2 are used as differential transistors, and NMOS transistor T5 is used as a current source transistor.
  • NMOS transistors T3' and T4' are used as load transistors, and PMOS transistors T1', T2', and T5' are used as differential transistors and current source transistors.
  • FIG. 22 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the ninth embodiment
  • FIG. 23 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the ninth embodiment.
  • this comparator CM9 has NMOS transistors T3', T4' and PMOS transistors T1', T2', T5' of the second embodiment described above, instead of the PMOS transistors T3, T4 and NMOS transistors T1, T2, T5 of the seventh embodiment described above.
  • the rest of the configuration of the comparator CM9 of the ninth embodiment is the same as the configuration of the comparator CM7 of the seventh embodiment described above.
  • the switching unit K3 switches the connection between the offset capacitance CF and the bias capacitance CB.
  • the switch W7 switches the connection between the first terminal of the offset capacitance CF and the drain of the PMOS transistor T1'.
  • the operation of the AZ switches Z1, Z2 and switches W1, W2, W5 to W8 is the same as the operation of the AZ switches Z1, Z2 and switches W1, W2, W5 to W8 in the seventh embodiment described above.
  • the NMOS transistors T3' and T4' operate as current sources based on the bias voltage VB1, allowing the charge that generates the bias voltage for the PMOS transistor T5' to be stored in the bias capacitor CB, and the offset capacitor CF to be connected in series with the bias capacitor CB.
  • the imbalance in the threshold voltages of the PMOS transistors T1', T2', and T5' can be absorbed based on the offset voltage generated by the offset capacitor CF.
  • an offset capacitance CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2, PMOS transistors T3 and T4 are used as load transistors, NMOS transistors T1 and T2 are used as differential transistors, and NMOS transistor T5 is used as a current source transistor.
  • an offset capacitance CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2, NMOS transistors T3' and T4' are used as load transistors, and PMOS transistors T1', T2', and T5' are used as differential transistors and current source transistors.
  • FIG. 24 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the tenth embodiment
  • FIG. 25 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the tenth embodiment.
  • this comparator CM10 has NMOS transistors T3' and T4' and PMOS transistors T1', T2', and T5' instead of the PMOS transistors T3 and T4 and NMOS transistors T1, T2, and T5 of the eighth embodiment described above.
  • the rest of the configuration of the comparator CM10 of the tenth embodiment is the same as the configuration of the comparator CM8 of the eighth embodiment described above.
  • the switching unit K3' switches the connection between the offset capacitance CF and the bias capacitance CB.
  • the switch W7' switches the connection between the first terminal of the offset capacitance CF and the drain of the PMOS transistor T2'.
  • the operation of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W7', and W8 is the same as the operation of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W7', and W8 in the eighth embodiment described above.
  • an offset capacitance CF is connected between the gate of PMOS transistor T5' and the drain of PMOS transistor T2', NMOS transistors T3' and T4' are used as load transistors, and PMOS transistors T1', T2', and T5' are used as differential and current source transistors.
  • the NMOS transistors T3′ and T4′ are operated as current sources based on the bias voltage VB1, so that the charge that generates the bias voltage for the PMOS transistor T5′ can be stored in the bias capacitance CB, and the offset capacitance CF can be connected in series with the bias capacitance CB.
  • the NMOS transistors T3′ and T4′ are operated as current sources based on the bias voltage VB1, so that the charge that generates the bias voltage for the PMOS transistor T5′ can be stored in the bias capacitance CB, and the offset capacitance CF can be connected in series with the bias capacitance CB, and an amplifier is provided to amplify the comparator output.
  • FIG. 26 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the 11th embodiment
  • FIG. 27 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the 11th embodiment.
  • comparator CM11 is configured by adding an NMOS transistor T10', a PMOS transistor T11', a switch W14', a switching unit K4', and a capacitor C4' to comparator CM10 of the tenth embodiment described above.
  • the rest of the configuration of comparator CM11 of the eleventh embodiment is the same as the configuration of comparator CM10 of the tenth embodiment described above.
  • the NMOS transistor T10' and the PMOS transistor T11' are connected in series.
  • the source of the PMOS transistor T11' is connected to the power supply voltage VDD.
  • a switch W14' is connected between the gate and drain of the PMOS transistor T11'.
  • a capacitor C4' is connected to the gate of the PMOS transistor T11'.
  • a switching unit K4' is connected to the gate of the NMOS transistor T10', and an output voltage VO is output from the drain of the PMOS transistor T11'.
  • the switching unit K4' switches the connection of the gate of the NMOS transistor T10' between the bias voltage VB3' and the drain of the NMOS transistor T4'.
  • the switching unit K4' includes switches W12' and W13'.
  • the switch W12' switches the input of the bias voltage VB3' to the gate of the NMOS transistor T10'.
  • the switch W13' switches the connection between the gate of the NMOS transistor T10' and the drain of the NMOS transistor T4'.
  • Switching signal SN is input to switches W12' and W14', and switching signal SP is input to switch W13'.
  • the operation of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W7', and W8 is the same as the operation of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W7', and W8 in the tenth embodiment described above.
  • switches W12' and W14' are turned on based on switching signal SN, and switch W13' is turned off based on switching signal SP.
  • bias voltage VB3 is applied to the gate of NMOS transistor T10', causing current to flow through NMOS transistor T10'.
  • the voltage drop across NMOS transistor T10' is equivalent to source-drain voltage Vds5 of NMOS transistor T10'.
  • the gate potential of PMOS transistor T11' becomes equal to the drain potential of PMOS transistor T11'. At this time, a charge corresponding to the drain potential of PMOS transistor T11' is stored in capacitor C4'.
  • comparator inputs DV1 and DV2 are compared by comparator CM11, and a voltage VO corresponding to the comparison result is amplified and output from comparator CM11.
  • switches W12' and W14' are turned off based on switching signal SN, and switch W13' is turned on based on switching signal SP.
  • the gate of NMOS transistor T10' is then connected to the drain of NMOS transistor T4', and voltage VO corresponding to the drain potential of NMOS transistor T4' is output from the drain of NMOS transistor T10'.
  • PMOS transistor T11' becomes equal to the bias potential generated by capacitor C4'.
  • PMOS transistor T11' can operate in the saturation region based on the bias potential generated by capacitor C4'.
  • the NMOS transistors T3' and T4' are operated as current sources based on the bias voltage VB1, allowing the charge that generates the bias voltage for the PMOS transistor T5' to be stored in the bias capacitor CB, and an offset capacitor CF can be connected in series with the bias capacitor CB, and an amplifier is provided that amplifies the comparator output.
  • This makes it possible to absorb imbalances in the threshold voltages of the PMOS transistors T1', T2', and T5' based on the offset voltage generated by the offset capacitor CF, while amplifying and outputting the comparison result of the comparator CM11.
  • the comparator CM10 of the tenth embodiment described above is provided with an amplifier that amplifies and outputs the comparison result.
  • any of the comparators CM7 to CM9 of the seventh to ninth embodiments described above may be provided with an amplifier that amplifies and outputs the comparison result.
  • the input signal VIN is input to the PMOS transistor T1' via the input capacitance C1
  • the input signal VIP is input to the PMOS transistor T2' via the input capacitance C2.
  • the signal voltage VSI and the reference voltage VRF are input in parallel to the PMOS transistor T1' via their respective input capacitances, and the input of the PMOS transistor T2' is set to a fixed potential via the input capacitance C2.
  • FIG. 28 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the twelfth embodiment
  • FIG. 29 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the twelfth embodiment.
  • this comparator CM12 has an input capacitance C1' instead of the input capacitance C1 of the eleventh embodiment described above. Furthermore, this comparator CM12 has input capacitance C3' and capacitance C5 added to the comparator CM10 of the eleventh embodiment described above. The rest of the configuration of the comparator CM12 of the twelfth embodiment is the same as the configuration of the comparator CM11 of the eleventh embodiment described above.
  • the input capacitance C1' can be a variable capacitance.
  • the other configuration of the input capacitance C1' in the 12th embodiment is the same as the configuration of the input capacitance C1 in the 11th embodiment described above.
  • a variable capacitor can be used for input capacitor C3'.
  • Input capacitor C3' is connected in parallel to input capacitor C1' with respect to the gate of PMOS transistor T1'.
  • signal voltage VSI and reference voltage VRF are input in parallel to the gate of PMOS transistor T1' via input capacitors C1' and C3', respectively.
  • the capacitance values of each input capacitor C1' and C3' can be set to achieve a balance between signal voltage VSI and reference voltage VRF.
  • Capacitor C5 is connected in parallel to NMOS transistor T4'. Capacitor C5 can limit the bandwidth of the output from NMOS transistor T4'.
  • the operation of the AZ switches Z1 and Z2 and switches W1, W2, W5, W6, W7', W8, and W12' to W14' is the same as the operation of the AZ switches Z1 and Z2 and switches W1, W2, W5, W6, W7', W8, and W12' to W14' in the eleventh embodiment described above.
  • the signal voltage VSI and the reference voltage VRF are input in parallel to the PMOS transistor T1' via the input capacitors C1' and C3', respectively, and the input of the PMOS transistor T2' is set to a fixed potential via the input capacitor C2. This makes it possible to reduce the dynamic range of the differential input in the comparison phase of the comparator CM12, and to lower the power supply voltage VDD.
  • the comparator CM10 of the tenth embodiment is provided with an amplifier that amplifies and outputs the comparison result, and the signal voltage VSI and reference voltage VRF are input in parallel to the PMOS transistor T1' via input capacitors C1' and C3', respectively, and the input of the PMOS transistor T2' is set to a fixed potential via input capacitor C2.
  • any of the comparators CM7 to CM9 of the seventh to ninth embodiments may be provided with an amplifier that amplifies and outputs the comparison result, and the signal voltage VSI and reference voltage VRF may be input in parallel to one of the differential inputs, with the other differential input set to a fixed potential.
  • an offset capacitance CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1 during the reset phase.
  • an offset capacitance CF is connected between the gate and drain of the NMOS transistor T5 during the reset phase.
  • FIG. 30 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the thirteenth embodiment
  • FIG. 31 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the thirteenth embodiment.
  • this comparator CM13 has a switching unit K13 instead of the switching unit K3 of the seventh embodiment described above.
  • the rest of the configuration of the comparator CM13 of the thirteenth embodiment is the same as the configuration of the comparator CM7 of the seventh embodiment described above.
  • the switching unit K13 switches the connection of the offset capacitance CF between the gate and drain of the NMOS transistor T5.
  • the switching unit K13 includes a switch W9 instead of the switch W7 of the seventh embodiment described above.
  • the switch W9 switches the connection between the first terminal of the offset capacitance CF and the drain of the NMOS transistor T5.
  • the offset voltage generated by the offset capacitance CF can be set to a negative value.
  • the relationship VOF1 ⁇ VOF2 can be satisfied.
  • the other configuration of the switching unit K3' of the eighth embodiment is the same as the configuration of the switching unit K3 of the seventh embodiment described above.
  • the operation of the AZ switches Z1 and Z2 and switches W1, W2, W5, W6, W9, and W8 is the same as the operation of the AZ switches Z1 and Z2 and switches W1, W2, W5 to W8 in the seventh embodiment described above.
  • Figure 32 shows the voltages applied to each transistor of the comparator in the reset phase and comparison phase according to the thirteenth embodiment. Note that in the figure, “a” indicates the voltage applied to each transistor of comparator CM13 in the reset phase, and “b” indicates the voltage applied to each transistor of comparator CM13 in the comparison phase.
  • the sum of the gate-source voltage Vgs3 of NMOS transistor T5 and the offset voltage Vof of offset capacitance CF can be set to the minimum drain-source voltage Vds3min of NMOS transistor T5.
  • the offset voltage Vof of offset capacitance CF is set to a negative level so as to cancel out the threshold voltage Vth3 of NMOS transistor T5.
  • the comparison phase shown at b is the same as that of the seventh embodiment described above.
  • Figure 33 is a circuit diagram showing an example configuration of an offset circuit according to the thirteenth embodiment.
  • the offset circuit OF2 is the offset circuit OF1 of the seventh embodiment described above, with the NMOS transistor T26 removed.
  • the drain of the PMOS transistor T23 is connected to the ground potential via resistor R2.
  • An offset voltage VOF1 is output from the drain of the PMOS transistor T23.
  • the rest of the configuration of the offset circuit OF2 of the thirteenth embodiment is the same as the configuration of the offset circuit OF1 of the seventh embodiment described above.
  • an offset capacitance CF is connected between the gate and drain of NMOS transistor T5 during the reset phase. This makes it possible to absorb imbalances in the threshold voltages of the NMOS transistors T1, T2, and T5 based on the offset voltage generated by the offset capacitance CF.
  • connection position of the offset capacitor CF is changed in the comparator CM7 of the seventh embodiment.
  • connection position of the offset capacitor CF may be changed in any of the comparators CM7 to CM12 of the seventh to twelfth embodiments.
  • an offset capacitance CF is connected between the gate and drain of the NMOS transistor T5, and PMOS transistors T3 and T4 are used as load transistors, NMOS transistors T1 and T2 are used as differential transistors, and NMOS transistor T5 is used as a current source transistor.
  • NMOS transistors T3' and T4' are used as load transistors, and PMOS transistors T1', T2', and T5' are used as differential transistors and current source transistors.
  • FIG. 34 is a circuit diagram showing an example configuration of the reset phase of a comparator according to the fourteenth embodiment
  • FIG. 35 is a circuit diagram showing an example configuration of the comparison phase of a comparator according to the fourteenth embodiment.
  • this comparator CM14 has a switching unit K13' instead of the switching unit K13 of the thirteenth embodiment described above.
  • the rest of the configuration of the comparator CM14 of the fourteenth embodiment is the same as the configuration of the comparator CM13 of the thirteenth embodiment described above.
  • the switching unit K13' switches the connection of the offset capacitance CF between the gate and drain of the PMOS transistor T5'.
  • the switching unit K13' includes a switch W9' instead of the switch W9 of the thirteenth embodiment described above.
  • the switch W9' switches the connection between the first terminal of the offset capacitance CF and the drain of the PMOS transistor T5'.
  • the offset voltage generated by the offset capacitance CF can be set to a negative value. In this case, the relationship VOF1 ⁇ VOF2 can be satisfied.
  • the other configuration of the switching unit K13' of the fourteenth embodiment is the same as the configuration of the switching unit K13 of the thirteenth embodiment described above.
  • the operation of the AZ switches Z1 and Z2 and the switches W1, W2, W5, W6, W9', and W8 is the same as the operation of the AZ switches Z1 and Z2 and the switches W1, W2, W5, W6, W9, and W8 in the thirteenth embodiment described above.
  • an offset capacitance CF is connected between the gate and drain of PMOS transistor T5' during the reset phase. This makes it possible to absorb imbalances in the threshold voltages of the PMOS transistors T1', T2', and T5' based on the offset voltage generated by the offset capacitance CF.
  • FIG. 36 is a block diagram showing an example configuration of an imaging device according to the fifteenth embodiment.
  • the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a memory unit 105, a display unit 106, and an operation unit 107.
  • the imaging control unit 103, the image processing unit 104, the memory unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108.
  • the imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.
  • the optical system 101 allows light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102.
  • the optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture.
  • the optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.
  • the solid-state imaging device 102 converts the optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. Single-slope AD conversion can be used to digitize the electrical signal.
  • the solid-state imaging device 102 may support CDS (Correlated Double Sampling) readout or DDS (Double Data Sampling) readout. Each pixel may have a single photodiode or multiple photodiodes with different sensitivities.
  • the solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
  • the CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor.
  • the solid-state imaging device 102 may also be a LOFIC (Lateral Overflow Integration Capacitor) image sensor.
  • the imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.
  • the image processing unit 104 performs image processing based on the output from the solid-state imaging device 102.
  • Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing.
  • the image processing unit 104 may also include a processor that executes processing based on software.
  • the storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102.
  • the storage unit 105 can also store programs that operate the imaging device 100 based on software.
  • the storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.
  • the display unit 106 displays captured images and various information that supports the capture operation.
  • the display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.
  • the operation unit 107 provides a user interface for operating the imaging device 100.
  • the operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100.
  • the operation unit 107 may also be configured as a touch panel together with the display unit 106.
  • FIG. 37 is a block diagram showing an example configuration of a solid-state imaging device according to the fifteenth embodiment.
  • the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.
  • the pixel array section 111 comprises a plurality of pixels PX.
  • the pixels PX are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction).
  • Each pixel PX can form a source follower with the column readout circuit 113 when reading out a signal.
  • Each pixel PX is connected to a horizontal drive line HSL for each row, and to a vertical signal line VSL for each column.
  • the horizontal drive line HSL drives each pixel PX for each row when reading out a signal from each pixel PX.
  • the vertical signal line VSL transmits the pixel signals read out from the pixels PX to the column signal processing section 114 for each column.
  • Each pixel PX may be a single pixel, a four-pixel shared pixel, or an eight-pixel shared pixel.
  • the pixels PX may also be arranged in a Bayer array or a quad-Bayer array.
  • the light received by each pixel PX may be visible light, near-infrared light (NIR: Near InfraRed), short-wave infrared light (SWIR: Short Wavelength InfraRed), ultraviolet light, or X-rays.
  • NIR Near InfraRed
  • SWIR Short Wavelength InfraRed
  • the vertical scanning circuit 112 scans the pixels PX to be read in the column direction.
  • the vertical scanning circuit 112 may also include a vertical register.
  • the vertical scanning circuit 112 can drive each pixel PX row by row via the horizontal drive line HSL.
  • the column readout circuit 113 When reading out a signal from each pixel PX, the column readout circuit 113 can form a source follower with each pixel PX. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL for each column based on the charge held in each pixel PX.
  • the column signal processing unit 114 processes signals transmitted in the column direction from each pixel PX. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel PX. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel PX, and output the image signal Gout.
  • the column signal processing unit 114 includes a column ADC unit 114A.
  • the column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the results of comparing the pixel signal read from the pixel PX with the reference signal REF.
  • the horizontal scanning circuit 115 scans the pixels PX to be read in the row direction.
  • the horizontal scanning circuit 115 may also be configured to include a horizontal register.
  • the control circuit 116 controls the vertical scanning circuit 112, column readout circuit 113, column signal processing unit 114, and horizontal scanning circuit 115.
  • the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114.
  • the control circuit 116 can coordinate the vertical scanning circuit 112, column readout circuit 113, column signal processing unit 114, and horizontal scanning circuit 115 so that the accumulation operation, shutter operation, and read operation are performed for each row in each frame.
  • Figure 38 is a block diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to the fifteenth embodiment.
  • pixel PX includes a photodiode PD, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD.
  • MOS transistors can be used as the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125.
  • the amplification transistor 124 and selection transistor 125 are connected in series.
  • the cathode of the photodiode PD is connected to the floating diffusion FD via the transfer transistor 122.
  • the floating diffusion FD is connected to the power supply VDD via the reset transistor 123.
  • the power supply VDD is connected to the vertical signal line VSL via the series circuit of the amplification transistor 124 and selection transistor 125.
  • the gate of the amplification transistor 124 is connected to the floating diffusion FD.
  • a transfer signal TGL is applied to the gate of the transfer transistor 122.
  • a reset signal RST is applied to the gate of the reset transistor 123.
  • a selection signal SEL is applied to the gate of the selection transistor 125.
  • the transfer signal TGL, reset signal RST, and selection signal SEL can be transmitted to each pixel PX via the horizontal drive line HSL in Figure 37.
  • the transfer transistor 122 When the transfer transistor 122 is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD.
  • the selection transistor 125 When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes depending on the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is then applied to the vertical signal line VSL via the selection transistor 125 and transmitted via the vertical signal line VSL.
  • the reset transistor 123 When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.
  • Figure 39 is a block diagram showing an example configuration of a signal readout unit according to the fifteenth embodiment. Note that while the figure shows two columns of vertical signal lines VSL1 and VSL2, the same can be applied to cases where there are more vertical signal lines.
  • pixels PX1 and PX2 are connected to vertical signal lines VSL1 and VSL2, respectively.
  • the amplification transistors 124 of pixels PX1 and PX2 are connected to vertical signal lines VSL1 and VSL2 via selection transistors 125, respectively.
  • the column readout circuit 113 includes current sources LM1 and LM2.
  • Current sources LM1 and LM2 are provided for each column.
  • Each current source LM1 and LM2 is connected to a vertical signal line VSL1 or VSL2, respectively.
  • each current source LM1 or LM2 can form a source follower with each pixel PX1 or PX2 via the vertical signal line VSL1 or VSL2, respectively.
  • Each current source LM1 or LM2 may be a MOS transistor.
  • the column ADC unit 114A has comparators CP1 and CP2 and counters CN1 and CN2 for each column.
  • Comparator CP1 compares the pixel signal transmitted via vertical signal line VSL1 with the reference signal REF.
  • Comparator CP2 compares the pixel signal transmitted via vertical signal line VSL2 with the reference signal REF.
  • An auto-zero signal AZ is also input to each comparator CP1, CP2.
  • the auto-zero signal AZ activates auto-zero operation during the auto-zero period.
  • a DC-blocking capacitor CA1 is connected to the non-inverting input terminal of comparator CP1, and a DC-blocking capacitor CB1 is connected to the inverting input terminal.
  • a DC-blocking capacitor CA2 is connected to the non-inverting input terminal of comparator CP2, and a DC-blocking capacitor CB2 is connected to the inverting input terminal.
  • Each comparator CP1 and CP2 may use any of the comparators CM1 to CM14 in the first to fourteenth embodiments described above.
  • each DC-blocking capacitor CA1, CB1 In auto-zero operation, the charge stored in each DC-blocking capacitor CA1, CB1 is controlled so that the non-inverting input and inverting input of comparator CP1 are balanced. In auto-zero operation, the charge stored in each DC-blocking capacitor CA2, CB2 is controlled so that the non-inverting input and inverting input of comparator CP2 are balanced.
  • Each counter CN1, CN2 performs a counting operation for each column until the level of the pixel signal read out from each pixel PX1, PX2 matches the level of the ramp wave of the reference signal REF, and holds the digital values D1, D2 of the pixel signal read out from each pixel PX1, PX2 for each column. At this time, the pixel signals read out from each pixel PX1, PX2 can be digitized for each row in each comparator CP1, CP2. The digital values D1, D2 held in each counter CN1, CN2 can then be updated for each row.
  • each comparator CP1, CP2 during the AD conversion period provided in each horizontal scanning period, the pixel signals read out from each pixel PX1, PX2 are compared with the ramp wave contained in the reference signal REF for each column. Then, based on the comparison results in each comparator CP1, CP2 during that AD conversion period, the digital values D1, D2 of the pixel signals read out from each pixel PX1, PX2 are held in each counter CN1, CN2.
  • Figure 40 is a timing chart showing an example of waveforms at various parts during signal readout of a solid-state imaging device according to the fifteenth embodiment. Note that the figure shows an example of waveforms within a 1H period (one horizontal synchronization period).
  • the reset signal RST rises (t1), turning on the reset transistor 123 and resetting the floating diffusion 126. Furthermore, the selection signal SEL rises, turning on the selection transistor 125. At this time, the potential of each vertical signal line VSL1, VSL2 is set based on the source follower operation when the power supply voltage VDD is applied to the gate of the amplification transistor 124.
  • the reset signal RST falls (t2), turning off the reset transistor 123.
  • the potential of each vertical signal line VSL1, VSL2 is set based on the source follower operation when the P-phase level of the floating diffusion 126 is applied to the gate of the amplification transistor 124.
  • each comparator CP1, CP2 the potential of each vertical signal line VSL1, VSL2 corresponding to the P-phase level is compared with the reference signal REF, and the timing when the level of the reference signal REF matches the potential of each vertical signal line VSL1, VSL2 is output as the comparison result.
  • the P-phase level read out from the pixel PX is AD converted for each column based on the counting operation until the level of the reference signal REF matches the potential of each vertical signal line VSL1, VSL2.
  • the transfer transistor 122 turns on and the charge accumulated in the photodiode 121 is transferred to the floating diffusion 126.
  • the potential of each vertical signal line VSL1, VSL2 is set based on the source follower action when the cathode potential of the photodiode 121 is applied to the gate of the amplification transistor 124.
  • the transfer transistor 122 turns off.
  • the potential of each vertical signal line VSL1, VSL2 is set based on the source follower operation when the D-phase level of the floating diffusion 126 is applied to the gate of the amplification transistor 124.
  • each comparator CP1, CP2 the potential of each vertical signal line VSL1, VSL2 corresponding to the D-phase level is compared with the reference signal REF, and the timing when the level of the reference signal REF matches the potential of each vertical signal line VSL1, VSL2 is output as the comparison result.
  • the D-phase level read out from the pixel PX is AD converted for each column based on the counting operation until the level of the reference signal REF matches the potential of each vertical signal line VSL1, VSL2.
  • any of the comparators CM1 to CM14 whose power supply voltage VDD during the reset phase has been reduced, is applied to the solid-state imaging device 102. This allows the power supply voltage VDD of the column ADC unit 114A to be reduced, thereby reducing power consumption.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.
  • Figure 41 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the vehicle control system 12000 includes multiple electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • the functional configuration of the integrated control unit 12050 also includes a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
  • the drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain in accordance with various programs.
  • the drivetrain control unit 12010 functions as a control device for a driveforce generating device such as an internal combustion engine or drive motor that generates vehicle driveforce, a driveforce transmission mechanism that transmits driveforce to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a braking device that generates vehicle braking force.
  • the body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps.
  • radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020.
  • the body system control unit 12020 accepts these radio waves or signal inputs and controls the vehicle's door lock device, power window device, lamps, etc.
  • the outside vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the outside vehicle information detection unit 12030 is connected to an imaging unit 12031.
  • the outside vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images.
  • the outside vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received.
  • the imaging unit 12031 can output the electrical signal as an image, or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects information inside the vehicle. Connected to the in-vehicle information detection unit 12040 is, for example, a driver state detection unit 12041 that detects the driver's state.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
  • the microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output control commands to the drive system control unit 12010.
  • the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the vehicle's surroundings acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby enabling cooperative control aimed at autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.
  • the microcomputer 12051 can output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle exterior information detection unit 12030.
  • the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.
  • the audio/video output unit 12052 transmits at least one audio and/or video output signal to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle of information.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • Figure 42 shows an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, on the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100.
  • the imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly capture images of the front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided on the side mirrors mainly capture images of the sides of the vehicle 12100.
  • the imaging unit 12104 provided on the rear bumper or back door mainly captures images of the rear of the vehicle 12100.
  • the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
  • Imaging range 12111 indicates the imaging range of imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 provided on the side mirrors, respectively
  • imaging range 12114 indicates the imaging range of imaging unit 12104 provided on the rear bumper or back door.
  • At least one of the image capturing units 12101 to 12104 may have a function for acquiring distance information.
  • at least one of the image capturing units 12101 to 12104 may be a stereo camera consisting of multiple image capturing elements, or an image capturing element having pixels for phase difference detection.
  • the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the closest three-dimensional object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or higher). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 can classify and extract three-dimensional object data regarding three-dimensional objects into categories such as motorcycles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see.
  • the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and a collision is possible, it can provide driving assistance to avoid a collision by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drivetrain control unit 12010.
  • At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points in the images captured by the image capturing units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian.
  • the audio/video output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis.
  • the audio/video output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian in a desired position.
  • the foregoing describes an example of a vehicle control system to which the technology disclosed herein can be applied.
  • the technology disclosed herein can be applied to the imaging unit 12031 of the configuration described above.
  • each comparator in the above-described embodiment can be applied to the imaging unit 12031.
  • the power supply voltage VDD of the imaging unit 12031 can be lowered, thereby reducing power consumption.
  • the present technology can also be configured as follows. (1) a first transistor having a gate to which a first input is applied; a second transistor having a gate to which the second input is applied; a third transistor connected in series with the first transistor; a fourth transistor connected in series to the second transistor and having a gate connected to a gate of the third transistor; a fifth transistor connected to the first transistor and the second transistor; a bias capacitor connected to the gate of the fifth transistor; a first switching unit that switches the connection of the gates of the third transistor and the fourth transistor between a first bias voltage and the drain of the third transistor.
  • the comparator according to (1) further comprising a second switching unit that switches the connection between the gate of the fifth transistor and the drain of the first transistor or the drain of the second transistor.
  • the first switching unit a first switch for switching an input of a first bias voltage to a gate of the third transistor; a second switch that switches a connection between the gate and the drain of the third transistor;
  • the second switching unit further includes a fourth switch that switches the connection between the gate of the fifth transistor and the drain of the fourth transistor.
  • the comparator according to any one of (1) to (5), further comprising a third switching unit that switches a connection between the offset capacitance and the bias capacitance.
  • the third switching unit a fifth switch that switches the input of a first offset voltage to a first terminal of the offset capacitor; a sixth switch that switches the input of a second offset voltage to a second terminal of the offset capacitor;
  • the comparator according to (6) further comprising: a seventh switch that switches a connection between the offset capacitance and the bias capacitance; and an eighth switch that switches a connection between a first terminal of the offset capacitance and a drain of the first transistor or the second transistor.
  • the comparator according to (7) further comprising a second dummy transistor that operates as a dummy for the fifth transistor and generates the second offset voltage.
  • the third switching unit a fifth switch that switches the input of a first offset voltage to a first terminal of the offset capacitor; a sixth switch that switches the input of a second offset voltage to a second terminal of the offset capacitor;
  • the comparator according to (6) further comprising: a seventh switch that switches a connection between the offset capacitance and the bias capacitance; and a ninth switch that switches a connection between a first terminal of the offset capacitance and a drain of the fifth transistor.
  • (11) a mirror transistor that generates the first offset voltage based on a current mirror operation;
  • (12) a first AZ (Auto Zero) switch connected between the gate and the drain of the first transistor;
  • (13) a first input capacitance connected in series to the gate of the first transistor;
  • a tenth transistor whose gate is connected to the drain of the second transistor; an eleventh transistor connected in series with the tenth transistor;
  • the fourth switching unit a twelfth switch that switches the input of a second bias voltage to the gate of the tenth transistor;
  • the comparator according to (16) further comprising a sixth switch that switches the connection between the drain of the second transistor and the gate of the tenth transistor.
  • a pixel array section in which pixels are arranged in a matrix in row and column directions; a column ADC unit that performs AD (Analog to Digital) conversion on pixel signals output from the pixels for each column, the column ADC unit includes a comparator that compares the pixel signal with a reference signal; The comparator a first transistor having a gate to which the first input is applied; a second transistor having a gate to which the second input is applied; a third transistor connected in series with the first transistor; a fourth transistor connected in series to the second transistor and having a gate connected to a gate of the third transistor; a fifth transistor connected to the first transistor and the second transistor; a bias capacitor connected to the gate of the fifth transistor; a first switching unit that switches connection of the gates of the third transistor and the fourth transistor between a first bias voltage and the drain of the third transistor.
  • AD Analog to Digital
  • the comparator The imaging device according to (18), further comprising a second switching unit that switches a connection between the gate of the fifth transistor and the drain of the first transistor or the second transistor.
  • the comparator an offset capacitor connected in series to the bias capacitor;

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

Le but de la présente invention est d'améliorer la flexibilité d'une tension appliquée à un comparateur dans une phase de réinitialisation pour équilibrer des entrées différentielles.　Ce comparateur comprend : un premier transistor ayant une grille à laquelle une première entrée est appliquée ; un deuxième transistor ayant une grille à laquelle une deuxième entrée est appliquée ; un troisième transistor connecté en série au premier transistor ; un quatrième transistor connecté en série au deuxième transistor et ayant une grille connectée à la grille du troisième transistor ; un cinquième transistor connecté au premier transistor et au deuxième transistor ; un condensateur de polarisation connecté à la grille du cinquième transistor ; et une première unité de commutation qui commute la connexion des grilles du troisième transistor et du quatrième transistor entre une première tension de polarisation et le drain du troisième transistor.
PCT/JP2025/022344 2024-08-15 2025-06-20 Comparateur et dispositif d'imagerie Pending WO2026038416A1 (fr)

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JP2024135722 2024-08-15
JP2024-135722 2024-08-15

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014197772A (ja) * 2013-03-29 2014-10-16 ソニー株式会社 コンパレータ、固体撮像素子、電子機器、および、駆動方法
WO2019150917A1 (fr) * 2018-02-02 2019-08-08 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie et dispositif électronique
WO2020012943A1 (fr) * 2018-07-09 2020-01-16 ソニーセミコンダクタソリューションズ株式会社 Comparateur et dispositif d'imagerie
US20220078362A1 (en) * 2020-09-09 2022-03-10 Samsung Electronics Co., Ltd. Image sensor
WO2022153901A1 (fr) * 2021-01-14 2022-07-21 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie et appareil électronique

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014197772A (ja) * 2013-03-29 2014-10-16 ソニー株式会社 コンパレータ、固体撮像素子、電子機器、および、駆動方法
WO2019150917A1 (fr) * 2018-02-02 2019-08-08 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie et dispositif électronique
WO2020012943A1 (fr) * 2018-07-09 2020-01-16 ソニーセミコンダクタソリューションズ株式会社 Comparateur et dispositif d'imagerie
US20220078362A1 (en) * 2020-09-09 2022-03-10 Samsung Electronics Co., Ltd. Image sensor
WO2022153901A1 (fr) * 2021-01-14 2022-07-21 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie et appareil électronique

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