WO2026080949A2 - Systèmes et procédés de codage convolutif pour des dispositifs de l'ido-a - Google Patents
Systèmes et procédés de codage convolutif pour des dispositifs de l'ido-aInfo
- Publication number
- WO2026080949A2 WO2026080949A2 PCT/US2026/013134 US2026013134W WO2026080949A2 WO 2026080949 A2 WO2026080949 A2 WO 2026080949A2 US 2026013134 W US2026013134 W US 2026013134W WO 2026080949 A2 WO2026080949 A2 WO 2026080949A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- sequence
- encoder
- length
- encoding
- bits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
- H03M13/235—Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/413—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors tail biting Viterbi decoding
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
Abstract
Conformément à des modes de réalisation, un appareil obtient une première séquence de bits d'une première longueur de séquence. La première séquence de bits comprend une première partie d'une première longueur de partie et une seconde partie. L'appareil obtient une seconde séquence de bits d'une seconde longueur de séquence généré à partir de la première séquence de bits. L'appareil code une séquence d'entrée afin de générer une séquence codée. Un ordonnancement de la séquence d'entrée comprend la seconde partie, la seconde séquence de bits et la première partie. Un codeur pour le codage comprend un état. Une valeur initiale de l'état avant le codage est définie en fonction de la première partie. Le dispositif transmet la séquence codée.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202563755037P | 2025-02-06 | 2025-02-06 | |
| US63/755,037 | 2025-02-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2026080949A2 true WO2026080949A2 (fr) | 2026-04-16 |
Family
ID=98975257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2026/013134 Pending WO2026080949A2 (fr) | 2025-02-06 | 2026-01-29 | Systèmes et procédés de codage convolutif pour des dispositifs de l'ido-a |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2026080949A2 (fr) |
-
2026
- 2026-01-29 WO PCT/US2026/013134 patent/WO2026080949A2/fr active Pending
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