ZA891240B - Memory addressing system - Google Patents

Memory addressing system

Info

Publication number
ZA891240B
ZA891240B ZA891240A ZA891240A ZA891240B ZA 891240 B ZA891240 B ZA 891240B ZA 891240 A ZA891240 A ZA 891240A ZA 891240 A ZA891240 A ZA 891240A ZA 891240 B ZA891240 B ZA 891240B
Authority
ZA
South Africa
Prior art keywords
memory addressing
addressing system
memory
addressing
Prior art date
Application number
ZA891240A
Other languages
English (en)
Inventor
Anthony Peter Lumb
Peter Lumb Anthony
Michael John Mills
John Mills Michael
Howard Williams
Williams Howard
Original Assignee
Plessey Telecomm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Telecomm filed Critical Plessey Telecomm
Publication of ZA891240B publication Critical patent/ZA891240B/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0692—Multiconfiguration, e.g. local and global addressing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Telephonic Communication Services (AREA)
  • Hardware Redundancy (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
ZA891240A 1988-02-19 1989-02-17 Memory addressing system ZA891240B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB888803926A GB8803926D0 (en) 1988-02-19 1988-02-19 Memory addressing system

Publications (1)

Publication Number Publication Date
ZA891240B true ZA891240B (en) 1989-10-25

Family

ID=10632029

Family Applications (1)

Application Number Title Priority Date Filing Date
ZA891240A ZA891240B (en) 1988-02-19 1989-02-17 Memory addressing system

Country Status (8)

Country Link
EP (1) EP0329420A3 (de)
JP (1) JPH01282667A (de)
AU (1) AU613153B2 (de)
GB (2) GB8803926D0 (de)
MT (1) MTP1035B (de)
NZ (1) NZ227980A (de)
PT (1) PT89741A (de)
ZA (1) ZA891240B (de)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4340932A (en) * 1978-05-17 1982-07-20 Harris Corporation Dual mapping memory expansion unit
DE2846054C2 (de) * 1978-10-23 1985-08-14 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur Erweiterung des Adressierungsvolumens einer Zentraleinheit, insbesondere eines Mikroprozessors
GB2099619B (en) * 1981-05-29 1985-09-18 Gen Electric Plc Data processing arrangements

Also Published As

Publication number Publication date
JPH01282667A (ja) 1989-11-14
GB8903453D0 (en) 1989-04-05
EP0329420A2 (de) 1989-08-23
MTP1035B (en) 1991-09-30
EP0329420A3 (de) 1991-01-16
GB8803926D0 (en) 1988-03-23
GB2216302A (en) 1989-10-04
NZ227980A (en) 1990-09-26
AU3005689A (en) 1989-08-24
GB2216302B (en) 1992-09-09
PT89741A (pt) 1989-10-04
AU613153B2 (en) 1991-07-25

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