AR026082A2 - Un procesador de senales digitales para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable, y un metodo para realizaruna operacion de multiplicacion de doble precision que utiliza dicho procesador de senales - Google Patents

Un procesador de senales digitales para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable, y un metodo para realizaruna operacion de multiplicacion de doble precision que utiliza dicho procesador de senales

Info

Publication number
AR026082A2
AR026082A2 ARP000105486A ARP000105486A AR026082A2 AR 026082 A2 AR026082 A2 AR 026082A2 AR P000105486 A ARP000105486 A AR P000105486A AR P000105486 A ARP000105486 A AR P000105486A AR 026082 A2 AR026082 A2 AR 026082A2
Authority
AR
Argentina
Prior art keywords
digital signal
signal processor
instructions
processing
processing units
Prior art date
Application number
ARP000105486A
Other languages
English (en)
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/044,086 external-priority patent/US6425070B1/en
Priority claimed from US09/044,088 external-priority patent/US6496920B1/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of AR026082A2 publication Critical patent/AR026082A2/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Memory System (AREA)

Abstract

Un procesador de senales digitales para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable. Almacenar una parte de lasinstrucciones con longitudes variables en lugares adyacentes dentro del espacio de la memoria yen el que el comienzo y el fin de las instrucciones tienenlugar entre los límites de palabras de memoria. Adicionalmente, otros aspectos adicionales de la presente se llevan a la práctica al contar con instruccionesque contengan cantidades variablesde fragmentos de instruccion. Cada fragmento de instruccion hace que se lleve a cabo una o más operaciones en particular, loque permite que se realicen multiples operaciones durante el ciclo de reloj. De esta manera, se llevan a cabo multiples operaciones durante caca ciclo de reloj, algo que reduce la cantidad total de ciclos de reloj necesarios para la realizacion de una tarea. Un método para realizar una operacion de multiplicacion dedoble precision que utiliza dicho procesador de senales digitales, se realiza por el uso de un banco de registro que cuenta con registros a los que puedenacceder al menos dos unidades de procesamiento. Esto hace posible que las multiples unidades de procesamiento puedan realizar multiples operaciones en ungrupode datos particular sin leer ni escribir los datos en y desde una memoria. Las unidades de procesamiento en la forma de realizacion ejemplar de la invencionincluyen una unidad aritmética logica (ALU) y una unidad de multiplicacion-acumulacion (MAC). Cuando se las combina con el uso de una arquitectura con busesmultiples, de instrucciones sumamente paralelas, o ambas, puede ponerse en práctica un aspecto adicional de la invencion, en el que se lleva a cabo unprocesamiento extremadamente encauzado y de multiples operaciones.
ARP000105486A 1998-03-18 2000-10-18 Un procesador de senales digitales para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable, y un metodo para realizaruna operacion de multiplicacion de doble precision que utiliza dicho procesador de senales AR026082A2 (es)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US4410498A 1998-03-18 1998-03-18
US4410898A 1998-03-18 1998-03-18
US4408798A 1998-03-18 1998-03-18
US4408998A 1998-03-18 1998-03-18
US09/044,086 US6425070B1 (en) 1998-03-18 1998-03-18 Variable length instruction decoder
US09/044,088 US6496920B1 (en) 1998-03-18 1998-03-18 Digital signal processor having multiple access registers

Publications (1)

Publication Number Publication Date
AR026082A2 true AR026082A2 (es) 2002-12-26

Family

ID=27556460

Family Applications (5)

Application Number Title Priority Date Filing Date
ARP000105482A AR026078A2 (es) 1998-03-18 2000-10-18 Un procesador de senales digitales, para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable
ARP000105484A AR026080A2 (es) 1998-03-18 2000-10-18 Una disposicion para controlar un procesador de senales digitales con instrucciones de longitud variable
ARP000105486A AR026082A2 (es) 1998-03-18 2000-10-18 Un procesador de senales digitales para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable, y un metodo para realizaruna operacion de multiplicacion de doble precision que utiliza dicho procesador de senales
ARP000105483A AR026079A2 (es) 1998-03-18 2000-10-18 Un metodo para operar un procesador de senales digitales que utiliza instrucciones de longitud variable y un procesador de senales digitales para llevar ala practica dicho metodo
ARP000105485A AR026081A2 (es) 1998-03-18 2000-10-18 Un metodo para controlar un procesador de senales digitales en respuesta a instrucciones de longitud variable

Family Applications Before (2)

Application Number Title Priority Date Filing Date
ARP000105482A AR026078A2 (es) 1998-03-18 2000-10-18 Un procesador de senales digitales, para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable
ARP000105484A AR026080A2 (es) 1998-03-18 2000-10-18 Una disposicion para controlar un procesador de senales digitales con instrucciones de longitud variable

Family Applications After (2)

Application Number Title Priority Date Filing Date
ARP000105483A AR026079A2 (es) 1998-03-18 2000-10-18 Un metodo para operar un procesador de senales digitales que utiliza instrucciones de longitud variable y un procesador de senales digitales para llevar ala practica dicho metodo
ARP000105485A AR026081A2 (es) 1998-03-18 2000-10-18 Un metodo para controlar un procesador de senales digitales en respuesta a instrucciones de longitud variable

Country Status (11)

Country Link
EP (2) EP1457876B1 (es)
JP (4) JP2002507789A (es)
KR (3) KR100835148B1 (es)
CN (2) CN1279435C (es)
AR (5) AR026078A2 (es)
AT (1) ATE297567T1 (es)
AU (1) AU2986099A (es)
CA (1) CA2324219C (es)
DE (1) DE69925720T2 (es)
DK (1) DK1066559T3 (es)
WO (1) WO1999047999A1 (es)

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DK1066559T3 (da) * 1998-03-18 2005-10-03 Qualcomm Inc Digital signalprocessor
JP4100300B2 (ja) * 2003-09-02 2008-06-11 セイコーエプソン株式会社 信号出力調整回路及び表示ドライバ
JP4661169B2 (ja) * 2003-11-14 2011-03-30 ヤマハ株式会社 ディジタルシグナルプロセッサ
JP4300151B2 (ja) * 2004-04-19 2009-07-22 Ｏｋｉセミコンダクタ株式会社 演算処理装置
US7246218B2 (en) * 2004-11-01 2007-07-17 Via Technologies, Inc. Systems for increasing register addressing space in instruction-width limited processors
US7337272B2 (en) * 2006-05-01 2008-02-26 Qualcomm Incorporated Method and apparatus for caching variable length instructions
US10001993B2 (en) 2013-08-08 2018-06-19 Linear Algebra Technologies Limited Variable-length instruction buffer management
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EP4116819A1 (en) * 2014-07-30 2023-01-11 Movidius Limited Vector processor
JP6695320B2 (ja) * 2014-07-30 2020-05-20 リニア アルジェブラ テクノロジーズ リミテッド 低電力コンピュータイメージング
WO2018012828A1 (ko) * 2016-07-13 2018-01-18 김태형 다기능 연산 장치 및 고속 푸리에 변환 연산 장치
JP7384374B2 (ja) * 2019-02-27 2023-11-21 株式会社ウーノラボ 中央演算処理装置
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EP4080354A1 (en) * 2021-04-23 2022-10-26 Nxp B.V. Processor and instruction set

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Also Published As

Publication number Publication date
CA2324219C (en) 2011-05-10
JP2010282637A (ja) 2010-12-16
KR20060040749A (ko) 2006-05-10
AR026078A2 (es) 2002-12-26
EP1066559A1 (en) 2001-01-10
JP2015028793A (ja) 2015-02-12
HK1094608A1 (zh) 2007-04-04
JP6300284B2 (ja) 2018-03-28
DE69925720T2 (de) 2006-03-16
AR026079A2 (es) 2002-12-26
CN1301363A (zh) 2001-06-27
EP1457876A3 (en) 2006-11-02
AR026080A2 (es) 2002-12-26
DK1066559T3 (da) 2005-10-03
AU2986099A (en) 1999-10-11
JP6152558B2 (ja) 2017-06-28
CA2324219A1 (en) 1999-09-23
KR100896674B1 (ko) 2009-05-14
ATE297567T1 (de) 2005-06-15
JP5677774B2 (ja) 2015-02-25
CN1279435C (zh) 2006-10-11
JP2016146189A (ja) 2016-08-12
EP1457876A2 (en) 2004-09-15
KR100940465B1 (ko) 2010-02-04
EP1066559B1 (en) 2005-06-08
HK1035594A1 (en) 2001-11-30
KR20010082524A (ko) 2001-08-30
JP2002507789A (ja) 2002-03-12
AR026081A2 (es) 2002-12-26
EP1457876B1 (en) 2017-10-04
CN1523491A (zh) 2004-08-25
KR20060040748A (ko) 2006-05-10
DE69925720D1 (de) 2005-07-14
WO1999047999A1 (en) 1999-09-23
KR100835148B1 (ko) 2008-06-04

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