ATE128778T1 - Verfahren und gerät zur binärzählerprüfung. - Google Patents

Verfahren und gerät zur binärzählerprüfung.

Info

Publication number
ATE128778T1
ATE128778T1 AT90302684T AT90302684T ATE128778T1 AT E128778 T1 ATE128778 T1 AT E128778T1 AT 90302684 T AT90302684 T AT 90302684T AT 90302684 T AT90302684 T AT 90302684T AT E128778 T1 ATE128778 T1 AT E128778T1
Authority
AT
Austria
Prior art keywords
bit
stages
counter
stage
counters
Prior art date
Application number
AT90302684T
Other languages
English (en)
Inventor
Mayur M Mehta
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE128778T1 publication Critical patent/ATE128778T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G01R31/31853—Test of registers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G01R31/318527—Test of counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
AT90302684T 1989-04-26 1990-03-14 Verfahren und gerät zur binärzählerprüfung. ATE128778T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/343,215 US4979193A (en) 1989-04-26 1989-04-26 Method and apparatus for testing a binary counter

Publications (1)

Publication Number Publication Date
ATE128778T1 true ATE128778T1 (de) 1995-10-15

Family

ID=23345167

Family Applications (1)

Application Number Title Priority Date Filing Date
AT90302684T ATE128778T1 (de) 1989-04-26 1990-03-14 Verfahren und gerät zur binärzählerprüfung.

Country Status (5)

Country Link
US (1) US4979193A (de)
EP (1) EP0395209B1 (de)
JP (1) JPH0316429A (de)
AT (1) ATE128778T1 (de)
DE (1) DE69022766T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04351118A (ja) * 1991-05-29 1992-12-04 Sharp Corp カウンタ回路
US5185769A (en) * 1991-10-15 1993-02-09 Acer Incorporated Easily testable high speed digital counter
DE4214841C2 (de) * 1992-05-05 1994-10-06 Telefunken Microelectron Schlatungsanordnung für den Funktionstest eines in einem Schaltkreis integrierten Zeitglieds
US5386582A (en) * 1993-03-12 1995-01-31 Intel Corporation High speed time base counter in a field programmable gate array (FPGA)
US5481580A (en) * 1995-01-26 1996-01-02 At&T Corp. Method and apparatus for testing long counters
DE19522839C2 (de) * 1995-06-23 2003-12-18 Atmel Germany Gmbh Verfahren zum Testen von Impulszählern
DE10020685A1 (de) * 2000-04-27 2002-01-03 Siemens Ag Zählerstruktur mit Fehlertest-Konfiguration
JP2002369844A (ja) * 2001-06-15 2002-12-24 Matsunaga Seisakusho:Kk すくい上げ式担架
JP4899996B2 (ja) * 2007-03-30 2012-03-21 株式会社イトーキ デスクにおける上キャビネット装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4611337A (en) * 1983-08-29 1986-09-09 General Electric Company Minimal logic synchronous up/down counter implementations for CMOS
US4661930A (en) * 1984-08-02 1987-04-28 Texas Instruments Incorporated High speed testing of integrated circuit
JPS61253918A (ja) * 1985-05-02 1986-11-11 Fujitsu Ltd 論理回路
US4745630A (en) * 1986-06-18 1988-05-17 Hughes Aircraft Company Multi-mode counter network
ATE113770T1 (de) * 1986-09-02 1994-11-15 Siemens Ag Sukzessives approximations-register.
US4759043A (en) * 1987-04-02 1988-07-19 Raytheon Company CMOS binary counter
DE3801220A1 (de) * 1988-01-18 1989-07-27 Siemens Ag Vielstufiger binaerzaehler mit einer ausstattung zur durchfuehrung von testlaeufen

Also Published As

Publication number Publication date
JPH0316429A (ja) 1991-01-24
DE69022766D1 (de) 1995-11-09
EP0395209B1 (de) 1995-10-04
EP0395209A3 (de) 1991-08-21
DE69022766T2 (de) 1996-05-02
US4979193A (en) 1990-12-18
EP0395209A2 (de) 1990-10-31

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee