ATE129827T1 - Vorrichtung zur erzeugung von datensignalverzögerungen. - Google Patents

Vorrichtung zur erzeugung von datensignalverzögerungen.

Info

Publication number
ATE129827T1
ATE129827T1 AT88300953T AT88300953T ATE129827T1 AT E129827 T1 ATE129827 T1 AT E129827T1 AT 88300953 T AT88300953 T AT 88300953T AT 88300953 T AT88300953 T AT 88300953T AT E129827 T1 ATE129827 T1 AT E129827T1
Authority
AT
Austria
Prior art keywords
current
voltage controlled
control nodes
delay
sources
Prior art date
Application number
AT88300953T
Other languages
English (en)
Inventor
Yun-Che Wang
Paul H Scott
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE129827T1 publication Critical patent/ATE129827T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10212—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter compensation for data shift, e.g. pulse-crowding effects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Digital Magnetic Recording (AREA)
  • Dc Digital Transmission (AREA)
  • Stereo-Broadcasting Methods (AREA)
AT88300953T 1987-02-12 1988-02-04 Vorrichtung zur erzeugung von datensignalverzögerungen. ATE129827T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/013,846 US4878028A (en) 1987-02-12 1987-02-12 Technique for generating precompensation delay for writing data to disks

Publications (1)

Publication Number Publication Date
ATE129827T1 true ATE129827T1 (de) 1995-11-15

Family

ID=21762086

Family Applications (1)

Application Number Title Priority Date Filing Date
AT88300953T ATE129827T1 (de) 1987-02-12 1988-02-04 Vorrichtung zur erzeugung von datensignalverzögerungen.

Country Status (5)

Country Link
US (1) US4878028A (de)
EP (1) EP0282159B1 (de)
JP (1) JP2602047B2 (de)
AT (1) ATE129827T1 (de)
DE (1) DE3854625T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047967A (en) * 1989-07-19 1991-09-10 Apple Computer, Inc. Digital front end for time measurement and generation of electrical signals
US5192886A (en) * 1990-03-15 1993-03-09 Hewlett-Packard Company Sub-nanosecond calibrated delay line structure
US5255130A (en) * 1991-03-29 1993-10-19 Archive Corporation Adjustable write equalization for tape drives
US5325241A (en) * 1991-06-14 1994-06-28 Fujitsu Limited Write precompensation with frequency synthesizer
US5175452A (en) * 1991-09-30 1992-12-29 Data Delay Devices, Inc. Programmable compensated digital delay circuit
US5195064A (en) * 1991-10-15 1993-03-16 Brian A. Hegarty Sound supplemented clock system
US5180937A (en) * 1992-02-28 1993-01-19 Lsi Logic Corporation Delay compensator and monitor circuit having timing generator and sequencer
US5262690A (en) * 1992-04-29 1993-11-16 International Business Machines Corporation Variable delay clock circuit
KR100489847B1 (ko) * 1996-05-20 2005-09-14 텍사스 인스트루먼츠 인코포레이티드 고장안전및기입범위확장방법및장치
US6721114B1 (en) 2001-05-09 2004-04-13 Marvell International, Ltd. Precompensation circuit for magnetic recording
US7184231B1 (en) 2001-05-09 2007-02-27 Marvell International Ltd. Precompensation circuit for magnetic recording
US7251739B1 (en) * 2003-12-31 2007-07-31 Intel Corporation System and method for sequencing multiple write state machines
US7515372B2 (en) * 2006-04-03 2009-04-07 Seagate Technology Llc Compensating the effects of static head-media spacing variations and nonlinear transition shift in heat assisted magnetic recording

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5422514U (de) * 1977-07-15 1979-02-14
JPS5835703A (ja) * 1981-08-24 1983-03-02 Asahi Optical Co Ltd 記録情報の再生装置
US4514647A (en) * 1983-08-01 1985-04-30 At&T Bell Laboratories Chipset synchronization arrangement
US4565976A (en) * 1983-08-05 1986-01-21 Advanced Micro Devices, Inc. Interruptable voltage-controlled oscillator and phase-locked loop using same
US4628461A (en) * 1984-04-30 1986-12-09 Advanced Micro Devices, Inc. Phase detector
US4608543A (en) * 1984-12-17 1986-08-26 Advanced Micro Devices, Inc. Controllable effective resistance and phase lock loop with controllable filter

Also Published As

Publication number Publication date
JPS63201904A (ja) 1988-08-22
US4878028A (en) 1989-10-31
DE3854625D1 (de) 1995-12-07
EP0282159A2 (de) 1988-09-14
DE3854625T2 (de) 1996-05-15
EP0282159B1 (de) 1995-11-02
EP0282159A3 (de) 1991-03-20
JP2602047B2 (ja) 1997-04-23

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties