ATE142831T1 - Digitaler phasenregelkreis - Google Patents

Digitaler phasenregelkreis

Info

Publication number
ATE142831T1
ATE142831T1 AT89307390T AT89307390T ATE142831T1 AT E142831 T1 ATE142831 T1 AT E142831T1 AT 89307390 T AT89307390 T AT 89307390T AT 89307390 T AT89307390 T AT 89307390T AT E142831 T1 ATE142831 T1 AT E142831T1
Authority
AT
Austria
Prior art keywords
early
read data
reference signal
digital phase
sequence
Prior art date
Application number
AT89307390T
Other languages
English (en)
Inventor
Robert A Shaw
Original Assignee
Quantum Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quantum Corp filed Critical Quantum Corp
Application granted granted Critical
Publication of ATE142831T1 publication Critical patent/ATE142831T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
AT89307390T 1988-11-02 1989-07-20 Digitaler phasenregelkreis ATE142831T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/266,089 US4975930A (en) 1988-11-02 1988-11-02 Digital phase locked loop

Publications (1)

Publication Number Publication Date
ATE142831T1 true ATE142831T1 (de) 1996-09-15

Family

ID=23013137

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89307390T ATE142831T1 (de) 1988-11-02 1989-07-20 Digitaler phasenregelkreis

Country Status (6)

Country Link
US (1) US4975930A (de)
EP (1) EP0367378B1 (de)
JP (1) JPH02257718A (de)
AT (1) ATE142831T1 (de)
CA (1) CA1307327C (de)
DE (1) DE68927148T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075575A (en) * 1989-12-11 1991-12-24 Fuji Photo Film Co., Ltd. Externally synchronized programmable device
US5406592A (en) * 1993-07-30 1995-04-11 At&T Corp. First order FLL/PLL system with low phase error
US5404743A (en) * 1993-08-12 1995-04-11 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Pulsed phase locked loop strain monitor
US5602883A (en) * 1993-10-13 1997-02-11 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method of implementing digital phase-locked loops
US5832048A (en) * 1993-12-30 1998-11-03 International Business Machines Corporation Digital phase-lock loop control system
JPH08167841A (ja) * 1994-12-13 1996-06-25 Pioneer Electron Corp ディジタルｐｌｌ回路
US5652773A (en) * 1996-01-31 1997-07-29 Holtek Microelectronics, Inc. Digital phase-locked loop for data separation
US5931968A (en) 1996-02-09 1999-08-03 Overland Data, Inc. Digital data recording channel
US5768235A (en) * 1996-10-08 1998-06-16 Imation Corp. Control signal for recording a disc according to a clock signal, data signal, and an index signal
US5944834A (en) * 1997-09-26 1999-08-31 International Business Machines Corporation Timing analysis method for PLLS
US6597526B1 (en) 1998-08-14 2003-07-22 Overland Storage, Inc. Magnetic tape drive apparatus including a variable rate encoder
US6987817B1 (en) * 2000-07-17 2006-01-17 Lsi Logic Corporation Digital clock recovery PLL
US8650470B2 (en) 2003-03-20 2014-02-11 Arm Limited Error recovery within integrated circuit
DE602004001869T2 (de) * 2003-03-20 2007-05-03 Arm Ltd., Cherry Hinton Fehlererkennung und fehlerbehebung für systematische und zufällige fehler innerhalb einer verarbeitungsstufe einer integrierten schaltung
US8185812B2 (en) 2003-03-20 2012-05-22 Arm Limited Single event upset error detection within an integrated circuit
US7278080B2 (en) * 2003-03-20 2007-10-02 Arm Limited Error detection and recovery within processing stages of an integrated circuit
US7126404B1 (en) * 2004-01-20 2006-10-24 Marvell Semiconductor Israel Ltd. High resolution digital delay circuit for PLL and DLL
JP4829571B2 (ja) 2005-09-09 2011-12-07 株式会社日立製作所 受信装置および測位測距システム
US8171386B2 (en) 2008-03-27 2012-05-01 Arm Limited Single event upset error detection within sequential storage circuitry of an integrated circuit
US8161367B2 (en) 2008-10-07 2012-04-17 Arm Limited Correction of single event upset error within sequential storage circuitry of an integrated circuit
US8493120B2 (en) 2011-03-10 2013-07-23 Arm Limited Storage circuitry and method with increased resilience to single event upsets
CN103427836A (zh) * 2013-07-25 2013-12-04 京东方科技集团股份有限公司 一种频率信号发生系统和显示装置
DE102018129189B4 (de) * 2018-11-20 2021-03-04 Beckhoff Automation Gmbh Verfahren zum betreiben eines netzwerkteilnehmers in einem automatisierungskommunikationsnetzwerk
DE102019123348A1 (de) 2019-08-30 2021-03-04 Beckhoff Automation Gmbh Automatisierungssystem, Funkvorrichtung und Verfahren zum drahtlosen Einbinden eines Funkteilnehmers an ein Automatisierungssystem

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3509471A (en) * 1966-11-16 1970-04-28 Communications Satellite Corp Digital phase lock loop for bit timing recovery
US3947634A (en) * 1974-11-21 1976-03-30 Ncr Corporation System for synchronizing local pseudo-noise sequence to a received baseband signal
US4017803A (en) * 1976-01-29 1977-04-12 Sperry Rand Corporation Data recovery system resistant to frequency deviations
US4210776A (en) * 1977-08-11 1980-07-01 Harris Corporation Linear digital phase lock loop
US4242639A (en) * 1978-09-05 1980-12-30 Ncr Corporation Digital phase lock circuit
US4259740A (en) * 1979-03-07 1981-03-31 Harris Corporation Sequential detection system
US4357707A (en) * 1979-04-11 1982-11-02 Pertec Computer Corporation Digital phase lock loop for flexible disk data recovery system
US4374438A (en) * 1980-07-21 1983-02-15 Rca Corporation Digital frequency and phase lock loop
DE3140431C2 (de) * 1980-10-13 1986-09-25 Hitachi, Ltd., Tokio/Tokyo Demodulatorschaltung zum Demodulieren eines modulierten Digitalsignals
US4396991A (en) * 1981-04-07 1983-08-02 Honeywell Information Systems Inc. Long term response enhancement for digital phase-locked loop
US4462110A (en) * 1981-04-07 1984-07-24 Honeywell Information Systems Inc. Digital phase-locked loop
US4441195A (en) * 1981-07-10 1984-04-03 Honeywell Information Systems Inc. Short term response enhancement for digital phase-locked loop
US4513429A (en) * 1981-12-03 1985-04-23 The United States Of America As Represented By The Secretary Of The Air Force Sample data phase locked loop for adaptive doppler tracker
US4563657A (en) * 1982-03-15 1986-01-07 Codex Corporation Frequency synthesizer and digital phase lock loop
US4456890A (en) * 1982-04-05 1984-06-26 Computer Peripherals Inc. Data tracking clock recovery system using digitally controlled oscillator
US4596937A (en) * 1982-04-28 1986-06-24 International Computers Limited Digital phase-locked loop
US4519086A (en) * 1982-06-16 1985-05-21 Western Digital Corporation MOS Phase lock loop synchronization circuit
US4617679A (en) * 1983-09-20 1986-10-14 Nec Electronics U.S.A., Inc. Digital phase lock loop circuit
US4574243A (en) * 1984-01-03 1986-03-04 Motorola, Inc. Multiple frequency digital phase locked loop
US4644420A (en) * 1984-03-29 1987-02-17 Archive Corporation Circuit and methodology for reading and tracking binary data from magnetic tape independently of the data pattern on the tape
EP0185779B1 (de) * 1984-12-21 1990-02-28 International Business Machines Corporation Digitale Phasenregelschleife
US4808884A (en) * 1985-12-02 1989-02-28 Western Digital Corporation High order digital phase-locked loop system
US4803680A (en) * 1985-12-27 1989-02-07 Nec Corporation Destuffing circuit with a digital phase-locked loop

Also Published As

Publication number Publication date
US4975930A (en) 1990-12-04
EP0367378A3 (de) 1992-01-22
JPH02257718A (ja) 1990-10-18
EP0367378B1 (de) 1996-09-11
CA1307327C (en) 1992-09-08
DE68927148T2 (de) 1997-01-30
DE68927148D1 (de) 1996-10-17
EP0367378A2 (de) 1990-05-09

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties