ATE172310T1 - Datencache-speicher und verfahren zur speicherfehlerbehandlung während zurückschreiben - Google Patents

Datencache-speicher und verfahren zur speicherfehlerbehandlung während zurückschreiben

Info

Publication number
ATE172310T1
ATE172310T1 AT92300017T AT92300017T ATE172310T1 AT E172310 T1 ATE172310 T1 AT E172310T1 AT 92300017 T AT92300017 T AT 92300017T AT 92300017 T AT92300017 T AT 92300017T AT E172310 T1 ATE172310 T1 AT E172310T1
Authority
AT
Austria
Prior art keywords
data
data cache
processor
write buffer
error handling
Prior art date
Application number
AT92300017T
Other languages
English (en)
Inventor
Stephen C Horne
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE172310T1 publication Critical patent/ATE172310T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT92300017T 1991-02-05 1992-01-02 Datencache-speicher und verfahren zur speicherfehlerbehandlung während zurückschreiben ATE172310T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/650,681 US5295259A (en) 1991-02-05 1991-02-05 Data cache and method for handling memory errors during copy-back

Publications (1)

Publication Number Publication Date
ATE172310T1 true ATE172310T1 (de) 1998-10-15

Family

ID=24609860

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92300017T ATE172310T1 (de) 1991-02-05 1992-01-02 Datencache-speicher und verfahren zur speicherfehlerbehandlung während zurückschreiben

Country Status (6)

Country Link
US (1) US5295259A (de)
EP (1) EP0498520B1 (de)
JP (1) JPH04336641A (de)
AT (1) ATE172310T1 (de)
DE (1) DE69227267T2 (de)
ES (1) ES2121818T3 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994010632A1 (de) * 1992-11-04 1994-05-11 Siemens Aktiengesellschaft Anordnung mit mehreren aktiven und passiven busteilnehmern
US5479636A (en) * 1992-11-16 1995-12-26 Intel Corporation Concurrent cache line replacement method and apparatus in microprocessor system with write-back cache memory
US5594863A (en) * 1995-06-26 1997-01-14 Novell, Inc. Method and apparatus for network file recovery
TW379298B (en) * 1996-09-30 2000-01-11 Toshiba Corp Memory updating history saving device and memory updating history saving method
JP3489967B2 (ja) 1997-06-06 2004-01-26 松下電器産業株式会社 半導体記憶装置及びキャッシュメモリ装置
US20050240806A1 (en) * 2004-03-30 2005-10-27 Hewlett-Packard Development Company, L.P. Diagnostic memory dump method in a redundant processor
US7441081B2 (en) * 2004-12-29 2008-10-21 Lsi Corporation Write-back caching for disk drives
EP2073553A1 (de) * 2007-12-21 2009-06-24 Thomson Licensing Verfahren und Vorrichtung zur Entblockungsfilterung eines Videobildes
US20130166251A1 (en) * 2011-12-23 2013-06-27 Robert A. Latimer Particle monitoring with secure data logging
JP5800058B2 (ja) * 2014-05-26 2015-10-28 富士通株式会社 情報処理装置、制御方法および制御プログラム

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4392200A (en) * 1980-01-28 1983-07-05 Digital Equipment Corporation Cached multiprocessor system with pipeline timing
US4523275A (en) * 1980-11-14 1985-06-11 Sperry Corporation Cache/disk subsystem with floating entry
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US5025366A (en) * 1988-01-20 1991-06-18 Advanced Micro Devices, Inc. Organization of an integrated cache unit for flexible usage in cache system design
US5065354A (en) * 1988-09-16 1991-11-12 Compaq Computer Corporation Queued posted-write disk write method with improved error handling
US4995041A (en) * 1989-02-03 1991-02-19 Digital Equipment Corporation Write back buffer with error correcting capabilities
DE3912705C2 (de) * 1989-04-18 1996-06-20 Siemens Nixdorf Inf Syst Verfahren und Anordnung zur Steuerung des Datenaustausches bei Schreibanforderungen von Verarbeitungseinheiten an einen Cachespeicher
US5155824A (en) * 1989-05-15 1992-10-13 Motorola, Inc. System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
US5197144A (en) * 1990-02-26 1993-03-23 Motorola, Inc. Data processor for reloading deferred pushes in a copy-back data cache

Also Published As

Publication number Publication date
EP0498520B1 (de) 1998-10-14
ES2121818T3 (es) 1998-12-16
EP0498520A2 (de) 1992-08-12
US5295259A (en) 1994-03-15
DE69227267D1 (de) 1998-11-19
JPH04336641A (ja) 1992-11-24
EP0498520A3 (en) 1993-07-14
DE69227267T2 (de) 1999-06-10

Similar Documents

Publication Publication Date Title
KR100204741B1 (ko) 제1및 제2캐시 메모리 사용방법
KR920000040A (ko) 카피-백 데이타 캐시를 구비한 데이타 치리기
EP0348652A3 (de) Prüfpunkt-Wiederholungssystem
ATE172310T1 (de) Datencache-speicher und verfahren zur speicherfehlerbehandlung während zurückschreiben
US6038631A (en) Data processing system and method using virtual storage system
EP0377436A3 (de) Vorrichtung und Verfahren zur Operandenverfügbarkeitserhöhung in einer Datenverarbeitungseinheit mit einer Durchschreibcache
ES8606688A1 (es) Procedimiento para controlar una memoria intermedia de un aparato de proceso de datos
DE69429059D1 (de) Adaptive speichersteureinrichtung für ein symmetrisches mehrprozessorsystem
EP0310446A3 (de) Verwaltungsverfahren für einen Cachespeicher
JP3145479B2 (ja) マルチプロセッサシステムとそのキャッシュメモリ制御方法および装置
JPS6141019B2 (de)
JPS58121190A (ja) 記憶制御方式
JP3047992B2 (ja) 主記憶キー制御方法
JPS6027045A (ja) パツフア記憶の誤りデ−タ切離し方法
JPS5999522A (ja) 入出力制御方式
JPS6222165A (ja) 主記憶装置アクセス制御方式
JPS5712469A (en) Buffer memory control system
JPH03189844A (ja) 情報処理装置
JPS6385949A (ja) キヤツシユメモリストア方式
JPH0567975B2 (de)
JPH0497459A (ja) キャッシュ一致処理方式
JPS6244850A (ja) 書き込みキヤンセル制御方式
JPH03260824A (ja) ディスクキャッシュ制御方式
JPH04114228A (ja) ディスクキャッシュシステム
KR970071241A (ko) 다중처리 시스템의 캐시 스테이트 램(ram) 관리방법

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties