ATE175042T1 - Datenübereinstimmung zwischen cache-speichern und dem hauptspeicher in einem multiprozessorsystem - Google Patents

Datenübereinstimmung zwischen cache-speichern und dem hauptspeicher in einem multiprozessorsystem

Info

Publication number
ATE175042T1
ATE175042T1 AT89309861T AT89309861T ATE175042T1 AT E175042 T1 ATE175042 T1 AT E175042T1 AT 89309861 T AT89309861 T AT 89309861T AT 89309861 T AT89309861 T AT 89309861T AT E175042 T1 ATE175042 T1 AT E175042T1
Authority
AT
Austria
Prior art keywords
data
cache
processor
main memory
scu
Prior art date
Application number
AT89309861T
Other languages
English (en)
Inventor
David A Webb Jr
Michael E Flynn
Ricky C Hetherington
Tryggve Fossum
Scott Arnold
La Hunt Stephen J De
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE175042T1 publication Critical patent/ATE175042T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
AT89309861T 1989-02-03 1989-09-28 Datenübereinstimmung zwischen cache-speichern und dem hauptspeicher in einem multiprozessorsystem ATE175042T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US30677689A 1989-02-03 1989-02-03

Publications (1)

Publication Number Publication Date
ATE175042T1 true ATE175042T1 (de) 1999-01-15

Family

ID=23186785

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89309861T ATE175042T1 (de) 1989-02-03 1989-09-28 Datenübereinstimmung zwischen cache-speichern und dem hauptspeicher in einem multiprozessorsystem

Country Status (5)

Country Link
EP (1) EP0380861B1 (de)
JP (1) JPH0315965A (de)
AT (1) ATE175042T1 (de)
CA (1) CA1325289C (de)
DE (1) DE68928887T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4037332C2 (de) * 1990-11-23 1995-06-29 Siemens Nixdorf Inf Syst Verfahren zur Fehlerüberwachung der Datenkonsistenz in einem Datenverarbeitungssystem und Schaltungsanordnung zur Durchführung des Verfahrens
US5724549A (en) * 1992-04-06 1998-03-03 Cyrix Corporation Cache coherency without bus master arbitration signals
EP0567708A1 (de) * 1992-04-30 1993-11-03 International Business Machines Corporation Einrichtung zur Optimierung der Ungültigkeitserklärung eines Cachespeichers
JP3360933B2 (ja) * 1994-06-01 2003-01-07 富士通株式会社 情報処理システムにおける記憶制御方法および記憶制御装置
EP0735481B1 (de) * 1995-03-31 2003-05-14 Sun Microsystems, Inc. Mechanismus auf Systemebene zum Entwerten von Daten, die im externen Cache eines Prozessors in einem Computersystem gespeichert sind

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53116041A (en) * 1977-03-18 1978-10-11 Nec Corp System controller
US4503497A (en) * 1982-05-27 1985-03-05 International Business Machines Corporation System for independent cache-to-cache transfer

Also Published As

Publication number Publication date
JPH0315965A (ja) 1991-01-24
DE68928887T2 (de) 1999-08-05
DE68928887D1 (de) 1999-02-04
CA1325289C (en) 1993-12-14
EP0380861B1 (de) 1998-12-23
EP0380861A3 (de) 1991-06-12
EP0380861A2 (de) 1990-08-08

Similar Documents

Publication Publication Date Title
US4959777A (en) Write-shared cache circuit for multiprocessor system
Stenstrom A survey of cache coherence schemes for multiprocessors
US5226150A (en) Apparatus for suppressing an error report from an address for which an error has already been reported
Katz et al. Implementing a cache consistency protocol
US5652859A (en) Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues
US8250334B2 (en) Providing metadata in a translation lookaside buffer (TLB)
US6073211A (en) Method and system for memory updates within a multiprocessor data processing system
US6438660B1 (en) Method and apparatus for collapsing writebacks to a memory for resource efficiency
US6625698B2 (en) Method and apparatus for controlling memory storage locks based on cache line ownership
US20060095673A1 (en) Mechanism for resolving ambiguous invalidates in a computer system
KR20240122529A (ko) 근접 메모리 컴퓨팅 요소들에 대한 일관성 디렉토리 제어기 오버헤드를 줄이기 위한 메커니즘
US6098156A (en) Method and system for rapid line ownership transfer for multiprocessor updates
EP0358863A2 (de) Laden/Speichern mit Schreibabsicht für Nachschreib-Cache-Speicher
US7003635B2 (en) Generalized active inheritance consistency mechanism having linked writes
US8312225B2 (en) Method and apparatus for supporting scalable coherence on many-core products through restricted exposure
JP3700787B2 (ja) セマフォ・バイパス法
US7051163B2 (en) Directory structure permitting efficient write-backs in a shared memory computer system
US7895400B2 (en) Hybrid cache coherence using fine-grained hardware message passing
US8117399B2 (en) Processing of coherent and incoherent accesses at a uniform cache
US6560681B1 (en) Split sparse directory for a distributed shared memory multiprocessor system
US6898676B2 (en) Computer system supporting both dirty-shared and non-dirty-shared data processing entities
US6598120B1 (en) Assignment of building block collector agent to receive acknowledgments from other building block agents
US20060236039A1 (en) Method and apparatus for synchronizing shared data between components in a group
ATE175042T1 (de) Datenübereinstimmung zwischen cache-speichern und dem hauptspeicher in einem multiprozessorsystem
US5526512A (en) Dynamic management of snoop granularity for a coherent asynchronous DMA cache

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties