ATE187844T1 - Verfahren zur herstellung einer oxidschicht in der halbleitertechnik - Google Patents

Verfahren zur herstellung einer oxidschicht in der halbleitertechnik

Info

Publication number
ATE187844T1
ATE187844T1 AT95304917T AT95304917T ATE187844T1 AT E187844 T1 ATE187844 T1 AT E187844T1 AT 95304917 T AT95304917 T AT 95304917T AT 95304917 T AT95304917 T AT 95304917T AT E187844 T1 ATE187844 T1 AT E187844T1
Authority
AT
Austria
Prior art keywords
layer
semiconductor body
oxide
gate
heavily
Prior art date
Application number
AT95304917T
Other languages
English (en)
Inventor
H Jim Fulford Jr
Mark I Gardner
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE187844T1 publication Critical patent/ATE187844T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01342—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid by deposition, e.g. evaporation, ALD or laser deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01344—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a nitrogen-containing ambient, e.g. N2O oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01346—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a gaseous ambient using an oxygen or a water vapour, e.g. oxidation through a layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Formation Of Insulating Films (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
AT95304917T 1994-07-26 1995-07-13 Verfahren zur herstellung einer oxidschicht in der halbleitertechnik ATE187844T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/280,416 US5498577A (en) 1994-07-26 1994-07-26 Method for fabricating thin oxides for a semiconductor technology

Publications (1)

Publication Number Publication Date
ATE187844T1 true ATE187844T1 (de) 2000-01-15

Family

ID=23072985

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95304917T ATE187844T1 (de) 1994-07-26 1995-07-13 Verfahren zur herstellung einer oxidschicht in der halbleitertechnik

Country Status (5)

Country Link
US (1) US5498577A (de)
EP (1) EP0696051B1 (de)
JP (2) JPH08172138A (de)
AT (1) ATE187844T1 (de)
DE (1) DE69513899T2 (de)

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US5869405A (en) 1996-01-03 1999-02-09 Micron Technology, Inc. In situ rapid thermal etch and rapid thermal oxidation
US5741737A (en) * 1996-06-27 1998-04-21 Cypress Semiconductor Corporation MOS transistor with ramped gate oxide thickness and method for making same
US6033943A (en) * 1996-08-23 2000-03-07 Advanced Micro Devices, Inc. Dual gate oxide thickness integrated circuit and process for making same
JP3593825B2 (ja) * 1996-11-08 2004-11-24 ソニー株式会社 半導体装置及びその製造方法、並びに固体撮像素子の製造方法
US6461984B1 (en) * 1997-03-18 2002-10-08 Korea Advanced Institute Of Science & Technology Semiconductor device using N2O plasma oxide and a method of fabricating the same
US5937308A (en) * 1997-03-26 1999-08-10 Advanced Micro Devices, Inc. Semiconductor trench isolation structure formed substantially within a single chamber
US5904542A (en) * 1997-03-26 1999-05-18 Advanced Micro Devices, Inc. Performing a semiconductor fabrication sequence within a common chamber and without opening the chamber beginning with forming a field dielectric and concluding with a gate dielectric
US5891793A (en) * 1997-04-04 1999-04-06 Advanced Micro Devices, Inc. Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation
US6051510A (en) * 1997-05-02 2000-04-18 Advanced Micro Devices, Inc. Method of using a hard mask to grow dielectrics with varying characteristics
US6037224A (en) * 1997-05-02 2000-03-14 Advanced Micro Devices, Inc. Method for growing dual oxide thickness using nitrided oxides for oxidation suppression
US6555484B1 (en) * 1997-06-19 2003-04-29 Cypress Semiconductor Corp. Method for controlling the oxidation of implanted silicon
US6100149A (en) * 1997-07-01 2000-08-08 Steag Rtp Systems Method for rapid thermal processing (RTP) of silicon substrates
US5935650A (en) * 1997-10-17 1999-08-10 Lerch; Wilfried Method of oxidation of semiconductor wafers in a rapid thermal processing (RTP) system
US5918133A (en) * 1997-12-18 1999-06-29 Advanced Micro Devices Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof
US6146934A (en) * 1997-12-19 2000-11-14 Advanced Micro Devices, Inc. Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof
US6077751A (en) * 1998-01-29 2000-06-20 Steag Rtp Systems Gmbh Method of rapid thermal processing (RTP) of ion implanted silicon
US6221789B1 (en) * 1998-07-29 2001-04-24 Intel Corporation Thin oxides of silicon
US6235590B1 (en) 1998-12-18 2001-05-22 Lsi Logic Corporation Fabrication of differential gate oxide thicknesses on a single integrated circuit chip
KR100455737B1 (ko) 1998-12-30 2005-04-19 주식회사 하이닉스반도체 반도체소자의게이트산화막형성방법
JP2000232222A (ja) 1999-02-10 2000-08-22 Nec Corp 半導体装置の製造方法
US6110780A (en) * 1999-04-01 2000-08-29 Taiwan Semiconductor Manufacturing Company Using NO or N2 O treatment to generate different oxide thicknesses in one oxidation step for single poly non-volatile memory
US6380033B1 (en) * 1999-09-20 2002-04-30 Advanced Micro Devices, Inc. Process to improve read disturb for NAND flash memory devices
US6284602B1 (en) * 1999-09-20 2001-09-04 Advanced Micro Devices, Inc. Process to reduce post cycling program VT dispersion for NAND flash memory devices
US6407008B1 (en) 2000-05-05 2002-06-18 Integrated Device Technology, Inc. Method of forming an oxide layer
US6339001B1 (en) 2000-06-16 2002-01-15 International Business Machines Corporation Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist
US6261972B1 (en) * 2000-11-06 2001-07-17 Infineon Technologies Ag Dual gate oxide process for uniform oxide thickness
JP2003168796A (ja) * 2001-11-30 2003-06-13 Sanyo Electric Co Ltd 半導体装置の製造方法
US6635584B2 (en) * 2001-12-28 2003-10-21 Texas Instruments Incorporated Versatile system for forming uniform wafer surfaces
US6821868B2 (en) * 2002-12-27 2004-11-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming nitrogen enriched gate dielectric with low effective oxide thickness
US9123572B2 (en) 2004-05-06 2015-09-01 Sidense Corporation Anti-fuse memory cell
WO2005109516A1 (en) * 2004-05-06 2005-11-17 Sidense Corp. Split-channel antifuse array architecture
US7879694B1 (en) 2004-07-13 2011-02-01 National Semiconductor Corporation System and method for applying a pre-gate plasma etch in a semiconductor device manufacturing process
KR100933835B1 (ko) * 2007-11-12 2009-12-24 주식회사 하이닉스반도체 플래시 메모리 소자의 제조 방법
US20110147817A1 (en) * 2009-12-17 2011-06-23 Infineon Technologies Austria Ag Semiconductor component having an oxide layer

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Also Published As

Publication number Publication date
US5498577A (en) 1996-03-12
EP0696051B1 (de) 1999-12-15
DE69513899D1 (de) 2000-01-20
EP0696051A1 (de) 1996-02-07
JPH08172138A (ja) 1996-07-02
JP2008028403A (ja) 2008-02-07
DE69513899T2 (de) 2000-06-21

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Legal Events

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