ATE188557T1 - Verfahren und anordung zur erzeugung von summeinformation-/rundungskontrolle-signal - Google Patents

Verfahren und anordung zur erzeugung von summeinformation-/rundungskontrolle-signal

Info

Publication number
ATE188557T1
ATE188557T1 AT92308407T AT92308407T ATE188557T1 AT E188557 T1 ATE188557 T1 AT E188557T1 AT 92308407 T AT92308407 T AT 92308407T AT 92308407 T AT92308407 T AT 92308407T AT E188557 T1 ATE188557 T1 AT E188557T1
Authority
AT
Austria
Prior art keywords
control signal
arrangement
rounding control
sum information
generating sum
Prior art date
Application number
AT92308407T
Other languages
English (en)
Inventor
Charles E Hauck Jr
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ATE188557T1 publication Critical patent/ATE188557T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49952—Sticky bit

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Selective Calling Equipment (AREA)
  • Image Processing (AREA)
  • Hardware Redundancy (AREA)
AT92308407T 1991-09-20 1992-09-16 Verfahren und anordung zur erzeugung von summeinformation-/rundungskontrolle-signal ATE188557T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/763,127 US5245563A (en) 1991-09-20 1991-09-20 Fast control for round unit

Publications (1)

Publication Number Publication Date
ATE188557T1 true ATE188557T1 (de) 2000-01-15

Family

ID=25066950

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92308407T ATE188557T1 (de) 1991-09-20 1992-09-16 Verfahren und anordung zur erzeugung von summeinformation-/rundungskontrolle-signal

Country Status (6)

Country Link
US (1) US5245563A (de)
EP (1) EP0539010B1 (de)
JP (1) JPH05204602A (de)
AT (1) ATE188557T1 (de)
CA (1) CA2078319C (de)
DE (1) DE69230520T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5671171A (en) * 1995-07-05 1997-09-23 Sun Microsystems, Inc. Shared rounding hardware for multiplier and divider/square root unit using conditional sum adder
US6374329B1 (en) 1996-02-20 2002-04-16 Intergraph Corporation High-availability super server
US6026474A (en) * 1996-11-22 2000-02-15 Mangosoft Corporation Shared client-side web caching using globally addressable memory
US5909540A (en) * 1996-11-22 1999-06-01 Mangosoft Corporation System and method for providing highly available data storage using globally addressable memory
US6647393B1 (en) 1996-11-22 2003-11-11 Mangosoft Corporation Dynamic directory service
US6148377A (en) * 1996-11-22 2000-11-14 Mangosoft Corporation Shared memory computer networks
US5987506A (en) * 1996-11-22 1999-11-16 Mangosoft Corporation Remote access and geographically distributed computers in a globally addressable storage environment
US7058696B1 (en) 1996-11-22 2006-06-06 Mangosoft Corporation Internet-based shared file service with native PC client access and semantics
GB2575121B (en) 2018-06-29 2022-12-28 Imagination Tech Ltd Guaranteed data compression
GB2575122B (en) 2018-06-29 2021-12-01 Imagination Tech Ltd Mapping an n-bit number to an m-bit number
GB2575434B (en) 2018-06-29 2020-07-22 Imagination Tech Ltd Guaranteed data compression
GB2608878B (en) 2018-06-29 2023-04-12 Imagination Tech Ltd Guaranteed data compression

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4179734A (en) * 1976-07-02 1979-12-18 Floating Point Systems, Inc. Floating point data processor having fast access memory means
US4480963A (en) * 1982-11-22 1984-11-06 Deere & Company Pump swashplate control assist
IT1157960B (it) * 1982-11-29 1987-02-18 Fiat Veicoli Ind Dispositivo per focalizzare ed omogeneizzare un fascio laser
US4589084A (en) * 1983-05-16 1986-05-13 Rca Corporation Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals
US4589087A (en) * 1983-06-30 1986-05-13 International Business Machines Corporation Condition register architecture for a primitive instruction set machine
JPS61213927A (ja) * 1985-03-18 1986-09-22 Hitachi Ltd 浮動小数点演算処理装置
US5055999A (en) * 1987-12-22 1991-10-08 Kendall Square Research Corporation Multiprocessor digital data processing system
US5119481A (en) * 1987-12-22 1992-06-02 Kendall Square Research Corporation Register bus multiprocessor system with shift
US4924422A (en) * 1988-02-17 1990-05-08 International Business Machines Corporation Method and apparatus for modified carry-save determination of arithmetic/logic zero results
JPH01277931A (ja) * 1988-04-29 1989-11-08 Nec Ic Microcomput Syst Ltd 零検出回路
US4972362A (en) * 1988-06-17 1990-11-20 Bipolar Integrated Technology, Inc. Method and apparatus for implementing binary multiplication using booth type multiplication
CA2019299C (en) * 1989-06-22 2002-01-15 Steven Frank Multiprocessor system with multiple instruction sources
CA2019300C (en) * 1989-06-22 2001-06-12 Kendall Square Research Corporation Multiprocessor system with shared memory

Also Published As

Publication number Publication date
EP0539010B1 (de) 2000-01-05
EP0539010A2 (de) 1993-04-28
US5245563A (en) 1993-09-14
EP0539010A3 (en) 1994-06-15
CA2078319A1 (en) 1993-03-21
DE69230520T2 (de) 2000-07-27
JPH05204602A (ja) 1993-08-13
CA2078319C (en) 2000-07-18
DE69230520D1 (de) 2000-02-10

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