ATE213872T1 - Schutzstruktur mit versetzten kontakten zum schutz vor elektrostatischer entladung - Google Patents

Schutzstruktur mit versetzten kontakten zum schutz vor elektrostatischer entladung

Info

Publication number
ATE213872T1
ATE213872T1 AT96939640T AT96939640T ATE213872T1 AT E213872 T1 ATE213872 T1 AT E213872T1 AT 96939640 T AT96939640 T AT 96939640T AT 96939640 T AT96939640 T AT 96939640T AT E213872 T1 ATE213872 T1 AT E213872T1
Authority
AT
Austria
Prior art keywords
row
contacts
contact
electrostatic discharge
protect against
Prior art date
Application number
AT96939640T
Other languages
English (en)
Inventor
Joseph C Sher
Manny K F Ma
Stephen L Casper
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE213872T1 publication Critical patent/ATE213872T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
AT96939640T 1995-11-13 1996-11-13 Schutzstruktur mit versetzten kontakten zum schutz vor elektrostatischer entladung ATE213872T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US55918495A 1995-11-13 1995-11-13
PCT/US1996/018049 WO1997018587A1 (en) 1995-11-13 1996-11-13 Semiconductor interlayer staggered contact structure

Publications (1)

Publication Number Publication Date
ATE213872T1 true ATE213872T1 (de) 2002-03-15

Family

ID=24232621

Family Applications (1)

Application Number Title Priority Date Filing Date
AT96939640T ATE213872T1 (de) 1995-11-13 1996-11-13 Schutzstruktur mit versetzten kontakten zum schutz vor elektrostatischer entladung

Country Status (8)

Country Link
US (1) US5801421A (de)
EP (1) EP0861503B1 (de)
JP (1) JP4041873B2 (de)
KR (1) KR100298820B1 (de)
AT (1) ATE213872T1 (de)
AU (1) AU7676796A (de)
DE (1) DE69619541T2 (de)
WO (1) WO1997018587A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW388912B (en) * 1996-04-22 2000-05-01 Toshiba Corp Semiconductor device and method of manufacturing the same
US6526548B1 (en) * 1999-07-23 2003-02-25 International Business Machines Corporation Method for evaluating circuit design for ESD electrostatic discharge robustness
US20070176295A1 (en) * 2006-02-01 2007-08-02 International Business Machines Corporation Contact via scheme with staggered vias
TWI321873B (en) * 2006-07-10 2010-03-11 Fci Connectors Singapore Pte High speed connector
US7462038B2 (en) 2007-02-20 2008-12-09 Qimonda Ag Interconnection structure and method of manufacturing the same
US8325529B2 (en) 2009-08-03 2012-12-04 Sandisk Technologies Inc. Bit-line connections for non-volatile storage

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3868166A (en) * 1973-07-16 1975-02-25 Elfab Corp Printed circuit board connector having contacts arranged in a staggered grid array
US4242720A (en) * 1977-09-09 1980-12-30 Donn Moore Integrated circuit mounting board having internal termination resistors
US4616406A (en) * 1984-09-27 1986-10-14 Advanced Micro Devices, Inc. Process of making a semiconductor device having parallel leads directly connected perpendicular to integrated circuit layers therein
US4760554A (en) * 1986-08-15 1988-07-26 Texas Instruments Incorporated Staggered contacts in arrays of programmable memory cells
US5060037A (en) * 1987-04-03 1991-10-22 Texas Instruments Incorporated Output buffer with enhanced electrostatic discharge protection
JPS647549A (en) * 1987-06-30 1989-01-11 Fujitsu Ltd Integrated circuit
JPH01117045A (ja) * 1987-10-29 1989-05-09 Seiko Epson Corp 半導体集積回路装置
US5247197A (en) * 1987-11-05 1993-09-21 Fujitsu Limited Dynamic random access memory device having improved contact hole structures
JP2667866B2 (ja) * 1988-03-25 1997-10-27 株式会社日立製作所 多層配線構造
JP2580301B2 (ja) * 1988-12-27 1997-02-12 株式会社日立製作所 半導体集積回路装置
JPH02178975A (ja) * 1988-12-29 1990-07-11 Fuji Electric Co Ltd Ｍｏｓ型半導体装置
JP2777896B2 (ja) * 1989-01-20 1998-07-23 富士通株式会社 半導体記憶装置
US5066999A (en) * 1989-10-23 1991-11-19 Micron Technology, Inc. Resistor under wirebond pad
JPH03149827A (ja) * 1989-11-07 1991-06-26 Seiko Epson Corp 半導体装置
US5153507A (en) * 1990-11-16 1992-10-06 Vlsi Technology, Inc. Multi-purpose bond pad test die
KR940006689B1 (ko) * 1991-10-21 1994-07-25 삼성전자 주식회사 반도체장치의 접촉창 형성방법
US5343366A (en) * 1992-06-24 1994-08-30 International Business Machines Corporation Packages for stacked integrated circuit chip cubes
US5451799A (en) * 1992-12-28 1995-09-19 Matsushita Electric Industrial Co., Ltd. MOS transistor for protection against electrostatic discharge
JP2638462B2 (ja) * 1993-12-29 1997-08-06 日本電気株式会社 半導体装置

Also Published As

Publication number Publication date
DE69619541D1 (de) 2002-04-04
EP0861503A1 (de) 1998-09-02
DE69619541T2 (de) 2002-08-29
JPH11504765A (ja) 1999-04-27
JP4041873B2 (ja) 2008-02-06
WO1997018587A1 (en) 1997-05-22
US5801421A (en) 1998-09-01
AU7676796A (en) 1997-06-05
KR100298820B1 (ko) 2001-11-02
EP0861503B1 (de) 2002-02-27
KR19990067503A (ko) 1999-08-25

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties