ATE214192T1 - Eine integrierte schaltung mit freigabesteuerschaltung - Google Patents

Eine integrierte schaltung mit freigabesteuerschaltung

Info

Publication number
ATE214192T1
ATE214192T1 AT96923430T AT96923430T ATE214192T1 AT E214192 T1 ATE214192 T1 AT E214192T1 AT 96923430 T AT96923430 T AT 96923430T AT 96923430 T AT96923430 T AT 96923430T AT E214192 T1 ATE214192 T1 AT E214192T1
Authority
AT
Austria
Prior art keywords
circuit
standby
signal
response
internal
Prior art date
Application number
AT96923430T
Other languages
English (en)
Inventor
Fariborz F Roohparvar
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE214192T1 publication Critical patent/ATE214192T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Credit Cards Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Read Only Memory (AREA)
AT96923430T 1995-06-29 1996-06-24 Eine integrierte schaltung mit freigabesteuerschaltung ATE214192T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/496,436 US5524096A (en) 1995-06-29 1995-06-29 Circuit for generating a delayed standby signal in response to an external standby command
PCT/US1996/010876 WO1997001846A1 (en) 1995-06-29 1996-06-24 An integrated circuit having enable control circuitry

Publications (1)

Publication Number Publication Date
ATE214192T1 true ATE214192T1 (de) 2002-03-15

Family

ID=23972609

Family Applications (1)

Application Number Title Priority Date Filing Date
AT96923430T ATE214192T1 (de) 1995-06-29 1996-06-24 Eine integrierte schaltung mit freigabesteuerschaltung

Country Status (8)

Country Link
US (2) US5524096A (de)
EP (1) EP0840928B1 (de)
JP (1) JPH10510388A (de)
KR (1) KR100284985B1 (de)
AT (1) ATE214192T1 (de)
AU (1) AU6394396A (de)
DE (1) DE69619679T2 (de)
WO (1) WO1997001846A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5524096A (en) * 1995-06-29 1996-06-04 Micron Quantum Devices, Inc. Circuit for generating a delayed standby signal in response to an external standby command
US5787484A (en) 1996-08-08 1998-07-28 Micron Technology, Inc. System and method which compares data preread from memory cells to data to be written to the cells
US5754567A (en) 1996-10-15 1998-05-19 Micron Quantum Devices, Inc. Write reduction in flash memory systems through ECC usage
US6260149B1 (en) * 1997-02-12 2001-07-10 Intel Corporation Method and apparatus for logic and power isolation during power management
US6289476B1 (en) 1998-06-10 2001-09-11 Micron Technology, Inc. Method and apparatus for testing the timing of integrated circuits
JP2001344987A (ja) * 2000-05-29 2001-12-14 Nec Corp 半導体記憶装置及びデータの読み出し方法
KR100380025B1 (ko) * 2001-04-18 2003-04-18 삼성전자주식회사 반도체 메모리 장치에 적용되는 입력 버퍼의 노이즈면역성 향상장치
US6510096B2 (en) * 2001-04-27 2003-01-21 Samsung Electronics Co., Ltd. Power down voltage control method and apparatus
US7177208B2 (en) * 2005-03-11 2007-02-13 Micron Technology, Inc. Circuit and method for operating a delay-lock loop in a power saving manner
US7747903B2 (en) 2007-07-09 2010-06-29 Micron Technology, Inc. Error correction for memory
WO2009058128A1 (en) * 2007-10-30 2009-05-07 Agere Systems Inc. Electrostatic discharge protection circuit
US8908709B1 (en) * 2009-01-08 2014-12-09 Juniper Networks, Inc. Methods and apparatus for power management associated with a switch fabric
US8578191B2 (en) 2010-06-10 2013-11-05 Juniper Networks, Inc. Dynamic fabric plane allocation for power savings
KR102375058B1 (ko) 2015-08-31 2022-03-17 에스케이하이닉스 주식회사 반도체 장치 및 시스템
TWI702611B (zh) * 2018-12-06 2020-08-21 旺宏電子股份有限公司 記憶體電路
US11508422B2 (en) 2019-08-02 2022-11-22 Micron Technology, Inc. Methods for memory power management and memory devices and systems employing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4959816A (en) * 1987-12-28 1990-09-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
JPH0289292A (ja) * 1988-09-26 1990-03-29 Toshiba Corp 半導体メモリ
JP2728533B2 (ja) * 1990-01-19 1998-03-18 富士通株式会社 半導体装置
US5524096A (en) * 1995-06-29 1996-06-04 Micron Quantum Devices, Inc. Circuit for generating a delayed standby signal in response to an external standby command

Also Published As

Publication number Publication date
KR100284985B1 (ko) 2001-03-15
EP0840928A1 (de) 1998-05-13
US5680352A (en) 1997-10-21
DE69619679D1 (de) 2002-04-11
JPH10510388A (ja) 1998-10-06
DE69619679T2 (de) 2002-10-17
EP0840928A4 (de) 1998-12-02
US5524096A (en) 1996-06-04
WO1997001846A1 (en) 1997-01-16
KR19990028475A (ko) 1999-04-15
EP0840928B1 (de) 2002-03-06
AU6394396A (en) 1997-01-30

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties