KR970077998A - 동기화 반도체 메모리에 사용하기 위한 제어된 지연 회로 - Google Patents

동기화 반도체 메모리에 사용하기 위한 제어된 지연 회로 Download PDF

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KR970077998A
KR970077998A KR1019970019100A KR19970019100A KR970077998A KR 970077998 A KR970077998 A KR 970077998A KR 1019970019100 A KR1019970019100 A KR 1019970019100A KR 19970019100 A KR19970019100 A KR 19970019100A KR 970077998 A KR970077998 A KR 970077998A
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delay
circuit
synchronization signal
controlled
comparing
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KR100249415B1 (ko
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신지 사쿠라기
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가네꼬 히사시
닛폰 덴키 가부시끼가이샤
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Pulse Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

기준 회로와, 내부 회로를 제어하는 지연 회로, 및 기준 딜레이의 지연량을 외부 동기 회로의 사이클과 비교하고, 그 비교의 결과에 기초해서 지연 회로의 지연 시간을 자동으로 조정하는 비교 및 조정 수단을 포함하는, 동기화 반도체 메모리에 사용하기 위한 제어된 지연 회로.

Description

동기화 반도체 메모리에 사용하기 위한 제어된 지연 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제7도는 동기화 반도체 메모리에 사용하기 위한 본 발명에 따른 제어된 지연회로의 제1구체예의 회로도이다. 제12도는 동기화 반도체 메모리에 사용하기 위한 본 발명에 따른 제어된 지연회로의 제2 구체예의 회로도이다.

Claims (4)

  1. 동기화 반도체 메모리에 사용하기 위한 제어된 지연 회로에 있어서, 기준 딜레이와, 내부 회로를 제어하는 지연 회로, 및 기준 딜레이의 지연량을 외부 동기 신호의 사이클과 비교하고, 그 비교의 결과에 기초해서 지연 회로의 지연 시간을 자동으로 조정하는 비교 및 조정 수단을 포함하는 것을 특징으로 하는 제어된 지연 회로.
  2. 제1항에 있어서, 상기 비교 및 조정 수단은, 모드 레지스터 조정할 때에, 상기 기준 딜레이의 지연량을, 외부 동기 신호의 사이클과 자동적으로 비교하도록 구성된 것을 특징으로 하는 제어된 지연 회로.
  3. 동기화 반도체 메모리에 사용하기 위한 제어된 지연 회로에 있어서, 이 반도체 장치 칩 내에, 조정 가능한 지연량을 갖고, 지연된 내부 동기 신호를 출력하기 위한 내부 동기 신호를 수신하는 지연 회로와; 서로 다른 지연시간들을 갖는 다수의 지연된 신호를 출력하기 위한 외부 동기 신호를 수신하는 기준 딜레이와; 설계된 지연값과 실제 지연값 사이의 대-소 관계를 결정할 수 있도록, 다수의 지연신호의 각각을 외부 동기 신호의 상태변화 말단과 비교하기 위한 다수의 지연된 신호와 외부 동기 신호를 수신하는 비교수단; 및 지연된 내부 동기 신호의 실제 지연량을 설계된 지연량에 가깝게 만들 수 있도록, 상기 비교수단에 의해 주어진 실제 지연값과 설계된 지연값 사이의 대-소 관계에 기초해서 지연 회로의 조정 가능한 지연량을 조정하는 조정 수단을 포함하는 것을 특징으로 하는 제어된 지연 회로.
  4. 제3항에 있어서, 상기 기준 딜레이는 다수의 지연된 신호들 중의 하나가 최소 사이클 시간과 같은 지연 시간을 갖도록 구성된 것을 특징으로 하는 제어된 지연 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970019100A 1996-05-13 1997-05-13 동기화 반도체 메모리에 사용하기 위한 제어된 지연 회로 Expired - Fee Related KR100249415B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8142242A JPH09304484A (ja) 1996-05-13 1996-05-13 半導体記憶装置
JP96-142242 1996-05-13

Publications (2)

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KR970077998A true KR970077998A (ko) 1997-12-12
KR100249415B1 KR100249415B1 (ko) 2000-03-15

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US (1) US5768177A (ko)
JP (1) JPH09304484A (ko)
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US8065550B2 (en) 2007-11-02 2011-11-22 Hynix Semiconductor, Inc. Digital delay locked loop circuit using mode register set
KR102690235B1 (ko) * 2021-11-29 2024-08-05 주식회사 와이씨 타이밍 생성기를 포함하는 반도체 테스트 장치

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US6912680B1 (en) 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
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JPH1174783A (ja) * 1997-06-18 1999-03-16 Mitsubishi Electric Corp 内部クロック信号発生回路、および同期型半導体記憶装置
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US6101197A (en) 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
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US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
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US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
JP4212159B2 (ja) * 1998-09-28 2009-01-21 株式会社ルネサステクノロジ 同期型半導体記憶装置
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
JP4323009B2 (ja) * 1999-06-25 2009-09-02 富士通マイクロエレクトロニクス株式会社 半導体装置
US6111812A (en) * 1999-07-23 2000-08-29 Micron Technology, Inc. Method and apparatus for adjusting control signal timing in a memory device
KR100355229B1 (ko) * 2000-01-28 2002-10-11 삼성전자 주식회사 카스 명령의 동작 지연 기능을 구비한 반도체 메모리 장치및 이에 적용되는 버퍼와 신호전송 회로
US6337830B1 (en) * 2000-08-31 2002-01-08 Mosel Vitelic, Inc. Integrated clocking latency and multiplexer control technique for double data rate (DDR) synchronous dynamic random access memory (SDRAM) device data paths
KR100401491B1 (ko) * 2000-11-01 2003-10-11 주식회사 하이닉스반도체 데이터 출력 버퍼 제어 회로
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
JP3831277B2 (ja) * 2001-12-28 2006-10-11 株式会社東芝 半導体装置
DE10208716B4 (de) * 2002-02-28 2009-03-19 Qimonda Ag Steuerschaltung für ein S-DRAM
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US8753354B2 (en) * 2004-03-09 2014-06-17 John P. Cole Enhanced follicular extraction punch and method
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8065550B2 (en) 2007-11-02 2011-11-22 Hynix Semiconductor, Inc. Digital delay locked loop circuit using mode register set
KR102690235B1 (ko) * 2021-11-29 2024-08-05 주식회사 와이씨 타이밍 생성기를 포함하는 반도체 테스트 장치

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KR100249415B1 (ko) 2000-03-15
US5768177A (en) 1998-06-16

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