ATE221279T1 - Viterbi pipelinedekoder - Google Patents

Viterbi pipelinedekoder

Info

Publication number
ATE221279T1
ATE221279T1 AT94932131T AT94932131T ATE221279T1 AT E221279 T1 ATE221279 T1 AT E221279T1 AT 94932131 T AT94932131 T AT 94932131T AT 94932131 T AT94932131 T AT 94932131T AT E221279 T1 ATE221279 T1 AT E221279T1
Authority
AT
Austria
Prior art keywords
stage
sequence
validity
sample
decoder
Prior art date
Application number
AT94932131T
Other languages
English (en)
Inventor
Nan-Hsing Yeh
Charles R Olson
Original Assignee
Ampex
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ampex filed Critical Ampex
Application granted granted Critical
Publication of ATE221279T1 publication Critical patent/ATE221279T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6343—Error control coding in combination with techniques for partial response channels, e.g. recording
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Medicines Containing Plant Substances (AREA)
  • Detection And Correction Of Errors (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
AT94932131T 1993-10-29 1994-10-31 Viterbi pipelinedekoder ATE221279T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/146,365 US5410556A (en) 1993-10-29 1993-10-29 Pipelined viterbi decoder
PCT/US1994/012492 WO1995012249A1 (en) 1993-10-29 1994-10-31 Pipelined viterbi recorder

Publications (1)

Publication Number Publication Date
ATE221279T1 true ATE221279T1 (de) 2002-08-15

Family

ID=22517056

Family Applications (1)

Application Number Title Priority Date Filing Date
AT94932131T ATE221279T1 (de) 1993-10-29 1994-10-31 Viterbi pipelinedekoder

Country Status (6)

Country Link
US (1) US5410556A (de)
EP (1) EP0728382B1 (de)
JP (2) JPH09331264A (de)
AT (1) ATE221279T1 (de)
DE (1) DE69431065T2 (de)
WO (1) WO1995012249A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557538A (en) * 1994-05-18 1996-09-17 Zoran Microelectronics Ltd. MPEG decoder
US5633897A (en) * 1995-11-16 1997-05-27 Atmel Corporation Digital signal processor optimized for decoding a signal encoded in accordance with a Viterbi algorithm
CN1099165C (zh) * 1996-03-18 2003-01-15 三星电子株式会社 维特比译码器
US5949820A (en) * 1996-08-01 1999-09-07 Nec Electronics Inc. Method for optimizing an equalization and receive filter
US5808573A (en) * 1996-08-01 1998-09-15 Nec Electronics Incorporated Methods and structure for sampled-data timing recovery with reduced complexity and latency
DE69717412T2 (de) * 1996-09-17 2003-07-17 Koninklijke Philips Electronics N.V., Eindhoven Übertragungssystem mit verbesserter verriegelungserkennung
US5914989A (en) * 1997-02-19 1999-06-22 Nec Electronics, Inc. PRML system with reduced complexity maximum likelihood detector
US6167552A (en) * 1997-10-02 2000-12-26 Harris Corporation Apparatus for convolutional self-doubly orthogonal encoding and decoding
US6246731B1 (en) * 1998-07-30 2001-06-12 Stmicroelectronics, Inc. Method and structure for increasing the maximum channel speed of a given channel
US6404831B1 (en) 1998-10-07 2002-06-11 International Business Machines Corp. Data detection with digital filter detector
US6272661B1 (en) 1998-12-29 2001-08-07 Texas Instruments Incorporated Minimum memory implementation of high speed viterbi decoder
US7107499B1 (en) * 2001-12-07 2006-09-12 Applied Micro Circuits Corporation System and method for adjusting a non-return to zero data stream input threshold
JP4602246B2 (ja) * 2005-12-28 2010-12-22 株式会社東芝 半導体集積回路
US20080061842A1 (en) * 2006-09-07 2008-03-13 Micron Technology, Inc. Circuit and method for detecting timed amplitude reduction of a signal relative to a threshold voltage
US7560959B2 (en) * 2006-09-18 2009-07-14 Micron Technology, Inc. Absolute value peak differential voltage detector circuit and method
US8922923B2 (en) * 2011-03-01 2014-12-30 Seagate Technology Llc Interleaved automatic gain control for asymmetric data signals
US20150268962A1 (en) * 2014-03-24 2015-09-24 GoofyFoot Labs Asynchronous Circuit Design

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5325443B2 (de) * 1972-12-29 1978-07-27
GB2059224B (en) * 1979-07-16 1983-08-03 Gen Electric Co Ltd Data transmission compensating for intersymbol interference
US4504872A (en) * 1983-02-08 1985-03-12 Ampex Corporation Digital maximum likelihood detector for class IV partial response
DE3721884A1 (de) * 1987-07-02 1989-01-12 Meyr Heinrich Prof Dr Verfahren zur ausfuehrung des viterbi-algorithmus mit hilfe parallelverarbeitender strukturen
US5014276A (en) * 1989-02-06 1991-05-07 Scientific Atlanta, Inc. Convolutional encoder and sequential decoder with parallel architecture and block coding properties
EP0438993B1 (de) * 1990-01-25 1997-03-05 International Business Machines Corporation Dekodierungsverfahren mit hoher Datenrate für die Signalverarbeitung in kodierten Kanälen
US5097486A (en) * 1990-07-31 1992-03-17 Ampex Corporation Pipelined decision feedback decoder
US5341387A (en) * 1992-08-27 1994-08-23 Quantum Corporation Viterbi detector having adjustable detection thresholds for PRML class IV sampling data detection

Also Published As

Publication number Publication date
JP2004350299A (ja) 2004-12-09
DE69431065D1 (en) 2002-08-29
EP0728382A1 (de) 1996-08-28
EP0728382A4 (de) 1998-02-25
EP0728382B1 (de) 2002-07-24
WO1995012249A1 (en) 1995-05-04
DE69431065T2 (de) 2003-03-27
JPH09331264A (ja) 1997-12-22
JP4303165B2 (ja) 2009-07-29
US5410556A (en) 1995-04-25

Similar Documents

Publication Publication Date Title
ATE221279T1 (de) Viterbi pipelinedekoder
KR950035111A (ko) 비터비 프로세서의 트렐리스 티코딩 방법
US20060140311A1 (en) Composite data detector and a method for detecting data
CA2134996A1 (en) Apparatus and Method for Trellis Decoder
EP0801501A3 (de) Viterbi-Dekoder für digitale Paketsignale
EP0751625A3 (de) Viterbi-Dekoder mit L=2 besten Dekodierungspfaden
BR0212645A (pt) Arquitetura de tubulação para decodificadores máximos a posteriori (map)
AU2001285732A1 (en) Optimization of acceptance of erroneous codewords and throughput
US6606328B1 (en) Look ahead encoder/decoder architecture
EP0700182B1 (de) Gerät zur Dekodierung mit Fehlerkorrektur in digitalen Datenübertragungssystemen
DE60111974D1 (de) Abbruchkriterium für einen Turbodekoder
US3825924A (en) Pulse code modulation code conversion
KR950015072A (ko) 디지탈 프로세서 및 코프로세서를 구비한 집적 회로
US4573155A (en) Maximum likelihood sequence decoder for linear cyclic codes
US6209109B1 (en) Code synchronization decision circuit of Viterbi decoder
ATE268517T1 (de) Optimierter turbo-decodierer
DE69526644D1 (de) Digitales übertragungs- und aufzeichungsystem mit einfacher fehlerkorrektur
Nuha et al. Binary Data Correction Simulation Using Convolutional Code on Additive White Gaussian Noise Channel
KR980006956A (ko) 비터비 복호 신호의 동기/비동기 판단 방법 및 장치
EP0748057A4 (de) Bitfehler zählverfahren und zähler
TW368781B (en) Signal decoding for either Manhattan or Hamming metric based Viterbi decoders
SU1367164A1 (ru) Декодер рекуррентной последовательности
US20250192797A1 (en) Codec system and its encoding circuit and decoding circuit
EP0909038A3 (de) Decodierung von Faltungscodes mit Gleitkomma ACS Verarbeitung
KR0133501B1 (ko) 가변장 복호기의 에러처리회로

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties